| commit | fb4b5d3a379824d94fd71fc1aa78e9dbcb15b948 | [log] [tgz] |
|---|---|---|
| author | Mike Frysinger <vapier@gentoo.org> | Mon Jun 29 14:20:10 2009 -0400 |
| committer | Mike Frysinger <vapier@gentoo.org> | Thu Jul 16 01:52:24 2009 -0400 |
| tree | 104b640b09ebbc58f4eb3b67fd190bf7bf9a3912 | |
| parent | 8399a74f61c69c7d233924de3dd314ca0effa16a [diff] |
Blackfin: handle BF561 Core B memory regions better when SMP=n Rather than assume Core B is always run with caches turned on, let people load into any of the on-chip memory regions. It is their business how the SRAM/Cache regions are utilized, so don't prevent them from being able to load into them. Signed-off-by: Mike Frysinger <vapier@gentoo.org>