msm_serial_hs: remove unused code
Remove support for all pre BLSP Hardware such as Data Mover
DMA and GSBI. Clean up all checks for non BLSP hardware and
refactor the code.
CRs-Fixed: 647392
Change-Id: I2df3d036b0ce4a16d5a693059ca4bc51f17eef85
Signed-off-by: Naveen Kaje <nkaje@codeaurora.org>
diff --git a/drivers/tty/serial/msm_serial_hs.c b/drivers/tty/serial/msm_serial_hs.c
index c79482b..1050b3f 100644
--- a/drivers/tty/serial/msm_serial_hs.c
+++ b/drivers/tty/serial/msm_serial_hs.c
@@ -62,8 +62,6 @@
#include <asm/atomic.h>
#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <mach/dma.h>
#include <mach/sps.h>
#include <mach/msm_serial_hs.h>
#include <mach/msm_bus.h>
@@ -176,11 +174,6 @@
unsigned int dma_in_flight; /* tx dma in progress */
enum flush_reason flush;
wait_queue_head_t wait;
- struct msm_dmov_cmd xfer;
- dmov_box *command_ptr;
- u32 *command_ptr_ptr;
- dma_addr_t mapped_cmd_ptr;
- dma_addr_t mapped_cmd_ptr_ptr;
int tx_count;
dma_addr_t dma_base;
struct tasklet_struct tlet;
@@ -189,11 +182,6 @@
struct msm_hs_rx {
enum flush_reason flush;
- struct msm_dmov_cmd xfer;
- dma_addr_t cmdptr_dmaaddr;
- dmov_box *command_ptr;
- u32 *command_ptr_ptr;
- dma_addr_t mapped_cmd_ptr;
wait_queue_head_t wait;
dma_addr_t rbuffer;
unsigned char *buffer;
@@ -230,14 +218,6 @@
struct clk *pclk;
struct msm_hs_tx tx;
struct msm_hs_rx rx;
- /* gsbi uarts have to do additional writes to gsbi memory */
- /* block and top control status block. The following pointers */
- /* keep a handle to these blocks. */
- unsigned char __iomem *mapped_gsbi;
- int dma_tx_channel;
- int dma_rx_channel;
- int dma_tx_crci;
- int dma_rx_crci;
struct hrtimer clk_off_timer; /* to poll TXEMT before clock off */
ktime_t clk_off_delay;
enum msm_hs_clk_states_e clk_state;
@@ -266,70 +246,15 @@
u32 bus_perf_client;
/* BLSP UART required BUS Scaling data */
struct msm_bus_scale_pdata *bus_scale_table;
- bool rx_discard_flush_issued;
int rx_count_callback;
bool rx_bam_inprogress;
- unsigned int *reg_ptr;
wait_queue_head_t bam_disconnect_wait;
};
-unsigned int regmap_nonblsp[UART_DM_LAST] = {
- [UART_DM_MR1] = UARTDM_MR1_ADDR,
- [UART_DM_MR2] = UARTDM_MR2_ADDR,
- [UART_DM_IMR] = UARTDM_IMR_ADDR,
- [UART_DM_SR] = UARTDM_SR_ADDR,
- [UART_DM_CR] = UARTDM_CR_ADDR,
- [UART_DM_CSR] = UARTDM_CSR_ADDR,
- [UART_DM_IPR] = UARTDM_IPR_ADDR,
- [UART_DM_ISR] = UARTDM_ISR_ADDR,
- [UART_DM_RX_TOTAL_SNAP] = UARTDM_RX_TOTAL_SNAP_ADDR,
- [UART_DM_TFWR] = UARTDM_TFWR_ADDR,
- [UART_DM_RFWR] = UARTDM_RFWR_ADDR,
- [UART_DM_RF] = UARTDM_RF_ADDR,
- [UART_DM_TF] = UARTDM_TF_ADDR,
- [UART_DM_MISR] = UARTDM_MISR_ADDR,
- [UART_DM_DMRX] = UARTDM_DMRX_ADDR,
- [UART_DM_NCF_TX] = UARTDM_NCF_TX_ADDR,
- [UART_DM_DMEN] = UARTDM_DMEN_ADDR,
- [UART_DM_TXFS] = UARTDM_TXFS_ADDR,
- [UART_DM_RXFS] = UARTDM_RXFS_ADDR,
- [UART_DM_RX_TRANS_CTRL] = UARTDM_RX_TRANS_CTRL_ADDR,
-};
-
-unsigned int regmap_blsp[UART_DM_LAST] = {
- [UART_DM_MR1] = 0x0,
- [UART_DM_MR2] = 0x4,
- [UART_DM_IMR] = 0xb0,
- [UART_DM_SR] = 0xa4,
- [UART_DM_CR] = 0xa8,
- [UART_DM_CSR] = 0xa0,
- [UART_DM_IPR] = 0x18,
- [UART_DM_ISR] = 0xb4,
- [UART_DM_RX_TOTAL_SNAP] = 0xbc,
- [UART_DM_TFWR] = 0x1c,
- [UART_DM_RFWR] = 0x20,
- [UART_DM_RF] = 0x140,
- [UART_DM_TF] = 0x100,
- [UART_DM_MISR] = 0xac,
- [UART_DM_DMRX] = 0x34,
- [UART_DM_NCF_TX] = 0x40,
- [UART_DM_DMEN] = 0x3c,
- [UART_DM_TXFS] = 0x4c,
- [UART_DM_RXFS] = 0x50,
- [UART_DM_RX_TRANS_CTRL] = 0xcc,
- [UART_DM_BCR] = 0xc8,
-};
-
static struct of_device_id msm_hs_match_table[] = {
{ .compatible = "qcom,msm-hsuart-v14",
- .data = regmap_blsp
},
- {
- .compatible = "qcom,msm-hsuart-v13",
- .data = regmap_nonblsp
- },
- {}
};
@@ -536,21 +461,11 @@
return (msm_uport->wakeup.irq > 0);
}
-static inline int is_gsbi_uart(struct msm_hs_port *msm_uport)
-{
- /* assume gsbi uart if gsbi resource found in pdata */
- return ((msm_uport->mapped_gsbi != NULL));
-}
-static unsigned int is_blsp_uart(struct msm_hs_port *msm_uport)
-{
- return (msm_uport->uart_type == BLSP_HSUART);
-}
-
static void msm_hs_bus_voting(struct msm_hs_port *msm_uport, unsigned int vote)
{
int ret;
- if (is_blsp_uart(msm_uport) && msm_uport->bus_perf_client) {
+ if (msm_uport->bus_perf_client) {
MSM_HS_DBG("Bus voting:%d\n", vote);
ret = msm_bus_scale_client_update_request(
msm_uport->bus_perf_client, vote);
@@ -563,22 +478,13 @@
static inline unsigned int msm_hs_read(struct uart_port *uport,
unsigned int index)
{
- struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
- unsigned int offset;
-
- offset = *(msm_uport->reg_ptr + index);
-
- return readl_relaxed(uport->membase + offset);
+ return readl_relaxed(uport->membase + index);
}
static inline void msm_hs_write(struct uart_port *uport, unsigned int index,
unsigned int value)
{
- struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
- unsigned int offset;
-
- offset = *(msm_uport->reg_ptr + index);
- writel_relaxed(value, uport->membase + offset);
+ writel_relaxed(value, uport->membase + index);
}
static int sps_rx_disconnect(struct sps_pipe *sps_pipe_handler)
@@ -642,55 +548,6 @@
MSM_HS_DBG("clk_state:%d", msm_uport->clk_state);
}
-static void msm_hs_release_port(struct uart_port *port)
-{
- struct msm_hs_port *msm_uport = UARTDM_TO_MSM(port);
- struct platform_device *pdev = to_platform_device(port->dev);
- struct resource *gsbi_resource;
- resource_size_t size;
-
- if (is_gsbi_uart(msm_uport)) {
- iowrite32(GSBI_PROTOCOL_IDLE, msm_uport->mapped_gsbi +
- GSBI_CONTROL_ADDR);
- gsbi_resource = platform_get_resource_byname(pdev,
- IORESOURCE_MEM,
- "gsbi_resource");
- if (unlikely(!gsbi_resource))
- return;
-
- size = resource_size(gsbi_resource);
- release_mem_region(gsbi_resource->start, size);
- iounmap(msm_uport->mapped_gsbi);
- msm_uport->mapped_gsbi = NULL;
- }
-}
-
-static int msm_hs_request_port(struct uart_port *port)
-{
- struct msm_hs_port *msm_uport = UARTDM_TO_MSM(port);
- struct platform_device *pdev = to_platform_device(port->dev);
- struct resource *gsbi_resource;
- resource_size_t size;
-
- gsbi_resource = platform_get_resource_byname(pdev,
- IORESOURCE_MEM,
- "gsbi_resource");
- if (gsbi_resource) {
- size = resource_size(gsbi_resource);
- if (unlikely(!request_mem_region(gsbi_resource->start, size,
- "msm_serial_hs")))
- return -EBUSY;
- msm_uport->mapped_gsbi = ioremap(gsbi_resource->start,
- size);
- if (!msm_uport->mapped_gsbi) {
- release_mem_region(gsbi_resource->start, size);
- return -EBUSY;
- }
- }
- /* no gsbi uart */
- return 0;
-}
-
static int msm_serial_loopback_enable_set(void *data, u64 val)
{
struct msm_hs_port *msm_uport = data;
@@ -703,21 +560,15 @@
if (val) {
spin_lock_irqsave(&uport->lock, flags);
ret = msm_hs_read(uport, UART_DM_MR2);
- if (is_blsp_uart(msm_uport))
- ret |= (UARTDM_MR2_LOOP_MODE_BMSK |
- UARTDM_MR2_RFR_CTS_LOOP_MODE_BMSK);
- else
- ret |= UARTDM_MR2_LOOP_MODE_BMSK;
+ ret |= (UARTDM_MR2_LOOP_MODE_BMSK |
+ UARTDM_MR2_RFR_CTS_LOOP_MODE_BMSK);
msm_hs_write(uport, UART_DM_MR2, ret);
spin_unlock_irqrestore(&uport->lock, flags);
} else {
spin_lock_irqsave(&uport->lock, flags);
ret = msm_hs_read(uport, UART_DM_MR2);
- if (is_blsp_uart(msm_uport))
- ret &= ~(UARTDM_MR2_LOOP_MODE_BMSK |
- UARTDM_MR2_RFR_CTS_LOOP_MODE_BMSK);
- else
- ret &= ~UARTDM_MR2_LOOP_MODE_BMSK;
+ ret &= ~(UARTDM_MR2_LOOP_MODE_BMSK |
+ UARTDM_MR2_RFR_CTS_LOOP_MODE_BMSK);
msm_hs_write(uport, UART_DM_MR2, ret);
spin_unlock_irqrestore(&uport->lock, flags);
}
@@ -791,19 +642,10 @@
sysfs_remove_file(&pdev->dev.kobj, &dev_attr_clock.attr);
debugfs_remove(msm_uport->loopback_dir);
- dma_unmap_single(dev, msm_uport->rx.mapped_cmd_ptr, sizeof(dmov_box),
- DMA_TO_DEVICE);
dma_pool_free(msm_uport->rx.pool, msm_uport->rx.buffer,
msm_uport->rx.rbuffer);
dma_pool_destroy(msm_uport->rx.pool);
- dma_unmap_single(dev, msm_uport->rx.cmdptr_dmaaddr, sizeof(u32),
- DMA_TO_DEVICE);
- dma_unmap_single(dev, msm_uport->tx.mapped_cmd_ptr_ptr, sizeof(u32),
- DMA_TO_DEVICE);
- dma_unmap_single(dev, msm_uport->tx.mapped_cmd_ptr, sizeof(dmov_box),
- DMA_TO_DEVICE);
-
wake_lock_destroy(&msm_uport->rx.wake_lock);
wake_lock_destroy(&msm_uport->dma_wake_lock);
destroy_workqueue(msm_uport->hsuart_wq);
@@ -814,14 +656,6 @@
if (msm_uport->pclk)
clk_put(msm_uport->pclk);
- /* Free the tx resources */
- kfree(msm_uport->tx.command_ptr);
- kfree(msm_uport->tx.command_ptr_ptr);
-
- /* Free the rx resources */
- kfree(msm_uport->rx.command_ptr);
- kfree(msm_uport->rx.command_ptr_ptr);
-
iounmap(msm_uport->uport.membase);
return 0;
@@ -873,14 +707,14 @@
ret = sps_connect(sps_pipe_handle, sps_config);
if (ret) {
MSM_HS_ERR("msm_serial_hs: sps_connect() failed for tx!!\n"
- "pipe_handle=0x%x ret=%d", (u32)sps_pipe_handle, ret);
+ "pipe_handle=0x%p ret=%d", sps_pipe_handle, ret);
return ret;
}
/* Register callback event for EOT (End of transfer) event. */
ret = sps_register_event(sps_pipe_handle, sps_event);
if (ret) {
MSM_HS_ERR("msm_serial_hs: sps_connect() failed for tx!!\n"
- "pipe_handle=0x%x ret=%d", (u32)sps_pipe_handle, ret);
+ "pipe_handle=0x%p ret=%d", sps_pipe_handle, ret);
goto reg_event_err;
}
return 0;
@@ -914,14 +748,14 @@
ret = sps_connect(sps_pipe_handle, sps_config);
if (ret) {
MSM_HS_ERR("msm_serial_hs: sps_connect() failed for rx!!\n"
- "pipe_handle=0x%x ret=%d", (u32)sps_pipe_handle, ret);
+ "pipe_handle=0x%p ret=%d", sps_pipe_handle, ret);
return ret;
}
/* Register callback event for DESC_DONE event. */
ret = sps_register_event(sps_pipe_handle, sps_event);
if (ret) {
MSM_HS_ERR("msm_serial_hs: sps_connect() failed for rx!!\n"
- "pipe_handle=0x%x ret=%d", (u32)sps_pipe_handle, ret);
+ "pipe_handle=0x%p ret=%d", sps_pipe_handle, ret);
goto reg_event_err;
}
return 0;
@@ -1037,17 +871,15 @@
mb();
if (bps > 460800) {
uport->uartclk = bps * 16;
- if (is_blsp_uart(msm_uport)) {
- /* BLSP based UART supports maximum clock frequency
- * of 63.16 Mhz. With this (63.16 Mhz) clock frequency
- * UART can support baud rate of 3.94 Mbps which is
- * equivalent to 4 Mbps.
- * UART hardware is robust enough to handle this
- * deviation to achieve baud rate ~4 Mbps.
- */
- if (bps == 4000000)
- uport->uartclk = BLSP_UART_CLK_FMAX;
- }
+ /* BLSP based UART supports maximum clock frequency
+ * of 63.16 Mhz. With this (63.16 Mhz) clock frequency
+ * UART can support baud rate of 3.94 Mbps which is
+ * equivalent to 4 Mbps.
+ * UART hardware is robust enough to handle this
+ * deviation to achieve baud rate ~4 Mbps.
+ */
+ if (bps == 4000000)
+ uport->uartclk = BLSP_UART_CLK_FMAX;
} else {
uport->uartclk = 7372800;
}
@@ -1169,12 +1001,8 @@
* suggested to do disable/reset or reset/disable at the same time.
*/
data = msm_hs_read(uport, UART_DM_DMEN);
- if (is_blsp_uart(msm_uport)) {
- /* Disable UARTDM RX BAM Interface */
- data &= ~UARTDM_RX_BAM_ENABLE_BMSK;
- } else {
- data &= ~UARTDM_RX_DM_EN_BMSK;
- }
+ /* Disable UARTDM RX BAM Interface */
+ data &= ~UARTDM_RX_BAM_ENABLE_BMSK;
msm_hs_write(uport, UART_DM_DMEN, data);
@@ -1250,37 +1078,18 @@
if (msm_uport->rx.flush == FLUSH_NONE) {
wake_lock(&msm_uport->rx.wake_lock);
msm_uport->rx.flush = FLUSH_DATA_INVALID;
- /*
- * Before using dmov APIs make sure that
- * previous writel are completed. Hence
- * dsb requires here.
- */
mb();
- if (is_blsp_uart(msm_uport)) {
- if (msm_uport->rx_bam_inprogress)
- ret = wait_event_timeout(msm_uport->rx.wait,
- msm_uport->rx_bam_inprogress == false,
- RX_FLUSH_COMPLETE_TIMEOUT);
- ret = sps_rx_disconnect(sps_pipe_handle);
- if (ret)
- MSM_HS_ERR("%s(): sps_disconnect failed\n",
- __func__);
- msm_hs_spsconnect_rx(uport);
- msm_uport->rx.flush = FLUSH_IGNORE;
- msm_serial_hs_rx_tlet((unsigned long) &rx->tlet);
- } else {
- msm_uport->rx_discard_flush_issued = true;
- /* do discard flush */
- msm_dmov_flush(msm_uport->dma_rx_channel, 0);
- MSM_HS_DBG("%s(): wainting for flush completion.\n",
- __func__);
+ if (msm_uport->rx_bam_inprogress)
ret = wait_event_timeout(msm_uport->rx.wait,
- msm_uport->rx_discard_flush_issued == false,
+ msm_uport->rx_bam_inprogress == false,
RX_FLUSH_COMPLETE_TIMEOUT);
- if (!ret)
- MSM_HS_ERR("%s(): Discard flush pending.\n",
- __func__);
- }
+ ret = sps_rx_disconnect(sps_pipe_handle);
+ if (ret)
+ MSM_HS_ERR("%s(): sps_disconnect failed\n",
+ __func__);
+ msm_hs_spsconnect_rx(uport);
+ msm_uport->rx.flush = FLUSH_IGNORE;
+ msm_serial_hs_rx_tlet((unsigned long) &rx->tlet);
}
/* Configure HW flow control
@@ -1383,10 +1192,7 @@
if (msm_uport->clk_state != MSM_HS_CLK_OFF) {
/* disable dlink */
data = msm_hs_read(uport, UART_DM_DMEN);
- if (is_blsp_uart(msm_uport))
- data &= ~UARTDM_RX_BAM_ENABLE_BMSK;
- else
- data &= ~UARTDM_RX_DM_EN_BMSK;
+ data &= ~UARTDM_RX_BAM_ENABLE_BMSK;
msm_hs_write(uport, UART_DM_DMEN, data);
/* calling DMOV or CLOCK API. Hence mb() */
@@ -1395,19 +1201,11 @@
/* Disable the receiver */
if (msm_uport->rx.flush == FLUSH_NONE) {
wake_lock(&msm_uport->rx.wake_lock);
- if (is_blsp_uart(msm_uport)) {
- msm_uport->rx.flush = FLUSH_STOP;
- /* workqueue for BAM rx endpoint disconnect */
- queue_work(msm_uport->hsuart_wq,
- &msm_uport->disconnect_rx_endpoint);
- } else {
- /* do discard flush */
- msm_dmov_flush(msm_uport->dma_rx_channel, 0);
- }
- }
- if (!is_blsp_uart(msm_uport) && msm_uport->rx.flush != FLUSH_SHUTDOWN)
msm_uport->rx.flush = FLUSH_STOP;
-
+ /* workqueue for BAM rx endpoint disconnect */
+ queue_work(msm_uport->hsuart_wq,
+ &msm_uport->disconnect_rx_endpoint);
+ }
}
/* Transmit the next chunk of data */
@@ -1457,43 +1255,15 @@
dma_sync_single_for_device(uport->dev, aligned_src_addr,
aligned_tx_count, DMA_TO_DEVICE);
- if (is_blsp_uart(msm_uport))
- tx->tx_count = tx_count;
- else {
- tx->command_ptr->num_rows =
- (((tx_count + 15) >> 4) << 16) |
- ((tx_count + 15) >> 4);
- tx->command_ptr->src_row_addr = src_addr;
-
- dma_sync_single_for_device(uport->dev, tx->mapped_cmd_ptr,
- sizeof(dmov_box), DMA_TO_DEVICE);
-
- *tx->command_ptr_ptr = CMD_PTR_LP |
- DMOV_CMD_ADDR(tx->mapped_cmd_ptr);
- /* Save tx_count to use in Callback */
- tx->tx_count = tx_count;
- msm_hs_write(uport, UART_DM_NCF_TX, tx_count);
- msm_uport->imr_reg &= ~UARTDM_ISR_TX_READY_BMSK;
- msm_hs_write(uport, UART_DM_IMR, msm_uport->imr_reg);
- /* Calling next DMOV API. Hence mb() here. */
- mb();
-
- }
+ tx->tx_count = tx_count;
msm_uport->tx.flush = FLUSH_NONE;
- if (is_blsp_uart(msm_uport)) {
- sps_pipe_handle = tx->cons.pipe_handle;
- /* Queue transfer request to SPS */
- sps_transfer_one(sps_pipe_handle, src_addr, tx_count,
- msm_uport, flags);
- } else {
- dma_sync_single_for_device(uport->dev, tx->mapped_cmd_ptr_ptr,
- sizeof(u32), DMA_TO_DEVICE);
+ sps_pipe_handle = tx->cons.pipe_handle;
+ /* Queue transfer request to SPS */
+ sps_transfer_one(sps_pipe_handle, src_addr, tx_count,
+ msm_uport, flags);
- msm_dmov_enqueue_cmd(msm_uport->dma_tx_channel, &tx->xfer);
-
- }
MSM_HS_DBG("%s:Enqueue Tx Cmd\n", __func__);
dump_uart_hs_registers(msm_uport);
}
@@ -1531,43 +1301,34 @@
* disable in set_termios before configuring baud rate.
*/
data = msm_hs_read(uport, UART_DM_DMEN);
- if (is_blsp_uart(msm_uport)) {
- /* Enable UARTDM Rx BAM Interface */
- data |= UARTDM_RX_BAM_ENABLE_BMSK;
- } else {
- data |= UARTDM_RX_DM_EN_BMSK;
- }
+ /* Enable UARTDM Rx BAM Interface */
+ data |= UARTDM_RX_BAM_ENABLE_BMSK;
msm_hs_write(uport, UART_DM_DMEN, data);
msm_hs_write(uport, UART_DM_IMR, msm_uport->imr_reg);
/* Calling next DMOV API. Hence mb() here. */
mb();
- if (is_blsp_uart(msm_uport)) {
- /*
- * RX-transfer will be automatically re-activated
- * after last data of previous transfer was read.
- */
- data = (RX_STALE_AUTO_RE_EN | RX_TRANS_AUTO_RE_ACTIVATE |
- RX_DMRX_CYCLIC_EN);
- msm_hs_write(uport, UART_DM_RX_TRANS_CTRL, data);
- /* Issue RX BAM Start IFC command */
- msm_hs_write(uport, UART_DM_CR, START_RX_BAM_IFC);
- mb();
- }
+ /*
+ * RX-transfer will be automatically re-activated
+ * after last data of previous transfer was read.
+ */
+ data = (RX_STALE_AUTO_RE_EN | RX_TRANS_AUTO_RE_ACTIVATE |
+ RX_DMRX_CYCLIC_EN);
+ msm_hs_write(uport, UART_DM_RX_TRANS_CTRL, data);
+ /* Issue RX BAM Start IFC command */
+ msm_hs_write(uport, UART_DM_CR, START_RX_BAM_IFC);
+ mb();
msm_uport->rx.flush = FLUSH_NONE;
-
- if (is_blsp_uart(msm_uport)) {
- msm_uport->rx_bam_inprogress = true;
- sps_pipe_handle = rx->prod.pipe_handle;
- /* Queue transfer request to SPS */
- sps_transfer_one(sps_pipe_handle, rx->rbuffer,
- UARTDM_RX_BUF_SIZE, msm_uport, flags);
- msm_uport->rx_bam_inprogress = false;
- msm_uport->rx.rx_cmd_queued = true;
- wake_up(&msm_uport->rx.wait);
- }
+ msm_uport->rx_bam_inprogress = true;
+ sps_pipe_handle = rx->prod.pipe_handle;
+ /* Queue transfer request to SPS */
+ sps_transfer_one(sps_pipe_handle, rx->rbuffer,
+ UARTDM_RX_BUF_SIZE, msm_uport, flags);
+ msm_uport->rx_bam_inprogress = false;
+ msm_uport->rx.rx_cmd_queued = true;
+ wake_up(&msm_uport->rx.wait);
MSM_HS_DBG("%s:Enqueue Rx Cmd\n", __func__);
dump_uart_hs_registers(msm_uport);
}
@@ -1657,9 +1418,6 @@
spin_lock_irqsave(&uport->lock, flags);
- if (!is_blsp_uart(msm_uport))
- msm_hs_write(uport, UART_DM_CR, STALE_EVENT_DISABLE);
-
MSM_HS_DBG("In %s\n", __func__);
dump_uart_hs_registers(msm_uport);
@@ -1716,16 +1474,7 @@
if (flush >= FLUSH_DATA_INVALID)
goto out;
- if (is_blsp_uart(msm_uport)) {
- rx_count = msm_uport->rx_count_callback;
- } else {
- if (msm_uport->clk_state == MSM_HS_CLK_ON) {
- rx_count = msm_hs_read(uport, UART_DM_RX_TOTAL_SNAP);
- /* order the read of rx.buffer */
- rmb();
- } else
- MSM_HS_WARN("%s: Failed.Clocks are OFF\n", __func__);
- }
+ rx_count = msm_uport->rx_count_callback;
MSM_HS_DBG("%s():[UART_RX]<%d>\n", __func__, rx_count);
hex_dump_ipc("HSUART Read: ", msm_uport->rx.buffer, rx_count);
@@ -1740,20 +1489,16 @@
}
}
if (!msm_uport->rx.buffer_pending && !msm_uport->rx.rx_cmd_queued) {
- if (is_blsp_uart(msm_uport)) {
- msm_uport->rx.flush = FLUSH_NONE;
- msm_uport->rx_bam_inprogress = true;
- sps_pipe_handle = rx->prod.pipe_handle;
- MSM_HS_DBG("Queing bam descriptor\n");
- /* Queue transfer request to SPS */
- sps_transfer_one(sps_pipe_handle, rx->rbuffer,
- UARTDM_RX_BUF_SIZE, msm_uport, sps_flags);
- msm_uport->rx_bam_inprogress = false;
- msm_uport->rx.rx_cmd_queued = true;
- wake_up(&msm_uport->rx.wait);
-
- } else
- msm_hs_start_rx_locked(uport);
+ msm_uport->rx.flush = FLUSH_NONE;
+ msm_uport->rx_bam_inprogress = true;
+ sps_pipe_handle = rx->prod.pipe_handle;
+ MSM_HS_DBG("Queing bam descriptor\n");
+ /* Queue transfer request to SPS */
+ sps_transfer_one(sps_pipe_handle, rx->rbuffer,
+ UARTDM_RX_BUF_SIZE, msm_uport, sps_flags);
+ msm_uport->rx_bam_inprogress = false;
+ msm_uport->rx.rx_cmd_queued = true;
+ wake_up(&msm_uport->rx.wait);
}
out:
if (msm_uport->rx.buffer_pending) {
@@ -1782,12 +1527,9 @@
if (msm_uport->clk_state != MSM_HS_CLK_ON) {
MSM_HS_WARN("%s: Failed.Clocks are OFF\n", __func__);
}
- if (msm_uport->tx.tx_ready_int_en == 0) {
- if (!is_blsp_uart(msm_uport))
- msm_uport->tx.tx_ready_int_en = 1;
- if (msm_uport->tx.dma_in_flight == 0)
+ if ((msm_uport->tx.tx_ready_int_en == 0) &&
+ (msm_uport->tx.dma_in_flight == 0))
msm_hs_submit_tx_locked(uport);
- }
}
/**
@@ -1807,7 +1549,7 @@
msm_uport->notify = *notify;
MSM_HS_DBG("%s: ev_id=%d, addr=0x%x, size=0x%x, flags=0x%x, line=%d\n",
- __func__, notify->event_id,
+ __func__, notify->event_id,
notify->data.transfer.iovec.addr,
notify->data.transfer.iovec.size,
notify->data.transfer.iovec.flags,
@@ -1816,30 +1558,6 @@
tasklet_schedule(&msm_uport->tx.tlet);
}
-/*
- * This routine is called when we are done with a DMA transfer
- *
- * This routine is registered with Data mover when we set
- * up a Data Mover transfer. It is called from Data mover ISR
- * when the DMA transfer is done.
- */
-static void msm_hs_dmov_tx_callback(struct msm_dmov_cmd *cmd_ptr,
- unsigned int result,
- struct msm_dmov_errdata *err)
-{
- struct msm_hs_port *msm_uport;
-
- msm_uport = container_of(cmd_ptr, struct msm_hs_port, tx.xfer);
- if (msm_uport->tx.flush == FLUSH_STOP)
- /* DMA FLUSH unsuccesfful */
- WARN_ON(!(result & DMOV_RSLT_FLUSH));
- else
- /* DMA did not finish properly */
- WARN_ON(!(result & DMOV_RSLT_DONE));
-
- tasklet_schedule(&msm_uport->tx.tlet);
-}
-
static void msm_serial_hs_tx_tlet(unsigned long tlet_ptr)
{
unsigned long flags;
@@ -1883,15 +1601,6 @@
return;
}
- /* TX_READY_BMSK only if non BAM mode */
- if (!is_blsp_uart(msm_uport)) {
- msm_uport->imr_reg |= UARTDM_ISR_TX_READY_BMSK;
- msm_hs_write(&(msm_uport->uport), UART_DM_IMR,
- msm_uport->imr_reg);
- /* Calling clk API. Hence mb() requires. */
- mb();
- }
-
spin_unlock_irqrestore(&(msm_uport->uport.lock), flags);
MSM_HS_DBG("In %s()\n", __func__);
dump_uart_hs_registers(msm_uport);
@@ -1933,39 +1642,6 @@
}
/*
- * This routine is called when we are done with a DMA transfer or the
- * a flush has been sent to the data mover driver.
- *
- * This routine is registered with Data mover when we set up a Data Mover
- * transfer. It is called from Data mover ISR when the DMA transfer is done.
- */
-static void msm_hs_dmov_rx_callback(struct msm_dmov_cmd *cmd_ptr,
- unsigned int result,
- struct msm_dmov_errdata *err)
-{
- struct msm_hs_port *msm_uport;
- struct uart_port *uport;
- unsigned long flags;
-
- msm_uport = container_of(cmd_ptr, struct msm_hs_port, rx.xfer);
- uport = &(msm_uport->uport);
-
- MSM_HS_DBG("%s(): called result:%x\n", __func__, result);
- if (!(result & DMOV_RSLT_ERROR)) {
- if (result & DMOV_RSLT_FLUSH) {
- if (msm_uport->rx_discard_flush_issued) {
- spin_lock_irqsave(&uport->lock, flags);
- msm_uport->rx_discard_flush_issued = false;
- spin_unlock_irqrestore(&uport->lock, flags);
- wake_up(&msm_uport->rx.wait);
- }
- }
- }
-
- tasklet_schedule(&msm_uport->rx.tlet);
-}
-
-/*
* Standard API, Current states of modem control inputs
*
* Since CTS can be handled entirely by HARDWARE we always
@@ -2075,24 +1751,9 @@
static void msm_hs_config_port(struct uart_port *uport, int cfg_flags)
{
- unsigned long flags;
- struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
-
- if (cfg_flags & UART_CONFIG_TYPE) {
+ if (cfg_flags & UART_CONFIG_TYPE)
uport->type = PORT_MSM;
- msm_hs_request_port(uport);
- }
- if (is_gsbi_uart(msm_uport)) {
- if (msm_uport->pclk)
- clk_prepare_enable(msm_uport->pclk);
- spin_lock_irqsave(&uport->lock, flags);
- iowrite32(GSBI_PROTOCOL_UART, msm_uport->mapped_gsbi +
- GSBI_CONTROL_ADDR);
- spin_unlock_irqrestore(&uport->lock, flags);
- if (msm_uport->pclk)
- clk_disable_unprepare(msm_uport->pclk);
- }
}
/* Handle CTS changes (Called from interrupt handler) */
@@ -2165,11 +1826,8 @@
}
if (msm_uport->rx.flush != FLUSH_SHUTDOWN) {
- if (msm_uport->rx.flush == FLUSH_NONE) {
+ if (msm_uport->rx.flush == FLUSH_NONE)
msm_hs_stop_rx_locked(uport);
- if (!is_blsp_uart(msm_uport))
- msm_uport->rx_discard_flush_issued = true;
- }
MSM_HS_DBG("%s: rx.flush %d clk_state %d\n", __func__,
msm_uport->rx.flush, msm_uport->clk_state);
@@ -2262,11 +1920,6 @@
*/
mb();
MSM_HS_DBG("%s:Stal Interrupt\n", __func__);
-
- if (!is_blsp_uart(msm_uport) && (rx->flush == FLUSH_NONE)) {
- rx->flush = FLUSH_DATA_READY;
- msm_dmov_flush(msm_uport->dma_rx_channel, 1);
- }
}
/* tx ready interrupt */
if (isr_status & UARTDM_ISR_TX_READY_BMSK) {
@@ -2435,10 +2088,7 @@
msm_uport->rx.flush == FLUSH_SHUTDOWN) {
msm_hs_write(uport, UART_DM_CR, RESET_RX);
data = msm_hs_read(uport, UART_DM_DMEN);
- if (is_blsp_uart(msm_uport))
- data |= UARTDM_RX_BAM_ENABLE_BMSK;
- else
- data |= UARTDM_RX_DM_EN_BMSK;
+ data |= UARTDM_RX_BAM_ENABLE_BMSK;
msm_hs_write(uport, UART_DM_DMEN, data);
/* Complete above device write. Hence mb() here. */
mb();
@@ -2446,11 +2096,9 @@
MSM_HS_DBG("%s: rx.flush %d\n", __func__, msm_uport->rx.flush);
if (msm_uport->rx.flush == FLUSH_SHUTDOWN) {
- if (is_blsp_uart(msm_uport)) {
- spin_unlock_irqrestore(&uport->lock, flags);
- msm_hs_spsconnect_rx(uport);
- spin_lock_irqsave(&uport->lock, flags);
- }
+ spin_unlock_irqrestore(&uport->lock, flags);
+ msm_hs_spsconnect_rx(uport);
+ spin_lock_irqsave(&uport->lock, flags);
msm_hs_start_rx_locked(uport);
}
if (msm_uport->rx.flush == FLUSH_STOP)
@@ -2616,9 +2264,6 @@
unsigned long flags;
unsigned int data;
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
- struct platform_device *pdev = to_platform_device(uport->dev);
- const struct msm_serial_hs_platform_data *pdata =
- pdev->dev.platform_data;
struct circ_buf *tx_buf = &uport->state->xmit;
struct msm_hs_tx *tx = &msm_uport->tx;
struct msm_hs_rx *rx = &msm_uport->rx;
@@ -2641,33 +2286,25 @@
return ret;
}
- if (is_blsp_uart(msm_uport)) {
- ret = msm_hs_config_uart_gpios(uport);
- if (ret) {
- MSM_HS_ERR("Uart GPIO request failed\n");
- goto deinit_uart_clk;
- }
- } else {
- if (pdata && pdata->gpio_config)
- if (unlikely(pdata->gpio_config(1)))
- dev_err(uport->dev, "Cannot configure gpios\n");
+ ret = msm_hs_config_uart_gpios(uport);
+ if (ret) {
+ MSM_HS_ERR("Uart GPIO request failed\n");
+ goto deinit_uart_clk;
}
/* SPS Connect for BAM endpoints */
- if (is_blsp_uart(msm_uport)) {
- /* SPS connect for TX */
- ret = msm_hs_spsconnect_tx(uport);
- if (ret) {
- MSM_HS_ERR("msm_serial_hs: SPS connect failed for TX");
- goto unconfig_uart_gpios;
- }
+ /* SPS connect for TX */
+ ret = msm_hs_spsconnect_tx(uport);
+ if (ret) {
+ MSM_HS_ERR("msm_serial_hs: SPS connect failed for TX");
+ goto unconfig_uart_gpios;
+ }
- /* SPS connect for RX */
- ret = msm_hs_spsconnect_rx(uport);
- if (ret) {
- MSM_HS_ERR("msm_serial_hs: SPS connect failed for RX");
- goto sps_disconnect_tx;
- }
+ /* SPS connect for RX */
+ ret = msm_hs_spsconnect_rx(uport);
+ if (ret) {
+ MSM_HS_ERR("msm_serial_hs: SPS connect failed for RX");
+ goto sps_disconnect_tx;
}
data = (UARTDM_BCR_TX_BREAK_DISABLE | UARTDM_BCR_STALE_IRQ_EMPTY |
@@ -2690,13 +2327,8 @@
msm_hs_write(uport, UART_DM_IPR, data);
}
- if (is_blsp_uart(msm_uport)) {
- /* Enable BAM mode */
- data = UARTDM_TX_BAM_ENABLE_BMSK | UARTDM_RX_BAM_ENABLE_BMSK;
- } else {
- /* Enable Data Mover Mode */
- data = UARTDM_TX_DM_EN_BMSK | UARTDM_RX_DM_EN_BMSK;
- }
+ /* Enable BAM mode */
+ data = UARTDM_TX_BAM_ENABLE_BMSK | UARTDM_RX_BAM_ENABLE_BMSK;
msm_hs_write(uport, UART_DM_DMEN, data);
/* Reset TX */
@@ -2718,23 +2350,6 @@
tx->dma_in_flight = 0;
rx->rx_cmd_exec = false;
- if (!is_blsp_uart(msm_uport)) {
- tx->xfer.complete_func = msm_hs_dmov_tx_callback;
-
- tx->command_ptr->cmd = CMD_LC |
- CMD_DST_CRCI(msm_uport->dma_tx_crci) | CMD_MODE_BOX;
-
- tx->command_ptr->src_dst_len = (MSM_UARTDM_BURST_SIZE << 16)
- | (MSM_UARTDM_BURST_SIZE);
-
- tx->command_ptr->row_offset = (MSM_UARTDM_BURST_SIZE << 16);
-
- tx->command_ptr->dst_row_addr =
- msm_uport->uport.mapbase + UARTDM_TF_ADDR;
-
- msm_uport->imr_reg |= UARTDM_ISR_RXSTALE_BMSK;
- }
-
/* Enable reading the current CTS, no harm even if CTS is ignored */
msm_uport->imr_reg |= UARTDM_ISR_CURRENT_CTS_BMSK;
@@ -2789,14 +2404,11 @@
if (use_low_power_wakeup(msm_uport))
irq_set_irq_wake(msm_uport->wakeup.irq, 0);
sps_disconnect_rx:
- if (is_blsp_uart(msm_uport))
- sps_disconnect(sps_pipe_handle_rx);
+ sps_disconnect(sps_pipe_handle_rx);
sps_disconnect_tx:
- if (is_blsp_uart(msm_uport))
- sps_disconnect(sps_pipe_handle_tx);
+ sps_disconnect(sps_pipe_handle_tx);
unconfig_uart_gpios:
- if (is_blsp_uart(msm_uport))
- msm_hs_unconfig_uart_gpios(uport);
+ msm_hs_unconfig_uart_gpios(uport);
deinit_uart_clk:
msm_hs_clock_unvote(msm_uport);
wake_unlock(&msm_uport->dma_wake_lock);
@@ -2829,7 +2441,7 @@
if (!rx->pool) {
MSM_HS_ERR("%s(): cannot allocate rx_buffer_pool", __func__);
ret = -ENOMEM;
- goto exit_tasket_init;
+ goto exit_tasklet_init;
}
rx->buffer = dma_pool_alloc(rx->pool, GFP_KERNEL, &rx->rbuffer);
@@ -2840,99 +2452,15 @@
}
/* Set up Uart Receive */
- if (is_blsp_uart(msm_uport))
- msm_hs_write(uport, UART_DM_RFWR, 32);
- else
- msm_hs_write(uport, UART_DM_RFWR, 0);
+ msm_hs_write(uport, UART_DM_RFWR, 32);
INIT_DELAYED_WORK(&rx->flip_insert_work, flip_insert_work);
- if (is_blsp_uart(msm_uport))
- return ret;
-
- /* Allocate the command pointer. Needs to be 64 bit aligned */
- tx->command_ptr = kmalloc(sizeof(dmov_box), GFP_KERNEL | __GFP_DMA);
- if (!tx->command_ptr) {
- return -ENOMEM;
- goto free_rx_buffer;
- }
-
- tx->command_ptr_ptr = kmalloc(sizeof(u32), GFP_KERNEL | __GFP_DMA);
- if (!tx->command_ptr_ptr) {
- ret = -ENOMEM;
- goto free_tx_command_ptr;
- }
-
- tx->mapped_cmd_ptr = dma_map_single(uport->dev, tx->command_ptr,
- sizeof(dmov_box), DMA_TO_DEVICE);
- tx->mapped_cmd_ptr_ptr = dma_map_single(uport->dev,
- tx->command_ptr_ptr,
- sizeof(u32), DMA_TO_DEVICE);
- tx->xfer.cmdptr = DMOV_CMD_ADDR(tx->mapped_cmd_ptr_ptr);
-
- /* Allocate the command pointer. Needs to be 64 bit aligned */
- rx->command_ptr = kmalloc(sizeof(dmov_box), GFP_KERNEL | __GFP_DMA);
- if (!rx->command_ptr) {
- MSM_HS_ERR("%s(): cannot allocate rx->command_ptr", __func__);
- ret = -ENOMEM;
- goto free_tx_command_ptr_ptr;
- }
-
- rx->command_ptr_ptr = kmalloc(sizeof(u32), GFP_KERNEL | __GFP_DMA);
- if (!rx->command_ptr_ptr) {
- MSM_HS_ERR("%s(): cannot allocate rx->command_ptr_ptr",
- __func__);
- ret = -ENOMEM;
- goto free_rx_command_ptr;
- }
-
- rx->command_ptr->num_rows = ((UARTDM_RX_BUF_SIZE >> 4) << 16) |
- (UARTDM_RX_BUF_SIZE >> 4);
-
- rx->command_ptr->dst_row_addr = rx->rbuffer;
-
- rx->xfer.complete_func = msm_hs_dmov_rx_callback;
-
- rx->command_ptr->cmd = CMD_LC |
- CMD_SRC_CRCI(msm_uport->dma_rx_crci) | CMD_MODE_BOX;
-
- rx->command_ptr->src_dst_len = (MSM_UARTDM_BURST_SIZE << 16)
- | (MSM_UARTDM_BURST_SIZE);
- rx->command_ptr->row_offset = MSM_UARTDM_BURST_SIZE;
- rx->command_ptr->src_row_addr = uport->mapbase + UARTDM_RF_ADDR;
-
- rx->mapped_cmd_ptr = dma_map_single(uport->dev, rx->command_ptr,
- sizeof(dmov_box), DMA_TO_DEVICE);
-
- *rx->command_ptr_ptr = CMD_PTR_LP | DMOV_CMD_ADDR(rx->mapped_cmd_ptr);
-
- rx->cmdptr_dmaaddr = dma_map_single(uport->dev, rx->command_ptr_ptr,
- sizeof(u32), DMA_TO_DEVICE);
- rx->xfer.cmdptr = DMOV_CMD_ADDR(rx->cmdptr_dmaaddr);
-
return ret;
-
-free_rx_command_ptr:
- kfree(rx->command_ptr);
-
-free_tx_command_ptr_ptr:
- kfree(msm_uport->tx.command_ptr_ptr);
- dma_unmap_single(uport->dev, msm_uport->tx.mapped_cmd_ptr_ptr,
- sizeof(u32), DMA_TO_DEVICE);
- dma_unmap_single(uport->dev, msm_uport->tx.mapped_cmd_ptr,
- sizeof(dmov_box), DMA_TO_DEVICE);
-
-free_tx_command_ptr:
- kfree(msm_uport->tx.command_ptr);
-
-free_rx_buffer:
- dma_pool_free(msm_uport->rx.pool, msm_uport->rx.buffer,
- msm_uport->rx.rbuffer);
-
free_pool:
dma_pool_destroy(msm_uport->rx.pool);
-exit_tasket_init:
+exit_tasklet_init:
wake_lock_destroy(&msm_uport->rx.wake_lock);
wake_lock_destroy(&msm_uport->dma_wake_lock);
tasklet_kill(&msm_uport->tx.tlet);
@@ -3076,8 +2604,8 @@
/* Allocate endpoint context */
sps_pipe_handle = sps_alloc_endpoint();
if (!sps_pipe_handle) {
- MSM_HS_ERR("msm_serial_hs: sps_alloc_endpoint() failed!!\n"
- "is_producer=%d", is_producer);
+ MSM_HS_ERR("%s(): sps_alloc_endpoint() failed!!\n"
+ "is_producer=%d", __func__, is_producer);
rc = -ENOMEM;
goto out;
}
@@ -3085,8 +2613,8 @@
/* Get default connection configuration for an endpoint */
rc = sps_get_config(sps_pipe_handle, sps_config);
if (rc) {
- MSM_HS_ERR("msm_serial_hs: sps_get_config() failed!!\n"
- "pipe_handle=0x%x rc=%d", (u32)sps_pipe_handle, rc);
+ MSM_HS_ERR("%s(): failed! pipe_handle=0x%p rc=%d",
+ __func__, sps_pipe_handle, rc);
goto get_config_err;
}
@@ -3138,10 +2666,10 @@
/* Now save the sps pipe handle */
ep->pipe_handle = sps_pipe_handle;
- MSM_HS_DBG("msm_serial_hs: success !! %s: pipe_handle=0x%x\n"
- "desc_fifo.phys_base=0x%llx\n",
+ MSM_HS_DBG("msm_serial_hs: success !! %s: pipe_handle=0x%p\n"
+ "desc_fifo.phys_base=0x%pa\n",
is_producer ? "READ" : "WRITE",
- (u32) sps_pipe_handle, (u64) sps_config->desc.phys_base);
+ sps_pipe_handle, &sps_config->desc.phys_base);
return 0;
get_config_err:
@@ -3182,10 +2710,10 @@
bam.irq = (u32)msm_uport->bam_irq;
bam.manage = SPS_BAM_MGR_DEVICE_REMOTE;
- MSM_HS_DBG("msm_serial_hs: bam physical base=0x%x\n",
- (u32)bam.phys_addr);
- MSM_HS_DBG("msm_serial_hs: bam virtual base=0x%x\n",
- (u32)bam.virt_addr);
+ MSM_HS_DBG("msm_serial_hs: bam physical base=0x%pa\n",
+ &bam.phys_addr);
+ MSM_HS_DBG("msm_serial_hs: bam virtual base=0x%p\n",
+ bam.virt_addr);
/* Register UART Peripheral BAM device to SPS driver */
rc = sps_register_bam_device(&bam, &bam_handle);
@@ -3265,10 +2793,8 @@
struct msm_hs_port *msm_uport;
struct resource *core_resource;
struct resource *bam_resource;
- struct resource *resource;
int core_irqres, bam_irqres, wakeup_irqres;
struct msm_serial_hs_platform_data *pdata = pdev->dev.platform_data;
- const struct of_device_id *match;
unsigned long data;
if (pdev->dev.of_node) {
@@ -3306,96 +2832,71 @@
uport = &msm_uport->uport;
uport->dev = &pdev->dev;
- match = of_match_device(msm_hs_match_table, &pdev->dev);
- if (match)
- msm_uport->reg_ptr = (unsigned int *)match->data;
- else if (is_gsbi_uart(msm_uport))
- msm_uport->reg_ptr = regmap_nonblsp;
-
if (pdev->dev.of_node)
msm_uport->uart_type = BLSP_HSUART;
/* Get required resources for BAM HSUART */
- if (is_blsp_uart(msm_uport)) {
- core_resource = platform_get_resource_byname(pdev,
- IORESOURCE_MEM, "core_mem");
- if (!core_resource) {
- MSM_HS_ERR("Invalid core HSUART Resources.\n");
- return -ENXIO;
- }
- bam_resource = platform_get_resource_byname(pdev,
- IORESOURCE_MEM, "bam_mem");
- if (!bam_resource) {
- MSM_HS_ERR("Invalid BAM HSUART Resources.\n");
- return -ENXIO;
- }
- core_irqres = platform_get_irq_byname(pdev, "core_irq");
- if (core_irqres < 0) {
- MSM_HS_ERR("Invalid core irqres Resources.\n");
- return -ENXIO;
- }
- bam_irqres = platform_get_irq_byname(pdev, "bam_irq");
- if (bam_irqres < 0) {
- MSM_HS_ERR("Invalid bam irqres Resources.\n");
- return -ENXIO;
- }
- wakeup_irqres = platform_get_irq_byname(pdev, "wakeup_irq");
- if (wakeup_irqres < 0) {
- wakeup_irqres = -1;
- MSM_HS_DBG("Wakeup irq not specified.\n");
- }
+ core_resource = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM, "core_mem");
+ if (!core_resource) {
+ MSM_HS_ERR("Invalid core HSUART Resources.\n");
+ return -ENXIO;
+ }
+ bam_resource = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM, "bam_mem");
+ if (!bam_resource) {
+ MSM_HS_ERR("Invalid BAM HSUART Resources.\n");
+ return -ENXIO;
+ }
+ core_irqres = platform_get_irq_byname(pdev, "core_irq");
+ if (core_irqres < 0) {
+ MSM_HS_ERR("Invalid core irqres Resources.\n");
+ return -ENXIO;
+ }
+ bam_irqres = platform_get_irq_byname(pdev, "bam_irq");
+ if (bam_irqres < 0) {
+ MSM_HS_ERR("Invalid bam irqres Resources.\n");
+ return -ENXIO;
+ }
+ wakeup_irqres = platform_get_irq_byname(pdev, "wakeup_irq");
+ if (wakeup_irqres < 0) {
+ wakeup_irqres = -1;
+ MSM_HS_DBG("Wakeup irq not specified.\n");
+ }
- uport->mapbase = core_resource->start;
+ uport->mapbase = core_resource->start;
- uport->membase = ioremap(uport->mapbase,
- resource_size(core_resource));
- if (unlikely(!uport->membase)) {
- MSM_HS_ERR("UART Resource ioremap Failed.\n");
- return -ENOMEM;
- }
- msm_uport->bam_mem = bam_resource->start;
- msm_uport->bam_base = ioremap(msm_uport->bam_mem,
- resource_size(bam_resource));
- if (unlikely(!msm_uport->bam_base)) {
- MSM_HS_ERR("UART BAM Resource ioremap Failed.\n");
- iounmap(uport->membase);
- return -ENOMEM;
- }
+ uport->membase = ioremap(uport->mapbase,
+ resource_size(core_resource));
+ if (unlikely(!uport->membase)) {
+ MSM_HS_ERR("UART Resource ioremap Failed.\n");
+ return -ENOMEM;
+ }
+ msm_uport->bam_mem = bam_resource->start;
+ msm_uport->bam_base = ioremap(msm_uport->bam_mem,
+ resource_size(bam_resource));
+ if (unlikely(!msm_uport->bam_base)) {
+ MSM_HS_ERR("UART BAM Resource ioremap Failed.\n");
+ iounmap(uport->membase);
+ return -ENOMEM;
+ }
- uport->irq = core_irqres;
- msm_uport->bam_irq = bam_irqres;
- pdata->wakeup_irq = wakeup_irqres;
+ uport->irq = core_irqres;
+ msm_uport->bam_irq = bam_irqres;
+ pdata->wakeup_irq = wakeup_irqres;
- msm_uport->bus_scale_table = msm_bus_cl_get_pdata(pdev);
- if (!msm_uport->bus_scale_table) {
- MSM_HS_ERR("BLSP UART: Bus scaling is disabled.\n");
- } else {
- msm_uport->bus_perf_client =
- msm_bus_scale_register_client
- (msm_uport->bus_scale_table);
- if (IS_ERR(&msm_uport->bus_perf_client)) {
- MSM_HS_ERR("%s(): Bus client register failed.\n",
- __func__);
- ret = -EINVAL;
- goto unmap_memory;
- }
- }
+ msm_uport->bus_scale_table = msm_bus_cl_get_pdata(pdev);
+ if (!msm_uport->bus_scale_table) {
+ MSM_HS_ERR("BLSP UART: Bus scaling is disabled.\n");
} else {
-
- resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (unlikely(!resource))
- return -ENXIO;
- uport->mapbase = resource->start;
- uport->membase = ioremap(uport->mapbase,
- resource_size(resource));
- if (unlikely(!uport->membase))
- return -ENOMEM;
-
- uport->irq = platform_get_irq(pdev, 0);
- if (unlikely((int)uport->irq < 0)) {
- MSM_HS_ERR("UART IRQ Failed.\n");
- iounmap(uport->membase);
- return -ENXIO;
+ msm_uport->bus_perf_client =
+ msm_bus_scale_register_client
+ (msm_uport->bus_scale_table);
+ if (IS_ERR(&msm_uport->bus_perf_client)) {
+ MSM_HS_ERR("%s():Bus client register failed\n",
+ __func__);
+ ret = -EINVAL;
+ goto unmap_memory;
}
}
@@ -3407,35 +2908,10 @@
msm_uport->wakeup.inject_rx = pdata->inject_rx_on_wakeup;
msm_uport->wakeup.rx_to_inject = pdata->rx_to_inject;
- if (is_blsp_uart(msm_uport)) {
- msm_uport->bam_tx_ep_pipe_index =
- pdata->bam_tx_ep_pipe_index;
- msm_uport->bam_rx_ep_pipe_index =
- pdata->bam_rx_ep_pipe_index;
- }
- }
-
- if (!is_blsp_uart(msm_uport)) {
-
- resource = platform_get_resource_byname(pdev,
- IORESOURCE_DMA, "uartdm_channels");
- if (unlikely(!resource)) {
- ret = -ENXIO;
- goto deregister_bus_client;
- }
-
- msm_uport->dma_tx_channel = resource->start;
- msm_uport->dma_rx_channel = resource->end;
-
- resource = platform_get_resource_byname(pdev,
- IORESOURCE_DMA, "uartdm_crci");
- if (unlikely(!resource)) {
- ret = -ENXIO;
- goto deregister_bus_client;
- }
-
- msm_uport->dma_tx_crci = resource->start;
- msm_uport->dma_rx_crci = resource->end;
+ msm_uport->bam_tx_ep_pipe_index =
+ pdata->bam_tx_ep_pipe_index;
+ msm_uport->bam_rx_ep_pipe_index =
+ pdata->bam_rx_ep_pipe_index;
}
uport->iotype = UPIO_MEM;
@@ -3484,12 +2960,10 @@
/* Initialize SPS HW connected with UART core */
- if (is_blsp_uart(msm_uport)) {
- ret = msm_hs_sps_init(msm_uport);
- if (unlikely(ret)) {
- MSM_HS_ERR("SPS Initialization failed ! err=%d", ret);
- goto destroy_mutex;
- }
+ ret = msm_hs_sps_init(msm_uport);
+ if (unlikely(ret)) {
+ MSM_HS_ERR("SPS Initialization failed ! err=%d", ret);
+ goto destroy_mutex;
}
msm_hs_clock_vote(msm_uport);
@@ -3556,12 +3030,10 @@
clk_put(msm_uport->clk);
deregister_bus_client:
- if (is_blsp_uart(msm_uport))
- msm_bus_scale_unregister_client(msm_uport->bus_perf_client);
+ msm_bus_scale_unregister_client(msm_uport->bus_perf_client);
unmap_memory:
iounmap(uport->membase);
- if (is_blsp_uart(msm_uport))
- iounmap(msm_uport->bam_base);
+ iounmap(msm_uport->bam_base);
return ret;
}
@@ -3604,45 +3076,17 @@
static void msm_hs_shutdown(struct uart_port *uport)
{
int ret;
- unsigned int data;
- unsigned long flags;
struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport);
- struct platform_device *pdev = to_platform_device(uport->dev);
- const struct msm_serial_hs_platform_data *pdata =
- pdev->dev.platform_data;
struct msm_hs_tx *tx = &msm_uport->tx;
struct sps_pipe *sps_pipe_handle = tx->cons.pipe_handle;
msm_hs_clock_vote(msm_uport);
if (msm_uport->tx.dma_in_flight) {
- if (!is_blsp_uart(msm_uport)) {
- spin_lock_irqsave(&uport->lock, flags);
- /* disable UART TX interface to DM */
- data = msm_hs_read(uport, UART_DM_DMEN);
- data &= ~UARTDM_TX_DM_EN_BMSK;
- msm_hs_write(uport, UART_DM_DMEN, data);
- /* turn OFF UART Transmitter */
- msm_hs_write(uport, UART_DM_CR,
- UARTDM_CR_TX_DISABLE_BMSK);
- /* reset UART TX */
- msm_hs_write(uport, UART_DM_CR, RESET_TX);
- /* reset UART TX Error */
- msm_hs_write(uport, UART_DM_CR, RESET_TX_ERROR);
- msm_uport->tx.flush = FLUSH_STOP;
- spin_unlock_irqrestore(&uport->lock, flags);
- /* discard flush */
- msm_dmov_flush(msm_uport->dma_tx_channel, 0);
- ret = wait_event_timeout(msm_uport->tx.wait,
- msm_uport->tx.flush == FLUSH_SHUTDOWN, 100);
- if (!ret)
- MSM_HS_ERR("%s():HSUART TX Stalls.\n", __func__);
- } else {
- /* BAM Disconnect for TX */
- ret = sps_disconnect(sps_pipe_handle);
- if (ret)
- MSM_HS_ERR("%s(): sps_disconnect failed\n",
- __func__);
- }
+ /* BAM Disconnect for TX */
+ ret = sps_disconnect(sps_pipe_handle);
+ if (ret)
+ MSM_HS_ERR("%s(): sps_disconnect failed\n",
+ __func__);
}
tasklet_kill(&msm_uport->tx.tlet);
BUG_ON(msm_uport->rx.flush < FLUSH_STOP);
@@ -3684,13 +3128,7 @@
if (use_low_power_wakeup(msm_uport))
free_irq(msm_uport->wakeup.irq, msm_uport);
- if (is_blsp_uart(msm_uport)) {
- msm_hs_unconfig_uart_gpios(uport);
- } else {
- if (pdata && pdata->gpio_config)
- if (pdata->gpio_config(0))
- dev_err(uport->dev, "GPIO config error\n");
- }
+ msm_hs_unconfig_uart_gpios(uport);
}
static void __exit msm_serial_hs_exit(void)
@@ -3776,8 +3214,6 @@
.set_termios = msm_hs_set_termios,
.type = msm_hs_type,
.config_port = msm_hs_config_port,
- .release_port = msm_hs_release_port,
- .request_port = msm_hs_request_port,
.flush_buffer = NULL,
.ioctl = msm_hs_ioctl,
};
diff --git a/drivers/tty/serial/msm_serial_hs_hwreg.h b/drivers/tty/serial/msm_serial_hs_hwreg.h
index 064bbda..47f9dca 100644
--- a/drivers/tty/serial/msm_serial_hs_hwreg.h
+++ b/drivers/tty/serial/msm_serial_hs_hwreg.h
@@ -1,6 +1,6 @@
/* drivers/serial/msm_serial_hs_hwreg.h
*
- * Copyright (c) 2007-2009, 2012-2013,The Linux Foundation. All rights reserved.
+ * Copyright (c) 2007-2009, 2012-2014,The Linux Foundation. All rights reserved.
*
* All source code in this file is licensed under the following license
* except where indicated.
@@ -61,28 +61,27 @@
};
enum msm_hs_regs {
- UART_DM_MR1,
- UART_DM_MR2,
- UART_DM_IMR,
- UART_DM_SR,
- UART_DM_CR,
- UART_DM_CSR,
- UART_DM_IPR,
- UART_DM_ISR,
- UART_DM_RX_TOTAL_SNAP,
- UART_DM_RFWR,
- UART_DM_TFWR,
- UART_DM_RF,
- UART_DM_TF,
- UART_DM_MISR,
- UART_DM_DMRX,
- UART_DM_NCF_TX,
- UART_DM_DMEN,
- UART_DM_TXFS,
- UART_DM_RXFS,
- UART_DM_RX_TRANS_CTRL,
- UART_DM_BCR,
- UART_DM_LAST,
+ UART_DM_MR1 = 0x0,
+ UART_DM_MR2 = 0x4,
+ UART_DM_IMR = 0xb0,
+ UART_DM_SR = 0xa4,
+ UART_DM_CR = 0xa8,
+ UART_DM_CSR = 0xa0,
+ UART_DM_IPR = 0x18,
+ UART_DM_ISR = 0xb4,
+ UART_DM_RX_TOTAL_SNAP = 0xbc,
+ UART_DM_TFWR = 0x1c,
+ UART_DM_RFWR = 0x20,
+ UART_DM_RF = 0x140,
+ UART_DM_TF = 0x100,
+ UART_DM_MISR = 0xac,
+ UART_DM_DMRX = 0x34,
+ UART_DM_NCF_TX = 0x40,
+ UART_DM_DMEN = 0x3c,
+ UART_DM_TXFS = 0x4c,
+ UART_DM_RXFS = 0x50,
+ UART_DM_RX_TRANS_CTRL = 0xcc,
+ UART_DM_BCR = 0xc8,
};
#define UARTDM_MR1_ADDR 0x0