| commit | fcb45611448098a36b893bda71e72bd39730a3dd | [log] [tgz] |
|---|---|---|
| author | Zhao Yakui <yakui.zhao@intel.com> | Wed Oct 14 09:11:25 2009 +0800 |
| committer | Dave Airlie <airlied@redhat.com> | Wed Oct 28 11:23:39 2009 +1000 |
| tree | 3e5c025495f058408fa4f7a72854d2b6cba8587a | |
| parent | 93239ea158368016a017200cb133e1057fb3ef89 [diff] |
drm: Add the basic check for the detailed timing in EDID Sometimes we will get the incorrect display modeline when parsing the detailed timing in EDID. For example: >hsync/vsync width is zero >sync is beyond the blank. So add the basic check for the detailed timing in EDID to avoid the incorrect display modeline. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>