msm: pm: save registers to noncached area before pc
The power collapse path is simplified if a noncached area is
used for the purpose of saving register state prior to power
collapsing. This is especially beneficial in the case of targets
with an outer cache, where the process of cleaning the register
state would require complex operations.
Change-Id: I9edac28e4091548e2843fc87c89e3451df2b6ae9
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>
diff --git a/arch/arm/mach-msm/pm2.c b/arch/arm/mach-msm/pm2.c
index 7903eab..58f2075 100644
--- a/arch/arm/mach-msm/pm2.c
+++ b/arch/arm/mach-msm/pm2.c
@@ -1879,6 +1879,17 @@
pmd[0] = __pmd(pmdval);
pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
+ msm_saved_state_phys =
+ allocate_contiguous_ebi_nomap(CPU_SAVED_STATE_SIZE *
+ num_possible_cpus(), 4);
+ if (!msm_saved_state_phys)
+ return -ENOMEM;
+ msm_saved_state = ioremap_nocache(msm_saved_state_phys,
+ CPU_SAVED_STATE_SIZE *
+ num_possible_cpus());
+ if (!msm_saved_state)
+ return -ENOMEM;
+
/* It is remotely possible that the code in msm_pm_collapse_exit()
* which turns on the MMU with this mapping is in the
* next even-numbered megabyte beyond the