tree 1f819fd0655b0ea0193dddce41221d248df49524
parent 9d82ef7e5c34ed84d4fd9e977bc8f2b8f94572a7
author Xiaoming Zhou <zhoux@codeaurora.org> 1363827278 -0400
committer Xiaoming Zhou <zhoux@codeaurora.org> 1367003829 -0400

msm: clock-8610: add display DSI clock PLL configuration

Configure the DSI PLL VCO clock, bitclk, dsi clk, and byte clk.

Change-Id: Ibe4fe1ae1c8ae79951a1b1678d5e84185fc61bb4
Signed-off-by: Xiaoming Zhou <zhoux@codeaurora.org>