msm: clock-8974: Add initial DSI PLL support
The display clocks require the display driver to configure a PHY PLL.
Add support for calling into the PLL configuration code and link this
into the clock ops for the DSI pixel and byte clocks.
The RCG clock type is re-used here for the pixel and byte clocks; the
interaction between the DSI PLL code and these clocks can fit into
the existing RCG ops. As the design matures, this decision may change
in the future.
Change-Id: I9bfbec5a2b3f7bbc8b74c4a8199068e6a2e478c6
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
2 files changed