Merge "ASoC: wcd9xxx: Add device tree support in codec for I2C"
diff --git a/Documentation/devicetree/bindings/slimbus/slim-msm-ctrl.txt b/Documentation/devicetree/bindings/slimbus/slim-msm-ctrl.txt
index ecac09d..6b090fa 100644
--- a/Documentation/devicetree/bindings/slimbus/slim-msm-ctrl.txt
+++ b/Documentation/devicetree/bindings/slimbus/slim-msm-ctrl.txt
@@ -1,4 +1,19 @@
Qualcomm SLIMBUS controller
+Qualcomm implements 2 type of slimbus controllers:
+1. "qcom,slim-msm": This controller is used if applications processor
+ driver is controlling slimbus master component. This driver is
+ responsible for communicating with slave HW directly using
+ messaging interface, and doing data channel management. Driver
+ also communicates with satellite component (driver implemented
+ by other execution environment, such as ADSP) to get its
+ requirements for data channel and bandwidth requirements.
+2. "qcom,slim-ngd": This controller is used if applications processor
+ driver is controlling slimbus satellite component (also known as
+ Non-ported Generic Device, or NGD). This is light-weight slimbus
+ controller responsible for communicating with slave HW directly
+ over bus messaging interface, and communicating with master component
+ (driver residing on other execution environment, such as ADSP)
+ for bandwidth and data channel management.
Required properties:
@@ -8,7 +23,8 @@
"slimbus_physical": Physical adderss of controller register blocks
"slimbus_bam_physical": Physical address of Bus Access Module (BAM)
for this controller
- - compatible : should be "qcom,slim-msm"
+ - compatible : should be "qcom,slim-msm" if this is master component driver
+ - compatible : should be "qcom,slim-ngd" if this is satellite component driver
- cell-index : SLIMBUS number used for this controller
- interrupts : Interrupt numbers used by this controller
- interrupt-names : Required interrupt resource entries are:
diff --git a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
index 2c74415..1e647a7 100644
--- a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
+++ b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
@@ -425,4 +425,52 @@
qcom,msm-mi2s-rx-lines = <2>;
qcom,msm-mi2s-tx-lines = <1>;
};
-};
\ No newline at end of file
+};
+
+* MSM9625 ASoC Machine driver
+
+Required properties:
+- compatible : "qcom,mdm9625-audio-taiko"
+- qcom,model : The user-visible name of this sound card.
+- qcom,audio-routing : A list of the connections between audio components.
+ Each entry is a pair of strings, the first being the connection's sink,
+ the second being the connection's source.
+- qcom,taiko-mclk-clk-freq : Master clock value given to codec. Some WCD9XXX
+ codec can run at different mclk values. Mclk value can be 9.6MHz or 12.288MHz.
+ This element represents the value for MCLK provided to codec.
+
+Example:
+
+sound {
+ compatible = "qcom,mdm9625-audio-taiko";
+ qcom,model = "mdm9625-taiko-i2s-snd-card";
+
+ qcom,audio-routing =
+ "RX_BIAS", "MCLK",
+ "LDO_H", "MCLK",
+ "Ext Spk Bottom Pos", "LINEOUT1",
+ "Ext Spk Bottom Neg", "LINEOUT3",
+ "Ext Spk Top Pos", "LINEOUT2",
+ "Ext Spk Top Neg", "LINEOUT4",
+ "AMIC1", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Handset Mic",
+ "AMIC2", "MIC BIAS2 External",
+ "MIC BIAS2 External", "Headset Mic",
+ "AMIC3", "MIC BIAS3 Internal1",
+ "MIC BIAS3 Internal1", "ANCRight Headset Mic",
+ "AMIC4", "MIC BIAS1 Internal2",
+ "MIC BIAS1 Internal2", "ANCLeft Headset Mic",
+ "DMIC1", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic1",
+ "DMIC2", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic2",
+ "DMIC3", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic3",
+ "DMIC4", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic4",
+ "DMIC5", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic5",
+ "DMIC6", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic6";
+ qcom,taiko-mclk-clk-freq = <12288000>;
+};
diff --git a/arch/arm/boot/dts/msm-pm8941.dtsi b/arch/arm/boot/dts/msm-pm8941.dtsi
index bf1c971..89d4df8 100644
--- a/arch/arm/boot/dts/msm-pm8941.dtsi
+++ b/arch/arm/boot/dts/msm-pm8941.dtsi
@@ -58,10 +58,10 @@
};
};
- bms@4000 {
+ pm8941_bms: bms@4000 {
#address-cells = <1>;
#size-cells = <1>;
-
+ status = "disabled";
compatible = "qcom,qpnp-bms";
reg = <0x4000 0x100>;
diff --git a/arch/arm/boot/dts/msm8226.dtsi b/arch/arm/boot/dts/msm8226.dtsi
index f0e950a..09b57a4 100644
--- a/arch/arm/boot/dts/msm8226.dtsi
+++ b/arch/arm/boot/dts/msm8226.dtsi
@@ -73,6 +73,15 @@
compatible = "qcom,android-usb";
};
+ qcom,wdt@f9017000 {
+ compatible = "qcom,msm-watchdog";
+ reg = <0xf9017000 0x1000>;
+ interrupts = <0 3 0>, <0 4 0>;
+ qcom,bark-time = <11000>;
+ qcom,pet-time = <10000>;
+ qcom,ipi-ping = <1>;
+ };
+
};
/include/ "msm8226-regulator.dtsi"
diff --git a/arch/arm/boot/dts/msm8974-mtp.dtsi b/arch/arm/boot/dts/msm8974-mtp.dtsi
index e2c80c2..80d2440 100644
--- a/arch/arm/boot/dts/msm8974-mtp.dtsi
+++ b/arch/arm/boot/dts/msm8974-mtp.dtsi
@@ -213,6 +213,10 @@
qcom,otg-capability;
};
+&pm8941_bms {
+ status = "ok";
+};
+
&pm8941_chg {
status = "ok";
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index 20249be..93ba2bf 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -299,14 +299,12 @@
slim_msm: slim@fe12f000 {
cell-index = <1>;
- compatible = "qcom,slim-msm";
+ compatible = "qcom,slim-ngd";
reg = <0xfe12f000 0x35000>,
<0xfe104000 0x20000>;
reg-names = "slimbus_physical", "slimbus_bam_physical";
interrupts = <0 163 0 0 164 0>;
interrupt-names = "slimbus_irq", "slimbus_bam_irq";
- qcom,min-clk-gear = <10>;
- qcom,rxreg-access;
taiko_codec {
compatible = "qcom,taiko-slim-pgd";
diff --git a/arch/arm/boot/dts/msm9625-cdp.dts b/arch/arm/boot/dts/msm9625-cdp.dts
index ba5bbcf..232fba7 100644
--- a/arch/arm/boot/dts/msm9625-cdp.dts
+++ b/arch/arm/boot/dts/msm9625-cdp.dts
@@ -37,6 +37,14 @@
summit,temperature-max = <3>; /* 45 C */
};
};
+
+ wlan0: qca,wlan {
+ cell-index = <0>;
+ compatible = "qca,ar6004-sdio";
+ qca,chip-pwd-l-gpios = <&msmgpio 62 0>;
+ qca,pm-enable-gpios = <&pm8019_gpios 3 0x0>;
+ qca,ar6004-vdd-io-supply = <&pm8019_l11>;
+ };
};
/* PM8019 GPIO and MPP configuration */
diff --git a/arch/arm/boot/dts/msm9625-mtp.dts b/arch/arm/boot/dts/msm9625-mtp.dts
index 7780686..faf86d4 100644
--- a/arch/arm/boot/dts/msm9625-mtp.dts
+++ b/arch/arm/boot/dts/msm9625-mtp.dts
@@ -37,6 +37,14 @@
summit,temperature-max = <3>; /* 45 C */
};
};
+
+ wlan0: qca,wlan {
+ cell-index = <0>;
+ compatible = "qca,ar6004-sdio";
+ qca,chip-pwd-l-gpios = <&msmgpio 62 0>;
+ qca,pm-enable-gpios = <&pm8019_gpios 3 0x0>;
+ qca,ar6004-vdd-io-supply = <&pm8019_l11>;
+ };
};
/* PM8019 GPIO and MPP configuration */
diff --git a/arch/arm/boot/dts/msm9625.dtsi b/arch/arm/boot/dts/msm9625.dtsi
index a4bec1b..b79f370 100644
--- a/arch/arm/boot/dts/msm9625.dtsi
+++ b/arch/arm/boot/dts/msm9625.dtsi
@@ -274,7 +274,172 @@
compatible = "qcom,msm-rng";
reg = <0xf9bff000 0x200>;
qcom,msm-rng-iface-clk;
- };
+ };
+
+ wcd9xxx_intc: wcd9xxx-irq {
+ compatible = "qcom,wcd9xxx-irq";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <20 0>;
+ interrupt-names = "cdc-int";
+ };
+
+ i2c@f9925000 {
+ cell-index = <3>;
+ compatible = "qcom,i2c-qup";
+ reg = <0xf9925000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "qup_phys_addr";
+ interrupts = <0 97 0>;
+ interrupt-names = "qup_err_intr";
+ qcom,i2c-bus-freq = <100000>;
+ qcom,i2c-src-freq = <24000000>;
+
+ wcd9xxx_codec@0d{
+ compatible = "qcom,wcd9xxx-i2c";
+ reg = <0x0d>;
+ qcom,cdc-reset-gpio = <&msmgpio 22 0>;
+ interrupt-parent = <&wcd9xxx_intc>;
+ interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28>;
+ cdc-vdd-buck-supply = <&pm8019_l11>;
+ qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-buck-current = <25000>;
+
+ cdc-vdd-tx-h-supply = <&pm8019_l11>;
+ qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-tx-h-current = <25000>;
+
+ cdc-vdd-rx-h-supply = <&pm8019_l11>;
+ qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-rx-h-current = <25000>;
+
+ cdc-vddpx-1-supply = <&pm8019_l11>;
+ qcom,cdc-vddpx-1-voltage = <1800000 1800000>;
+ qcom,cdc-vddpx-1-current = <10000>;
+
+ cdc-vdd-a-1p2v-supply = <&pm8019_l9>;
+ qcom,cdc-vdd-a-1p2v-voltage = <1200000 1200000>;
+ qcom,cdc-vdd-a-1p2v-current = <10000>;
+
+ cdc-vddcx-1-supply = <&pm8019_l9>;
+ qcom,cdc-vddcx-1-voltage = <1200000 1200000>;
+ qcom,cdc-vddcx-1-current = <10000>;
+
+ cdc-vddcx-2-supply = <&pm8019_l9>;
+ qcom,cdc-vddcx-2-voltage = <1200000 1200000>;
+ qcom,cdc-vddcx-2-current = <10000>;
+
+ qcom,cdc-micbias-ldoh-v = <0x3>;
+ qcom,cdc-micbias-cfilt1-mv = <1800>;
+ qcom,cdc-micbias-cfilt2-mv = <2700>;
+ qcom,cdc-micbias-cfilt3-mv = <1800>;
+ qcom,cdc-micbias1-cfilt-sel = <0x0>;
+ qcom,cdc-micbias2-cfilt-sel = <0x1>;
+ qcom,cdc-micbias3-cfilt-sel = <0x2>;
+ qcom,cdc-micbias4-cfilt-sel = <0x2>;
+ };
+
+ wcd9xxx_codec@77{
+ compatible = "qcom,wcd9xxx-i2c";
+ reg = <0x77>;
+ };
+
+ wcd9xxx_codec@66{
+ compatible = "qcom,wcd9xxx-i2c";
+ reg = <0x66>;
+ };
+
+ wcd9xxx_codec@55{
+ compatible = "qcom,wcd9xxx-i2c";
+ reg = <0x55>;
+ };
+ };
+
+ sound {
+ compatible = "qcom,mdm9625-audio-taiko";
+ qcom,model = "mdm9625-taiko-i2s-snd-card";
+
+ qcom,audio-routing =
+ "RX_BIAS", "MCLK",
+ "LDO_H", "MCLK",
+ "Ext Spk Bottom Pos", "LINEOUT1",
+ "Ext Spk Bottom Neg", "LINEOUT3",
+ "Ext Spk Top Pos", "LINEOUT2",
+ "Ext Spk Top Neg", "LINEOUT4",
+ "AMIC1", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Handset Mic",
+ "AMIC2", "MIC BIAS2 External",
+ "MIC BIAS2 External", "Headset Mic",
+ "AMIC3", "MIC BIAS3 Internal1",
+ "MIC BIAS3 Internal1", "ANCRight Headset Mic",
+ "AMIC4", "MIC BIAS1 Internal2",
+ "MIC BIAS1 Internal2", "ANCLeft Headset Mic",
+ "DMIC1", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic1",
+ "DMIC2", "MIC BIAS1 External",
+ "MIC BIAS1 External", "Digital Mic2",
+ "DMIC3", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic3",
+ "DMIC4", "MIC BIAS3 External",
+ "MIC BIAS3 External", "Digital Mic4",
+ "DMIC5", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic5",
+ "DMIC6", "MIC BIAS4 External",
+ "MIC BIAS4 External", "Digital Mic6";
+ qcom,taiko-mclk-clk-freq = <12288000>;
+ };
+
+ qcom,msm-adsp-loader {
+ compatible = "qcom,adsp-loader";
+ };
+
+ qcom,msm-pcm {
+ compatible = "qcom,msm-pcm-dsp";
+ };
+
+ qcom,msm-pcm-routing {
+ compatible = "qcom,msm-pcm-routing";
+ };
+
+ qcom,msm-compr-dsp {
+ compatible = "qcom,msm-compr-dsp";
+ };
+
+ qcom,msm-voip-dsp {
+ compatible = "qcom,msm-voip-dsp";
+ };
+
+ qcom,msm-pcm-voice {
+ compatible = "qcom,msm-pcm-voice";
+ };
+
+ qcom,msm-dai-fe {
+ compatible = "qcom,msm-dai-fe";
+ };
+
+ qcom,msm-pcm-afe {
+ compatible = "qcom,msm-pcm-afe";
+ };
+
+ qcom,msm-pcm-hostless {
+ compatible = "qcom,msm-pcm-hostless";
+ };
+
+ qcom,msm-dai-mi2s {
+ compatible = "qcom,msm-dai-mi2s";
+ qcom,msm-dai-q6-mi2s-prim {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <0>;
+ qcom,msm-mi2s-rx-lines = <2>;
+ qcom,msm-mi2s-tx-lines = <1>;
+ };
+ };
+
+ qcom,msm-dai-q6 {
+ compatible = "qcom,msm-dai-q6";
+ };
};
/include/ "msm-pm8019-rpm-regulator.dtsi"
diff --git a/arch/arm/configs/msm8910_defconfig b/arch/arm/configs/msm8910_defconfig
index 5876a0f..e2e05b2 100644
--- a/arch/arm/configs/msm8910_defconfig
+++ b/arch/arm/configs/msm8910_defconfig
@@ -40,8 +40,10 @@
# CONFIG_MSM_FIQ_SUPPORT is not set
# CONFIG_MSM_PROC_COMM is not set
CONFIG_MSM_SMD=y
+CONFIG_MSM_SMD_PKG4=y
# CONFIG_MSM_HW3D is not set
CONFIG_MSM_DIRECT_SCLK_ACCESS=y
+CONFIG_MSM_WATCHDOG_V2=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
# CONFIG_SMP_ON_UP is not set
diff --git a/arch/arm/configs/msm8974-perf_defconfig b/arch/arm/configs/msm8974-perf_defconfig
index 5e1fa4a..0070e22 100644
--- a/arch/arm/configs/msm8974-perf_defconfig
+++ b/arch/arm/configs/msm8974-perf_defconfig
@@ -264,7 +264,7 @@
CONFIG_SPMI=y
CONFIG_SPMI_MSM_PMIC_ARB=y
CONFIG_MSM_QPNP_INT=y
-CONFIG_SLIMBUS_MSM_CTRL=y
+CONFIG_SLIMBUS_MSM_NGD=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_QPNP_PIN=y
diff --git a/arch/arm/configs/msm8974_defconfig b/arch/arm/configs/msm8974_defconfig
index 4d68a72..33400ea 100644
--- a/arch/arm/configs/msm8974_defconfig
+++ b/arch/arm/configs/msm8974_defconfig
@@ -266,7 +266,7 @@
CONFIG_SPMI=y
CONFIG_SPMI_MSM_PMIC_ARB=y
CONFIG_MSM_QPNP_INT=y
-CONFIG_SLIMBUS_MSM_CTRL=y
+CONFIG_SLIMBUS_MSM_NGD=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_QPNP_PIN=y
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 8690df8..88e5ce2 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -298,7 +298,7 @@
obj-$(CONFIG_ARCH_MSM8974) += krait-regulator.o
obj-$(CONFIG_ARCH_MSM9625) += board-9625.o board-9625-gpiomux.o
obj-$(CONFIG_ARCH_MSM9625) += clock-local2.o clock-pll.o clock-9625.o clock-rpm.o clock-voter.o acpuclock-9625.o
-obj-$(CONFIG_ARCH_MSM8930) += acpuclock-8930.o acpuclock-8627.o acpuclock-8930aa.o
+obj-$(CONFIG_ARCH_MSM8930) += acpuclock-8930.o acpuclock-8627.o acpuclock-8930aa.o acpuclock-8930ab.o
obj-$(CONFIG_ARCH_MPQ8092) += board-8092.o board-8092-gpiomux.o
obj-$(CONFIG_ARCH_MSM8226) += board-8226.o board-8226-gpiomux.o
obj-$(CONFIG_ARCH_MSM8910) += board-8910.o board-8910-gpiomux.o
diff --git a/arch/arm/mach-msm/acpuclock-8930ab.c b/arch/arm/mach-msm/acpuclock-8930ab.c
new file mode 100644
index 0000000..764ae41
--- /dev/null
+++ b/arch/arm/mach-msm/acpuclock-8930ab.c
@@ -0,0 +1,284 @@
+/*
+ * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <mach/rpm-regulator.h>
+#include <mach/msm_bus_board.h>
+#include <mach/msm_bus.h>
+
+#include "acpuclock.h"
+#include "acpuclock-krait.h"
+
+/* Corner type vreg VDD values */
+#define LVL_NONE RPM_VREG_CORNER_NONE
+#define LVL_LOW RPM_VREG_CORNER_LOW
+#define LVL_NOM RPM_VREG_CORNER_NOMINAL
+#define LVL_HIGH RPM_VREG_CORNER_HIGH
+
+static struct hfpll_data hfpll_data __initdata = {
+ .mode_offset = 0x00,
+ .l_offset = 0x08,
+ .m_offset = 0x0C,
+ .n_offset = 0x10,
+ .config_offset = 0x04,
+ .config_val = 0x7845C665,
+ .has_droop_ctl = true,
+ .droop_offset = 0x14,
+ .droop_val = 0x0108C000,
+ .low_vdd_l_max = 37,
+ .nom_vdd_l_max = 74,
+ .vdd[HFPLL_VDD_NONE] = LVL_NONE,
+ .vdd[HFPLL_VDD_LOW] = LVL_LOW,
+ .vdd[HFPLL_VDD_NOM] = LVL_NOM,
+ .vdd[HFPLL_VDD_HIGH] = LVL_HIGH,
+};
+
+static struct scalable scalable_pm8917[] __initdata = {
+ [CPU0] = {
+ .hfpll_phys_base = 0x00903200,
+ .aux_clk_sel_phys = 0x02088014,
+ .aux_clk_sel = 3,
+ .sec_clk_sel = 2,
+ .l2cpmr_iaddr = 0x4501,
+ .vreg[VREG_CORE] = { "krait0", 1300000 },
+ .vreg[VREG_MEM] = { "krait0_mem", 1150000 },
+ .vreg[VREG_DIG] = { "krait0_dig", 1150000 },
+ .vreg[VREG_HFPLL_A] = { "krait0_s8", 2050000 },
+ .vreg[VREG_HFPLL_B] = { "krait0_l23", 1800000 },
+ },
+ [CPU1] = {
+ .hfpll_phys_base = 0x00903300,
+ .aux_clk_sel_phys = 0x02098014,
+ .aux_clk_sel = 3,
+ .sec_clk_sel = 2,
+ .l2cpmr_iaddr = 0x5501,
+ .vreg[VREG_CORE] = { "krait1", 1300000 },
+ .vreg[VREG_MEM] = { "krait1_mem", 1150000 },
+ .vreg[VREG_DIG] = { "krait1_dig", 1150000 },
+ .vreg[VREG_HFPLL_A] = { "krait1_s8", 2050000 },
+ .vreg[VREG_HFPLL_B] = { "krait1_l23", 1800000 },
+ },
+ [L2] = {
+ .hfpll_phys_base = 0x00903400,
+ .aux_clk_sel_phys = 0x02011028,
+ .aux_clk_sel = 3,
+ .sec_clk_sel = 2,
+ .l2cpmr_iaddr = 0x0500,
+ .vreg[VREG_HFPLL_A] = { "l2_s8", 2050000 },
+ .vreg[VREG_HFPLL_B] = { "l2_l23", 1800000 },
+ },
+};
+
+static struct scalable scalable[] __initdata = {
+ [CPU0] = {
+ .hfpll_phys_base = 0x00903200,
+ .aux_clk_sel_phys = 0x02088014,
+ .aux_clk_sel = 3,
+ .sec_clk_sel = 2,
+ .l2cpmr_iaddr = 0x4501,
+ .vreg[VREG_CORE] = { "krait0", 1300000 },
+ .vreg[VREG_MEM] = { "krait0_mem", 1150000 },
+ .vreg[VREG_DIG] = { "krait0_dig", 1150000 },
+ .vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
+ },
+ [CPU1] = {
+ .hfpll_phys_base = 0x00903300,
+ .aux_clk_sel_phys = 0x02098014,
+ .aux_clk_sel = 3,
+ .sec_clk_sel = 2,
+ .l2cpmr_iaddr = 0x5501,
+ .vreg[VREG_CORE] = { "krait1", 1300000 },
+ .vreg[VREG_MEM] = { "krait1_mem", 1150000 },
+ .vreg[VREG_DIG] = { "krait1_dig", 1150000 },
+ .vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
+ },
+ [L2] = {
+ .hfpll_phys_base = 0x00903400,
+ .aux_clk_sel_phys = 0x02011028,
+ .aux_clk_sel = 3,
+ .sec_clk_sel = 2,
+ .l2cpmr_iaddr = 0x0500,
+ .vreg[VREG_HFPLL_A] = { "l2_hfpll", 1800000 },
+ },
+};
+
+static struct msm_bus_paths bw_level_tbl[] __initdata = {
+ [0] = BW_MBPS(640), /* At least 80 MHz on bus. */
+ [1] = BW_MBPS(1064), /* At least 133 MHz on bus. */
+ [2] = BW_MBPS(1600), /* At least 200 MHz on bus. */
+ [3] = BW_MBPS(2128), /* At least 266 MHz on bus. */
+ [4] = BW_MBPS(3200), /* At least 400 MHz on bus. */
+ [5] = BW_MBPS(4800), /* At least 600 MHz on bus. */
+};
+
+static struct msm_bus_scale_pdata bus_scale_data __initdata = {
+ .usecase = bw_level_tbl,
+ .num_usecases = ARRAY_SIZE(bw_level_tbl),
+ .active_only = 1,
+ .name = "acpuclk-8930ab",
+};
+
+/* TODO: Update new L2 freqs once they are available */
+static struct l2_level l2_freq_tbl[] __initdata = {
+ [0] = { { 384000, PLL_8, 0, 0x00 }, LVL_NOM, 1050000, 1 },
+ [1] = { { 432000, HFPLL, 2, 0x20 }, LVL_NOM, 1050000, 2 },
+ [2] = { { 486000, HFPLL, 2, 0x24 }, LVL_NOM, 1050000, 2 },
+ [3] = { { 540000, HFPLL, 2, 0x28 }, LVL_NOM, 1050000, 2 },
+ [4] = { { 594000, HFPLL, 1, 0x16 }, LVL_NOM, 1050000, 2 },
+ [5] = { { 648000, HFPLL, 1, 0x18 }, LVL_NOM, 1050000, 4 },
+ [6] = { { 702000, HFPLL, 1, 0x1A }, LVL_NOM, 1050000, 4 },
+ [7] = { { 756000, HFPLL, 1, 0x1C }, LVL_HIGH, 1150000, 4 },
+ [8] = { { 810000, HFPLL, 1, 0x1E }, LVL_HIGH, 1150000, 4 },
+ [9] = { { 864000, HFPLL, 1, 0x20 }, LVL_HIGH, 1150000, 4 },
+ [10] = { { 918000, HFPLL, 1, 0x22 }, LVL_HIGH, 1150000, 5 },
+ [11] = { { 972000, HFPLL, 1, 0x24 }, LVL_HIGH, 1150000, 5 },
+ [12] = { { 1026000, HFPLL, 1, 0x26 }, LVL_HIGH, 1150000, 5 },
+ [13] = { { 1080000, HFPLL, 1, 0x28 }, LVL_HIGH, 1150000, 5 },
+ [14] = { { 1134000, HFPLL, 1, 0x2A }, LVL_HIGH, 1150000, 5 },
+ [15] = { { 1188000, HFPLL, 1, 0x2C }, LVL_HIGH, 1150000, 5 },
+ { }
+};
+
+static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
+ { 1, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
+ { 1, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
+ { 1, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
+ { 1, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1075000 },
+ { 1, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1100000 },
+ { 1, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1125000 },
+ { 1, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
+ { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1200000 },
+ { 1, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1225000 },
+ { 1, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1237500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1237500 },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1250000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1250000 },
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1262500 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1262500 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1287500 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_nom[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
+ { 1, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
+ { 1, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
+ { 1, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
+ { 1, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1075000 },
+ { 1, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1100000 },
+ { 1, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1125000 },
+ { 1, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
+ { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1200000 },
+ { 1, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1225000 },
+ { 1, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1237500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1237500 },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1250000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1250000 },
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1262500 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1262500 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1287500 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_fast[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
+ { 1, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
+ { 1, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
+ { 1, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
+ { 1, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1075000 },
+ { 1, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1100000 },
+ { 1, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1125000 },
+ { 1, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
+ { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 1200000 },
+ { 1, { 1296000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1225000 },
+ { 1, { 1404000, HFPLL, 1, 0x34 }, L2(15), 1237500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1237500 },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(15), 1250000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1250000 },
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1262500 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1262500 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1287500 },
+ { 0, { 0 } }
+};
+
+/* TODO: Update boost voltage once the pvs data is available */
+static struct pvs_table pvs_tables[NUM_SPEED_BINS][NUM_PVS] __initdata = {
+[0][PVS_SLOW] = { acpu_freq_tbl_slow, sizeof(acpu_freq_tbl_slow), 0 },
+[0][PVS_NOMINAL] = { acpu_freq_tbl_nom, sizeof(acpu_freq_tbl_nom), 0 },
+[0][PVS_FAST] = { acpu_freq_tbl_fast, sizeof(acpu_freq_tbl_fast), 0 },
+};
+
+static struct acpuclk_krait_params acpuclk_8930ab_params __initdata = {
+ .scalable = scalable,
+ .scalable_size = sizeof(scalable),
+ .hfpll_data = &hfpll_data,
+ .pvs_tables = pvs_tables,
+ .l2_freq_tbl = l2_freq_tbl,
+ .l2_freq_tbl_size = sizeof(l2_freq_tbl),
+ .bus_scale = &bus_scale_data,
+ .pte_efuse_phys = 0x007000C0,
+ .stby_khz = 384000,
+};
+
+static int __init acpuclk_8930ab_probe(struct platform_device *pdev)
+{
+ struct acpuclk_platform_data *pdata = pdev->dev.platform_data;
+ if (pdata && pdata->uses_pm8917)
+ acpuclk_8930ab_params.scalable = scalable_pm8917;
+
+ return acpuclk_krait_init(&pdev->dev, &acpuclk_8930ab_params);
+}
+
+static struct platform_driver acpuclk_8930ab_driver = {
+ .driver = {
+ .name = "acpuclk-8930ab",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init acpuclk_8930ab_init(void)
+{
+ return platform_driver_probe(&acpuclk_8930ab_driver,
+ acpuclk_8930ab_probe);
+}
+device_initcall(acpuclk_8930ab_init);
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index 61213cf..0fbd6dc 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -113,14 +113,14 @@
};
static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 300000, PLL_0, 0, 0 }, LVL_LOW, 950000, 0 },
- [1] = { { 384000, HFPLL, 2, 40 }, LVL_NOM, 950000, 1 },
- [2] = { { 460800, HFPLL, 2, 48 }, LVL_NOM, 950000, 1 },
- [3] = { { 537600, HFPLL, 1, 28 }, LVL_NOM, 950000, 2 },
- [4] = { { 576000, HFPLL, 1, 30 }, LVL_NOM, 950000, 2 },
- [5] = { { 652800, HFPLL, 1, 34 }, LVL_NOM, 950000, 2 },
- [6] = { { 729600, HFPLL, 1, 38 }, LVL_NOM, 950000, 2 },
- [7] = { { 806400, HFPLL, 1, 42 }, LVL_NOM, 950000, 2 },
+ [0] = { { 300000, PLL_0, 0, 0 }, LVL_LOW, 1050000, 0 },
+ [1] = { { 345600, HFPLL, 2, 36 }, LVL_NOM, 1050000, 1 },
+ [2] = { { 422400, HFPLL, 2, 44 }, LVL_NOM, 1050000, 1 },
+ [3] = { { 499200, HFPLL, 2, 52 }, LVL_NOM, 1050000, 2 },
+ [4] = { { 576000, HFPLL, 1, 30 }, LVL_NOM, 1050000, 2 },
+ [5] = { { 652800, HFPLL, 1, 34 }, LVL_NOM, 1050000, 2 },
+ [6] = { { 729600, HFPLL, 1, 38 }, LVL_NOM, 1050000, 2 },
+ [7] = { { 806400, HFPLL, 1, 42 }, LVL_NOM, 1050000, 2 },
[8] = { { 883200, HFPLL, 1, 46 }, LVL_HIGH, 1050000, 2 },
[9] = { { 960000, HFPLL, 1, 50 }, LVL_HIGH, 1050000, 2 },
[10] = { { 1036800, HFPLL, 1, 54 }, LVL_HIGH, 1050000, 3 },
@@ -143,30 +143,30 @@
};
static struct acpu_level acpu_freq_tbl[] __initdata = {
- { 1, { 300000, PLL_0, 0, 0 }, L2(0), 950000, 100000 },
- { 1, { 384000, HFPLL, 2, 40 }, L2(3), 950000, 3200000 },
- { 1, { 460800, HFPLL, 2, 48 }, L2(3), 950000, 3200000 },
- { 1, { 537600, HFPLL, 1, 28 }, L2(5), 950000, 3200000 },
- { 1, { 576000, HFPLL, 1, 30 }, L2(5), 950000, 3200000 },
- { 1, { 652800, HFPLL, 1, 34 }, L2(5), 950000, 3200000 },
- { 1, { 729600, HFPLL, 1, 38 }, L2(5), 950000, 3200000 },
- { 1, { 806400, HFPLL, 1, 42 }, L2(7), 950000, 3200000 },
- { 1, { 883200, HFPLL, 1, 46 }, L2(7), 950000, 3200000 },
- { 1, { 960000, HFPLL, 1, 50 }, L2(7), 950000, 3200000 },
- { 1, { 1036800, HFPLL, 1, 54 }, L2(7), 950000, 3200000 },
- { 1, { 1113600, HFPLL, 1, 58 }, L2(12), 1050000, 3200000 },
- { 1, { 1190400, HFPLL, 1, 62 }, L2(12), 1050000, 3200000 },
- { 1, { 1267200, HFPLL, 1, 66 }, L2(12), 1050000, 3200000 },
- { 1, { 1344000, HFPLL, 1, 70 }, L2(15), 1050000, 3200000 },
- { 1, { 1420800, HFPLL, 1, 74 }, L2(15), 1050000, 3200000 },
- { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 1050000, 3200000 },
- { 0, { 1574400, HFPLL, 1, 82 }, L2(20), 1050000, 3200000 },
- { 0, { 1651200, HFPLL, 1, 86 }, L2(20), 1050000, 3200000 },
- { 0, { 1728000, HFPLL, 1, 90 }, L2(20), 1050000, 3200000 },
- { 0, { 1804800, HFPLL, 1, 94 }, L2(25), 1050000, 3200000 },
- { 0, { 1881600, HFPLL, 1, 98 }, L2(25), 1050000, 3200000 },
- { 0, { 1958400, HFPLL, 1, 102 }, L2(25), 1050000, 3200000 },
- { 0, { 1996800, HFPLL, 1, 104 }, L2(25), 1050000, 3200000 },
+ { 1, { 300000, PLL_0, 0, 0 }, L2(0), 850000, 100000 },
+ { 0, { 345600, HFPLL, 2, 36 }, L2(0), 850000, 3200000 },
+ { 1, { 422400, HFPLL, 2, 44 }, L2(0), 850000, 3200000 },
+ { 0, { 499200, HFPLL, 2, 52 }, L2(0), 850000, 3200000 },
+ { 1, { 576000, HFPLL, 1, 30 }, L2(0), 850000, 3200000 },
+ { 1, { 652800, HFPLL, 1, 34 }, L2(16), 850000, 3200000 },
+ { 0, { 729600, HFPLL, 1, 38 }, L2(16), 850000, 3200000 },
+ { 1, { 806400, HFPLL, 1, 42 }, L2(16), 850000, 3200000 },
+ { 1, { 883200, HFPLL, 1, 46 }, L2(16), 870000, 3200000 },
+ { 1, { 960000, HFPLL, 1, 50 }, L2(16), 880000, 3200000 },
+ { 1, { 1036800, HFPLL, 1, 54 }, L2(16), 900000, 3200000 },
+ { 1, { 1113600, HFPLL, 1, 58 }, L2(16), 915000, 3200000 },
+ { 1, { 1190400, HFPLL, 1, 62 }, L2(16), 935000, 3200000 },
+ { 1, { 1267200, HFPLL, 1, 66 }, L2(16), 950000, 3200000 },
+ { 1, { 1344000, HFPLL, 1, 70 }, L2(16), 970000, 3200000 },
+ { 1, { 1420800, HFPLL, 1, 74 }, L2(16), 985000, 3200000 },
+ { 1, { 1497600, HFPLL, 1, 78 }, L2(16), 1000000, 3200000 },
+ { 1, { 1574400, HFPLL, 1, 82 }, L2(16), 1015000, 3200000 },
+ { 1, { 1651200, HFPLL, 1, 86 }, L2(16), 1030000, 3200000 },
+ { 1, { 1728000, HFPLL, 1, 90 }, L2(16), 1050000, 3200000 },
+ { 0, { 1804800, HFPLL, 1, 94 }, L2(16), 1050000, 3200000 },
+ { 0, { 1881600, HFPLL, 1, 98 }, L2(16), 1050000, 3200000 },
+ { 0, { 1958400, HFPLL, 1, 102 }, L2(16), 1050000, 3200000 },
+ { 0, { 1996800, HFPLL, 1, 104 }, L2(16), 1050000, 3200000 },
{ 0, { 0 } }
};
diff --git a/arch/arm/mach-msm/board-8930-display.c b/arch/arm/mach-msm/board-8930-display.c
index a0bfabf..7e477b1 100644
--- a/arch/arm/mach-msm/board-8930-display.c
+++ b/arch/arm/mach-msm/board-8930-display.c
@@ -740,11 +740,29 @@
return 0;
if (on) {
+ if (!(hdmi_msm_data.is_mhl_enabled)) {
+ rc = gpio_request(HDMI_MHL_MUX_GPIO, "MHL_HDMI_MUX");
+ if (rc < 0) {
+ pr_err("gpio hdmi_mhl mux req failed:%d\n",
+ rc);
+ return rc;
+ }
+ rc = gpio_direction_output(HDMI_MHL_MUX_GPIO, 1);
+ if (rc < 0) {
+ pr_err("set gpio hdmi_mhl dir failed:%d\n",
+ rc);
+ goto error0;
+ }
+ gpio_set_value(HDMI_MHL_MUX_GPIO, 1);
+ pr_debug("set gpio hdmi mhl mux %d to 1\n",
+ HDMI_MHL_MUX_GPIO);
+ }
+
rc = gpio_request(100, "HDMI_DDC_CLK");
if (rc) {
pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
"HDMI_DDC_CLK", 100, rc);
- return rc;
+ goto error0;
}
rc = gpio_request(101, "HDMI_DDC_DATA");
if (rc) {
@@ -760,6 +778,8 @@
}
pr_debug("%s(on): success\n", __func__);
} else {
+ if (!(hdmi_msm_data.is_mhl_enabled))
+ gpio_free(HDMI_MHL_MUX_GPIO);
gpio_free(100);
gpio_free(101);
gpio_free(102);
@@ -773,6 +793,9 @@
gpio_free(101);
error1:
gpio_free(100);
+error0:
+ if (!(hdmi_msm_data.is_mhl_enabled))
+ gpio_free(HDMI_MHL_MUX_GPIO);
return rc;
}
diff --git a/arch/arm/mach-msm/board-8930-regulator-pm8038.c b/arch/arm/mach-msm/board-8930-regulator-pm8038.c
index c74dc26..947697a 100644
--- a/arch/arm/mach-msm/board-8930-regulator-pm8038.c
+++ b/arch/arm/mach-msm/board-8930-regulator-pm8038.c
@@ -189,12 +189,14 @@
REGULATOR_SUPPLY("krait0", "acpuclk-8627"),
REGULATOR_SUPPLY("krait0", "acpuclk-8930"),
REGULATOR_SUPPLY("krait0", "acpuclk-8930aa"),
+ REGULATOR_SUPPLY("krait0", "acpuclk-8930ab"),
};
VREG_CONSUMERS(S6) = {
REGULATOR_SUPPLY("8038_s6", NULL),
REGULATOR_SUPPLY("krait1", "acpuclk-8627"),
REGULATOR_SUPPLY("krait1", "acpuclk-8930"),
REGULATOR_SUPPLY("krait1", "acpuclk-8930aa"),
+ REGULATOR_SUPPLY("krait1", "acpuclk-8930ab"),
};
VREG_CONSUMERS(LVS1) = {
REGULATOR_SUPPLY("8038_lvs1", NULL),
@@ -564,6 +566,14 @@
RPM_REG_MAP(L24, 0, 2, "krait1_mem", "acpuclk-8930aa"),
RPM_REG_MAP(VDD_DIG_CORNER, 0, 1, "krait0_dig", "acpuclk-8930aa"),
RPM_REG_MAP(VDD_DIG_CORNER, 0, 2, "krait1_dig", "acpuclk-8930aa"),
+
+ RPM_REG_MAP(L23, 0, 1, "krait0_hfpll", "acpuclk-8930ab"),
+ RPM_REG_MAP(L23, 0, 2, "krait1_hfpll", "acpuclk-8930ab"),
+ RPM_REG_MAP(L23, 0, 6, "l2_hfpll", "acpuclk-8930ab"),
+ RPM_REG_MAP(L24, 0, 1, "krait0_mem", "acpuclk-8930ab"),
+ RPM_REG_MAP(L24, 0, 2, "krait1_mem", "acpuclk-8930ab"),
+ RPM_REG_MAP(VDD_DIG_CORNER, 0, 1, "krait0_dig", "acpuclk-8930ab"),
+ RPM_REG_MAP(VDD_DIG_CORNER, 0, 2, "krait1_dig", "acpuclk-8930ab"),
};
struct rpm_regulator_platform_data
diff --git a/arch/arm/mach-msm/board-8930-regulator-pm8917.c b/arch/arm/mach-msm/board-8930-regulator-pm8917.c
index 6f58771..3ee052b 100644
--- a/arch/arm/mach-msm/board-8930-regulator-pm8917.c
+++ b/arch/arm/mach-msm/board-8930-regulator-pm8917.c
@@ -206,12 +206,14 @@
REGULATOR_SUPPLY("krait0", "acpuclk-8627"),
REGULATOR_SUPPLY("krait0", "acpuclk-8930"),
REGULATOR_SUPPLY("krait0", "acpuclk-8930aa"),
+ REGULATOR_SUPPLY("krait0", "acpuclk-8930ab"),
};
VREG_CONSUMERS(S6) = {
REGULATOR_SUPPLY("8917_s6", NULL),
REGULATOR_SUPPLY("krait1", "acpuclk-8627"),
REGULATOR_SUPPLY("krait1", "acpuclk-8930"),
REGULATOR_SUPPLY("krait1", "acpuclk-8930aa"),
+ REGULATOR_SUPPLY("krait1", "acpuclk-8930ab"),
};
VREG_CONSUMERS(S7) = {
REGULATOR_SUPPLY("8917_s7", NULL),
@@ -631,6 +633,18 @@
RPM_REG_MAP(L24, 0, 2, "krait1_mem", "acpuclk-8930aa"),
RPM_REG_MAP(VDD_DIG_CORNER, 0, 1, "krait0_dig", "acpuclk-8930aa"),
RPM_REG_MAP(VDD_DIG_CORNER, 0, 2, "krait1_dig", "acpuclk-8930aa"),
+
+ RPM_REG_MAP(L23, 0, 1, "krait0_l23", "acpuclk-8930ab"),
+ RPM_REG_MAP(S8, 0, 1, "krait0_s8", "acpuclk-8930ab"),
+ RPM_REG_MAP(L23, 0, 2, "krait1_l23", "acpuclk-8930ab"),
+ RPM_REG_MAP(S8, 0, 2, "krait1_s8", "acpuclk-8930ab"),
+ RPM_REG_MAP(L23, 0, 6, "l2_l23", "acpuclk-8930ab"),
+ RPM_REG_MAP(S8, 0, 6, "l2_s8", "acpuclk-8930ab"),
+ RPM_REG_MAP(L24, 0, 1, "krait0_mem", "acpuclk-8930ab"),
+ RPM_REG_MAP(L24, 0, 2, "krait1_mem", "acpuclk-8930ab"),
+ RPM_REG_MAP(VDD_DIG_CORNER, 0, 1, "krait0_dig", "acpuclk-8930ab"),
+ RPM_REG_MAP(VDD_DIG_CORNER, 0, 2, "krait1_dig", "acpuclk-8930ab"),
+
};
struct rpm_regulator_platform_data
diff --git a/arch/arm/mach-msm/board-8930.c b/arch/arm/mach-msm/board-8930.c
index 1b487fa..512ae72 100644
--- a/arch/arm/mach-msm/board-8930.c
+++ b/arch/arm/mach-msm/board-8930.c
@@ -112,7 +112,6 @@
#define KS8851_IRQ_GPIO 90
#define HAP_SHIFT_LVL_OE_GPIO 47
-#define HDMI_MHL_MUX_GPIO 73
#define MHL_GPIO_INT 72
#define MHL_GPIO_RESET 71
#define MHL_GPIO_PWR_EN 5
@@ -2756,6 +2755,9 @@
pdata = msm8930_device_acpuclk.dev.platform_data;
pdata->uses_pm8917 = true;
+
+ pdata = msm8930ab_device_acpuclk.dev.platform_data;
+ pdata->uses_pm8917 = true;
}
static void __init msm8930_cdp_init(void)
@@ -2829,6 +2831,8 @@
platform_device_register(&msm8930_device_acpuclk);
else if (cpu_is_msm8930aa())
platform_device_register(&msm8930aa_device_acpuclk);
+ else if (cpu_is_msm8930ab())
+ platform_device_register(&msm8930ab_device_acpuclk);
platform_add_devices(early_common_devices,
ARRAY_SIZE(early_common_devices));
if (socinfo_get_pmic_model() != PMIC_MODEL_PM8917)
diff --git a/arch/arm/mach-msm/board-8930.h b/arch/arm/mach-msm/board-8930.h
index 055576f..dbcfa9d 100644
--- a/arch/arm/mach-msm/board-8930.h
+++ b/arch/arm/mach-msm/board-8930.h
@@ -164,5 +164,7 @@
#define MSM_8930_GSBI10_QUP_I2C_BUS_ID 10
#define MSM_8930_GSBI12_QUP_I2C_BUS_ID 12
+#define HDMI_MHL_MUX_GPIO 73
+
extern struct msm_rtb_platform_data msm8930_rtb_pdata;
extern struct msm_cache_dump_platform_data msm8930_cache_dump_pdata;
diff --git a/arch/arm/mach-msm/board-8974-gpiomux.c b/arch/arm/mach-msm/board-8974-gpiomux.c
index 50b59e1..89ad4ef 100644
--- a/arch/arm/mach-msm/board-8974-gpiomux.c
+++ b/arch/arm/mach-msm/board-8974-gpiomux.c
@@ -152,6 +152,26 @@
};
+static struct gpiomux_setting mhl_suspend_config = {
+ .func = GPIOMUX_FUNC_GPIO,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_DOWN,
+};
+
+static struct gpiomux_setting mhl_active_1_cfg = {
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_UP,
+ .dir = GPIOMUX_OUT_HIGH,
+};
+
+static struct gpiomux_setting mhl_active_2_cfg = {
+ .func = GPIOMUX_FUNC_1,
+ .drv = GPIOMUX_DRV_2MA,
+ .pull = GPIOMUX_PULL_UP,
+};
+
+
static struct gpiomux_setting hdmi_suspend_cfg = {
.func = GPIOMUX_FUNC_GPIO,
.drv = GPIOMUX_DRV_2MA,
@@ -170,6 +190,34 @@
.pull = GPIOMUX_PULL_DOWN,
};
+static struct msm_gpiomux_config msm_mhl_configs[] __initdata = {
+ {
+ /* mhl-sii8334 pwr */
+ .gpio = 12,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &mhl_suspend_config,
+ [GPIOMUX_ACTIVE] = &mhl_active_1_cfg,
+ },
+ },
+ {
+ /* mhl-sii8334 intr */
+ .gpio = 82,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &mhl_suspend_config,
+ [GPIOMUX_ACTIVE] = &mhl_active_1_cfg,
+ },
+ },
+ {
+ /* mhl-sii8334 reset */
+ .gpio = 8,
+ .settings = {
+ [GPIOMUX_SUSPENDED] = &mhl_suspend_config,
+ [GPIOMUX_ACTIVE] = &mhl_active_2_cfg,
+ },
+ },
+};
+
+
static struct msm_gpiomux_config msm_hdmi_configs[] __initdata = {
{
.gpio = 31,
@@ -575,4 +623,5 @@
msm_gpiomux_install(msm_taiko_config, ARRAY_SIZE(msm_taiko_config));
msm_gpiomux_install(msm_hdmi_configs, ARRAY_SIZE(msm_hdmi_configs));
+ msm_gpiomux_install(msm_mhl_configs, ARRAY_SIZE(msm_mhl_configs));
}
diff --git a/arch/arm/mach-msm/clock-7x30.c b/arch/arm/mach-msm/clock-7x30.c
index e1390db..3f59035 100644
--- a/arch/arm/mach-msm/clock-7x30.c
+++ b/arch/arm/mach-msm/clock-7x30.c
@@ -279,8 +279,8 @@
.en_mask = BIT(1),
.status_reg = PLL1_STATUS_BASE_REG,
.status_mask = BIT(16),
- .parent = &tcxo_clk.c,
.c = {
+ .parent = &tcxo_clk.c,
.dbg_name = "pll1_clk",
.rate = 768000000,
.ops = &clk_ops_pll_vote,
@@ -293,8 +293,8 @@
.en_mask = BIT(2),
.status_reg = PLL2_STATUS_BASE_REG,
.status_mask = BIT(16),
- .parent = &tcxo_clk.c,
.c = {
+ .parent = &tcxo_clk.c,
.dbg_name = "pll2_clk",
.rate = 806400000, /* TODO: Support scaling */
.ops = &clk_ops_pll_vote,
@@ -307,8 +307,8 @@
.en_mask = BIT(3),
.status_reg = PLL3_STATUS_BASE_REG,
.status_mask = BIT(16),
- .parent = &lpxo_clk.c,
.c = {
+ .parent = &lpxo_clk.c,
.dbg_name = "pll3_clk",
.rate = 737280000,
.ops = &clk_ops_pll_vote,
@@ -321,8 +321,8 @@
.en_mask = BIT(4),
.status_reg = PLL4_STATUS_BASE_REG,
.status_mask = BIT(16),
- .parent = &lpxo_clk.c,
.c = {
+ .parent = &lpxo_clk.c,
.dbg_name = "pll4_clk",
.rate = 891000000,
.ops = &clk_ops_pll_vote,
@@ -363,8 +363,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 2,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "axi_li_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_li_apps_clk.c),
@@ -379,8 +379,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 14,
},
- .parent = &axi_li_apps_clk.c,
.c = {
+ .parent = &axi_li_apps_clk.c,
.dbg_name = "axi_li_adsp_a_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_li_adsp_a_clk.c),
@@ -395,8 +395,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 19,
},
- .parent = &axi_li_apps_clk.c,
.c = {
+ .parent = &axi_li_apps_clk.c,
.dbg_name = "axi_li_jpeg_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_li_jpeg_clk.c),
@@ -411,8 +411,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 23,
},
- .parent = &axi_li_apps_clk.c,
.c = {
+ .parent = &axi_li_apps_clk.c,
.dbg_name = "axi_li_vfe_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_li_vfe_clk.c),
@@ -427,8 +427,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 29,
},
- .parent = &axi_li_apps_clk.c,
.c = {
+ .parent = &axi_li_apps_clk.c,
.dbg_name = "axi_mdp_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_mdp_clk.c),
@@ -443,8 +443,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 3,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "axi_li_vg_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_li_vg_clk.c),
@@ -459,8 +459,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 21,
},
- .parent = &axi_li_vg_clk.c,
.c = {
+ .parent = &axi_li_vg_clk.c,
.dbg_name = "axi_grp_2d_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_grp_2d_clk.c),
@@ -475,8 +475,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 22,
},
- .parent = &axi_li_vg_clk.c,
.c = {
+ .parent = &axi_li_vg_clk.c,
.dbg_name = "axi_li_grp_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_li_grp_clk.c),
@@ -491,8 +491,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 20,
},
- .parent = &axi_li_vg_clk.c,
.c = {
+ .parent = &axi_li_vg_clk.c,
.dbg_name = "axi_mfc_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_mfc_clk.c),
@@ -508,8 +508,8 @@
.halt_bit = 22,
.reset_mask = P_AXI_ROTATOR_CLK,
},
- .parent = &axi_li_vg_clk.c,
.c = {
+ .parent = &axi_li_vg_clk.c,
.dbg_name = "axi_rotator_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_rotator_clk.c),
@@ -524,8 +524,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 21,
},
- .parent = &axi_li_vg_clk.c,
.c = {
+ .parent = &axi_li_vg_clk.c,
.dbg_name = "axi_vpe_clk",
.ops = &clk_ops_branch,
CLK_INIT(axi_vpe_clk.c),
@@ -542,8 +542,8 @@
.halt_bit = 5,
.reset_mask = P_ADM_CLK,
},
- .parent = &axi_li_apps_clk.c,
.c = {
+ .parent = &axi_li_apps_clk.c,
.dbg_name = "adm_clk",
.ops = &clk_ops_branch,
CLK_INIT(adm_clk.c),
@@ -558,8 +558,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 15,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "adm_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(adm_p_clk.c),
@@ -575,8 +575,8 @@
.halt_bit = 6,
.reset_mask = P_CE_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "ce_clk",
.ops = &clk_ops_branch,
CLK_INIT(ce_clk.c),
@@ -592,8 +592,8 @@
.halt_bit = 9,
.reset_mask = P_CAMIF_PAD_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "camif_pad_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(camif_pad_p_clk.c),
@@ -609,8 +609,8 @@
.halt_bit = 30,
.reset_mask = P_CSI0_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "csi0_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi0_p_clk.c),
@@ -626,8 +626,8 @@
.halt_bit = 3,
.reset_mask = P_EMDH_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "emdh_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(emdh_p_clk.c),
@@ -643,8 +643,8 @@
.halt_bit = 24,
.reset_mask = P_GRP_2D_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "grp_2d_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(grp_2d_p_clk.c),
@@ -660,8 +660,8 @@
.halt_bit = 17,
.reset_mask = P_GRP_3D_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "grp_3d_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(grp_3d_p_clk.c),
@@ -677,8 +677,8 @@
.halt_bit = 24,
.reset_mask = P_JPEG_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "jpeg_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(jpeg_p_clk.c),
@@ -694,8 +694,8 @@
.halt_bit = 7,
.reset_mask = P_LPA_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "lpa_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(lpa_p_clk.c),
@@ -711,8 +711,8 @@
.halt_bit = 6,
.reset_mask = P_MDP_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "mdp_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdp_p_clk.c),
@@ -728,8 +728,8 @@
.halt_bit = 26,
.reset_mask = P_MFC_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "mfc_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(mfc_p_clk.c),
@@ -745,8 +745,8 @@
.halt_bit = 4,
.reset_mask = P_PMDH_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "pmdh_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(pmdh_p_clk.c),
@@ -762,8 +762,8 @@
.halt_bit = 23,
.reset_mask = P_ROTATOR_IMEM_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "rotator_imem_clk",
.ops = &clk_ops_branch,
CLK_INIT(rotator_imem_clk.c),
@@ -779,8 +779,8 @@
.halt_bit = 25,
.reset_mask = P_ROTATOR_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "rotator_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(rotator_p_clk.c),
@@ -796,8 +796,8 @@
.halt_bit = 7,
.reset_mask = P_SDC1_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "sdc1_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(sdc1_p_clk.c),
@@ -813,8 +813,8 @@
.halt_bit = 8,
.reset_mask = P_SDC2_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "sdc2_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(sdc2_p_clk.c),
@@ -830,8 +830,8 @@
.halt_bit = 27,
.reset_mask = P_SDC3_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "sdc3_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(sdc3_p_clk.c),
@@ -847,8 +847,8 @@
.halt_bit = 28,
.reset_mask = P_SDC4_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "sdc4_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(sdc4_p_clk.c),
@@ -864,8 +864,8 @@
.halt_bit = 10,
.reset_mask = P_SPI_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "spi_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(spi_p_clk.c),
@@ -881,8 +881,8 @@
.halt_bit = 18,
.reset_mask = P_TSIF_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "tsif_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(tsif_p_clk.c),
@@ -897,8 +897,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 17,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "uart1dm_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(uart1dm_p_clk.c),
@@ -913,8 +913,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 26,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "uart2dm_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(uart2dm_p_clk.c),
@@ -930,8 +930,8 @@
.halt_bit = 8,
.reset_mask = P_USB_HS2_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "usb_hs2_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hs2_p_clk.c),
@@ -947,8 +947,8 @@
.halt_bit = 9,
.reset_mask = P_USB_HS3_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "usb_hs3_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hs3_p_clk.c),
@@ -964,8 +964,8 @@
.halt_bit = 25,
.reset_mask = P_USB_HS_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "usb_hs_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hs_p_clk.c),
@@ -981,8 +981,8 @@
.halt_bit = 27,
.reset_mask = P_VFE_P_CLK,
},
- .parent = &glbl_root_clk.c,
.c = {
+ .parent = &glbl_root_clk.c,
.dbg_name = "vfe_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(vfe_p_clk.c),
@@ -1320,8 +1320,8 @@
.halt_bit = 18,
.reset_mask = P_GRP_3D_CLK,
},
- .parent = &grp_3d_src_clk.c,
.c = {
+ .parent = &grp_3d_src_clk.c,
.dbg_name = "grp_3d_clk",
.ops = &clk_ops_branch,
CLK_INIT(grp_3d_clk.c),
@@ -1336,8 +1336,8 @@
.halt_bit = 19,
.reset_mask = P_IMEM_CLK,
},
- .parent = &grp_3d_src_clk.c,
.c = {
+ .parent = &grp_3d_src_clk.c,
.dbg_name = "imem_clk",
.ops = &clk_ops_branch,
CLK_INIT(imem_clk.c),
@@ -1542,8 +1542,8 @@
.halt_bit = 29,
.reset_mask = P_MDP_LCDC_PAD_PCLK_CLK,
},
- .parent = &mdp_lcdc_pclk_clk.c,
.c = {
+ .parent = &mdp_lcdc_pclk_clk.c,
.dbg_name = "mdp_lcdc_pad_pclk_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdp_lcdc_pad_pclk_clk.c),
@@ -1616,8 +1616,8 @@
.halt_bit = 13,
.reset_mask = P_MI2S_CODEC_RX_S_CLK,
},
- .parent = &mi2s_codec_rx_m_clk.c,
.c = {
+ .parent = &mi2s_codec_rx_m_clk.c,
.dbg_name = "mi2s_codec_rx_s_clk",
.ops = &clk_ops_branch,
CLK_INIT(mi2s_codec_rx_s_clk.c),
@@ -1656,8 +1656,8 @@
.halt_bit = 11,
.reset_mask = P_MI2S_CODEC_TX_S_CLK,
},
- .parent = &mi2s_codec_tx_m_clk.c,
.c = {
+ .parent = &mi2s_codec_tx_m_clk.c,
.dbg_name = "mi2s_codec_tx_s_clk",
.ops = &clk_ops_branch,
CLK_INIT(mi2s_codec_tx_s_clk.c),
@@ -1702,8 +1702,8 @@
.halt_bit = 3,
.reset_mask = P_MI2S_S_CLK,
},
- .parent = &mi2s_m_clk.c,
.c = {
+ .parent = &mi2s_m_clk.c,
.dbg_name = "mi2s_s_clk",
.ops = &clk_ops_branch,
CLK_INIT(mi2s_s_clk.c),
@@ -1763,8 +1763,8 @@
.halt_bit = 17,
.reset_mask = P_SDAC_M_CLK,
},
- .parent = &sdac_clk.c,
.c = {
+ .parent = &sdac_clk.c,
.dbg_name = "sdac_m_clk",
.ops = &clk_ops_branch,
CLK_INIT(sdac_m_clk.c),
@@ -1807,8 +1807,8 @@
.halt_bit = 7,
.reset_mask = P_HDMI_CLK,
},
- .parent = &tv_clk.c,
.c = {
+ .parent = &tv_clk.c,
.dbg_name = "hdmi_clk",
.ops = &clk_ops_branch,
CLK_INIT(hdmi_clk.c),
@@ -1823,8 +1823,8 @@
.halt_bit = 27,
.reset_mask = P_TV_DAC_CLK,
},
- .parent = &tv_clk.c,
.c = {
+ .parent = &tv_clk.c,
.dbg_name = "tv_dac_clk",
.ops = &clk_ops_branch,
CLK_INIT(tv_dac_clk.c),
@@ -1839,8 +1839,8 @@
.halt_bit = 10,
.reset_mask = P_TV_ENC_CLK,
},
- .parent = &tv_clk.c,
.c = {
+ .parent = &tv_clk.c,
.dbg_name = "tv_enc_clk",
.ops = &clk_ops_branch,
CLK_INIT(tv_enc_clk.c),
@@ -1856,8 +1856,8 @@
.halt_bit = 11,
.reset_mask = P_TSIF_REF_CLK,
},
- .parent = &tv_clk.c,
.c = {
+ .parent = &tv_clk.c,
.dbg_name = "tsif_ref_clk",
.ops = &clk_ops_branch,
CLK_INIT(tsif_ref_clk.c),
@@ -1915,8 +1915,8 @@
.halt_bit = 27,
.reset_mask = P_USB_HS_CORE_CLK,
},
- .parent = &usb_hs_src_clk.c,
.c = {
+ .parent = &usb_hs_src_clk.c,
.dbg_name = "usb_hs_core_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hs_core_clk.c),
@@ -1931,8 +1931,8 @@
.halt_bit = 3,
.reset_mask = P_USB_HS2_CLK,
},
- .parent = &usb_hs_src_clk.c,
.c = {
+ .parent = &usb_hs_src_clk.c,
.dbg_name = "usb_hs2_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hs2_clk.c),
@@ -1947,8 +1947,8 @@
.halt_bit = 28,
.reset_mask = P_USB_HS2_CORE_CLK,
},
- .parent = &usb_hs_src_clk.c,
.c = {
+ .parent = &usb_hs_src_clk.c,
.dbg_name = "usb_hs2_core_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hs2_core_clk.c),
@@ -1963,8 +1963,8 @@
.halt_bit = 2,
.reset_mask = P_USB_HS3_CLK,
},
- .parent = &usb_hs_src_clk.c,
.c = {
+ .parent = &usb_hs_src_clk.c,
.dbg_name = "usb_hs3_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hs3_clk.c),
@@ -1979,8 +1979,8 @@
.halt_bit = 29,
.reset_mask = P_USB_HS3_CORE_CLK,
},
- .parent = &usb_hs_src_clk.c,
.c = {
+ .parent = &usb_hs_src_clk.c,
.dbg_name = "usb_hs3_core_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hs3_core_clk.c),
@@ -2062,8 +2062,8 @@
.halt_bit = 9,
.reset_mask = P_VFE_MDC_CLK,
},
- .parent = &vfe_clk.c,
.c = {
+ .parent = &vfe_clk.c,
.dbg_name = "vfe_mdc_clk",
.ops = &clk_ops_branch,
CLK_INIT(vfe_mdc_clk.c),
@@ -2078,8 +2078,8 @@
.halt_bit = 13,
.reset_mask = P_VFE_CAMIF_CLK,
},
- .parent = &vfe_clk.c,
.c = {
+ .parent = &vfe_clk.c,
.dbg_name = "vfe_camif_clk",
.ops = &clk_ops_branch,
CLK_INIT(vfe_camif_clk.c),
@@ -2094,8 +2094,8 @@
.halt_bit = 16,
.reset_mask = P_CSI0_VFE_CLK,
},
- .parent = &vfe_clk.c,
.c = {
+ .parent = &vfe_clk.c,
.dbg_name = "csi0_vfe_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi0_vfe_clk.c),
@@ -2219,8 +2219,8 @@
.halt_bit = 11,
.reset_mask = P_MFC_DIV2_CLK,
},
- .parent = &mfc_clk.c,
.c = {
+ .parent = &mfc_clk.c,
.dbg_name = "mfc_div2_clk",
.ops = &clk_ops_branch,
CLK_INIT(mfc_div2_clk.c),
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index ca47ea1..a4d7e61 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -525,8 +525,8 @@
static struct pll_clk pll2_clk = {
.mode_reg = MM_PLL1_MODE_REG,
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "pll2_clk",
.rate = 800000000,
.ops = &clk_ops_local_pll,
@@ -536,8 +536,8 @@
static struct pll_clk pll3_clk = {
.mode_reg = BB_MMCC_PLL2_MODE_REG,
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "pll3_clk",
.rate = 1200000000,
.ops = &clk_ops_local_pll,
@@ -555,8 +555,8 @@
.en_mask = BIT(4),
.status_reg = LCC_PLL0_STATUS_REG,
.status_mask = BIT(16),
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "pll4_clk",
.rate = 393216000,
.ops = &clk_ops_pll_vote,
@@ -569,8 +569,8 @@
.en_mask = BIT(8),
.status_reg = BB_PLL8_STATUS_REG,
.status_mask = BIT(16),
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "pll8_clk",
.rate = 384000000,
.ops = &clk_ops_pll_vote,
@@ -583,8 +583,8 @@
.en_mask = BIT(14),
.status_reg = BB_PLL14_STATUS_REG,
.status_mask = BIT(16),
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "pll14_clk",
.rate = 480000000,
.ops = &clk_ops_pll_vote,
@@ -594,8 +594,8 @@
static struct pll_clk pll15_clk = {
.mode_reg = MM_PLL3_MODE_REG,
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "pll15_clk",
.rate = 975000000,
.ops = &clk_ops_local_pll,
@@ -1701,8 +1701,8 @@
.halt_reg = CLK_HALT_CFPB_STATEA_REG,
.halt_bit = 24,
},
- .parent = &usb_hsic_xcvr_fs_clk.c,
.c = {
+ .parent = &usb_hsic_xcvr_fs_clk.c,
.dbg_name = "usb_hsic_system_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hsic_system_clk.c),
@@ -1743,8 +1743,8 @@
.halt_reg = CLK_HALT_CFPB_STATEA_REG,
.halt_bit = 19,
},
- .parent = &usb_hsic_hsic_src_clk.c,
.c = {
+ .parent = &usb_hsic_hsic_src_clk.c,
.dbg_name = "usb_hsic_hsic_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hsic_hsic_clk.c),
@@ -1823,8 +1823,8 @@
.halt_reg = CLK_HALT_CFPB_STATEA_REG,
.halt_bit = 15,
},
- .parent = &usb_fs1_src_clk.c,
.c = {
+ .parent = &usb_fs1_src_clk.c,
.dbg_name = "usb_fs1_xcvr_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_fs1_xcvr_clk.c),
@@ -1840,8 +1840,8 @@
.halt_reg = CLK_HALT_CFPB_STATEA_REG,
.halt_bit = 16,
},
- .parent = &usb_fs1_src_clk.c,
.c = {
+ .parent = &usb_fs1_src_clk.c,
.dbg_name = "usb_fs1_sys_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_fs1_sys_clk.c),
@@ -1858,8 +1858,8 @@
.halt_reg = CLK_HALT_CFPB_STATEA_REG,
.halt_bit = 12,
},
- .parent = &usb_fs2_src_clk.c,
.c = {
+ .parent = &usb_fs2_src_clk.c,
.dbg_name = "usb_fs2_xcvr_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_fs2_xcvr_clk.c),
@@ -1875,8 +1875,8 @@
.halt_reg = CLK_HALT_CFPB_STATEA_REG,
.halt_bit = 13,
},
- .parent = &usb_fs2_src_clk.c,
.c = {
+ .parent = &usb_fs2_src_clk.c,
.dbg_name = "usb_fs2_sys_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_fs2_sys_clk.c),
@@ -1962,8 +1962,8 @@
.halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
.halt_bit = 5,
},
- .parent = &ce3_src_clk.c,
.c = {
+ .parent = &ce3_src_clk.c,
.dbg_name = "ce3_core_clk",
.ops = &clk_ops_branch,
CLK_INIT(ce3_core_clk.c),
@@ -1979,8 +1979,8 @@
.halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG,
.halt_bit = 16,
},
- .parent = &ce3_src_clk.c,
.c = {
+ .parent = &ce3_src_clk.c,
.dbg_name = "ce3_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(ce3_p_clk.c),
@@ -2027,8 +2027,8 @@
.halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
.halt_bit = 26,
},
- .parent = &sata_src_clk.c,
.c = {
+ .parent = &sata_src_clk.c,
.dbg_name = "sata_rxoob_clk",
.ops = &clk_ops_branch,
CLK_INIT(sata_rxoob_clk.c),
@@ -2042,8 +2042,8 @@
.halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
.halt_bit = 25,
},
- .parent = &sata_src_clk.c,
.c = {
+ .parent = &sata_src_clk.c,
.dbg_name = "sata_pmalive_clk",
.ops = &clk_ops_branch,
CLK_INIT(sata_pmalive_clk.c),
@@ -2057,8 +2057,8 @@
.halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
.halt_bit = 24,
},
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "sata_phy_ref_clk",
.ops = &clk_ops_branch,
CLK_INIT(sata_phy_ref_clk.c),
@@ -2750,8 +2750,8 @@
.halt_reg = DBG_BUS_VEC_B_REG,
.halt_bit = 13,
},
- .parent = &csi0_src_clk.c,
.c = {
+ .parent = &csi0_src_clk.c,
.dbg_name = "csi0_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi0_clk.c),
@@ -2767,8 +2767,8 @@
.halt_reg = DBG_BUS_VEC_I_REG,
.halt_bit = 9,
},
- .parent = &csi0_src_clk.c,
.c = {
+ .parent = &csi0_src_clk.c,
.dbg_name = "csi0_phy_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi0_phy_clk.c),
@@ -2806,8 +2806,8 @@
.halt_reg = DBG_BUS_VEC_B_REG,
.halt_bit = 14,
},
- .parent = &csi1_src_clk.c,
.c = {
+ .parent = &csi1_src_clk.c,
.dbg_name = "csi1_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi1_clk.c),
@@ -2823,8 +2823,8 @@
.halt_reg = DBG_BUS_VEC_I_REG,
.halt_bit = 10,
},
- .parent = &csi1_src_clk.c,
.c = {
+ .parent = &csi1_src_clk.c,
.dbg_name = "csi1_phy_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi1_phy_clk.c),
@@ -2862,8 +2862,8 @@
.halt_reg = DBG_BUS_VEC_B_REG,
.halt_bit = 29,
},
- .parent = &csi2_src_clk.c,
.c = {
+ .parent = &csi2_src_clk.c,
.dbg_name = "csi2_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi2_clk.c),
@@ -2879,8 +2879,8 @@
.halt_reg = DBG_BUS_VEC_I_REG,
.halt_bit = 29,
},
- .parent = &csi2_src_clk.c,
.c = {
+ .parent = &csi2_src_clk.c,
.dbg_name = "csi2_phy_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi2_phy_clk.c),
@@ -2977,6 +2977,7 @@
mb();
udelay(1);
rdi->cur_rate = rate;
+ c->parent = mux_map[rate];
spin_unlock(&local_clock_reg_lock);
if (rdi->enabled)
@@ -3038,11 +3039,6 @@
return branch_reset(&to_pix_rdi_clk(c)->b, action);
}
-static struct clk *pix_rdi_clk_get_parent(struct clk *c)
-{
- return pix_rdi_mux_map[to_pix_rdi_clk(c)->cur_rate];
-}
-
static int pix_rdi_clk_list_rate(struct clk *c, unsigned n)
{
if (pix_rdi_mux_map[n])
@@ -3064,6 +3060,7 @@
rdi->cur_rate = reg & rdi->s_mask ? 1 : 0;
reg = readl_relaxed(rdi->s2_reg);
rdi->cur_rate = reg & rdi->s2_mask ? 2 : rdi->cur_rate;
+ c->parent = pix_rdi_mux_map[rdi->cur_rate];
return HANDOFF_ENABLED_CLK;
}
@@ -3078,7 +3075,6 @@
.get_rate = pix_rdi_clk_get_rate,
.list_rate = pix_rdi_clk_list_rate,
.reset = pix_rdi_clk_reset,
- .get_parent = pix_rdi_clk_get_parent,
};
static struct pix_rdi_clk csi_pix_clk = {
@@ -3220,8 +3216,8 @@
.halt_reg = DBG_BUS_VEC_I_REG,
.halt_bit = 17,
},
- .parent = &csiphy_timer_src_clk.c,
.c = {
+ .parent = &csiphy_timer_src_clk.c,
.dbg_name = "csi0phy_timer_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi0phy_timer_clk.c),
@@ -3235,8 +3231,8 @@
.halt_reg = DBG_BUS_VEC_I_REG,
.halt_bit = 18,
},
- .parent = &csiphy_timer_src_clk.c,
.c = {
+ .parent = &csiphy_timer_src_clk.c,
.dbg_name = "csi1phy_timer_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi1phy_timer_clk.c),
@@ -3250,8 +3246,8 @@
.halt_reg = DBG_BUS_VEC_I_REG,
.halt_bit = 30,
},
- .parent = &csiphy_timer_src_clk.c,
.c = {
+ .parent = &csiphy_timer_src_clk.c,
.dbg_name = "csi2phy_timer_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi2phy_timer_clk.c),
@@ -3719,8 +3715,8 @@
.halt_reg = DBG_BUS_VEC_J_REG,
.halt_bit = 25,
},
- .parent = &vcap_clk.c,
.c = {
+ .parent = &vcap_clk.c,
.dbg_name = "vcap_npl_clk",
.ops = &clk_ops_branch,
CLK_INIT(vcap_npl_clk.c),
@@ -3937,8 +3933,8 @@
.retain_reg = MDP_LUT_CC_REG,
.retain_mask = BIT(31),
},
- .parent = &mdp_clk.c,
.c = {
+ .parent = &mdp_clk.c,
.dbg_name = "lut_mdp_clk",
.ops = &clk_ops_branch,
CLK_INIT(lut_mdp_clk.c),
@@ -4058,18 +4054,13 @@
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
}
-static struct clk *hdmi_pll_clk_get_parent(struct clk *c)
-{
- return &pxo_clk.c;
-}
-
static struct clk_ops clk_ops_hdmi_pll = {
.enable = hdmi_pll_clk_enable,
.disable = hdmi_pll_clk_disable,
- .get_parent = hdmi_pll_clk_get_parent,
};
static struct clk hdmi_pll_clk = {
+ .parent = &pxo_clk.c,
.dbg_name = "hdmi_pll_clk",
.ops = &clk_ops_hdmi_pll,
.vdd_class = &vdd_sr2_hdmi_pll,
@@ -4176,8 +4167,8 @@
.halt_reg = DBG_BUS_VEC_D_REG,
.halt_bit = 9,
},
- .parent = &tv_src_clk.c,
.c = {
+ .parent = &tv_src_clk.c,
.dbg_name = "tv_enc_clk",
.ops = &clk_ops_branch,
CLK_INIT(tv_enc_clk.c),
@@ -4191,8 +4182,8 @@
.halt_reg = DBG_BUS_VEC_D_REG,
.halt_bit = 10,
},
- .parent = &tv_src_clk.c,
.c = {
+ .parent = &tv_src_clk.c,
.dbg_name = "tv_dac_clk",
.ops = &clk_ops_branch,
CLK_INIT(tv_dac_clk.c),
@@ -4210,8 +4201,8 @@
.retain_reg = TV_CC2_REG,
.retain_mask = BIT(10),
},
- .parent = &tv_src_clk.c,
.c = {
+ .parent = &tv_src_clk.c,
.dbg_name = "mdp_tv_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdp_tv_clk.c),
@@ -4227,8 +4218,8 @@
.halt_reg = DBG_BUS_VEC_D_REG,
.halt_bit = 11,
},
- .parent = &tv_src_clk.c,
.c = {
+ .parent = &tv_src_clk.c,
.dbg_name = "hdmi_tv_clk",
.ops = &clk_ops_branch,
CLK_INIT(hdmi_tv_clk.c),
@@ -4242,8 +4233,8 @@
.halt_reg = DBG_BUS_VEC_J_REG,
.halt_bit = 27,
},
- .parent = &tv_src_clk.c,
.c = {
+ .parent = &tv_src_clk.c,
.dbg_name = "rgb_tv_clk",
.ops = &clk_ops_branch,
CLK_INIT(rgb_tv_clk.c),
@@ -4257,8 +4248,8 @@
.halt_reg = DBG_BUS_VEC_J_REG,
.halt_bit = 26,
},
- .parent = &tv_src_clk.c,
.c = {
+ .parent = &tv_src_clk.c,
.dbg_name = "npl_tv_clk",
.ops = &clk_ops_branch,
CLK_INIT(npl_tv_clk.c),
@@ -4480,8 +4471,8 @@
.halt_reg = DBG_BUS_VEC_B_REG,
.halt_bit = 8,
},
- .parent = &vfe_clk.c,
.c = {
+ .parent = &vfe_clk.c,
.dbg_name = "csi_vfe_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi_vfe_clk.c),
@@ -4753,8 +4744,8 @@
.halt_check = ENABLE,
.halt_bit = 1,
},
- .parent = &audio_slimbus_clk.c,
.c = {
+ .parent = &audio_slimbus_clk.c,
.dbg_name = "sps_slimbus_clk",
.ops = &clk_ops_branch,
CLK_INIT(sps_slimbus_clk.c),
@@ -4768,8 +4759,8 @@
.halt_reg = CLK_HALT_DFAB_STATE_REG,
.halt_bit = 28,
},
- .parent = &sps_slimbus_clk.c,
.c = {
+ .parent = &sps_slimbus_clk.c,
.dbg_name = "slimbus_xo_src_clk",
.ops = &clk_ops_branch,
CLK_INIT(slimbus_xo_src_clk.c),
diff --git a/arch/arm/mach-msm/clock-8974.c b/arch/arm/mach-msm/clock-8974.c
index 1395f05..c0a553f 100644
--- a/arch/arm/mach-msm/clock-8974.c
+++ b/arch/arm/mach-msm/clock-8974.c
@@ -694,9 +694,9 @@
.en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE_REG,
.status_reg = (void __iomem *)GPLL0_STATUS_REG,
.status_mask = BIT(17),
- .parent = &cxo_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.rate = 600000000,
.dbg_name = "gpll0_clk_src",
.ops = &clk_ops_pll_vote,
@@ -709,9 +709,9 @@
.en_mask = BIT(1),
.status_reg = (void __iomem *)GPLL1_STATUS_REG,
.status_mask = BIT(17),
- .parent = &cxo_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.rate = 480000000,
.dbg_name = "gpll1_clk_src",
.ops = &clk_ops_pll_vote,
@@ -724,9 +724,9 @@
.en_mask = BIT(0),
.status_reg = (void __iomem *)LPAPLL_STATUS_REG,
.status_mask = BIT(17),
- .parent = &cxo_clk_src.c,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.rate = 491520000,
.dbg_name = "lpapll0_clk_src",
.ops = &clk_ops_pll_vote,
@@ -739,9 +739,9 @@
.en_mask = BIT(0),
.status_reg = (void __iomem *)MMPLL0_STATUS_REG,
.status_mask = BIT(17),
- .parent = &cxo_clk_src.c,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "mmpll0_clk_src",
.rate = 800000000,
.ops = &clk_ops_pll_vote,
@@ -754,9 +754,9 @@
.en_mask = BIT(1),
.status_reg = (void __iomem *)MMPLL1_STATUS_REG,
.status_mask = BIT(17),
- .parent = &cxo_clk_src.c,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "mmpll1_clk_src",
.rate = 846000000,
.ops = &clk_ops_pll_vote,
@@ -767,9 +767,9 @@
static struct pll_clk mmpll3_clk_src = {
.mode_reg = (void __iomem *)MMPLL3_MODE_REG,
.status_reg = (void __iomem *)MMPLL3_STATUS_REG,
- .parent = &cxo_clk_src.c,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "mmpll3_clk_src",
.rate = 1000000000,
.ops = &clk_ops_local_pll,
@@ -1512,10 +1512,10 @@
static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c),
@@ -1524,9 +1524,9 @@
static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR,
- .parent = &blsp1_qup1_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup1_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup1_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c),
@@ -1535,10 +1535,10 @@
static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c),
@@ -1547,9 +1547,9 @@
static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR,
- .parent = &blsp1_qup2_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup2_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup2_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c),
@@ -1558,10 +1558,10 @@
static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c),
@@ -1570,9 +1570,9 @@
static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR,
- .parent = &blsp1_qup3_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup3_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup3_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c),
@@ -1581,10 +1581,10 @@
static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c),
@@ -1593,9 +1593,9 @@
static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR,
- .parent = &blsp1_qup4_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup4_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup4_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c),
@@ -1604,10 +1604,10 @@
static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP5_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup5_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup5_i2c_apps_clk.c),
@@ -1616,9 +1616,9 @@
static struct branch_clk gcc_blsp1_qup5_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP5_SPI_APPS_CBCR,
- .parent = &blsp1_qup5_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup5_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup5_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup5_spi_apps_clk.c),
@@ -1627,10 +1627,10 @@
static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP6_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup6_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup6_i2c_apps_clk.c),
@@ -1639,9 +1639,9 @@
static struct branch_clk gcc_blsp1_qup6_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP6_SPI_APPS_CBCR,
- .parent = &blsp1_qup6_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup6_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup6_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup6_spi_apps_clk.c),
@@ -1650,9 +1650,9 @@
static struct branch_clk gcc_blsp1_uart1_apps_clk = {
.cbcr_reg = BLSP1_UART1_APPS_CBCR,
- .parent = &blsp1_uart1_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart1_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart1_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart1_apps_clk.c),
@@ -1661,9 +1661,9 @@
static struct branch_clk gcc_blsp1_uart2_apps_clk = {
.cbcr_reg = BLSP1_UART2_APPS_CBCR,
- .parent = &blsp1_uart2_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart2_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart2_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart2_apps_clk.c),
@@ -1672,9 +1672,9 @@
static struct branch_clk gcc_blsp1_uart3_apps_clk = {
.cbcr_reg = BLSP1_UART3_APPS_CBCR,
- .parent = &blsp1_uart3_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart3_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart3_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart3_apps_clk.c),
@@ -1683,9 +1683,9 @@
static struct branch_clk gcc_blsp1_uart4_apps_clk = {
.cbcr_reg = BLSP1_UART4_APPS_CBCR,
- .parent = &blsp1_uart4_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart4_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart4_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart4_apps_clk.c),
@@ -1694,9 +1694,9 @@
static struct branch_clk gcc_blsp1_uart5_apps_clk = {
.cbcr_reg = BLSP1_UART5_APPS_CBCR,
- .parent = &blsp1_uart5_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart5_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart5_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart5_apps_clk.c),
@@ -1705,9 +1705,9 @@
static struct branch_clk gcc_blsp1_uart6_apps_clk = {
.cbcr_reg = BLSP1_UART6_APPS_CBCR,
- .parent = &blsp1_uart6_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart6_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart6_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart6_apps_clk.c),
@@ -1740,10 +1740,10 @@
static struct branch_clk gcc_blsp2_qup1_i2c_apps_clk = {
.cbcr_reg = BLSP2_QUP1_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp2_qup1_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup1_i2c_apps_clk.c),
@@ -1752,9 +1752,9 @@
static struct branch_clk gcc_blsp2_qup1_spi_apps_clk = {
.cbcr_reg = BLSP2_QUP1_SPI_APPS_CBCR,
- .parent = &blsp2_qup1_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_qup1_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp2_qup1_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup1_spi_apps_clk.c),
@@ -1763,10 +1763,10 @@
static struct branch_clk gcc_blsp2_qup2_i2c_apps_clk = {
.cbcr_reg = BLSP2_QUP2_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp2_qup2_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup2_i2c_apps_clk.c),
@@ -1775,9 +1775,9 @@
static struct branch_clk gcc_blsp2_qup2_spi_apps_clk = {
.cbcr_reg = BLSP2_QUP2_SPI_APPS_CBCR,
- .parent = &blsp2_qup2_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_qup2_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp2_qup2_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup2_spi_apps_clk.c),
@@ -1786,10 +1786,10 @@
static struct branch_clk gcc_blsp2_qup3_i2c_apps_clk = {
.cbcr_reg = BLSP2_QUP3_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp2_qup3_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup3_i2c_apps_clk.c),
@@ -1798,9 +1798,9 @@
static struct branch_clk gcc_blsp2_qup3_spi_apps_clk = {
.cbcr_reg = BLSP2_QUP3_SPI_APPS_CBCR,
- .parent = &blsp2_qup3_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_qup3_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp2_qup3_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup3_spi_apps_clk.c),
@@ -1809,10 +1809,10 @@
static struct branch_clk gcc_blsp2_qup4_i2c_apps_clk = {
.cbcr_reg = BLSP2_QUP4_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp2_qup4_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup4_i2c_apps_clk.c),
@@ -1821,9 +1821,9 @@
static struct branch_clk gcc_blsp2_qup4_spi_apps_clk = {
.cbcr_reg = BLSP2_QUP4_SPI_APPS_CBCR,
- .parent = &blsp2_qup4_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_qup4_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp2_qup4_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup4_spi_apps_clk.c),
@@ -1832,10 +1832,10 @@
static struct branch_clk gcc_blsp2_qup5_i2c_apps_clk = {
.cbcr_reg = BLSP2_QUP5_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp2_qup5_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup5_i2c_apps_clk.c),
@@ -1844,9 +1844,9 @@
static struct branch_clk gcc_blsp2_qup5_spi_apps_clk = {
.cbcr_reg = BLSP2_QUP5_SPI_APPS_CBCR,
- .parent = &blsp2_qup5_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_qup5_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp2_qup5_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup5_spi_apps_clk.c),
@@ -1855,10 +1855,10 @@
static struct branch_clk gcc_blsp2_qup6_i2c_apps_clk = {
.cbcr_reg = BLSP2_QUP6_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp2_qup6_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup6_i2c_apps_clk.c),
@@ -1867,9 +1867,9 @@
static struct branch_clk gcc_blsp2_qup6_spi_apps_clk = {
.cbcr_reg = BLSP2_QUP6_SPI_APPS_CBCR,
- .parent = &blsp2_qup6_spi_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_qup6_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp2_qup6_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_qup6_spi_apps_clk.c),
@@ -1878,9 +1878,9 @@
static struct branch_clk gcc_blsp2_uart1_apps_clk = {
.cbcr_reg = BLSP2_UART1_APPS_CBCR,
- .parent = &blsp2_uart1_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_uart1_apps_clk_src.c,
.dbg_name = "gcc_blsp2_uart1_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_uart1_apps_clk.c),
@@ -1889,9 +1889,9 @@
static struct branch_clk gcc_blsp2_uart2_apps_clk = {
.cbcr_reg = BLSP2_UART2_APPS_CBCR,
- .parent = &blsp2_uart2_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_uart2_apps_clk_src.c,
.dbg_name = "gcc_blsp2_uart2_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_uart2_apps_clk.c),
@@ -1900,9 +1900,9 @@
static struct branch_clk gcc_blsp2_uart3_apps_clk = {
.cbcr_reg = BLSP2_UART3_APPS_CBCR,
- .parent = &blsp2_uart3_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_uart3_apps_clk_src.c,
.dbg_name = "gcc_blsp2_uart3_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_uart3_apps_clk.c),
@@ -1911,9 +1911,9 @@
static struct branch_clk gcc_blsp2_uart4_apps_clk = {
.cbcr_reg = BLSP2_UART4_APPS_CBCR,
- .parent = &blsp2_uart4_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_uart4_apps_clk_src.c,
.dbg_name = "gcc_blsp2_uart4_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_uart4_apps_clk.c),
@@ -1922,9 +1922,9 @@
static struct branch_clk gcc_blsp2_uart5_apps_clk = {
.cbcr_reg = BLSP2_UART5_APPS_CBCR,
- .parent = &blsp2_uart5_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_uart5_apps_clk_src.c,
.dbg_name = "gcc_blsp2_uart5_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_uart5_apps_clk.c),
@@ -1933,9 +1933,9 @@
static struct branch_clk gcc_blsp2_uart6_apps_clk = {
.cbcr_reg = BLSP2_UART6_APPS_CBCR,
- .parent = &blsp2_uart6_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp2_uart6_apps_clk_src.c,
.dbg_name = "gcc_blsp2_uart6_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp2_uart6_apps_clk.c),
@@ -2016,9 +2016,9 @@
static struct branch_clk gcc_gp1_clk = {
.cbcr_reg = GP1_CBCR,
- .parent = &gp1_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &gp1_clk_src.c,
.dbg_name = "gcc_gp1_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_gp1_clk.c),
@@ -2027,9 +2027,9 @@
static struct branch_clk gcc_gp2_clk = {
.cbcr_reg = GP2_CBCR,
- .parent = &gp2_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &gp2_clk_src.c,
.dbg_name = "gcc_gp2_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_gp2_clk.c),
@@ -2038,9 +2038,9 @@
static struct branch_clk gcc_gp3_clk = {
.cbcr_reg = GP3_CBCR,
- .parent = &gp3_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &gp3_clk_src.c,
.dbg_name = "gcc_gp3_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_gp3_clk.c),
@@ -2049,9 +2049,9 @@
static struct branch_clk gcc_pdm2_clk = {
.cbcr_reg = PDM2_CBCR,
- .parent = &pdm2_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &pdm2_clk_src.c,
.dbg_name = "gcc_pdm2_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_pdm2_clk.c),
@@ -2094,9 +2094,9 @@
static struct branch_clk gcc_sdcc1_apps_clk = {
.cbcr_reg = SDCC1_APPS_CBCR,
- .parent = &sdcc1_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &sdcc1_apps_clk_src.c,
.dbg_name = "gcc_sdcc1_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_sdcc1_apps_clk.c),
@@ -2116,9 +2116,9 @@
static struct branch_clk gcc_sdcc2_apps_clk = {
.cbcr_reg = SDCC2_APPS_CBCR,
- .parent = &sdcc2_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &sdcc2_apps_clk_src.c,
.dbg_name = "gcc_sdcc2_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_sdcc2_apps_clk.c),
@@ -2138,9 +2138,9 @@
static struct branch_clk gcc_sdcc3_apps_clk = {
.cbcr_reg = SDCC3_APPS_CBCR,
- .parent = &sdcc3_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &sdcc3_apps_clk_src.c,
.dbg_name = "gcc_sdcc3_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_sdcc3_apps_clk.c),
@@ -2160,9 +2160,9 @@
static struct branch_clk gcc_sdcc4_apps_clk = {
.cbcr_reg = SDCC4_APPS_CBCR,
- .parent = &sdcc4_apps_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &sdcc4_apps_clk_src.c,
.dbg_name = "gcc_sdcc4_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_sdcc4_apps_clk.c),
@@ -2182,9 +2182,9 @@
static struct branch_clk gcc_tsif_ref_clk = {
.cbcr_reg = TSIF_REF_CBCR,
- .parent = &tsif_ref_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &tsif_ref_clk_src.c,
.dbg_name = "gcc_tsif_ref_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_tsif_ref_clk.c),
@@ -2193,10 +2193,10 @@
struct branch_clk gcc_sys_noc_usb3_axi_clk = {
.cbcr_reg = SYS_NOC_USB3_AXI_CBCR,
- .parent = &usb30_master_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb30_master_clk_src.c,
.dbg_name = "gcc_sys_noc_usb3_axi_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_sys_noc_usb3_axi_clk.c),
@@ -2206,10 +2206,10 @@
static struct branch_clk gcc_usb30_master_clk = {
.cbcr_reg = USB30_MASTER_CBCR,
.bcr_reg = USB_30_BCR,
- .parent = &usb30_master_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb30_master_clk_src.c,
.dbg_name = "gcc_usb30_master_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb30_master_clk.c),
@@ -2219,9 +2219,9 @@
static struct branch_clk gcc_usb30_mock_utmi_clk = {
.cbcr_reg = USB30_MOCK_UTMI_CBCR,
- .parent = &usb30_mock_utmi_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb30_mock_utmi_clk_src.c,
.dbg_name = "gcc_usb30_mock_utmi_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb30_mock_utmi_clk.c),
@@ -2275,9 +2275,9 @@
static struct branch_clk gcc_usb_hs_system_clk = {
.cbcr_reg = USB_HS_SYSTEM_CBCR,
.bcr_reg = USB_HS_BCR,
- .parent = &usb_hs_system_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb_hs_system_clk_src.c,
.dbg_name = "gcc_usb_hs_system_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb_hs_system_clk.c),
@@ -2298,9 +2298,9 @@
static struct branch_clk gcc_usb_hsic_clk = {
.cbcr_reg = USB_HSIC_CBCR,
.bcr_reg = USB_HS_HSIC_BCR,
- .parent = &usb_hsic_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb_hsic_clk_src.c,
.dbg_name = "gcc_usb_hsic_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb_hsic_clk.c),
@@ -2309,9 +2309,9 @@
static struct branch_clk gcc_usb_hsic_io_cal_clk = {
.cbcr_reg = USB_HSIC_IO_CAL_CBCR,
- .parent = &usb_hsic_io_cal_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb_hsic_io_cal_clk_src.c,
.dbg_name = "gcc_usb_hsic_io_cal_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb_hsic_io_cal_clk.c),
@@ -2320,9 +2320,9 @@
static struct branch_clk gcc_usb_hsic_system_clk = {
.cbcr_reg = USB_HSIC_SYSTEM_CBCR,
- .parent = &usb_hsic_system_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb_hsic_system_clk_src.c,
.dbg_name = "gcc_usb_hsic_system_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb_hsic_system_clk.c),
@@ -2807,18 +2807,15 @@
},
};
-static struct clk *dsi_pll_clk_get_parent(struct clk *c)
-{
- return &cxo_clk_src.c;
-}
-
static struct clk dsipll0_byte_clk_src = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "dsipll0_byte_clk_src",
.ops = &clk_ops_dsi_byte_pll,
CLK_INIT(dsipll0_byte_clk_src),
};
static struct clk dsipll0_pixel_clk_src = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "dsipll0_pixel_clk_src",
.ops = &clk_ops_dsi_pixel_pll,
CLK_INIT(dsipll0_pixel_clk_src),
@@ -2900,6 +2897,7 @@
.current_freq = &byte_freq,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &dsipll0_byte_clk_src,
.dbg_name = "byte0_clk_src",
.ops = &clk_ops_byte,
VDD_DIG_FMAX_MAP3(LOW, 93800000, NOMINAL, 187500000,
@@ -2913,6 +2911,7 @@
.current_freq = &byte_freq,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &dsipll0_byte_clk_src,
.dbg_name = "byte1_clk_src",
.ops = &clk_ops_byte,
VDD_DIG_FMAX_MAP3(LOW, 93800000, NOMINAL, 187500000,
@@ -3045,19 +3044,14 @@
return rc;
}
-static struct clk *hdmi_pll_clk_get_parent(struct clk *c)
-{
- return &cxo_clk_src.c;
-}
-
static struct clk_ops clk_ops_hdmi_pll = {
.enable = hdmi_pll_clk_enable,
.disable = hdmi_pll_clk_disable,
.set_rate = hdmi_pll_clk_set_rate,
- .get_parent = hdmi_pll_clk_get_parent,
};
static struct clk hdmipll_clk_src = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "hdmipll_clk_src",
.ops = &clk_ops_hdmi_pll,
CLK_INIT(hdmipll_clk_src),
@@ -3127,6 +3121,7 @@
.current_freq = &pixel_freq,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &dsipll0_pixel_clk_src,
.dbg_name = "pclk0_clk_src",
.ops = &clk_ops_pixel,
VDD_DIG_FMAX_MAP2(LOW, 125000000, NOMINAL, 250000000),
@@ -3139,6 +3134,7 @@
.current_freq = &pixel_freq,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &dsipll0_pixel_clk_src,
.dbg_name = "pclk1_clk_src",
.ops = &clk_ops_pixel,
VDD_DIG_FMAX_MAP2(LOW, 125000000, NOMINAL, 250000000),
@@ -3203,10 +3199,10 @@
static struct branch_clk camss_cci_cci_clk = {
.cbcr_reg = CAMSS_CCI_CCI_CBCR,
- .parent = &cci_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &cci_clk_src.c,
.dbg_name = "camss_cci_cci_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_cci_cci_clk.c),
@@ -3226,10 +3222,10 @@
static struct branch_clk camss_csi0_clk = {
.cbcr_reg = CAMSS_CSI0_CBCR,
- .parent = &csi0_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi0_clk_src.c,
.dbg_name = "camss_csi0_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi0_clk.c),
@@ -3238,10 +3234,10 @@
static struct branch_clk camss_csi0phy_clk = {
.cbcr_reg = CAMSS_CSI0PHY_CBCR,
- .parent = &csi0_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi0_clk_src.c,
.dbg_name = "camss_csi0phy_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi0phy_clk.c),
@@ -3250,10 +3246,10 @@
static struct branch_clk camss_csi0pix_clk = {
.cbcr_reg = CAMSS_CSI0PIX_CBCR,
- .parent = &csi0_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi0_clk_src.c,
.dbg_name = "camss_csi0pix_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi0pix_clk.c),
@@ -3262,10 +3258,10 @@
static struct branch_clk camss_csi0rdi_clk = {
.cbcr_reg = CAMSS_CSI0RDI_CBCR,
- .parent = &csi0_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi0_clk_src.c,
.dbg_name = "camss_csi0rdi_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi0rdi_clk.c),
@@ -3285,10 +3281,10 @@
static struct branch_clk camss_csi1_clk = {
.cbcr_reg = CAMSS_CSI1_CBCR,
- .parent = &csi1_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi1_clk_src.c,
.dbg_name = "camss_csi1_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi1_clk.c),
@@ -3297,10 +3293,10 @@
static struct branch_clk camss_csi1phy_clk = {
.cbcr_reg = CAMSS_CSI1PHY_CBCR,
- .parent = &csi1_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi1_clk_src.c,
.dbg_name = "camss_csi1phy_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi1phy_clk.c),
@@ -3309,10 +3305,10 @@
static struct branch_clk camss_csi1pix_clk = {
.cbcr_reg = CAMSS_CSI1PIX_CBCR,
- .parent = &csi1_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi1_clk_src.c,
.dbg_name = "camss_csi1pix_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi1pix_clk.c),
@@ -3321,10 +3317,10 @@
static struct branch_clk camss_csi1rdi_clk = {
.cbcr_reg = CAMSS_CSI1RDI_CBCR,
- .parent = &csi1_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi1_clk_src.c,
.dbg_name = "camss_csi1rdi_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi1rdi_clk.c),
@@ -3344,10 +3340,10 @@
static struct branch_clk camss_csi2_clk = {
.cbcr_reg = CAMSS_CSI2_CBCR,
- .parent = &csi2_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi2_clk_src.c,
.dbg_name = "camss_csi2_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi2_clk.c),
@@ -3356,10 +3352,10 @@
static struct branch_clk camss_csi2phy_clk = {
.cbcr_reg = CAMSS_CSI2PHY_CBCR,
- .parent = &csi2_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi2_clk_src.c,
.dbg_name = "camss_csi2phy_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi2phy_clk.c),
@@ -3368,10 +3364,10 @@
static struct branch_clk camss_csi2pix_clk = {
.cbcr_reg = CAMSS_CSI2PIX_CBCR,
- .parent = &csi2_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi2_clk_src.c,
.dbg_name = "camss_csi2pix_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi2pix_clk.c),
@@ -3380,10 +3376,10 @@
static struct branch_clk camss_csi2rdi_clk = {
.cbcr_reg = CAMSS_CSI2RDI_CBCR,
- .parent = &csi2_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi2_clk_src.c,
.dbg_name = "camss_csi2rdi_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi2rdi_clk.c),
@@ -3403,10 +3399,10 @@
static struct branch_clk camss_csi3_clk = {
.cbcr_reg = CAMSS_CSI3_CBCR,
- .parent = &csi3_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi3_clk_src.c,
.dbg_name = "camss_csi3_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi3_clk.c),
@@ -3415,10 +3411,10 @@
static struct branch_clk camss_csi3phy_clk = {
.cbcr_reg = CAMSS_CSI3PHY_CBCR,
- .parent = &csi3_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi3_clk_src.c,
.dbg_name = "camss_csi3phy_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi3phy_clk.c),
@@ -3427,10 +3423,10 @@
static struct branch_clk camss_csi3pix_clk = {
.cbcr_reg = CAMSS_CSI3PIX_CBCR,
- .parent = &csi3_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi3_clk_src.c,
.dbg_name = "camss_csi3pix_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi3pix_clk.c),
@@ -3439,10 +3435,10 @@
static struct branch_clk camss_csi3rdi_clk = {
.cbcr_reg = CAMSS_CSI3RDI_CBCR,
- .parent = &csi3_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi3_clk_src.c,
.dbg_name = "camss_csi3rdi_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi3rdi_clk.c),
@@ -3451,10 +3447,10 @@
static struct branch_clk camss_csi_vfe0_clk = {
.cbcr_reg = CAMSS_CSI_VFE0_CBCR,
- .parent = &vfe0_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &vfe0_clk_src.c,
.dbg_name = "camss_csi_vfe0_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi_vfe0_clk.c),
@@ -3463,10 +3459,10 @@
static struct branch_clk camss_csi_vfe1_clk = {
.cbcr_reg = CAMSS_CSI_VFE1_CBCR,
- .parent = &vfe1_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &vfe1_clk_src.c,
.dbg_name = "camss_csi_vfe1_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_csi_vfe1_clk.c),
@@ -3475,10 +3471,10 @@
static struct branch_clk camss_gp0_clk = {
.cbcr_reg = CAMSS_GP0_CBCR,
- .parent = &mmss_gp0_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &mmss_gp0_clk_src.c,
.dbg_name = "camss_gp0_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_gp0_clk.c),
@@ -3487,10 +3483,10 @@
static struct branch_clk camss_gp1_clk = {
.cbcr_reg = CAMSS_GP1_CBCR,
- .parent = &mmss_gp1_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &mmss_gp1_clk_src.c,
.dbg_name = "camss_gp1_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_gp1_clk.c),
@@ -3510,10 +3506,10 @@
static struct branch_clk camss_jpeg_jpeg0_clk = {
.cbcr_reg = CAMSS_JPEG_JPEG0_CBCR,
- .parent = &jpeg0_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &jpeg0_clk_src.c,
.dbg_name = "camss_jpeg_jpeg0_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_jpeg_jpeg0_clk.c),
@@ -3522,10 +3518,10 @@
static struct branch_clk camss_jpeg_jpeg1_clk = {
.cbcr_reg = CAMSS_JPEG_JPEG1_CBCR,
- .parent = &jpeg1_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &jpeg1_clk_src.c,
.dbg_name = "camss_jpeg_jpeg1_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_jpeg_jpeg1_clk.c),
@@ -3534,10 +3530,10 @@
static struct branch_clk camss_jpeg_jpeg2_clk = {
.cbcr_reg = CAMSS_JPEG_JPEG2_CBCR,
- .parent = &jpeg2_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &jpeg2_clk_src.c,
.dbg_name = "camss_jpeg_jpeg2_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_jpeg_jpeg2_clk.c),
@@ -3557,10 +3553,10 @@
static struct branch_clk camss_jpeg_jpeg_axi_clk = {
.cbcr_reg = CAMSS_JPEG_JPEG_AXI_CBCR,
- .parent = &axi_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &axi_clk_src.c,
.dbg_name = "camss_jpeg_jpeg_axi_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_jpeg_jpeg_axi_clk.c),
@@ -3569,10 +3565,10 @@
static struct branch_clk camss_jpeg_jpeg_ocmemnoc_clk = {
.cbcr_reg = CAMSS_JPEG_JPEG_OCMEMNOC_CBCR,
- .parent = &ocmemnoc_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &ocmemnoc_clk_src.c,
.dbg_name = "camss_jpeg_jpeg_ocmemnoc_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_jpeg_jpeg_ocmemnoc_clk.c),
@@ -3581,10 +3577,10 @@
static struct branch_clk camss_mclk0_clk = {
.cbcr_reg = CAMSS_MCLK0_CBCR,
- .parent = &mclk0_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &mclk0_clk_src.c,
.dbg_name = "camss_mclk0_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_mclk0_clk.c),
@@ -3593,10 +3589,10 @@
static struct branch_clk camss_mclk1_clk = {
.cbcr_reg = CAMSS_MCLK1_CBCR,
- .parent = &mclk1_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &mclk1_clk_src.c,
.dbg_name = "camss_mclk1_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_mclk1_clk.c),
@@ -3605,10 +3601,10 @@
static struct branch_clk camss_mclk2_clk = {
.cbcr_reg = CAMSS_MCLK2_CBCR,
- .parent = &mclk2_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &mclk2_clk_src.c,
.dbg_name = "camss_mclk2_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_mclk2_clk.c),
@@ -3617,10 +3613,10 @@
static struct branch_clk camss_mclk3_clk = {
.cbcr_reg = CAMSS_MCLK3_CBCR,
- .parent = &mclk3_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &mclk3_clk_src.c,
.dbg_name = "camss_mclk3_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_mclk3_clk.c),
@@ -3640,10 +3636,10 @@
static struct branch_clk camss_phy0_csi0phytimer_clk = {
.cbcr_reg = CAMSS_PHY0_CSI0PHYTIMER_CBCR,
- .parent = &csi0phytimer_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi0phytimer_clk_src.c,
.dbg_name = "camss_phy0_csi0phytimer_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_phy0_csi0phytimer_clk.c),
@@ -3652,10 +3648,10 @@
static struct branch_clk camss_phy1_csi1phytimer_clk = {
.cbcr_reg = CAMSS_PHY1_CSI1PHYTIMER_CBCR,
- .parent = &csi1phytimer_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi1phytimer_clk_src.c,
.dbg_name = "camss_phy1_csi1phytimer_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_phy1_csi1phytimer_clk.c),
@@ -3664,10 +3660,10 @@
static struct branch_clk camss_phy2_csi2phytimer_clk = {
.cbcr_reg = CAMSS_PHY2_CSI2PHYTIMER_CBCR,
- .parent = &csi2phytimer_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &csi2phytimer_clk_src.c,
.dbg_name = "camss_phy2_csi2phytimer_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_phy2_csi2phytimer_clk.c),
@@ -3698,10 +3694,10 @@
static struct branch_clk camss_vfe_cpp_clk = {
.cbcr_reg = CAMSS_VFE_CPP_CBCR,
- .parent = &cpp_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &cpp_clk_src.c,
.dbg_name = "camss_vfe_cpp_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_vfe_cpp_clk.c),
@@ -3710,10 +3706,10 @@
static struct branch_clk camss_vfe_vfe0_clk = {
.cbcr_reg = CAMSS_VFE_VFE0_CBCR,
- .parent = &vfe0_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &vfe0_clk_src.c,
.dbg_name = "camss_vfe_vfe0_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_vfe_vfe0_clk.c),
@@ -3722,10 +3718,10 @@
static struct branch_clk camss_vfe_vfe1_clk = {
.cbcr_reg = CAMSS_VFE_VFE1_CBCR,
- .parent = &vfe1_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &vfe1_clk_src.c,
.dbg_name = "camss_vfe_vfe1_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_vfe_vfe1_clk.c),
@@ -3745,10 +3741,10 @@
static struct branch_clk camss_vfe_vfe_axi_clk = {
.cbcr_reg = CAMSS_VFE_VFE_AXI_CBCR,
- .parent = &axi_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &axi_clk_src.c,
.dbg_name = "camss_vfe_vfe_axi_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_vfe_vfe_axi_clk.c),
@@ -3757,10 +3753,10 @@
static struct branch_clk camss_vfe_vfe_ocmemnoc_clk = {
.cbcr_reg = CAMSS_VFE_VFE_OCMEMNOC_CBCR,
- .parent = &ocmemnoc_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &ocmemnoc_clk_src.c,
.dbg_name = "camss_vfe_vfe_ocmemnoc_clk",
.ops = &clk_ops_branch,
CLK_INIT(camss_vfe_vfe_ocmemnoc_clk.c),
@@ -3780,10 +3776,10 @@
static struct branch_clk mdss_axi_clk = {
.cbcr_reg = MDSS_AXI_CBCR,
- .parent = &axi_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &axi_clk_src.c,
.dbg_name = "mdss_axi_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_axi_clk.c),
@@ -3792,10 +3788,10 @@
static struct branch_clk mdss_byte0_clk = {
.cbcr_reg = MDSS_BYTE0_CBCR,
- .parent = &byte0_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &byte0_clk_src.c,
.dbg_name = "mdss_byte0_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_byte0_clk.c),
@@ -3804,10 +3800,10 @@
static struct branch_clk mdss_byte1_clk = {
.cbcr_reg = MDSS_BYTE1_CBCR,
- .parent = &byte1_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &byte1_clk_src.c,
.dbg_name = "mdss_byte1_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_byte1_clk.c),
@@ -3816,10 +3812,10 @@
static struct branch_clk mdss_edpaux_clk = {
.cbcr_reg = MDSS_EDPAUX_CBCR,
- .parent = &edpaux_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &edpaux_clk_src.c,
.dbg_name = "mdss_edpaux_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_edpaux_clk.c),
@@ -3828,10 +3824,10 @@
static struct branch_clk mdss_edplink_clk = {
.cbcr_reg = MDSS_EDPLINK_CBCR,
- .parent = &edplink_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &edplink_clk_src.c,
.dbg_name = "mdss_edplink_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_edplink_clk.c),
@@ -3840,10 +3836,10 @@
static struct branch_clk mdss_edppixel_clk = {
.cbcr_reg = MDSS_EDPPIXEL_CBCR,
- .parent = &edppixel_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &edppixel_clk_src.c,
.dbg_name = "mdss_edppixel_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_edppixel_clk.c),
@@ -3852,10 +3848,10 @@
static struct branch_clk mdss_esc0_clk = {
.cbcr_reg = MDSS_ESC0_CBCR,
- .parent = &esc0_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &esc0_clk_src.c,
.dbg_name = "mdss_esc0_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_esc0_clk.c),
@@ -3864,10 +3860,10 @@
static struct branch_clk mdss_esc1_clk = {
.cbcr_reg = MDSS_ESC1_CBCR,
- .parent = &esc1_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &esc1_clk_src.c,
.dbg_name = "mdss_esc1_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_esc1_clk.c),
@@ -3876,10 +3872,10 @@
static struct branch_clk mdss_extpclk_clk = {
.cbcr_reg = MDSS_EXTPCLK_CBCR,
- .parent = &extpclk_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &extpclk_clk_src.c,
.dbg_name = "mdss_extpclk_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_extpclk_clk.c),
@@ -3899,10 +3895,10 @@
static struct branch_clk mdss_hdmi_clk = {
.cbcr_reg = MDSS_HDMI_CBCR,
- .parent = &hdmi_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &hdmi_clk_src.c,
.dbg_name = "mdss_hdmi_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_hdmi_clk.c),
@@ -3911,10 +3907,10 @@
static struct branch_clk mdss_mdp_clk = {
.cbcr_reg = MDSS_MDP_CBCR,
- .parent = &mdp_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &mdp_clk_src.c,
.dbg_name = "mdss_mdp_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_mdp_clk.c),
@@ -3923,10 +3919,10 @@
static struct branch_clk mdss_mdp_lut_clk = {
.cbcr_reg = MDSS_MDP_LUT_CBCR,
- .parent = &mdp_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &mdp_clk_src.c,
.dbg_name = "mdss_mdp_lut_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_mdp_lut_clk.c),
@@ -3935,10 +3931,10 @@
static struct branch_clk mdss_pclk0_clk = {
.cbcr_reg = MDSS_PCLK0_CBCR,
- .parent = &pclk0_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &pclk0_clk_src.c,
.dbg_name = "mdss_pclk0_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_pclk0_clk.c),
@@ -3947,10 +3943,10 @@
static struct branch_clk mdss_pclk1_clk = {
.cbcr_reg = MDSS_PCLK1_CBCR,
- .parent = &pclk1_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &pclk1_clk_src.c,
.dbg_name = "mdss_pclk1_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_pclk1_clk.c),
@@ -3959,10 +3955,10 @@
static struct branch_clk mdss_vsync_clk = {
.cbcr_reg = MDSS_VSYNC_CBCR,
- .parent = &vsync_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &vsync_clk_src.c,
.dbg_name = "mdss_vsync_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdss_vsync_clk.c),
@@ -3993,10 +3989,10 @@
static struct branch_clk mmss_mmssnoc_axi_clk = {
.cbcr_reg = MMSS_MMSSNOC_AXI_CBCR,
- .parent = &axi_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &axi_clk_src.c,
.dbg_name = "mmss_mmssnoc_axi_clk",
.ops = &clk_ops_branch,
CLK_INIT(mmss_mmssnoc_axi_clk.c),
@@ -4005,11 +4001,11 @@
static struct branch_clk mmss_s0_axi_clk = {
.cbcr_reg = MMSS_S0_AXI_CBCR,
- .parent = &axi_clk_src.c,
/* The bus driver needs set_rate to go through to the parent */
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &axi_clk_src.c,
.dbg_name = "mmss_s0_axi_clk",
.ops = &clk_ops_branch,
CLK_INIT(mmss_s0_axi_clk.c),
@@ -4019,11 +4015,11 @@
struct branch_clk ocmemnoc_clk = {
.cbcr_reg = OCMEMNOC_CBCR,
- .parent = &ocmemnoc_clk_src.c,
.has_sibling = 0,
.bcr_reg = 0x50b0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &ocmemnoc_clk_src.c,
.dbg_name = "ocmemnoc_clk",
.ops = &clk_ops_branch,
CLK_INIT(ocmemnoc_clk.c),
@@ -4032,10 +4028,10 @@
struct branch_clk ocmemcx_ocmemnoc_clk = {
.cbcr_reg = OCMEMCX_OCMEMNOC_CBCR,
- .parent = &ocmemnoc_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &ocmemnoc_clk_src.c,
.dbg_name = "ocmemcx_ocmemnoc_clk",
.ops = &clk_ops_branch,
CLK_INIT(ocmemcx_ocmemnoc_clk.c),
@@ -4055,10 +4051,10 @@
static struct branch_clk venus0_axi_clk = {
.cbcr_reg = VENUS0_AXI_CBCR,
- .parent = &axi_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &axi_clk_src.c,
.dbg_name = "venus0_axi_clk",
.ops = &clk_ops_branch,
CLK_INIT(venus0_axi_clk.c),
@@ -4067,10 +4063,10 @@
static struct branch_clk venus0_ocmemnoc_clk = {
.cbcr_reg = VENUS0_OCMEMNOC_CBCR,
- .parent = &ocmemnoc_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &ocmemnoc_clk_src.c,
.dbg_name = "venus0_ocmemnoc_clk",
.ops = &clk_ops_branch,
CLK_INIT(venus0_ocmemnoc_clk.c),
@@ -4079,10 +4075,10 @@
static struct branch_clk venus0_vcodec0_clk = {
.cbcr_reg = VENUS0_VCODEC0_CBCR,
- .parent = &vcodec0_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &vcodec0_clk_src.c,
.dbg_name = "venus0_vcodec0_clk",
.ops = &clk_ops_branch,
CLK_INIT(venus0_vcodec0_clk.c),
@@ -4091,10 +4087,10 @@
static struct branch_clk oxilicx_axi_clk = {
.cbcr_reg = OXILICX_AXI_CBCR,
- .parent = &axi_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &axi_clk_src.c,
.dbg_name = "oxilicx_axi_clk",
.ops = &clk_ops_branch,
CLK_INIT(oxilicx_axi_clk.c),
@@ -4103,9 +4099,9 @@
static struct branch_clk oxili_gfx3d_clk = {
.cbcr_reg = OXILI_GFX3D_CBCR,
- .parent = &oxili_gfx3d_clk_src.c,
.base = &virt_bases[MMSS_BASE],
.c = {
+ .parent = &oxili_gfx3d_clk_src.c,
.dbg_name = "oxili_gfx3d_clk",
.ops = &clk_ops_branch,
CLK_INIT(oxili_gfx3d_clk.c),
@@ -4145,9 +4141,9 @@
static struct branch_clk audio_core_slimbus_core_clk = {
.cbcr_reg = AUDIO_CORE_SLIMBUS_CORE_CBCR,
- .parent = &audio_core_slimbus_core_clk_src.c,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_slimbus_core_clk_src.c,
.dbg_name = "audio_core_slimbus_core_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_slimbus_core_clk.c),
@@ -4293,10 +4289,10 @@
static struct branch_clk audio_core_lpaif_codec_spkr_osr_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_CODEC_SPKR_OSR_CBCR,
- .parent = &audio_core_lpaif_codec_spkr_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_codec_spkr_clk_src.c,
.dbg_name = "audio_core_lpaif_codec_spkr_osr_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_codec_spkr_osr_clk.c),
@@ -4316,11 +4312,11 @@
static struct branch_clk audio_core_lpaif_codec_spkr_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_CODEC_SPKR_IBIT_CBCR,
- .parent = &audio_core_lpaif_codec_spkr_clk_src.c,
.has_sibling = 1,
.max_div = 15,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_codec_spkr_clk_src.c,
.dbg_name = "audio_core_lpaif_codec_spkr_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_codec_spkr_ibit_clk.c),
@@ -4329,10 +4325,10 @@
static struct branch_clk audio_core_lpaif_pri_osr_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PRI_OSR_CBCR,
- .parent = &audio_core_lpaif_pri_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pri_clk_src.c,
.dbg_name = "audio_core_lpaif_pri_osr_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pri_osr_clk.c),
@@ -4352,11 +4348,11 @@
static struct branch_clk audio_core_lpaif_pri_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PRI_IBIT_CBCR,
- .parent = &audio_core_lpaif_pri_clk_src.c,
.has_sibling = 1,
.max_div = 15,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pri_clk_src.c,
.dbg_name = "audio_core_lpaif_pri_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pri_ibit_clk.c),
@@ -4365,10 +4361,10 @@
static struct branch_clk audio_core_lpaif_sec_osr_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_SEC_OSR_CBCR,
- .parent = &audio_core_lpaif_sec_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_sec_clk_src.c,
.dbg_name = "audio_core_lpaif_sec_osr_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_sec_osr_clk.c),
@@ -4388,11 +4384,11 @@
static struct branch_clk audio_core_lpaif_sec_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_SEC_IBIT_CBCR,
- .parent = &audio_core_lpaif_sec_clk_src.c,
.has_sibling = 1,
.max_div = 15,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_sec_clk_src.c,
.dbg_name = "audio_core_lpaif_sec_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_sec_ibit_clk.c),
@@ -4401,10 +4397,10 @@
static struct branch_clk audio_core_lpaif_ter_osr_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_TER_OSR_CBCR,
- .parent = &audio_core_lpaif_ter_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_ter_clk_src.c,
.dbg_name = "audio_core_lpaif_ter_osr_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_ter_osr_clk.c),
@@ -4424,11 +4420,11 @@
static struct branch_clk audio_core_lpaif_ter_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_TER_IBIT_CBCR,
- .parent = &audio_core_lpaif_ter_clk_src.c,
.has_sibling = 1,
.max_div = 15,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_ter_clk_src.c,
.dbg_name = "audio_core_lpaif_ter_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_ter_ibit_clk.c),
@@ -4437,10 +4433,10 @@
static struct branch_clk audio_core_lpaif_quad_osr_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_QUAD_OSR_CBCR,
- .parent = &audio_core_lpaif_quad_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_quad_clk_src.c,
.dbg_name = "audio_core_lpaif_quad_osr_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_quad_osr_clk.c),
@@ -4460,11 +4456,11 @@
static struct branch_clk audio_core_lpaif_quad_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_QUAD_IBIT_CBCR,
- .parent = &audio_core_lpaif_quad_clk_src.c,
.has_sibling = 1,
.max_div = 15,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_quad_clk_src.c,
.dbg_name = "audio_core_lpaif_quad_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_quad_ibit_clk.c),
@@ -4484,10 +4480,10 @@
static struct branch_clk audio_core_lpaif_pcm0_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PCM0_IBIT_CBCR,
- .parent = &audio_core_lpaif_pcm0_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pcm0_clk_src.c,
.dbg_name = "audio_core_lpaif_pcm0_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pcm0_ibit_clk.c),
@@ -4496,10 +4492,10 @@
static struct branch_clk audio_core_lpaif_pcm1_ebit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PCM1_EBIT_CBCR,
- .parent = &audio_core_lpaif_pcm1_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pcm1_clk_src.c,
.dbg_name = "audio_core_lpaif_pcm1_ebit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pcm1_ebit_clk.c),
@@ -4508,10 +4504,10 @@
static struct branch_clk audio_core_lpaif_pcm1_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PCM1_IBIT_CBCR,
- .parent = &audio_core_lpaif_pcm1_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pcm1_clk_src.c,
.dbg_name = "audio_core_lpaif_pcm1_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pcm1_ibit_clk.c),
@@ -4520,9 +4516,9 @@
struct branch_clk audio_core_lpaif_pcmoe_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PCM_DATA_OE_CBCR,
- .parent = &audio_core_lpaif_pcmoe_clk_src.c,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pcmoe_clk_src.c,
.dbg_name = "audio_core_lpaif_pcmoe_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pcmoe_clk.c),
@@ -5681,11 +5677,9 @@
{
clk_ops_byte = clk_ops_rcg_mnd;
clk_ops_byte.set_rate = set_rate_byte;
- clk_ops_dsi_byte_pll.get_parent = dsi_pll_clk_get_parent;
clk_ops_pixel = clk_ops_rcg;
clk_ops_pixel.set_rate = set_rate_pixel;
- clk_ops_dsi_pixel_pll.get_parent = dsi_pll_clk_get_parent;
mdss_clk_ctrl_init();
}
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index 5a9799a..2ad425d 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -317,8 +317,8 @@
.en_mask = BIT(8),
.status_reg = BB_PLL8_STATUS_REG,
.status_mask = BIT(16),
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "pll8_clk",
.rate = 384000000,
.ops = &clk_ops_pll_vote,
@@ -328,8 +328,8 @@
static struct pll_clk pll2_clk = {
.mode_reg = MM_PLL1_MODE_REG,
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "pll2_clk",
.rate = 800000000,
.ops = &clk_ops_local_pll,
@@ -339,8 +339,8 @@
static struct pll_clk pll3_clk = {
.mode_reg = MM_PLL2_MODE_REG,
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "pll3_clk",
.rate = 0, /* TODO: Detect rate dynamically */
.ops = &clk_ops_local_pll,
@@ -360,11 +360,6 @@
msm_rpm_set_noirq(MSM_RPM_CTX_SET_0, &iv, 1);
}
-static struct clk *pll4_clk_get_parent(struct clk *c)
-{
- return &pxo_clk.c;
-}
-
static bool pll4_clk_is_local(struct clk *c)
{
return false;
@@ -383,13 +378,13 @@
static struct clk_ops clk_ops_pll4 = {
.enable = pll4_clk_enable,
.disable = pll4_clk_disable,
- .get_parent = pll4_clk_get_parent,
.is_local = pll4_clk_is_local,
.handoff = pll4_clk_handoff,
};
static struct fixed_clk pll4_clk = {
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "pll4_clk",
.rate = 540672000,
.ops = &clk_ops_pll4,
@@ -1386,8 +1381,8 @@
.halt_reg = CLK_HALT_CFPB_STATEA_REG,
.halt_bit = 15,
},
- .parent = &usb_fs1_src_clk.c,
.c = {
+ .parent = &usb_fs1_src_clk.c,
.dbg_name = "usb_fs1_xcvr_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_fs1_xcvr_clk.c),
@@ -1403,8 +1398,8 @@
.halt_reg = CLK_HALT_CFPB_STATEA_REG,
.halt_bit = 16,
},
- .parent = &usb_fs1_src_clk.c,
.c = {
+ .parent = &usb_fs1_src_clk.c,
.dbg_name = "usb_fs1_sys_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_fs1_sys_clk.c),
@@ -1421,8 +1416,8 @@
.halt_reg = CLK_HALT_CFPB_STATEA_REG,
.halt_bit = 12,
},
- .parent = &usb_fs2_src_clk.c,
.c = {
+ .parent = &usb_fs2_src_clk.c,
.dbg_name = "usb_fs2_xcvr_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_fs2_xcvr_clk.c),
@@ -1438,8 +1433,8 @@
.halt_reg = CLK_HALT_CFPB_STATEA_REG,
.halt_bit = 13,
},
- .parent = &usb_fs2_src_clk.c,
.c = {
+ .parent = &usb_fs2_src_clk.c,
.dbg_name = "usb_fs2_sys_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_fs2_sys_clk.c),
@@ -1454,8 +1449,8 @@
.halt_reg = CLK_HALT_CFPB_STATEC_REG,
.halt_bit = 0,
},
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "ce2_p_clk",
.ops = &clk_ops_branch,
CLK_INIT(ce2_p_clk.c),
@@ -1808,8 +1803,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 14,
},
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "adm0_clk",
.ops = &clk_ops_branch,
CLK_INIT(adm0_clk.c),
@@ -1839,8 +1834,8 @@
.halt_check = HALT_VOTED,
.halt_bit = 12,
},
- .parent = &pxo_clk.c,
.c = {
+ .parent = &pxo_clk.c,
.dbg_name = "adm1_clk",
.ops = &clk_ops_branch,
CLK_INIT(adm1_clk.c),
@@ -2044,8 +2039,8 @@
.halt_reg = DBG_BUS_VEC_B_REG,
.halt_bit = 13,
},
- .parent = &csi_src_clk.c,
.c = {
+ .parent = &csi_src_clk.c,
.dbg_name = "csi0_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi0_clk.c),
@@ -2061,8 +2056,8 @@
.halt_reg = DBG_BUS_VEC_B_REG,
.halt_bit = 14,
},
- .parent = &csi_src_clk.c,
.c = {
+ .parent = &csi_src_clk.c,
.dbg_name = "csi1_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi1_clk.c),
@@ -2566,8 +2561,8 @@
.halt_reg = DBG_BUS_VEC_C_REG,
.halt_bit = 21,
},
- .parent = &pixel_mdp_clk.c,
.c = {
+ .parent = &pixel_mdp_clk.c,
.dbg_name = "pixel_lcdc_clk",
.ops = &clk_ops_branch,
CLK_INIT(pixel_lcdc_clk.c),
@@ -2695,8 +2690,8 @@
.halt_reg = DBG_BUS_VEC_D_REG,
.halt_bit = 8,
},
- .parent = &tv_src_clk.c,
.c = {
+ .parent = &tv_src_clk.c,
.dbg_name = "tv_enc_clk",
.ops = &clk_ops_branch,
CLK_INIT(tv_enc_clk.c),
@@ -2710,8 +2705,8 @@
.halt_reg = DBG_BUS_VEC_D_REG,
.halt_bit = 9,
},
- .parent = &tv_src_clk.c,
.c = {
+ .parent = &tv_src_clk.c,
.dbg_name = "tv_dac_clk",
.ops = &clk_ops_branch,
CLK_INIT(tv_dac_clk.c),
@@ -2727,8 +2722,8 @@
.halt_reg = DBG_BUS_VEC_D_REG,
.halt_bit = 11,
},
- .parent = &tv_src_clk.c,
.c = {
+ .parent = &tv_src_clk.c,
.dbg_name = "mdp_tv_clk",
.ops = &clk_ops_branch,
CLK_INIT(mdp_tv_clk.c),
@@ -2744,8 +2739,8 @@
.halt_reg = DBG_BUS_VEC_D_REG,
.halt_bit = 10,
},
- .parent = &tv_src_clk.c,
.c = {
+ .parent = &tv_src_clk.c,
.dbg_name = "hdmi_tv_clk",
.ops = &clk_ops_branch,
CLK_INIT(hdmi_tv_clk.c),
@@ -2934,8 +2929,8 @@
.halt_reg = DBG_BUS_VEC_B_REG,
.halt_bit = 7,
},
- .parent = &vfe_clk.c,
.c = {
+ .parent = &vfe_clk.c,
.dbg_name = "csi0_vfe_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi0_vfe_clk.c),
@@ -2951,8 +2946,8 @@
.halt_reg = DBG_BUS_VEC_B_REG,
.halt_bit = 8,
},
- .parent = &vfe_clk.c,
.c = {
+ .parent = &vfe_clk.c,
.dbg_name = "csi1_vfe_clk",
.ops = &clk_ops_branch,
CLK_INIT(csi1_vfe_clk.c),
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index 338361b..fffbcea 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -228,10 +228,10 @@
.en_mask = BIT(0),
.status_reg = BB_PLL0_STATUS_REG,
.status_mask = BIT(16),
- .parent = &cxo_clk.c,
.soft_vote = &soft_vote_pll0,
.soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
.c = {
+ .parent = &cxo_clk.c,
.dbg_name = "pll0_clk",
.rate = 276000000,
.ops = &clk_ops_pll_acpu_vote,
@@ -259,8 +259,8 @@
.en_mask = BIT(4),
.status_reg = LCC_PLL0_STATUS_REG,
.status_mask = BIT(16),
- .parent = &cxo_clk.c,
.c = {
+ .parent = &cxo_clk.c,
.dbg_name = "pll4_clk",
.rate = 393216000,
.ops = &clk_ops_pll_vote,
@@ -275,10 +275,10 @@
.en_mask = BIT(8),
.status_reg = BB_PLL8_STATUS_REG,
.status_mask = BIT(16),
- .parent = &cxo_clk.c,
.soft_vote = &soft_vote_pll8,
.soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
.c = {
+ .parent = &cxo_clk.c,
.dbg_name = "pll8_clk",
.rate = 384000000,
.ops = &clk_ops_pll_acpu_vote,
@@ -316,8 +316,8 @@
.en_mask = BIT(11),
.status_reg = BB_PLL14_STATUS_REG,
.status_mask = BIT(16),
- .parent = &cxo_clk.c,
.c = {
+ .parent = &cxo_clk.c,
.dbg_name = "pll14_clk",
.rate = 480000000,
.ops = &clk_ops_pll_vote,
@@ -767,8 +767,8 @@
.halt_reg = CLK_HALT_DFAB_STATE_REG,
.halt_bit = 8,
},
- .parent = &cxo_clk.c,
.c = {
+ .parent = &cxo_clk.c,
.dbg_name = "usb_hsic_hsio_cal_clk",
.ops = &clk_ops_branch,
CLK_INIT(usb_hsic_hsio_cal_clk.c),
@@ -1295,8 +1295,8 @@
.halt_check = ENABLE,
.halt_bit = 1,
},
- .parent = &audio_slimbus_clk.c,
.c = {
+ .parent = &audio_slimbus_clk.c,
.dbg_name = "sps_slimbus_clk",
.ops = &clk_ops_branch,
CLK_INIT(sps_slimbus_clk.c),
@@ -1310,8 +1310,8 @@
.halt_reg = CLK_HALT_DFAB_STATE_REG,
.halt_bit = 28,
},
- .parent = &sps_slimbus_clk.c,
.c = {
+ .parent = &sps_slimbus_clk.c,
.dbg_name = "slimbus_xo_src_clk",
.ops = &clk_ops_branch,
CLK_INIT(slimbus_xo_src_clk.c),
diff --git a/arch/arm/mach-msm/clock-9625.c b/arch/arm/mach-msm/clock-9625.c
index 9f6a00c..33ec10a 100644
--- a/arch/arm/mach-msm/clock-9625.c
+++ b/arch/arm/mach-msm/clock-9625.c
@@ -388,11 +388,11 @@
.en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE_REG,
.status_reg = (void __iomem *)GPLL0_STATUS_REG,
.status_mask = BIT(17),
- .parent = &cxo_clk_src.c,
.soft_vote = &soft_vote_gpll0,
.soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.rate = 600000000,
.dbg_name = "gpll0_clk_src",
.ops = &clk_ops_pll_acpu_vote,
@@ -420,9 +420,9 @@
.en_mask = BIT(0),
.status_reg = (void __iomem *)LPAPLL_STATUS_REG,
.status_mask = BIT(17),
- .parent = &cxo_clk_src.c,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.rate = 393216000,
.dbg_name = "lpapll0_clk_src",
.ops = &clk_ops_pll_vote,
@@ -435,9 +435,9 @@
.en_mask = BIT(1),
.status_reg = (void __iomem *)GPLL1_STATUS_REG,
.status_mask = BIT(17),
- .parent = &cxo_clk_src.c,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.rate = 480000000,
.dbg_name = "gpll1_clk_src",
.ops = &clk_ops_pll_vote,
@@ -472,6 +472,7 @@
},
.base = &virt_bases[APCS_PLL_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "apcspll_clk_src",
.ops = &clk_ops_local_pll,
CLK_INIT(apcspll_clk_src.c),
@@ -988,10 +989,10 @@
static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c),
@@ -1000,10 +1001,10 @@
static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR,
- .parent = &blsp1_qup1_spi_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup1_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup1_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c),
@@ -1012,10 +1013,10 @@
static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c),
@@ -1024,10 +1025,10 @@
static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR,
- .parent = &blsp1_qup2_spi_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup2_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup2_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c),
@@ -1036,10 +1037,10 @@
static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c),
@@ -1048,10 +1049,10 @@
static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR,
- .parent = &blsp1_qup3_spi_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup3_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup3_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c),
@@ -1060,10 +1061,10 @@
static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c),
@@ -1072,10 +1073,10 @@
static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR,
- .parent = &blsp1_qup4_spi_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup4_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup4_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c),
@@ -1084,10 +1085,10 @@
static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP5_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup5_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup5_i2c_apps_clk.c),
@@ -1096,10 +1097,10 @@
static struct branch_clk gcc_blsp1_qup5_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP5_SPI_APPS_CBCR,
- .parent = &blsp1_qup5_spi_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup5_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup5_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup5_spi_apps_clk.c),
@@ -1108,10 +1109,10 @@
static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = {
.cbcr_reg = BLSP1_QUP6_I2C_APPS_CBCR,
- .parent = &cxo_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &cxo_clk_src.c,
.dbg_name = "gcc_blsp1_qup6_i2c_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup6_i2c_apps_clk.c),
@@ -1120,10 +1121,10 @@
static struct branch_clk gcc_blsp1_qup6_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP6_SPI_APPS_CBCR,
- .parent = &blsp1_qup6_spi_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_qup6_spi_apps_clk_src.c,
.dbg_name = "gcc_blsp1_qup6_spi_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_qup6_spi_apps_clk.c),
@@ -1132,10 +1133,10 @@
static struct branch_clk gcc_blsp1_uart1_apps_clk = {
.cbcr_reg = BLSP1_UART1_APPS_CBCR,
- .parent = &blsp1_uart1_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart1_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart1_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart1_apps_clk.c),
@@ -1144,10 +1145,10 @@
static struct branch_clk gcc_blsp1_uart2_apps_clk = {
.cbcr_reg = BLSP1_UART2_APPS_CBCR,
- .parent = &blsp1_uart2_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart2_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart2_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart2_apps_clk.c),
@@ -1156,10 +1157,10 @@
static struct branch_clk gcc_blsp1_uart3_apps_clk = {
.cbcr_reg = BLSP1_UART3_APPS_CBCR,
- .parent = &blsp1_uart3_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart3_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart3_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart3_apps_clk.c),
@@ -1168,10 +1169,10 @@
static struct branch_clk gcc_blsp1_uart4_apps_clk = {
.cbcr_reg = BLSP1_UART4_APPS_CBCR,
- .parent = &blsp1_uart4_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart4_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart4_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart4_apps_clk.c),
@@ -1180,10 +1181,10 @@
static struct branch_clk gcc_blsp1_uart5_apps_clk = {
.cbcr_reg = BLSP1_UART5_APPS_CBCR,
- .parent = &blsp1_uart5_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart5_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart5_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart5_apps_clk.c),
@@ -1192,10 +1193,10 @@
static struct branch_clk gcc_blsp1_uart6_apps_clk = {
.cbcr_reg = BLSP1_UART6_APPS_CBCR,
- .parent = &blsp1_uart6_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &blsp1_uart6_apps_clk_src.c,
.dbg_name = "gcc_blsp1_uart6_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_blsp1_uart6_apps_clk.c),
@@ -1252,10 +1253,10 @@
static struct branch_clk gcc_gp1_clk = {
.cbcr_reg = GP1_CBCR,
- .parent = &gp1_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &gp1_clk_src.c,
.dbg_name = "gcc_gp1_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_gp1_clk.c),
@@ -1264,10 +1265,10 @@
static struct branch_clk gcc_gp2_clk = {
.cbcr_reg = GP2_CBCR,
- .parent = &gp2_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &gp2_clk_src.c,
.dbg_name = "gcc_gp2_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_gp2_clk.c),
@@ -1276,10 +1277,10 @@
static struct branch_clk gcc_gp3_clk = {
.cbcr_reg = GP3_CBCR,
- .parent = &gp3_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &gp3_clk_src.c,
.dbg_name = "gcc_gp3_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_gp3_clk.c),
@@ -1288,10 +1289,10 @@
static struct branch_clk gcc_ipa_clk = {
.cbcr_reg = IPA_CBCR,
- .parent = &ipa_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &ipa_clk_src.c,
.dbg_name = "gcc_ipa_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_ipa_clk.c),
@@ -1311,10 +1312,10 @@
static struct branch_clk gcc_pdm2_clk = {
.cbcr_reg = PDM2_CBCR,
- .parent = &pdm2_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &pdm2_clk_src.c,
.dbg_name = "gcc_pdm2_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_pdm2_clk.c),
@@ -1357,10 +1358,10 @@
static struct branch_clk gcc_qpic_clk = {
.cbcr_reg = QPIC_CBCR,
- .parent = &qpic_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &qpic_clk_src.c,
.dbg_name = "gcc_qpic_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_qpic_clk.c),
@@ -1380,10 +1381,10 @@
static struct branch_clk gcc_sdcc2_apps_clk = {
.cbcr_reg = SDCC2_APPS_CBCR,
- .parent = &sdcc2_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &sdcc2_apps_clk_src.c,
.dbg_name = "gcc_sdcc2_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_sdcc2_apps_clk.c),
@@ -1403,10 +1404,10 @@
static struct branch_clk gcc_sdcc3_apps_clk = {
.cbcr_reg = SDCC3_APPS_CBCR,
- .parent = &sdcc3_apps_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &sdcc3_apps_clk_src.c,
.dbg_name = "gcc_sdcc3_apps_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_sdcc3_apps_clk.c),
@@ -1415,10 +1416,10 @@
static struct branch_clk gcc_sys_noc_ipa_axi_clk = {
.cbcr_reg = SYS_NOC_IPA_AXI_CBCR,
- .parent = &ipa_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &ipa_clk_src.c,
.dbg_name = "gcc_sys_noc_ipa_axi_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_sys_noc_ipa_axi_clk.c),
@@ -1439,10 +1440,10 @@
static struct branch_clk gcc_usb_hs_system_clk = {
.cbcr_reg = USB_HS_SYSTEM_CBCR,
.bcr_reg = USB_HS_BCR,
- .parent = &usb_hs_system_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb_hs_system_clk_src.c,
.dbg_name = "gcc_usb_hs_system_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb_hs_system_clk.c),
@@ -1462,10 +1463,10 @@
static struct branch_clk gcc_usb_hsic_clk = {
.cbcr_reg = USB_HSIC_CBCR,
- .parent = &usb_hsic_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb_hsic_clk_src.c,
.dbg_name = "gcc_usb_hsic_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb_hsic_clk.c),
@@ -1474,10 +1475,10 @@
static struct branch_clk gcc_usb_hsic_io_cal_clk = {
.cbcr_reg = USB_HSIC_IO_CAL_CBCR,
- .parent = &usb_hsic_io_cal_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb_hsic_io_cal_clk_src.c,
.dbg_name = "gcc_usb_hsic_io_cal_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb_hsic_io_cal_clk.c),
@@ -1487,10 +1488,10 @@
static struct branch_clk gcc_usb_hsic_system_clk = {
.cbcr_reg = USB_HSIC_SYSTEM_CBCR,
.bcr_reg = USB_HS_HSIC_BCR,
- .parent = &usb_hsic_system_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb_hsic_system_clk_src.c,
.dbg_name = "gcc_usb_hsic_system_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb_hsic_system_clk.c),
@@ -1499,10 +1500,10 @@
static struct branch_clk gcc_usb_hsic_xcvr_fs_clk = {
.cbcr_reg = USB_HSIC_XCVR_FS_CBCR,
- .parent = &usb_hsic_xcvr_fs_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[GCC_BASE],
.c = {
+ .parent = &usb_hsic_xcvr_fs_clk_src.c,
.dbg_name = "gcc_usb_hsic_xcvr_fs_clk",
.ops = &clk_ops_branch,
CLK_INIT(gcc_usb_hsic_xcvr_fs_clk.c),
@@ -1639,9 +1640,9 @@
static struct branch_clk audio_core_lpaif_pcm_data_oe_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PCM_DATA_OE_CBCR,
- .parent = &audio_core_lpaif_pcmoe_clk_src.c,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pcmoe_clk_src.c,
.dbg_name = "audio_core_lpaif_pcm_data_oe_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pcm_data_oe_clk.c),
@@ -1650,9 +1651,9 @@
static struct branch_clk audio_core_slimbus_core_clk = {
.cbcr_reg = AUDIO_CORE_SLIMBUS_CORE_CBCR,
- .parent = &audio_core_slimbus_core_clk_src.c,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_slimbus_core_clk_src.c,
.dbg_name = "audio_core_slimbus_core_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_slimbus_core_clk.c),
@@ -1672,11 +1673,11 @@
static struct branch_clk audio_core_lpaif_pri_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PRI_IBIT_CBCR,
- .parent = &audio_core_lpaif_pri_clk_src.c,
.has_sibling = 1,
.max_div = 15,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pri_clk_src.c,
.dbg_name = "audio_core_lpaif_pri_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pri_ibit_clk.c),
@@ -1685,10 +1686,10 @@
static struct branch_clk audio_core_lpaif_pri_osr_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PRI_OSR_CBCR,
- .parent = &audio_core_lpaif_pri_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pri_clk_src.c,
.dbg_name = "audio_core_lpaif_pri_osr_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pri_osr_clk.c),
@@ -1708,10 +1709,10 @@
static struct branch_clk audio_core_lpaif_pcm0_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PCM0_IBIT_CBCR,
- .parent = &audio_core_lpaif_pcm0_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pcm0_clk_src.c,
.dbg_name = "audio_core_lpaif_pcm0_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pcm0_ibit_clk.c),
@@ -1731,11 +1732,11 @@
static struct branch_clk audio_core_lpaif_sec_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_SEC_IBIT_CBCR,
- .parent = &audio_core_lpaif_sec_clk_src.c,
.has_sibling = 1,
.max_div = 15,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_sec_clk_src.c,
.dbg_name = "audio_core_lpaif_sec_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_sec_ibit_clk.c),
@@ -1744,10 +1745,10 @@
static struct branch_clk audio_core_lpaif_sec_osr_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_SEC_OSR_CBCR,
- .parent = &audio_core_lpaif_sec_clk_src.c,
.has_sibling = 1,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_sec_clk_src.c,
.dbg_name = "audio_core_lpaif_sec_osr_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_sec_osr_clk.c),
@@ -1767,10 +1768,10 @@
static struct branch_clk audio_core_lpaif_pcm1_ibit_clk = {
.cbcr_reg = AUDIO_CORE_LPAIF_PCM1_IBIT_CBCR,
- .parent = &audio_core_lpaif_pcm1_clk_src.c,
.has_sibling = 0,
.base = &virt_bases[LPASS_BASE],
.c = {
+ .parent = &audio_core_lpaif_pcm1_clk_src.c,
.dbg_name = "audio_core_lpaif_pcm1_ibit_clk",
.ops = &clk_ops_branch,
CLK_INIT(audio_core_lpaif_pcm1_ibit_clk.c),
diff --git a/arch/arm/mach-msm/clock-local.c b/arch/arm/mach-msm/clock-local.c
index c43ca46..4432795 100644
--- a/arch/arm/mach-msm/clock-local.c
+++ b/arch/arm/mach-msm/clock-local.c
@@ -527,6 +527,7 @@
* is called to make sure the MNCNTR_EN bit is set correctly.
*/
rcg->current_freq = nf;
+ c->parent = nf->src_clk;
/* Enable any clocks that were disabled. */
if (!rcg->bank_info) {
@@ -583,11 +584,6 @@
return (rcg->freq_tbl + n)->freq_hz;
}
-static struct clk *rcg_clk_get_parent(struct clk *c)
-{
- return to_rcg_clk(c)->current_freq->src_clk;
-}
-
/* Disable hw clock gating if not set at boot */
enum handoff branch_handoff(struct branch *b, struct clk *c)
{
@@ -644,6 +640,7 @@
return HANDOFF_UNKNOWN_RATE;
rcg->current_freq = freq;
+ c->parent = freq->src_clk;
c->rate = freq->freq_hz;
return HANDOFF_ENABLED_CLK;
@@ -683,11 +680,6 @@
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
}
-static struct clk *branch_clk_get_parent(struct clk *c)
-{
- return to_branch_clk(c)->parent;
-}
-
static int branch_clk_is_enabled(struct clk *c)
{
return to_branch_clk(c)->enabled;
@@ -834,7 +826,6 @@
.in_hwcg_mode = branch_clk_in_hwcg_mode,
.is_enabled = branch_clk_is_enabled,
.reset = branch_clk_reset,
- .get_parent = branch_clk_get_parent,
.handoff = branch_clk_handoff,
.set_flags = branch_clk_set_flags,
};
@@ -843,7 +834,6 @@
.prepare = branch_clk_enable,
.unprepare = branch_clk_disable,
.is_enabled = branch_clk_is_enabled,
- .get_parent = branch_clk_get_parent,
.handoff = branch_clk_handoff,
};
@@ -870,7 +860,6 @@
.is_enabled = rcg_clk_is_enabled,
.round_rate = rcg_clk_round_rate,
.reset = rcg_clk_reset,
- .get_parent = rcg_clk_get_parent,
.set_flags = rcg_clk_set_flags,
};
diff --git a/arch/arm/mach-msm/clock-local.h b/arch/arm/mach-msm/clock-local.h
index fca6486..ff6dc69 100644
--- a/arch/arm/mach-msm/clock-local.h
+++ b/arch/arm/mach-msm/clock-local.h
@@ -235,7 +235,6 @@
* struct branch_clk - branch
* @enabled: true if clock is on, false otherwise
* @b: branch
- * @parent: clock source
* @c: clock
*
* An on/off switch with a rate derived from the parent.
@@ -243,7 +242,6 @@
struct branch_clk {
bool enabled;
struct branch b;
- struct clk *parent;
struct clk c;
};
diff --git a/arch/arm/mach-msm/clock-local2.c b/arch/arm/mach-msm/clock-local2.c
index b9c3036..5923951 100644
--- a/arch/arm/mach-msm/clock-local2.c
+++ b/arch/arm/mach-msm/clock-local2.c
@@ -206,6 +206,7 @@
clk_unprepare(cf->src_clk);
rcg->current_freq = nf;
+ c->parent = nf->src_clk;
return 0;
}
@@ -234,11 +235,6 @@
return (rcg->freq_tbl + n)->freq_hz;
}
-static struct clk *rcg_clk_get_parent(struct clk *c)
-{
- return to_rcg_clk(c)->current_freq->src_clk;
-}
-
static enum handoff _rcg_clk_handoff(struct rcg_clk *rcg, int has_mnd)
{
u32 n_regval = 0, m_regval = 0, d_regval = 0;
@@ -306,6 +302,7 @@
return HANDOFF_UNKNOWN_RATE;
rcg->current_freq = freq;
+ rcg->c.parent = freq->src_clk;
rcg->c.rate = freq->freq_hz;
return HANDOFF_ENABLED_CLK;
@@ -431,7 +428,7 @@
return branch_cdiv_set_rate(branch, rate);
if (!branch->has_sibling)
- return clk_set_rate(branch->parent, rate);
+ return clk_set_rate(c->parent, rate);
return -EPERM;
}
@@ -444,7 +441,7 @@
return rate <= (branch->max_div) ? rate : -EPERM;
if (!branch->has_sibling)
- return clk_round_rate(branch->parent, rate);
+ return clk_round_rate(c->parent, rate);
return -EPERM;
}
@@ -457,16 +454,11 @@
return branch->c.rate;
if (!branch->has_sibling)
- return clk_get_rate(branch->parent);
+ return clk_get_rate(c->parent);
return 0;
}
-static struct clk *branch_clk_get_parent(struct clk *c)
-{
- return to_branch_clk(c)->parent;
-}
-
static int branch_clk_list_rate(struct clk *c, unsigned n)
{
struct branch_clk *branch = to_branch_clk(c);
@@ -474,8 +466,8 @@
if (branch->has_sibling == 1)
return -ENXIO;
- if (branch->parent && branch->parent->ops->list_rate)
- return branch->parent->ops->list_rate(branch->parent, n);
+ if (c->parent && c->parent->ops->list_rate)
+ return c->parent->ops->list_rate(c->parent, n);
else
return -ENXIO;
}
@@ -489,9 +481,9 @@
if ((cbcr_regval & CBCR_BRANCH_OFF_BIT))
return HANDOFF_DISABLED_CLK;
- if (branch->parent) {
- if (branch->parent->ops->handoff)
- return branch->parent->ops->handoff(branch->parent);
+ if (c->parent) {
+ if (c->parent->ops->handoff)
+ return c->parent->ops->handoff(c->parent);
}
return HANDOFF_ENABLED_CLK;
@@ -603,7 +595,6 @@
.set_rate = rcg_clk_set_rate,
.list_rate = rcg_clk_list_rate,
.round_rate = rcg_clk_round_rate,
- .get_parent = rcg_clk_get_parent,
.handoff = rcg_clk_handoff,
};
@@ -612,7 +603,6 @@
.set_rate = rcg_clk_set_rate,
.list_rate = rcg_clk_list_rate,
.round_rate = rcg_clk_round_rate,
- .get_parent = rcg_clk_get_parent,
.handoff = rcg_mnd_clk_handoff,
};
@@ -624,7 +614,6 @@
.list_rate = branch_clk_list_rate,
.round_rate = branch_clk_round_rate,
.reset = branch_clk_reset,
- .get_parent = branch_clk_get_parent,
.handoff = branch_clk_handoff,
};
diff --git a/arch/arm/mach-msm/clock-local2.h b/arch/arm/mach-msm/clock-local2.h
index 101dc2d..a6d2ed6 100644
--- a/arch/arm/mach-msm/clock-local2.h
+++ b/arch/arm/mach-msm/clock-local2.h
@@ -87,7 +87,6 @@
/**
* struct branch_clk - branch clock
* @set_rate: Set the frequency of this branch clock.
- * @parent: clock source
* @c: clk
* @cbcr_reg: branch control register
* @bcr_reg: block reset register
@@ -99,7 +98,6 @@
*/
struct branch_clk {
void (*set_rate)(struct branch_clk *, struct clk_freq_tbl *);
- struct clk *parent;
struct clk c;
const u32 cbcr_reg;
const u32 bcr_reg;
diff --git a/arch/arm/mach-msm/clock-pll.c b/arch/arm/mach-msm/clock-pll.c
index 240f4e4..8e11d37 100644
--- a/arch/arm/mach-msm/clock-pll.c
+++ b/arch/arm/mach-msm/clock-pll.c
@@ -98,11 +98,6 @@
spin_unlock_irqrestore(&pll_reg_lock, flags);
}
-static struct clk *pll_vote_clk_get_parent(struct clk *c)
-{
- return to_pll_vote_clk(c)->parent;
-}
-
static int pll_vote_clk_is_enabled(struct clk *c)
{
struct pll_vote_clk *pllv = to_pll_vote_clk(c);
@@ -122,7 +117,6 @@
.enable = pll_vote_clk_enable,
.disable = pll_vote_clk_disable,
.is_enabled = pll_vote_clk_is_enabled,
- .get_parent = pll_vote_clk_get_parent,
.handoff = pll_vote_clk_handoff,
};
@@ -229,11 +223,6 @@
return HANDOFF_DISABLED_CLK;
}
-static struct clk *local_pll_clk_get_parent(struct clk *c)
-{
- return to_pll_clk(c)->parent;
-}
-
static int local_pll_clk_set_rate(struct clk *c, unsigned long rate)
{
struct pll_freq_tbl *nf;
@@ -346,7 +335,6 @@
.disable = local_pll_clk_disable,
.set_rate = local_pll_clk_set_rate,
.handoff = local_pll_clk_handoff,
- .get_parent = local_pll_clk_get_parent,
};
struct pll_rate {
@@ -537,7 +525,6 @@
.enable = pll_acpu_vote_clk_enable,
.disable = pll_acpu_vote_clk_disable,
.is_enabled = pll_vote_clk_is_enabled,
- .get_parent = pll_vote_clk_get_parent,
};
static void __init __set_fsm_mode(void __iomem *mode_reg,
diff --git a/arch/arm/mach-msm/clock-pll.h b/arch/arm/mach-msm/clock-pll.h
index 33b35a8..cb334d7 100644
--- a/arch/arm/mach-msm/clock-pll.h
+++ b/arch/arm/mach-msm/clock-pll.h
@@ -35,7 +35,6 @@
* any HW voting
* @id: PLL ID
* @mode_reg: enable register
- * @parent: clock source
* @c: clock
*/
struct pll_shared_clk {
@@ -104,7 +103,6 @@
* @en_mask: ORed with @en_reg to enable the clock
* @status_mask: ANDed with @status_reg to determine if PLL is active.
* @status_reg: status register
- * @parent: clock source
* @c: clock
*/
struct pll_vote_clk {
@@ -115,7 +113,6 @@
void __iomem *const status_reg;
const u32 status_mask;
- struct clk *parent;
struct clk c;
void *const __iomem *base;
};
@@ -144,7 +141,6 @@
* @status_reg: status register, contains the lock detection bit
* @masks: masks used for settings in config_reg
* @freq_tbl: pll freq table
- * @parent: clock source
* @c: clk
* @base: pointer to base address of ioremapped registers.
*/
@@ -159,7 +155,6 @@
struct pll_config_masks masks;
struct pll_freq_tbl *freq_tbl;
- struct clk *parent;
struct clk c;
void *const __iomem *base;
};
diff --git a/arch/arm/mach-msm/clock-voter.c b/arch/arm/mach-msm/clock-voter.c
index fa170bf4..7421ba6 100644
--- a/arch/arm/mach-msm/clock-voter.c
+++ b/arch/arm/mach-msm/clock-voter.c
@@ -43,7 +43,7 @@
mutex_lock(&voter_clk_lock);
if (v->enabled) {
- struct clk *parent = v->parent;
+ struct clk *parent = clk->parent;
/*
* Get the aggregate rate without this clock's vote and update
@@ -79,7 +79,7 @@
struct clk_voter *v = to_clk_voter(clk);
mutex_lock(&voter_clk_lock);
- parent = v->parent;
+ parent = clk->parent;
/*
* Increase the rate if this clock is voting for a higher rate
@@ -105,7 +105,7 @@
struct clk_voter *v = to_clk_voter(clk);
mutex_lock(&voter_clk_lock);
- parent = v->parent;
+ parent = clk->parent;
/*
* Decrease the rate if this clock was the only one voting for
@@ -129,14 +129,7 @@
static long voter_clk_round_rate(struct clk *clk, unsigned long rate)
{
- struct clk_voter *v = to_clk_voter(clk);
- return clk_round_rate(v->parent, rate);
-}
-
-static struct clk *voter_clk_get_parent(struct clk *clk)
-{
- struct clk_voter *v = to_clk_voter(clk);
- return v->parent;
+ return clk_round_rate(clk->parent, rate);
}
static bool voter_clk_is_local(struct clk *clk)
@@ -159,7 +152,6 @@
.set_rate = voter_clk_set_rate,
.is_enabled = voter_clk_is_enabled,
.round_rate = voter_clk_round_rate,
- .get_parent = voter_clk_get_parent,
.is_local = voter_clk_is_local,
.handoff = voter_clk_handoff,
};
diff --git a/arch/arm/mach-msm/clock-voter.h b/arch/arm/mach-msm/clock-voter.h
index 82c071b..eb55a12 100644
--- a/arch/arm/mach-msm/clock-voter.h
+++ b/arch/arm/mach-msm/clock-voter.h
@@ -21,7 +21,6 @@
struct clk_voter {
bool enabled;
- struct clk *parent;
struct clk c;
};
@@ -32,8 +31,8 @@
#define DEFINE_CLK_VOTER(clk_name, _parent, _default_rate) \
struct clk_voter clk_name = { \
- .parent = _parent, \
.c = { \
+ .parent = _parent, \
.dbg_name = #clk_name, \
.ops = &clk_ops_voter, \
.rate = _default_rate, \
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index e9dd974..c2bf5ba 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -163,7 +163,7 @@
mutex_lock(&clk->prepare_lock);
if (clk->prepare_count == 0) {
- parent = clk_get_parent(clk);
+ parent = clk->parent;
ret = clk_prepare(parent);
if (ret)
@@ -213,7 +213,7 @@
WARN(!clk->prepare_count,
"%s: Don't call enable on unprepared clocks\n", name);
if (clk->count == 0) {
- parent = clk_get_parent(clk);
+ parent = clk->parent;
ret = clk_enable(parent);
if (ret)
@@ -258,7 +258,7 @@
if (WARN(clk->count == 0, "%s is unbalanced", name))
goto out;
if (clk->count == 1) {
- struct clk *parent = clk_get_parent(clk);
+ struct clk *parent = clk->parent;
trace_clock_disable(name, 0, smp_processor_id());
if (clk->ops->disable)
@@ -283,7 +283,7 @@
if (WARN(!clk->prepare_count, "%s is unbalanced (prepare)", name))
goto out;
if (clk->prepare_count == 1) {
- struct clk *parent = clk_get_parent(clk);
+ struct clk *parent = clk->parent;
WARN(clk->count,
"%s: Don't call unprepare when the clock is enabled\n",
@@ -411,10 +411,7 @@
if (IS_ERR_OR_NULL(clk))
return NULL;
- if (!clk->ops->get_parent)
- return NULL;
-
- return clk->ops->get_parent(clk);
+ return clk->parent;
}
EXPORT_SYMBOL(clk_get_parent);
@@ -438,7 +435,7 @@
for (n = 0; n < num_clocks; n++) {
clk = clock_tbl[n].clk;
- parent = clk_get_parent(clk);
+ parent = clk->parent;
if (parent && list_empty(&clk->siblings))
list_add(&clk->siblings, &parent->children);
}
@@ -492,11 +489,11 @@
/*
* Handoff functions for children must be called before their parents'
- * so that the correct parent is returned by the clk_get_parent() below.
+ * so that the correct parent is available below.
*/
ret = clk->ops->handoff(clk);
if (ret == HANDOFF_ENABLED_CLK) {
- ret = __handoff_clk(clk_get_parent(clk));
+ ret = __handoff_clk(clk->parent);
if (ret == HANDOFF_ENABLED_CLK) {
h = kmalloc(sizeof(*h), GFP_KERNEL);
if (!h) {
diff --git a/arch/arm/mach-msm/devices-8930.c b/arch/arm/mach-msm/devices-8930.c
index c3be6ce..0faf500 100644
--- a/arch/arm/mach-msm/devices-8930.c
+++ b/arch/arm/mach-msm/devices-8930.c
@@ -669,6 +669,18 @@
.id = -1,
};
+static struct acpuclk_platform_data acpuclk_8930ab_pdata = {
+ .uses_pm8917 = false,
+};
+
+struct platform_device msm8930ab_device_acpuclk = {
+ .name = "acpuclk-8930ab",
+ .id = -1,
+ .dev = {
+ .platform_data = &acpuclk_8930ab_pdata,
+ },
+};
+
static struct fs_driver_data gfx3d_fs_data = {
.clks = (struct fs_clk_data[]){
{ .name = "core_clk", .reset_rate = 27000000 },
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index eae01aa..bd5a20f 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -455,6 +455,7 @@
extern struct platform_device msm8x60_device_acpuclk;
extern struct platform_device msm8930_device_acpuclk;
extern struct platform_device msm8930aa_device_acpuclk;
+extern struct platform_device msm8930ab_device_acpuclk;
extern struct platform_device msm8960_device_acpuclk;
extern struct platform_device msm8960ab_device_acpuclk;
extern struct platform_device msm9615_device_acpuclk;
diff --git a/arch/arm/mach-msm/include/mach/clk-provider.h b/arch/arm/mach-msm/include/mach/clk-provider.h
index d47e88e..0f2feaa 100644
--- a/arch/arm/mach-msm/include/mach/clk-provider.h
+++ b/arch/arm/mach-msm/include/mach/clk-provider.h
@@ -103,6 +103,7 @@
* @depends: non-direct parent of clock to enable when this clock is enabled
* @vdd_class: voltage scaling requirement class
* @fmax: maximum frequency in Hz supported at each voltage level
+ * @parent: the current source of this clock
*/
struct clk {
uint32_t flags;
@@ -113,6 +114,7 @@
unsigned long *fmax;
int num_fmax;
unsigned long rate;
+ struct clk *parent;
struct list_head children;
struct list_head siblings;
diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h
index 054e70c..57b4bd3 100644
--- a/arch/arm/mach-msm/include/mach/iommu.h
+++ b/arch/arm/mach-msm/include/mach/iommu.h
@@ -161,6 +161,12 @@
}
#endif
+/*
+ * Function to program the global registers of an IOMMU securely.
+ * This should only be called on IOMMUs for which kernel programming
+ * of global registers is not possible
+ */
+int msm_iommu_sec_program_iommu(int sec_id);
static inline int msm_soc_version_supports_iommu_v1(void)
{
diff --git a/arch/arm/mach-msm/krait-regulator.c b/arch/arm/mach-msm/krait-regulator.c
index 63ae4e6..f7b2b1e 100644
--- a/arch/arm/mach-msm/krait-regulator.c
+++ b/arch/arm/mach-msm/krait-regulator.c
@@ -159,6 +159,7 @@
int retention_uV;
int headroom_uV;
int ldo_threshold_uV;
+ bool online;
};
static u32 version;
@@ -309,6 +310,7 @@
}
setpoint = DIV_ROUND_UP(uV, LV_RANGE_STEP);
+
return msm_spm_apcs_set_vdd(setpoint);
}
@@ -319,6 +321,8 @@
int rc = 0;
list_for_each_entry(kvreg, &pvreg->krait_power_vregs, link) {
+ if (!kvreg->online)
+ continue;
if (kvreg->uV > kvreg->ldo_threshold_uV
|| kvreg->uV > vmax - kvreg->headroom_uV) {
rc = switch_to_using_hs(kvreg);
@@ -482,6 +486,9 @@
struct pmic_gang_vreg *pvreg = from->pvreg;
list_for_each_entry(kvreg, &pvreg->krait_power_vregs, link) {
+ if (!kvreg->online)
+ continue;
+
v = kvreg->uV;
if (kvreg == from)
@@ -490,6 +497,7 @@
if (vmax < v)
vmax = v;
}
+
return vmax;
}
@@ -499,14 +507,17 @@
struct krait_power_vreg *kvreg;
struct pmic_gang_vreg *pvreg = from->pvreg;
- list_for_each_entry(kvreg, &pvreg->krait_power_vregs, link)
+ list_for_each_entry(kvreg, &pvreg->krait_power_vregs, link) {
+ if (!kvreg->online)
+ continue;
load_total += kvreg->load_uA;
+ }
return load_total;
}
#define ROUND_UP_VOLTAGE(v, res) (DIV_ROUND_UP(v, res) * res)
-static int krait_power_set_voltage(struct regulator_dev *rdev,
+static int _set_voltage(struct regulator_dev *rdev,
int min_uV, int max_uV, unsigned *selector)
{
struct krait_power_vreg *kvreg = rdev_get_drvdata(rdev);
@@ -514,6 +525,31 @@
int rc;
int vmax;
+ vmax = get_vmax(kvreg, min_uV);
+
+ /* round up the pmic voltage as per its resolution */
+ vmax = ROUND_UP_VOLTAGE(vmax, LV_RANGE_STEP);
+
+ rc = pmic_gang_set_voltage(kvreg, vmax);
+ if (rc < 0) {
+ dev_err(&rdev->dev, "%s failed set voltage (%d, %d) rc = %d\n",
+ kvreg->name, min_uV, max_uV, rc);
+ goto out;
+ }
+
+ pvreg->pmic_vmax_uV = vmax;
+
+out:
+ return rc;
+}
+
+static int krait_power_set_voltage(struct regulator_dev *rdev,
+ int min_uV, int max_uV, unsigned *selector)
+{
+ struct krait_power_vreg *kvreg = rdev_get_drvdata(rdev);
+ struct pmic_gang_vreg *pvreg = kvreg->pvreg;
+ int rc;
+
/*
* if the voltage requested is below LDO_THRESHOLD this cpu could
* switch to LDO mode. Hence round the voltage as per the LDO
@@ -526,49 +562,29 @@
}
mutex_lock(&pvreg->krait_power_vregs_lock);
-
- vmax = get_vmax(kvreg, min_uV);
-
- /* round up the pmic voltage as per its resolution */
- vmax = ROUND_UP_VOLTAGE(vmax, LV_RANGE_STEP);
-
- /*
- * Assign the voltage before updating the gang voltage as we iterate
- * over all the core voltages and choose HS or LDO for each of them
- */
kvreg->uV = min_uV;
- rc = pmic_gang_set_voltage(kvreg, vmax);
- if (rc < 0) {
- dev_err(&rdev->dev, "%s failed set voltage (%d, %d) rc = %d\n",
- kvreg->name, min_uV, max_uV, rc);
- goto out;
+ if (!kvreg->online) {
+ mutex_unlock(&pvreg->krait_power_vregs_lock);
+ return 0;
}
- pvreg->pmic_vmax_uV = vmax;
-
-out:
+ rc = _set_voltage(rdev, min_uV, max_uV, selector);
mutex_unlock(&pvreg->krait_power_vregs_lock);
+
return rc;
}
#define PMIC_FTS_MODE_PFM 0x00
#define PMIC_FTS_MODE_PWM 0x80
#define PFM_LOAD_UA 500000
-static unsigned int krait_power_get_optimum_mode(struct regulator_dev *rdev,
+static unsigned int _get_optimum_mode(struct regulator_dev *rdev,
int input_uV, int output_uV, int load_uA)
{
struct krait_power_vreg *kvreg = rdev_get_drvdata(rdev);
struct pmic_gang_vreg *pvreg = kvreg->pvreg;
int rc;
int load_total_uA;
- int reg_mode = -EINVAL;
-
- mutex_lock(&pvreg->krait_power_vregs_lock);
-
- reg_mode = kvreg->mode;
-
- kvreg->load_uA = load_uA;
load_total_uA = get_total_load(kvreg);
@@ -584,8 +600,7 @@
pvreg->pfm_mode = true;
}
}
- mutex_unlock(&pvreg->krait_power_vregs_lock);
- return reg_mode;
+ return kvreg->mode;
}
if (pvreg->pfm_mode) {
@@ -608,8 +623,27 @@
}
out:
+ return kvreg->mode;
+}
+
+static unsigned int krait_power_get_optimum_mode(struct regulator_dev *rdev,
+ int input_uV, int output_uV, int load_uA)
+{
+ struct krait_power_vreg *kvreg = rdev_get_drvdata(rdev);
+ struct pmic_gang_vreg *pvreg = kvreg->pvreg;
+ int rc;
+
+ mutex_lock(&pvreg->krait_power_vregs_lock);
+ kvreg->load_uA = load_uA;
+ if (!kvreg->online) {
+ mutex_unlock(&pvreg->krait_power_vregs_lock);
+ return kvreg->mode;
+ }
+
+ rc = _get_optimum_mode(rdev, input_uV, output_uV, load_uA);
mutex_unlock(&pvreg->krait_power_vregs_lock);
- return reg_mode;
+
+ return rc;
}
static int krait_power_set_mode(struct regulator_dev *rdev, unsigned int mode)
@@ -624,12 +658,62 @@
return kvreg->mode;
}
+static int krait_power_is_enabled(struct regulator_dev *rdev)
+{
+ struct krait_power_vreg *kvreg = rdev_get_drvdata(rdev);
+
+ return kvreg->online;
+}
+
+static int krait_power_enable(struct regulator_dev *rdev)
+{
+ struct krait_power_vreg *kvreg = rdev_get_drvdata(rdev);
+ struct pmic_gang_vreg *pvreg = kvreg->pvreg;
+ int rc;
+
+ mutex_lock(&pvreg->krait_power_vregs_lock);
+ kvreg->online = true;
+ rc = _get_optimum_mode(rdev, kvreg->uV, kvreg->uV,
+ kvreg->load_uA);
+ if (rc < 0)
+ goto en_err;
+ rc = _set_voltage(rdev, kvreg->uV,
+ rdev->constraints->max_uV, NULL);
+en_err:
+ mutex_unlock(&pvreg->krait_power_vregs_lock);
+ return rc;
+}
+
+static int krait_power_disable(struct regulator_dev *rdev)
+{
+ struct krait_power_vreg *kvreg = rdev_get_drvdata(rdev);
+ struct pmic_gang_vreg *pvreg = kvreg->pvreg;
+ int rc;
+
+ mutex_lock(&pvreg->krait_power_vregs_lock);
+ kvreg->online = false;
+
+ rc = _get_optimum_mode(rdev, kvreg->uV, kvreg->uV,
+ kvreg->load_uA);
+ if (rc < 0)
+ goto dis_err;
+
+ rc = _set_voltage(rdev, kvreg->uV,
+ rdev->constraints->max_uV, NULL);
+dis_err:
+ mutex_unlock(&pvreg->krait_power_vregs_lock);
+ return rc;
+}
+
static struct regulator_ops krait_power_ops = {
.get_voltage = krait_power_get_voltage,
.set_voltage = krait_power_set_voltage,
.get_optimum_mode = krait_power_get_optimum_mode,
.set_mode = krait_power_set_mode,
.get_mode = krait_power_get_mode,
+ .enable = krait_power_enable,
+ .disable = krait_power_disable,
+ .is_enabled = krait_power_is_enabled,
};
static void kvreg_hw_init(struct krait_power_vreg *kvreg)
diff --git a/drivers/input/misc/lis3dh_acc.c b/drivers/input/misc/lis3dh_acc.c
index af96d3f..cc4ee9f 100644
--- a/drivers/input/misc/lis3dh_acc.c
+++ b/drivers/input/misc/lis3dh_acc.c
@@ -1086,26 +1086,26 @@
static struct device_attribute attributes[] = {
- __ATTR(pollrate_ms, 0666, attr_get_polling_rate,
+ __ATTR(pollrate_ms, 0664, attr_get_polling_rate,
attr_set_polling_rate),
- __ATTR(range, 0666, attr_get_range, attr_set_range),
- __ATTR(enable, 0666, attr_get_enable, attr_set_enable),
- __ATTR(int1_config, 0666, attr_get_intconfig1, attr_set_intconfig1),
- __ATTR(int1_duration, 0666, attr_get_duration1, attr_set_duration1),
- __ATTR(int1_threshold, 0666, attr_get_thresh1, attr_set_thresh1),
+ __ATTR(range, 0664, attr_get_range, attr_set_range),
+ __ATTR(enable, 0664, attr_get_enable, attr_set_enable),
+ __ATTR(int1_config, 0664, attr_get_intconfig1, attr_set_intconfig1),
+ __ATTR(int1_duration, 0664, attr_get_duration1, attr_set_duration1),
+ __ATTR(int1_threshold, 0664, attr_get_thresh1, attr_set_thresh1),
__ATTR(int1_source, 0444, attr_get_source1, NULL),
- __ATTR(click_config, 0666, attr_get_click_cfg, attr_set_click_cfg),
+ __ATTR(click_config, 0664, attr_get_click_cfg, attr_set_click_cfg),
__ATTR(click_source, 0444, attr_get_click_source, NULL),
- __ATTR(click_threshold, 0666, attr_get_click_ths, attr_set_click_ths),
- __ATTR(click_timelimit, 0666, attr_get_click_tlim,
+ __ATTR(click_threshold, 0664, attr_get_click_ths, attr_set_click_ths),
+ __ATTR(click_timelimit, 0664, attr_get_click_tlim,
attr_set_click_tlim),
- __ATTR(click_timelatency, 0666, attr_get_click_tlat,
+ __ATTR(click_timelatency, 0664, attr_get_click_tlat,
attr_set_click_tlat),
- __ATTR(click_timewindow, 0666, attr_get_click_tw, attr_set_click_tw),
+ __ATTR(click_timewindow, 0664, attr_get_click_tw, attr_set_click_tw),
#ifdef DEBUG
- __ATTR(reg_value, 0666, attr_reg_get, attr_reg_set),
- __ATTR(reg_addr, 0222, NULL, attr_addr_set),
+ __ATTR(reg_value, 0664, attr_reg_get, attr_reg_set),
+ __ATTR(reg_addr, 0220, NULL, attr_addr_set),
#endif
};
diff --git a/drivers/input/misc/mpu3050.c b/drivers/input/misc/mpu3050.c
index 04a7598..db6f93c 100644
--- a/drivers/input/misc/mpu3050.c
+++ b/drivers/input/misc/mpu3050.c
@@ -288,7 +288,7 @@
static struct device_attribute attributes[] = {
- __ATTR(pollrate_ms, 0666,
+ __ATTR(pollrate_ms, 0664,
mpu3050_attr_get_polling_rate,
mpu3050_attr_set_polling_rate),
};
diff --git a/drivers/iommu/msm_iommu-v2.c b/drivers/iommu/msm_iommu-v2.c
index 9d88fdd..425eb8a 100644
--- a/drivers/iommu/msm_iommu-v2.c
+++ b/drivers/iommu/msm_iommu-v2.c
@@ -148,6 +148,9 @@
return ret;
}
+/*
+ * May only be called for non-secure iommus
+ */
static void __reset_iommu(void __iomem *base)
{
int i, smt_size;
@@ -170,6 +173,9 @@
mb();
}
+/*
+ * May only be called for non-secure iommus
+ */
static void __program_iommu(void __iomem *base,
struct msm_iommu_bfb_settings *bfb_settings)
{
@@ -223,14 +229,14 @@
static void __program_context(void __iomem *base, int ctx, int ncb,
phys_addr_t pgtable, int redirect,
- u32 *sids, int len)
+ u32 *sids, int len, bool is_secure)
{
unsigned int prrr, nmrr;
unsigned int pn;
int i, j, found, num = 0, smt_size;
__reset_context(base, ctx);
- smt_size = GET_IDR0_NUMSMRG(base);
+
pn = pgtable >> CB_TTBR0_ADDR_SHIFT;
SET_TTBCR(base, ctx, 0);
SET_CB_TTBR0_ADDR(base, ctx, pn);
@@ -266,41 +272,44 @@
SET_CB_TTBR0_RGN(base, ctx, 1); /* WB, WA */
}
- /* Program the M2V tables for this context */
- for (i = 0; i < len / sizeof(*sids); i++) {
- for (; num < smt_size; num++)
- if (GET_SMR_VALID(base, num) == 0)
- break;
- BUG_ON(num >= smt_size);
+ if (!is_secure) {
+ smt_size = GET_IDR0_NUMSMRG(base);
+ /* Program the M2V tables for this context */
+ for (i = 0; i < len / sizeof(*sids); i++) {
+ for (; num < smt_size; num++)
+ if (GET_SMR_VALID(base, num) == 0)
+ break;
+ BUG_ON(num >= smt_size);
- SET_SMR_VALID(base, num, 1);
- SET_SMR_MASK(base, num, 0);
- SET_SMR_ID(base, num, sids[i]);
+ SET_SMR_VALID(base, num, 1);
+ SET_SMR_MASK(base, num, 0);
+ SET_SMR_ID(base, num, sids[i]);
- SET_S2CR_N(base, num, 0);
- SET_S2CR_CBNDX(base, num, ctx);
- SET_S2CR_MEMATTR(base, num, 0x0A);
- /* Set security bit override to be Non-secure */
- SET_S2CR_NSCFG(base, num, 3);
+ SET_S2CR_N(base, num, 0);
+ SET_S2CR_CBNDX(base, num, ctx);
+ SET_S2CR_MEMATTR(base, num, 0x0A);
+ /* Set security bit override to be Non-secure */
+ SET_S2CR_NSCFG(base, num, 3);
+ }
+ SET_CBAR_N(base, ctx, 0);
+
+ /* Stage 1 Context with Stage 2 bypass */
+ SET_CBAR_TYPE(base, ctx, 1);
+
+ /* Route page faults to the non-secure interrupt */
+ SET_CBAR_IRPTNDX(base, ctx, 1);
+
+ /* Set VMID to non-secure HLOS */
+ SET_CBAR_VMID(base, ctx, 3);
+
+ /* Bypass is treated as inner-shareable */
+ SET_CBAR_BPSHCFG(base, ctx, 2);
+
+ /* Do not downgrade memory attributes */
+ SET_CBAR_MEMATTR(base, ctx, 0x0A);
+
}
- SET_CBAR_N(base, ctx, 0);
-
- /* Stage 1 Context with Stage 2 bypass */
- SET_CBAR_TYPE(base, ctx, 1);
-
- /* Route page faults to the non-secure interrupt */
- SET_CBAR_IRPTNDX(base, ctx, 1);
-
- /* Set VMID to non-secure HLOS */
- SET_CBAR_VMID(base, ctx, 3);
-
- /* Bypass is treated as inner-shareable */
- SET_CBAR_BPSHCFG(base, ctx, 2);
-
- /* Do not downgrade memory attributes */
- SET_CBAR_MEMATTR(base, ctx, 0x0A);
-
/* Find if this page table is used elsewhere, and re-use ASID */
found = 0;
for (i = 0; i < ncb; i++)
@@ -399,6 +408,7 @@
struct msm_iommu_ctx_drvdata *ctx_drvdata;
struct msm_iommu_ctx_drvdata *tmp_drvdata;
int ret;
+ int is_secure;
mutex_lock(&msm_iommu_lock);
@@ -426,6 +436,8 @@
goto fail;
}
+ is_secure = iommu_drvdata->sec_id != -1;
+
ret = regulator_enable(iommu_drvdata->gdsc);
if (ret)
goto fail;
@@ -436,13 +448,25 @@
goto fail;
}
- if (!msm_iommu_ctx_attached(dev->parent))
- __program_iommu(iommu_drvdata->base,
+ if (!msm_iommu_ctx_attached(dev->parent)) {
+ if (!is_secure) {
+ __program_iommu(iommu_drvdata->base,
iommu_drvdata->bfb_settings);
+ } else {
+ ret = msm_iommu_sec_program_iommu(
+ iommu_drvdata->sec_id);
+ if (ret) {
+ regulator_disable(iommu_drvdata->gdsc);
+ __disable_clocks(iommu_drvdata);
+ goto fail;
+ }
+ }
+ }
__program_context(iommu_drvdata->base, ctx_drvdata->num,
iommu_drvdata->ncb, __pa(priv->pt.fl_table),
- priv->pt.redirect, ctx_drvdata->sids, ctx_drvdata->nsid);
+ priv->pt.redirect, ctx_drvdata->sids, ctx_drvdata->nsid,
+ is_secure);
__disable_clocks(iommu_drvdata);
list_add(&(ctx_drvdata->attached_elm), &priv->list_attached);
@@ -460,6 +484,7 @@
struct msm_iommu_drvdata *iommu_drvdata;
struct msm_iommu_ctx_drvdata *ctx_drvdata;
int ret;
+ int is_secure;
mutex_lock(&msm_iommu_lock);
priv = domain->priv;
@@ -475,11 +500,14 @@
if (ret)
goto fail;
+ is_secure = iommu_drvdata->sec_id != -1;
+
SET_TLBIASID(iommu_drvdata->base, ctx_drvdata->num,
GET_CB_CONTEXTIDR_ASID(iommu_drvdata->base, ctx_drvdata->num));
__reset_context(iommu_drvdata->base, ctx_drvdata->num);
- __release_smg(iommu_drvdata->base, ctx_drvdata->num);
+ if (!is_secure)
+ __release_smg(iommu_drvdata->base, ctx_drvdata->num);
__disable_clocks(iommu_drvdata);
diff --git a/drivers/iommu/msm_iommu_sec.c b/drivers/iommu/msm_iommu_sec.c
index a89c4a8..72ec4a6 100644
--- a/drivers/iommu/msm_iommu_sec.c
+++ b/drivers/iommu/msm_iommu_sec.c
@@ -128,7 +128,7 @@
return ret;
}
-static int msm_iommu_sec_program_iommu(int sec_id)
+int msm_iommu_sec_program_iommu(int sec_id)
{
struct msm_scm_sec_cfg {
unsigned int id;
diff --git a/drivers/media/video/msm_vidc/msm_smem.c b/drivers/media/video/msm_vidc/msm_smem.c
index 3dd2193..83f33a1 100644
--- a/drivers/media/video/msm_vidc/msm_smem.c
+++ b/drivers/media/video/msm_vidc/msm_smem.c
@@ -24,7 +24,7 @@
static int get_device_address(struct ion_client *clnt,
struct ion_handle *hndl, int domain_num, int partition_num,
unsigned long align, unsigned long *iova,
- unsigned long *buffer_size)
+ unsigned long *buffer_size, int flags)
{
int rc;
if (!iova || !buffer_size || !hndl || !clnt) {
@@ -36,25 +36,39 @@
align = 4096;
dprintk(VIDC_DBG, "domain: %d, partition: %d\n",
domain_num, partition_num);
+ if (flags & SMEM_SECURE) {
+ if (flags & SMEM_INPUT)
+ rc = msm_ion_secure_buffer(clnt, hndl, 0x1, 0);
+ else
+ rc = msm_ion_secure_buffer(clnt, hndl, 0x2, 0);
+ if (rc) {
+ dprintk(VIDC_ERR, "Failed to secure memory\n");
+ goto mem_secure_failed;
+ }
+ }
rc = ion_map_iommu(clnt, hndl, domain_num, partition_num, align,
0, iova, buffer_size, 0, 0);
if (rc)
dprintk(VIDC_ERR,
"ion_map_iommu failed(%d).domain: %d,partition: %d\n",
rc, domain_num, partition_num);
-
+mem_secure_failed:
return rc;
}
static void put_device_address(struct ion_client *clnt,
- struct ion_handle *hndl, int domain_num, int partition_num)
+ struct ion_handle *hndl, int domain_num, int partition_num, int flags)
{
ion_unmap_iommu(clnt, hndl, domain_num, partition_num);
+ if (flags & SMEM_SECURE) {
+ if (msm_ion_unsecure_buffer(clnt, hndl))
+ dprintk(VIDC_ERR, "Failed to unsecure memory\n");
+ }
}
static int ion_user_to_kernel(struct smem_client *client,
int fd, u32 offset, int domain, int partition,
- struct msm_smem *mem)
+ struct msm_smem *mem, int flags)
{
struct ion_handle *hndl;
unsigned long iova = 0;
@@ -70,8 +84,9 @@
mem->kvaddr = NULL;
mem->domain = domain;
mem->partition_num = partition;
+ mem->flags = flags;
rc = get_device_address(client->clnt, hndl, mem->domain,
- mem->partition_num, 4096, &iova, &buffer_size);
+ mem->partition_num, 4096, &iova, &buffer_size, flags);
if (rc) {
dprintk(VIDC_ERR, "Failed to get device address: %d\n", rc);
goto fail_device_address;
@@ -101,11 +116,16 @@
unsigned long ionflags = 0;
unsigned long heap_mask = 0;
int rc = 0;
- if (flags == SMEM_CACHED)
+ if (flags & SMEM_CACHED)
ionflags = ION_SET_CACHED(ionflags);
else
ionflags = ION_SET_UNCACHED(ionflags);
+ if (flags & SMEM_SECURE) {
+ ionflags |= ION_SECURE;
+ size = (size + 0xfffff) & (~0xfffff);
+ }
+
heap_mask = ION_HEAP(ION_CP_MM_HEAP_ID);
if (align < 4096)
align = 4096;
@@ -124,6 +144,7 @@
mem->smem_priv = hndl;
mem->domain = domain;
mem->partition_num = partition;
+ mem->flags = flags;
if (map_kernel) {
mem->kvaddr = ion_map_kernel(client->clnt, hndl);
if (!mem->kvaddr) {
@@ -136,7 +157,7 @@
mem->kvaddr = NULL;
rc = get_device_address(client->clnt, hndl, mem->domain,
- mem->partition_num, align, &iova, &buffer_size);
+ mem->partition_num, align, &iova, &buffer_size, flags);
if (rc) {
dprintk(VIDC_ERR, "Failed to get device address: %d\n",
rc);
@@ -160,7 +181,8 @@
{
if (mem->device_addr)
put_device_address(client->clnt,
- mem->smem_priv, mem->domain, mem->partition_num);
+ mem->smem_priv, mem->domain,
+ mem->partition_num, mem->flags);
if (mem->kvaddr)
ion_unmap_kernel(client->clnt, mem->smem_priv);
if (mem->smem_priv)
@@ -182,7 +204,7 @@
}
struct msm_smem *msm_smem_user_to_kernel(void *clt, int fd, u32 offset,
- int domain, int partition)
+ int domain, int partition, int flags)
{
struct smem_client *client = clt;
int rc = 0;
@@ -199,7 +221,7 @@
switch (client->mem_type) {
case SMEM_ION:
rc = ion_user_to_kernel(clt, fd, offset,
- domain, partition, mem);
+ domain, partition, mem, flags);
break;
default:
dprintk(VIDC_ERR, "Mem type not supported\n");
diff --git a/drivers/media/video/msm_vidc/msm_smem.h b/drivers/media/video/msm_vidc/msm_smem.h
index c109abd..8241fdd 100644
--- a/drivers/media/video/msm_vidc/msm_smem.h
+++ b/drivers/media/video/msm_vidc/msm_smem.h
@@ -20,9 +20,10 @@
SMEM_ION,
};
-enum smem_cache_prop {
- SMEM_CACHED,
- SMEM_UNCACHED,
+enum smem_prop {
+ SMEM_CACHED = 0x1,
+ SMEM_SECURE = 0x2,
+ SMEM_INPUT = 0x4,
};
struct msm_smem {
@@ -32,6 +33,7 @@
unsigned long device_addr;
int domain;
int partition_num;
+ int flags;
void *smem_priv;
};
@@ -41,6 +43,6 @@
void msm_smem_free(void *clt, struct msm_smem *mem);
void msm_smem_delete_client(void *clt);
struct msm_smem *msm_smem_user_to_kernel(void *clt, int fd, u32 offset, int
- domain, int partition);
+ domain, int partition, int flags);
int msm_smem_clean_invalidate(void *clt, struct msm_smem *mem);
#endif
diff --git a/drivers/media/video/msm_vidc/msm_v4l2_vidc.c b/drivers/media/video/msm_vidc/msm_v4l2_vidc.c
index 912fad4..4f2373e 100644
--- a/drivers/media/video/msm_vidc/msm_v4l2_vidc.c
+++ b/drivers/media/video/msm_vidc/msm_v4l2_vidc.c
@@ -756,6 +756,8 @@
struct msm_v4l2_vid_inst *v4l2_inst;
int plane = 0;
int i, rc = 0;
+ int smem_flags = 0;
+ int domain;
vidc_inst = get_vidc_inst(file, fh);
v4l2_inst = get_v4l2_inst(file, fh);
if (!v4l2_inst->mem_client) {
@@ -776,6 +778,7 @@
goto exit;
}
for (i = 0; i < b->length; ++i) {
+ smem_flags = 0;
if (EXTRADATA_IDX(b->length) &&
(i == EXTRADATA_IDX(b->length)) &&
!b->m.planes[i].length) {
@@ -792,8 +795,22 @@
kfree(binfo);
goto exit;
}
+ if ((vidc_inst->mode == VIDC_SECURE)
+ && (!EXTRADATA_IDX(b->length)
+ || (i != EXTRADATA_IDX(b->length)))) {
+ smem_flags |= SMEM_SECURE;
+ domain =
+ vidc_inst->core->resources.io_map[CP_MAP].domain;
+ } else
+ domain =
+ vidc_inst->core->resources.io_map[NS_MAP].domain;
+
+ if (b->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
+ smem_flags |= SMEM_INPUT;
+
temp = get_same_fd_buffer(&v4l2_inst->registered_bufs,
b->m.planes[i].reserved[0], &plane);
+
if (temp) {
binfo->type = b->type;
binfo->fd[i] = b->m.planes[i].reserved[0];
@@ -807,8 +824,7 @@
handle = msm_smem_user_to_kernel(v4l2_inst->mem_client,
b->m.planes[i].reserved[0],
b->m.planes[i].reserved[1],
- vidc_inst->core->resources.io_map[NS_MAP].domain,
- 0);
+ domain, 0, smem_flags);
if (!handle) {
dprintk(VIDC_ERR,
"Failed to get device buffer address\n");
@@ -1119,9 +1135,11 @@
- SHARED_QSIZE;
partition[1].size = SHARED_QSIZE;
layout.npartitions = 2;
+ layout.is_secure = 0;
} else {
partition[0].size = io_map[i].addr_range[1];
layout.npartitions = 1;
+ layout.is_secure = 1;
}
layout.partitions = &partition[0];
layout.client_name = io_map[i].name;
diff --git a/drivers/media/video/msm_vidc/msm_vdec.c b/drivers/media/video/msm_vidc/msm_vdec.c
index 22063d4..c4bfaf4 100644
--- a/drivers/media/video/msm_vidc/msm_vdec.c
+++ b/drivers/media/video/msm_vidc/msm_vdec.c
@@ -156,7 +156,15 @@
.minimum = V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_DISABLE,
.maximum = V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_ENABLE,
.default_value = V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_DISABLE,
- .step = 1,
+ },
+ {
+ .id = V4L2_CID_MPEG_VIDC_VIDEO_SECURE,
+ .name = "Secure mode",
+ .type = V4L2_CTRL_TYPE_BUTTON,
+ .minimum = 0,
+ .maximum = 0,
+ .default_value = 0,
+ .step = 0,
.menu_skip_mask = 0,
.qmenu = NULL,
},
@@ -518,6 +526,9 @@
fmt->get_frame_size(i,
f->fmt.pix_mp.height,
f->fmt.pix_mp.width);
+ inst->bufq[OUTPUT_PORT].
+ vb2_bufq.plane_sizes[i] =
+ f->fmt.pix_mp.plane_fmt[i].sizeimage;
}
} else {
f->fmt.pix_mp.plane_fmt[0].sizeimage =
@@ -527,6 +538,11 @@
f->fmt.pix_mp.plane_fmt[extra_idx].sizeimage =
inst->buff_req.buffer[HAL_BUFFER_EXTRADATA_OUTPUT].buffer_size;
}
+ for (i = 0; i < fmt->num_planes; ++i)
+ inst->bufq[CAPTURE_PORT].
+ vb2_bufq.plane_sizes[i] =
+ f->fmt.pix_mp.plane_fmt[i].sizeimage;
+
}
} else {
dprintk(VIDC_ERR,
@@ -624,6 +640,10 @@
}
}
f->fmt.pix_mp.num_planes = fmt->num_planes;
+ for (i = 0; i < fmt->num_planes; ++i) {
+ inst->bufq[CAPTURE_PORT].vb2_bufq.plane_sizes[i] =
+ f->fmt.pix_mp.plane_fmt[i].sizeimage;
+ }
} else if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
inst->prop.width = f->fmt.pix_mp.width;
inst->prop.height = f->fmt.pix_mp.height;
@@ -652,6 +672,10 @@
fmt->get_frame_size(0, f->fmt.pix_mp.height,
f->fmt.pix_mp.width);
f->fmt.pix_mp.num_planes = fmt->num_planes;
+ for (i = 0; i < fmt->num_planes; ++i) {
+ inst->bufq[OUTPUT_PORT].vb2_bufq.plane_sizes[i] =
+ f->fmt.pix_mp.plane_fmt[i].sizeimage;
+ }
}
err_invalid_fmt:
return rc;
@@ -933,7 +957,8 @@
case V4L2_DEC_CMD_STOP:
rc = msm_comm_release_scratch_buffers(inst);
if (rc)
- pr_err("Failed to release scratch buffers: %d\n", rc);
+ dprintk(VIDC_ERR,
+ "Failed to release scratch buffers: %d\n", rc);
rc = msm_comm_release_persist_buffers(inst);
if (rc)
pr_err("Failed to release persist buffers: %d\n", rc);
@@ -1002,17 +1027,8 @@
void *pdata;
struct msm_vidc_inst *inst = container_of(ctrl->handler,
struct msm_vidc_inst, ctrl_handler);
- rc = msm_comm_try_state(inst, MSM_VIDC_OPEN_DONE);
-
- if (rc) {
- dprintk(VIDC_ERR,
- "Failed to move inst: %p to start done state\n", inst);
- goto failed_open_done;
- }
-
control.id = ctrl->id;
control.value = ctrl->val;
-
switch (control.id) {
case V4L2_CID_MPEG_VIDC_VIDEO_STREAM_FORMAT:
property_id =
@@ -1067,10 +1083,20 @@
hal_property.enable = control.value;
pdata = &hal_property;
break;
+ case V4L2_CID_MPEG_VIDC_VIDEO_SECURE:
+ inst->mode = VIDC_SECURE;
+ dprintk(VIDC_DBG, "Setting secure mode to :%d\n", inst->mode);
+ break;
default:
break;
- }
+ }
if (property_id) {
+ rc = msm_comm_try_state(inst, MSM_VIDC_OPEN_DONE);
+ if (rc) {
+ dprintk(VIDC_ERR,
+ "Failed to move inst: %p to start done state\n", inst);
+ goto failed_open_done;
+ }
dprintk(VIDC_DBG,
"Control: HAL property=%d,ctrl_id=%d,ctrl_value=%d\n",
property_id,
@@ -1082,9 +1108,7 @@
}
if (rc)
dprintk(VIDC_ERR, "Failed to set hal property for framesize\n");
-
failed_open_done:
-
return rc;
}
static int msm_vdec_op_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
diff --git a/drivers/media/video/msm_vidc/msm_venc.c b/drivers/media/video/msm_vidc/msm_venc.c
index d53da9e..d01841d 100644
--- a/drivers/media/video/msm_vidc/msm_venc.c
+++ b/drivers/media/video/msm_vidc/msm_venc.c
@@ -23,7 +23,6 @@
#define DEFAULT_WIDTH 1280
#define MIN_NUM_OUTPUT_BUFFERS 4
#define MAX_NUM_OUTPUT_BUFFERS 8
-#define MAX_INPUT_BUFFERS 32
#define MIN_BIT_RATE 64000
#define MAX_BIT_RATE 160000000
#define DEFAULT_BIT_RATE 64000
@@ -594,11 +593,11 @@
spin_lock_irqsave(&inst->lock, flags);
*num_buffers = inst->buff_req.buffer[0].buffer_count_actual =
max(*num_buffers, inst->buff_req.buffer[0].
- buffer_count_actual);
+ buffer_count_actual);
spin_unlock_irqrestore(&inst->lock, flags);
property_id = HAL_PARAM_BUFFER_COUNT_ACTUAL;
new_buf_count.buffer_type = HAL_BUFFER_INPUT;
- new_buf_count.buffer_count_actual = MAX_INPUT_BUFFERS;
+ new_buf_count.buffer_count_actual = *num_buffers;
rc = vidc_hal_session_set_property(inst->session,
property_id, &new_buf_count);
dprintk(VIDC_DBG, "size = %d, alignment = %d, count = %d\n",
diff --git a/drivers/media/video/msm_vidc/msm_vidc.c b/drivers/media/video/msm_vidc/msm_vidc.c
index 1d0124f..64897c7 100644
--- a/drivers/media/video/msm_vidc/msm_vidc.c
+++ b/drivers/media/video/msm_vidc/msm_vidc.c
@@ -413,7 +413,7 @@
inst = kzalloc(sizeof(*inst), GFP_KERNEL);
if (!inst) {
- pr_err("Failed to allocate memory\n") ;
+ dprintk(VIDC_ERR, "Failed to allocate memory\n");
rc = -ENOMEM;
goto err_invalid_core;
}
diff --git a/drivers/media/video/msm_vidc/msm_vidc_common.c b/drivers/media/video/msm_vidc/msm_vidc_common.c
index 9c81d40..9c7472a 100644
--- a/drivers/media/video/msm_vidc/msm_vidc_common.c
+++ b/drivers/media/video/msm_vidc/msm_vidc_common.c
@@ -18,6 +18,7 @@
#include <mach/iommu.h>
#include <mach/iommu_domains.h>
#include <mach/subsystem_restart.h>
+#include <mach/scm.h>
#include "msm_vidc_common.h"
#include "vidc_hal_api.h"
@@ -50,6 +51,18 @@
__mbs;\
})
+#define TZBSP_MEM_PROTECT_VIDEO_VAR 0x8
+struct tzbsp_memprot {
+ u32 cp_start;
+ u32 cp_size;
+ u32 cp_nonpixel_start;
+ u32 cp_nonpixel_size;
+};
+
+struct tzbsp_resp {
+ int ret;
+};
+
static const u32 bus_table[] = {
0,
36000,
@@ -140,6 +153,31 @@
return rc;
}
+static int protect_cp_mem(struct msm_vidc_core *core)
+{
+ struct tzbsp_memprot memprot;
+ unsigned int resp = 0;
+ int rc = 0;
+ struct msm_vidc_iommu_info *io_map = core->resources.io_map;
+ if (!io_map) {
+ dprintk(VIDC_ERR, "invalid params: %p\n", io_map);
+ return -EINVAL;
+ }
+ memprot.cp_start = 0x0;
+ memprot.cp_size = io_map[CP_MAP].addr_range[0] +
+ io_map[CP_MAP].addr_range[1];
+ memprot.cp_nonpixel_start = 0;
+ memprot.cp_nonpixel_size = 0;
+
+ rc = scm_call(SCM_SVC_CP, TZBSP_MEM_PROTECT_VIDEO_VAR, &memprot,
+ sizeof(memprot), &resp, sizeof(resp));
+ if (rc)
+ dprintk(VIDC_ERR,
+ "Failed to protect memory , rc is :%d, response : %d\n",
+ rc, resp);
+ return rc;
+}
+
struct msm_vidc_core *get_vidc_core(int core_id)
{
struct msm_vidc_core *core;
@@ -924,13 +962,16 @@
rc = -ENOMEM;
goto fail_subsystem_get;
}
-
rc = msm_comm_enable_clks(core);
if (rc) {
dprintk(VIDC_ERR, "Failed to enable clocks: %d\n", rc);
goto fail_enable_clks;
}
-
+ rc = protect_cp_mem(core);
+ if (rc) {
+ dprintk(VIDC_ERR, "Failed to protect memory\n");
+ goto fail_iommu_attach;
+ }
rc = msm_comm_iommu_attach(core);
if (rc) {
dprintk(VIDC_ERR, "Failed to attach iommu");
@@ -953,10 +994,10 @@
return;
}
if (core->resources.fw.cookie) {
- subsystem_put(core->resources.fw.cookie);
- core->resources.fw.cookie = NULL;
msm_comm_iommu_detach(core);
msm_comm_disable_clks(core);
+ subsystem_put(core->resources.fw.cookie);
+ core->resources.fw.cookie = NULL;
}
}
@@ -1431,6 +1472,25 @@
return rc;
}
+static int get_flipped_state(int present_state,
+ int desired_state)
+{
+ int flipped_state = present_state;
+ if (flipped_state < MSM_VIDC_STOP
+ && desired_state > MSM_VIDC_STOP) {
+ flipped_state = MSM_VIDC_STOP + (MSM_VIDC_STOP - flipped_state);
+ flipped_state &= 0xFFFE;
+ flipped_state = flipped_state - 1;
+ } else if (flipped_state > MSM_VIDC_STOP
+ && desired_state < MSM_VIDC_STOP) {
+ flipped_state = MSM_VIDC_STOP -
+ (flipped_state - MSM_VIDC_STOP + 1);
+ flipped_state &= 0xFFFE;
+ flipped_state = flipped_state - 1;
+ }
+ return flipped_state;
+}
+
int msm_comm_try_state(struct msm_vidc_inst *inst, int state)
{
int rc = 0;
@@ -1457,89 +1517,77 @@
"Core is in bad state can't change the state");
goto exit;
}
- flipped_state = inst->state;
- if (flipped_state < MSM_VIDC_STOP
- && state > MSM_VIDC_STOP) {
- flipped_state = MSM_VIDC_STOP + (MSM_VIDC_STOP - flipped_state);
- flipped_state &= 0xFFFE;
- flipped_state = flipped_state - 1;
- } else if (flipped_state > MSM_VIDC_STOP
- && state < MSM_VIDC_STOP) {
- flipped_state = MSM_VIDC_STOP -
- (flipped_state - MSM_VIDC_STOP + 1);
- flipped_state &= 0xFFFE;
- flipped_state = flipped_state - 1;
- }
+ flipped_state = get_flipped_state(inst->state, state);
dprintk(VIDC_DBG,
"flipped_state = 0x%x\n", flipped_state);
switch (flipped_state) {
case MSM_VIDC_CORE_UNINIT_DONE:
case MSM_VIDC_CORE_INIT:
rc = msm_comm_init_core(inst);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_CORE_INIT_DONE:
rc = msm_comm_init_core_done(inst);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_OPEN:
rc = msm_comm_session_init(flipped_state, inst);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_OPEN_DONE:
rc = wait_for_state(inst, flipped_state, MSM_VIDC_OPEN_DONE,
SESSION_INIT_DONE);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_LOAD_RESOURCES:
rc = msm_vidc_load_resources(flipped_state, inst);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_LOAD_RESOURCES_DONE:
case MSM_VIDC_START:
rc = msm_vidc_start(flipped_state, inst);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_START_DONE:
rc = wait_for_state(inst, flipped_state, MSM_VIDC_START_DONE,
SESSION_START_DONE);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_STOP:
rc = msm_vidc_stop(flipped_state, inst);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_STOP_DONE:
rc = wait_for_state(inst, flipped_state, MSM_VIDC_STOP_DONE,
SESSION_STOP_DONE);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
dprintk(VIDC_DBG, "Moving to Stop Done state\n");
case MSM_VIDC_RELEASE_RESOURCES:
rc = msm_vidc_release_res(flipped_state, inst);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_RELEASE_RESOURCES_DONE:
rc = wait_for_state(inst, flipped_state,
MSM_VIDC_RELEASE_RESOURCES_DONE,
SESSION_RELEASE_RESOURCE_DONE);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
dprintk(VIDC_DBG,
"Moving to release resources done state\n");
case MSM_VIDC_CLOSE:
rc = msm_comm_session_close(flipped_state, inst);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_CLOSE_DONE:
rc = wait_for_state(inst, flipped_state, MSM_VIDC_CLOSE_DONE,
SESSION_END_DONE);
- if (rc || state <= inst->state)
+ if (rc || state <= get_flipped_state(inst->state, state))
break;
case MSM_VIDC_CORE_UNINIT:
dprintk(VIDC_DBG, "Sending core uninit\n");
rc = msm_vidc_deinit_core(inst);
- if (rc || state == inst->state)
+ if (rc || state == get_flipped_state(inst->state, state))
break;
default:
dprintk(VIDC_ERR, "State not recognized\n");
@@ -1841,6 +1889,8 @@
struct internal_buf *binfo;
struct vidc_buffer_addr_info buffer_info;
unsigned long flags;
+ int domain;
+ unsigned long smem_flags = 0;
struct hal_buffer_requirements *scratch_buf =
&inst->buff_req.buffer[HAL_BUFFER_INTERNAL_SCRATCH];
int i;
@@ -1850,14 +1900,18 @@
scratch_buf->buffer_size);
if (msm_comm_release_scratch_buffers(inst))
dprintk(VIDC_WARN, "Failed to release scratch buffers\n");
+ if (inst->mode == VIDC_SECURE) {
+ domain = inst->core->resources.io_map[CP_MAP].domain;
+ smem_flags |= SMEM_SECURE;
+ } else
+ domain = inst->core->resources.io_map[NS_MAP].domain;
if (scratch_buf->buffer_size) {
for (i = 0; i < scratch_buf->buffer_count_actual;
i++) {
handle = msm_smem_alloc(inst->mem_client,
- scratch_buf->buffer_size, 1, SMEM_UNCACHED,
- inst->core->resources.io_map[NS_MAP].domain,
- 0, 0);
+ scratch_buf->buffer_size, 1, smem_flags,
+ domain, 0, 0);
if (!handle) {
dprintk(VIDC_ERR,
"Failed to allocate scratch memory\n");
@@ -1903,6 +1957,8 @@
struct internal_buf *binfo;
struct vidc_buffer_addr_info buffer_info;
unsigned long flags;
+ unsigned long smem_flags = 0;
+ int domain;
struct hal_buffer_requirements *persist_buf =
&inst->buff_req.buffer[HAL_BUFFER_INTERNAL_PERSIST];
int i;
@@ -1916,12 +1972,17 @@
return rc;
}
+ if (inst->mode == VIDC_SECURE) {
+ domain = inst->core->resources.io_map[CP_MAP].domain;
+ flags |= SMEM_SECURE;
+ } else
+ domain = inst->core->resources.io_map[NS_MAP].domain;
+
if (persist_buf->buffer_size) {
for (i = 0; i < persist_buf->buffer_count_actual; i++) {
handle = msm_smem_alloc(inst->mem_client,
- persist_buf->buffer_size, 1, SMEM_UNCACHED,
- inst->core->resources.io_map[NS_MAP].domain,
- 0, 0);
+ persist_buf->buffer_size, 1, smem_flags,
+ domain, 0, 0);
if (!handle) {
dprintk(VIDC_ERR,
"Failed to allocate persist memory\n");
diff --git a/drivers/media/video/msm_vidc/msm_vidc_internal.h b/drivers/media/video/msm_vidc/msm_vidc_internal.h
index 8e1a99e..5b2cced 100644
--- a/drivers/media/video/msm_vidc/msm_vidc_internal.h
+++ b/drivers/media/video/msm_vidc/msm_vidc_internal.h
@@ -210,6 +210,11 @@
bool ssr_in_progress;
};
+enum msm_vidc_mode {
+ VIDC_NON_SECURE,
+ VIDC_SECURE,
+};
+
struct msm_vidc_core {
struct list_head list;
struct mutex sync_lock;
@@ -260,6 +265,7 @@
void *priv;
struct msm_vidc_debug debug;
struct buf_count count;
+ enum msm_vidc_mode mode;
};
extern struct msm_vidc_drv *vidc_driver;
diff --git a/drivers/media/video/msm_vidc/vidc_hal.c b/drivers/media/video/msm_vidc/vidc_hal.c
index 2a3752f..f44be4d 100644
--- a/drivers/media/video/msm_vidc/vidc_hal.c
+++ b/drivers/media/video/msm_vidc/vidc_hal.c
@@ -541,7 +541,7 @@
mem_addr = &dev->mem_addr;
rc = vidc_hal_alloc((void *) mem_addr,
dev->hal_client, uc_size, 1,
- SMEM_UNCACHED, domain);
+ 0, domain);
if (rc) {
dprintk(VIDC_ERR, "iface_q_table_alloc_fail");
return -ENOMEM;
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
index b34b069..e7a3741 100644
--- a/drivers/mmc/host/sdhci-pci.c
+++ b/drivers/mmc/host/sdhci-pci.c
@@ -23,8 +23,9 @@
#include <linux/scatterlist.h>
#include <linux/io.h>
#include <linux/gpio.h>
-#include <linux/pm_runtime.h>
#include <linux/mmc/sdhci-pci-data.h>
+#include <linux/sfi.h>
+#include <linux/pm_runtime.h>
#include "sdhci.h"
@@ -1451,6 +1452,8 @@
int i;
struct sdhci_pci_chip *chip;
+ sdhci_pci_runtime_pm_forbid(&pdev->dev);
+
chip = pci_get_drvdata(pdev);
if (chip) {
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 55a164f..425d092 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -672,6 +672,7 @@
}
#ifdef CONFIG_PM_SLEEP
+
static int sdhci_s3c_suspend(struct device *dev)
{
struct sdhci_host *host = dev_get_drvdata(dev);
@@ -712,6 +713,13 @@
#define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
+static const struct dev_pm_ops sdhci_s3c_pmops = {
+ .suspend = sdhci_s3c_suspend,
+ .resume = sdhci_s3c_resume,
+};
+
+#define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
+
#else
#define SDHCI_S3C_PMOPS NULL
#endif
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 6df3410..6451d62 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -21,6 +21,7 @@
#include <linux/slab.h>
#include <linux/scatterlist.h>
#include <linux/regulator/consumer.h>
+#include <linux/pm_runtime.h>
#include <linux/leds.h>
@@ -42,14 +43,29 @@
#define MAX_TUNING_LOOP 40
static unsigned int debug_quirks = 0;
+static unsigned int debug_quirks2;
static void sdhci_finish_data(struct sdhci_host *);
static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
static void sdhci_finish_command(struct sdhci_host *);
-static int sdhci_execute_tuning(struct mmc_host *mmc);
+static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
static void sdhci_tuning_timer(unsigned long data);
+#ifdef CONFIG_PM_RUNTIME
+static int sdhci_runtime_pm_get(struct sdhci_host *host);
+static int sdhci_runtime_pm_put(struct sdhci_host *host);
+#else
+static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
+{
+ return 0;
+}
+static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
+{
+ return 0;
+}
+#endif
+
static void sdhci_dumpregs(struct sdhci_host *host)
{
printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
@@ -134,6 +150,9 @@
(host->mmc->caps & MMC_CAP_NONREMOVABLE))
return;
+ if (host->quirks2 & SDHCI_QUIRK2_OWN_CARD_DETECTION)
+ return;
+
if (enable)
sdhci_unmask_irqs(host, irqs);
else
@@ -249,11 +268,14 @@
spin_lock_irqsave(&host->lock, flags);
+ if (host->runtime_suspended)
+ goto out;
+
if (brightness == LED_OFF)
sdhci_deactivate_led(host);
else
sdhci_activate_led(host);
-
+out:
spin_unlock_irqrestore(&host->lock, flags);
}
#endif
@@ -653,9 +675,7 @@
break;
}
- if (count >= 0xF) {
- printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
- mmc_hostname(host->mmc), cmd->opcode);
+ if (count >= 0xF)
count = 0xE;
return count;
@@ -992,7 +1012,8 @@
flags |= SDHCI_CMD_INDEX;
/* CMD19 is special in that the Data Present Select should be set */
- if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
+ if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
+ cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
flags |= SDHCI_CMD_DATA;
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
@@ -1208,6 +1229,8 @@
host = mmc_priv(mmc);
+ sdhci_runtime_pm_get(host);
+
spin_lock_irqsave(&host->lock, flags);
WARN_ON(host->mrq != NULL);
@@ -1251,7 +1274,7 @@
if ((host->flags & SDHCI_NEEDS_RETUNING) &&
!(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
spin_unlock_irqrestore(&host->lock, flags);
- sdhci_execute_tuning(mmc);
+ sdhci_execute_tuning(mmc, mrq->cmd->opcode);
spin_lock_irqsave(&host->lock, flags);
/* Restore original mmc_request structure */
@@ -1268,14 +1291,11 @@
spin_unlock_irqrestore(&host->lock, flags);
}
-static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
{
- struct sdhci_host *host;
unsigned long flags;
u8 ctrl;
- host = mmc_priv(mmc);
-
spin_lock_irqsave(&host->lock, flags);
if (host->flags & SDHCI_DEVICE_DEAD)
@@ -1338,7 +1358,8 @@
unsigned int clock;
/* In case of UHS-I modes, set High Speed Enable */
- if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
+ if ((ios->timing == MMC_TIMING_MMC_HS200) ||
+ (ios->timing == MMC_TIMING_UHS_SDR50) ||
(ios->timing == MMC_TIMING_UHS_SDR104) ||
(ios->timing == MMC_TIMING_UHS_DDR50) ||
(ios->timing == MMC_TIMING_UHS_SDR25))
@@ -1391,7 +1412,9 @@
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
/* Select Bus Speed Mode for host */
ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
- if (ios->timing == MMC_TIMING_UHS_SDR12)
+ if (ios->timing == MMC_TIMING_MMC_HS200)
+ ctrl_2 |= SDHCI_CTRL_HS_SDR200;
+ else if (ios->timing == MMC_TIMING_UHS_SDR12)
ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
else if (ios->timing == MMC_TIMING_UHS_SDR25)
ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
@@ -1424,7 +1447,16 @@
spin_unlock_irqrestore(&host->lock, flags);
}
-static int check_ro(struct sdhci_host *host)
+static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+
+ sdhci_runtime_pm_get(host);
+ sdhci_do_set_ios(host, ios);
+ sdhci_runtime_pm_put(host);
+}
+
+static int sdhci_check_ro(struct sdhci_host *host)
{
unsigned long flags;
int is_readonly;
@@ -1448,19 +1480,16 @@
#define SAMPLE_COUNT 5
-static int sdhci_get_ro(struct mmc_host *mmc)
+static int sdhci_do_get_ro(struct sdhci_host *host)
{
- struct sdhci_host *host;
int i, ro_count;
- host = mmc_priv(mmc);
-
if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
- return check_ro(host);
+ return sdhci_check_ro(host);
ro_count = 0;
for (i = 0; i < SAMPLE_COUNT; i++) {
- if (check_ro(host)) {
+ if (sdhci_check_ro(host)) {
if (++ro_count > SAMPLE_COUNT / 2)
return 1;
}
@@ -1469,38 +1498,64 @@
return 0;
}
-static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+static void sdhci_hw_reset(struct mmc_host *mmc)
{
- struct sdhci_host *host;
- unsigned long flags;
+ struct sdhci_host *host = mmc_priv(mmc);
- host = mmc_priv(mmc);
+ if (host->ops && host->ops->hw_reset)
+ host->ops->hw_reset(host);
+}
- spin_lock_irqsave(&host->lock, flags);
+static int sdhci_get_ro(struct mmc_host *mmc)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ int ret;
+ sdhci_runtime_pm_get(host);
+ ret = sdhci_do_get_ro(host);
+ sdhci_runtime_pm_put(host);
+ return ret;
+}
+
+static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
+{
if (host->flags & SDHCI_DEVICE_DEAD)
goto out;
if (enable)
+ host->flags |= SDHCI_SDIO_IRQ_ENABLED;
+ else
+ host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
+
+ /* SDIO IRQ will be enabled as appropriate in runtime resume */
+ if (host->runtime_suspended)
+ goto out;
+
+ if (enable)
sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
else
sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
out:
mmiowb();
+}
+static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ unsigned long flags;
+
+ spin_lock_irqsave(&host->lock, flags);
+ sdhci_enable_sdio_irq_nolock(host, enable);
spin_unlock_irqrestore(&host->lock, flags);
}
-static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
- struct mmc_ios *ios)
+static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
+ struct mmc_ios *ios)
{
- struct sdhci_host *host;
u8 pwr;
u16 clk, ctrl;
u32 present_state;
- host = mmc_priv(mmc);
-
/*
* Signal Voltage Switching is only applicable for Host Controllers
* v3.00 and above.
@@ -1593,7 +1648,21 @@
return 0;
}
-static int sdhci_execute_tuning(struct mmc_host *mmc)
+static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ int err;
+
+ if (host->version < SDHCI_SPEC_300)
+ return 0;
+ sdhci_runtime_pm_get(host);
+ err = sdhci_do_start_signal_voltage_switch(host, ios);
+ sdhci_runtime_pm_put(host);
+ return err;
+}
+
+static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
{
struct sdhci_host *host;
u16 ctrl;
@@ -1601,26 +1670,35 @@
int tuning_loop_counter = MAX_TUNING_LOOP;
unsigned long timeout;
int err = 0;
+ bool requires_tuning_nonuhs = false;
host = mmc_priv(mmc);
+ sdhci_runtime_pm_get(host);
disable_irq(host->irq);
spin_lock(&host->lock);
ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
/*
- * Host Controller needs tuning only in case of SDR104 mode
- * and for SDR50 mode when Use Tuning for SDR50 is set in
+ * The Host Controller needs tuning only in case of SDR104 mode
+ * and for SDR50 mode when Use Tuning for SDR50 is set in the
* Capabilities register.
+ * If the Host Controller supports the HS200 mode then the
+ * tuning function has to be executed.
*/
+ if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
+ (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
+ host->flags & SDHCI_HS200_NEEDS_TUNING))
+ requires_tuning_nonuhs = true;
+
if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
- (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
- (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
+ requires_tuning_nonuhs)
ctrl |= SDHCI_CTRL_EXEC_TUNING;
else {
spin_unlock(&host->lock);
enable_irq(host->irq);
+ sdhci_runtime_pm_put(host);
return 0;
}
@@ -1646,12 +1724,12 @@
timeout = 150;
do {
struct mmc_command cmd = {0};
- struct mmc_request mrq = {0};
+ struct mmc_request mrq = {NULL};
if (!tuning_loop_counter && !timeout)
break;
- cmd.opcode = MMC_SEND_TUNING_BLOCK;
+ cmd.opcode = opcode;
cmd.arg = 0;
cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
cmd.retries = 0;
@@ -1666,7 +1744,17 @@
* block to the Host Controller. So we set the block size
* to 64 here.
*/
- sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
+ if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
+ if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
+ SDHCI_BLOCK_SIZE);
+ else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
+ SDHCI_BLOCK_SIZE);
+ } else {
+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
+ SDHCI_BLOCK_SIZE);
+ }
/*
* The tuning block is sent by the card to the host controller.
@@ -1764,18 +1852,16 @@
sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
spin_unlock(&host->lock);
enable_irq(host->irq);
+ sdhci_runtime_pm_put(host);
return err;
}
-static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
+static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
{
- struct sdhci_host *host;
u16 ctrl;
unsigned long flags;
- host = mmc_priv(mmc);
-
/* Host Controller v3.00 defines preset value registers */
if (host->version < SDHCI_SPEC_300)
return;
@@ -1791,18 +1877,30 @@
if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+ host->flags |= SDHCI_PV_ENABLED;
} else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+ host->flags &= ~SDHCI_PV_ENABLED;
}
spin_unlock_irqrestore(&host->lock, flags);
}
+static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+
+ sdhci_runtime_pm_get(host);
+ sdhci_do_enable_preset_value(host, enable);
+ sdhci_runtime_pm_put(host);
+}
+
static const struct mmc_host_ops sdhci_ops = {
.request = sdhci_request,
.set_ios = sdhci_set_ios,
.get_ro = sdhci_get_ro,
+ .hw_reset = sdhci_hw_reset,
.enable_sdio_irq = sdhci_enable_sdio_irq,
.start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
.execute_tuning = sdhci_execute_tuning,
@@ -1824,19 +1922,19 @@
spin_lock_irqsave(&host->lock, flags);
- if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
- if (host->mrq) {
- printk(KERN_ERR "%s: Card removed during transfer!\n",
- mmc_hostname(host->mmc));
- printk(KERN_ERR "%s: Resetting controller.\n",
- mmc_hostname(host->mmc));
+ /* Check host->mrq first in case we are runtime suspended */
+ if (host->mrq &&
+ !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
+ printk(KERN_ERR "%s: Card removed during transfer!\n",
+ mmc_hostname(host->mmc));
+ printk(KERN_ERR "%s: Resetting controller.\n",
+ mmc_hostname(host->mmc));
- sdhci_reset(host, SDHCI_RESET_CMD);
- sdhci_reset(host, SDHCI_RESET_DATA);
+ sdhci_reset(host, SDHCI_RESET_CMD);
+ sdhci_reset(host, SDHCI_RESET_DATA);
- host->mrq->cmd->error = -ENOMEDIUM;
- tasklet_schedule(&host->finish_tasklet);
- }
+ host->mrq->cmd->error = -ENOMEDIUM;
+ tasklet_schedule(&host->finish_tasklet);
}
spin_unlock_irqrestore(&host->lock, flags);
@@ -1852,14 +1950,16 @@
host = (struct sdhci_host*)param;
+ spin_lock_irqsave(&host->lock, flags);
+
/*
* If this tasklet gets rescheduled while running, it will
* be run again afterwards but without any active request.
*/
- if (!host->mrq)
+ if (!host->mrq) {
+ spin_unlock_irqrestore(&host->lock, flags);
return;
-
- spin_lock_irqsave(&host->lock, flags);
+ }
del_timer(&host->timer);
@@ -1903,6 +2003,7 @@
spin_unlock_irqrestore(&host->lock, flags);
mmc_request_done(host->mmc, mrq);
+ sdhci_runtime_pm_put(host);
}
static void sdhci_timeout_timer(unsigned long data)
@@ -2036,12 +2137,14 @@
static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
{
+ u32 command;
BUG_ON(intmask == 0);
/* CMD19 generates _only_ Buffer Read Ready interrupt */
if (intmask & SDHCI_INT_DATA_AVAIL) {
- if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
- MMC_SEND_TUNING_BLOCK) {
+ command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
+ if (command == MMC_SEND_TUNING_BLOCK ||
+ command == MMC_SEND_TUNING_BLOCK_HS200) {
host->tuning_done = 1;
wake_up(&host->buf_ready_int);
return;
@@ -2140,6 +2243,13 @@
spin_lock(&host->lock);
+ if (host->runtime_suspended) {
+ spin_unlock(&host->lock);
+ printk(KERN_WARNING "%s: got irq while runtime suspended\n",
+ mmc_hostname(host->mmc));
+ return IRQ_HANDLED;
+ }
+
intmask = sdhci_readl(host, SDHCI_INT_STATUS);
if (!intmask || intmask == 0xffffffff) {
@@ -2226,7 +2336,7 @@
#ifdef CONFIG_PM
-int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
+int sdhci_suspend_host(struct sdhci_host *host)
{
int ret;
@@ -2266,7 +2376,6 @@
return ret;
}
-
if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
if (host->ops->enable_dma)
host->ops->enable_dma(host);
@@ -2317,6 +2426,90 @@
#endif /* CONFIG_PM */
+#ifdef CONFIG_PM_RUNTIME
+
+static int sdhci_runtime_pm_get(struct sdhci_host *host)
+{
+ return pm_runtime_get_sync(host->mmc->parent);
+}
+
+static int sdhci_runtime_pm_put(struct sdhci_host *host)
+{
+ pm_runtime_mark_last_busy(host->mmc->parent);
+ return pm_runtime_put_autosuspend(host->mmc->parent);
+}
+
+int sdhci_runtime_suspend_host(struct sdhci_host *host)
+{
+ unsigned long flags;
+ int ret = 0;
+
+ /* Disable tuning since we are suspending */
+ if (host->version >= SDHCI_SPEC_300 &&
+ host->tuning_mode == SDHCI_TUNING_MODE_1) {
+ del_timer_sync(&host->tuning_timer);
+ host->flags &= ~SDHCI_NEEDS_RETUNING;
+ }
+
+ spin_lock_irqsave(&host->lock, flags);
+ sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ synchronize_irq(host->irq);
+
+ spin_lock_irqsave(&host->lock, flags);
+ host->runtime_suspended = true;
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
+
+int sdhci_runtime_resume_host(struct sdhci_host *host)
+{
+ unsigned long flags;
+ int ret = 0, host_flags = host->flags;
+
+ if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
+ if (host->ops->enable_dma)
+ host->ops->enable_dma(host);
+ }
+
+ sdhci_init(host, 0);
+
+ /* Force clock and power re-program */
+ host->pwr = 0;
+ host->clock = 0;
+ sdhci_do_set_ios(host, &host->mmc->ios);
+
+ sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
+ if (host_flags & SDHCI_PV_ENABLED)
+ sdhci_do_enable_preset_value(host, true);
+
+ /* Set the re-tuning expiration flag */
+ if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
+ (host->tuning_mode == SDHCI_TUNING_MODE_1))
+ host->flags |= SDHCI_NEEDS_RETUNING;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ host->runtime_suspended = false;
+
+ /* Enable SDIO IRQ */
+ if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
+ sdhci_enable_sdio_irq_nolock(host, true);
+
+ /* Enable Card Detection */
+ sdhci_enable_card_detection(host);
+
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
+
+#endif
+
/*****************************************************************************\
* *
* Device allocation/registration *
@@ -2359,6 +2552,8 @@
if (debug_quirks)
host->quirks = debug_quirks;
+ if (debug_quirks2)
+ host->quirks2 = debug_quirks2;
sdhci_reset(host, SDHCI_RESET_ALL);
@@ -2569,10 +2764,14 @@
if (caps[1] & SDHCI_SUPPORT_DDR50)
mmc->caps |= MMC_CAP_UHS_DDR50;
- /* Does the host needs tuning for SDR50? */
+ /* Does the host need tuning for SDR50? */
if (caps[1] & SDHCI_USE_SDR50_TUNING)
host->flags |= SDHCI_SDR50_NEEDS_TUNING;
+ /* Does the host need tuning for HS200? */
+ if (mmc->caps2 & MMC_CAP2_HS200)
+ host->flags |= SDHCI_HS200_NEEDS_TUNING;
+
/* Driver Type(s) (A, C, D) supported by the host */
if (caps[1] & SDHCI_DRIVER_TYPE_A)
mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
@@ -2893,9 +3092,11 @@
module_exit(sdhci_drv_exit);
module_param(debug_quirks, uint, 0444);
+module_param(debug_quirks2, uint, 0444);
MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
MODULE_LICENSE("GPL");
MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
+MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
diff --git a/drivers/video/msm/mdp4_overlay_dsi_video.c b/drivers/video/msm/mdp4_overlay_dsi_video.c
index f5df938..239d9f5 100644
--- a/drivers/video/msm/mdp4_overlay_dsi_video.c
+++ b/drivers/video/msm/mdp4_overlay_dsi_video.c
@@ -168,6 +168,8 @@
pipe = vctrl->base_pipe;
mixer = pipe->mixer_num;
+ mdp_update_pm(vctrl->mfd, vctrl->vsync_time);
+
if (vp->update_cnt == 0) {
mutex_unlock(&vctrl->update_lock);
return cnt;
@@ -1110,7 +1112,6 @@
mdp4_dsi_video_pipe_queue(0, pipe);
}
- mdp_update_pm(mfd, vsync_ctrl_db[0].vsync_time);
mdp4_overlay_mdp_perf_upd(mfd, 1);
cnt = mdp4_dsi_video_pipe_commit(cndx, 0);
diff --git a/drivers/video/msm/mdp4_overlay_dtv.c b/drivers/video/msm/mdp4_overlay_dtv.c
index 4db684b..398fafa 100644
--- a/drivers/video/msm/mdp4_overlay_dtv.c
+++ b/drivers/video/msm/mdp4_overlay_dtv.c
@@ -72,6 +72,7 @@
struct completion dmae_comp;
struct completion vsync_comp;
spinlock_t spin_lock;
+ struct msm_fb_data_type *mfd;
struct mdp4_overlay_pipe *base_pipe;
struct vsync_update vlist[2];
int vsync_irq_enabled;
@@ -180,6 +181,8 @@
mixer = pipe->mixer_num;
mdp4_overlay_iommu_unmap_freelist(mixer);
+ mdp_update_pm(vctrl->mfd, vctrl->vsync_time);
+
if (vp->update_cnt == 0) {
mutex_unlock(&vctrl->update_lock);
return 0;
@@ -442,6 +445,9 @@
int hsync_end_x;
struct fb_info *fbi;
struct fb_var_screeninfo *var;
+ struct vsycn_ctrl *vctrl;
+
+ vctrl = &vsync_ctrl_db[0];
if (!mfd)
return -ENODEV;
@@ -452,6 +458,8 @@
fbi = mfd->fbi;
var = &fbi->var;
+ vctrl->mfd = mfd;
+
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
if (hdmi_prim_display) {
if (is_mdp4_hw_reset()) {
@@ -1132,7 +1140,6 @@
pipe->srcp0_addr = (uint32)mfd->ibuf.buf;
mdp4_dtv_pipe_queue(0, pipe);
}
- mdp_update_pm(mfd, vsync_ctrl_db[0].vsync_time);
if (hdmi_prim_display)
wait = 1;
diff --git a/drivers/video/msm/mdp4_overlay_lcdc.c b/drivers/video/msm/mdp4_overlay_lcdc.c
index 172687a..a7058ce 100644
--- a/drivers/video/msm/mdp4_overlay_lcdc.c
+++ b/drivers/video/msm/mdp4_overlay_lcdc.c
@@ -172,6 +172,8 @@
pipe = vctrl->base_pipe;
mixer = pipe->mixer_num;
+ mdp_update_pm(vctrl->mfd, vctrl->vsync_time);
+
if (vp->update_cnt == 0) {
mutex_unlock(&vctrl->update_lock);
return 0;
@@ -969,7 +971,6 @@
mdp4_lcdc_pipe_queue(0, pipe);
}
- mdp_update_pm(mfd, vsync_ctrl_db[0].vsync_time);
mdp4_overlay_mdp_perf_upd(mfd, 1);
diff --git a/include/linux/diagchar.h b/include/linux/diagchar.h
index 45d7a3e..43daaf2 100644
--- a/include/linux/diagchar.h
+++ b/include/linux/diagchar.h
@@ -675,18 +675,18 @@
};
static const uint32_t msg_bld_masks_22[] = {
- MSG_LVL_HIGH,
- MSG_LVL_HIGH,
- MSG_LVL_HIGH,
- MSG_LVL_HIGH,
- MSG_LVL_HIGH,
- MSG_LVL_HIGH,
- MSG_LVL_HIGH,
- MSG_LVL_HIGH,
- MSG_LVL_HIGH,
- MSG_LVL_HIGH,
- MSG_LVL_HIGH,
- MSG_LVL_HIGH
+ MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW,
+ MSG_LVL_LOW
};
/* LOG CODES */
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index e9051e1..c5b492b 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -91,6 +91,7 @@
unsigned int quirks2; /* More deviations from spec. */
#define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0)
+#define SDHCI_QUIRK2_OWN_CARD_DETECTION (1<<1)
int irq; /* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h
index 41ff312..8f86fce 100644
--- a/include/linux/videodev2.h
+++ b/include/linux/videodev2.h
@@ -1810,6 +1810,8 @@
V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_DISABLE = 0,
V4L2_MPEG_VIDC_VIDEO_SYNC_FRAME_DECODE_ENABLE = 1
};
+#define V4L2_CID_MPEG_VIDC_VIDEO_SECURE (V4L2_CID_MPEG_MSM_VIDC_BASE+24)
+
/* Camera class control IDs */
#define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900)
#define V4L2_CID_CAMERA_CLASS (V4L2_CTRL_CLASS_CAMERA | 1)
diff --git a/sound/soc/msm/Kconfig b/sound/soc/msm/Kconfig
index 894e114..d5cada7 100644
--- a/sound/soc/msm/Kconfig
+++ b/sound/soc/msm/Kconfig
@@ -200,4 +200,15 @@
default n
help
To add support for SoC audio on APQ8060 board
+
+config SND_SOC_MDM9625
+ tristate "SoC Machine driver for MDM9625 boards"
+ depends on ARCH_MSM9625
+ select SND_SOC_QDSP6V2
+ select SND_SOC_MSM_STUB
+ select SND_SOC_WCD9320
+ select SND_SOC_MSM_HOSTLESS_PCM
+ select SND_DYNAMIC_MINORS
+ help
+ To add support for SoC audio on MDM9625 boards.
endmenu
diff --git a/sound/soc/msm/Makefile b/sound/soc/msm/Makefile
index a261184..a4c365a 100644
--- a/sound/soc/msm/Makefile
+++ b/sound/soc/msm/Makefile
@@ -84,3 +84,6 @@
snd-soc-qdsp6v2-objs := msm-dai-fe.o msm-dai-stub.o
obj-$(CONFIG_SND_SOC_QDSP6V2) += snd-soc-qdsp6v2.o
+#for MDM9625 sound card driver
+snd-soc-mdm9625-objs := mdm9625.o
+obj-$(CONFIG_SND_SOC_MDM9625) += snd-soc-mdm9625.o
diff --git a/sound/soc/msm/mdm9625.c b/sound/soc/msm/mdm9625.c
new file mode 100644
index 0000000..b1822f6
--- /dev/null
+++ b/sound/soc/msm/mdm9625.c
@@ -0,0 +1,798 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/qpnp/clkdiv.h>
+#include <sound/core.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/pcm.h>
+#include <sound/jack.h>
+#include <asm/mach-types.h>
+#include <mach/socinfo.h>
+#include <qdsp6v2/msm-pcm-routing-v2.h>
+#include "../codecs/wcd9320.h"
+
+/* MI2S GPIO SECTION */
+
+#define GPIO_MI2S_WS 12
+#define GPIO_MI2S_SCLK 15
+#define GPIO_MI2S_DOUT 14
+#define GPIO_MI2S_DIN 13
+#define GPIO_MI2S_MCLK 71
+
+/* Spk control */
+#define MDM9625_SPK_ON 1
+
+/* MDM9625 run Taiko at 12.288 Mhz.
+ * At present MDM supports 12.288mhz
+ * only. Taiko supports 9.6 MHz also.
+ */
+#define MDM_MCLK_CLK_12P288MHZ 12288000
+#define MDM_MCLK_CLK_9P6HZ 9600000
+#define MDM_IBIT_CLK_DIV_1P56MHZ 7
+
+/* Machine driver Name*/
+#define MDM9625_MACHINE_DRV_NAME "mdm9625-asoc-taiko"
+
+struct mdm9625_machine_data {
+ u32 mclk_freq;
+};
+
+/* MI2S clock */
+struct mdm_mi2s_clk {
+ struct clk *cdc_cr_clk;
+ struct clk *cdc_osr_clk;
+ struct clk *cdc_bit_clk;
+ bool clk_enable;
+
+};
+static struct mdm_mi2s_clk prim_clk;
+
+/* I2S GPIO */
+struct request_gpio {
+ unsigned gpio_no;
+ char *gpio_name;
+};
+static bool cdc_mclk_init;
+static struct mutex cdc_mclk_mutex;
+static int mdm9625_mi2s_rx_ch = 1;
+static int mdm9625_mi2s_tx_ch = 1;
+static int msm_spk_control;
+static atomic_t mi2s_ref_count;
+
+/* MI2S GPIO CONFIG */
+static struct request_gpio mi2s_gpio[] = {
+ {
+ .gpio_no = GPIO_MI2S_WS,
+ .gpio_name = "MI2S_WS",
+ },
+ {
+ .gpio_no = GPIO_MI2S_SCLK,
+ .gpio_name = "MI2S_SCLK",
+ },
+ {
+ .gpio_no = GPIO_MI2S_DOUT,
+ .gpio_name = "MI2S_DOUT",
+ },
+ {
+ .gpio_no = GPIO_MI2S_DIN,
+ .gpio_name = "MI2S_DIN",
+ },
+ {
+ .gpio_no = GPIO_MI2S_MCLK,
+ .gpio_name = "MI2S_MCLK",
+ },
+};
+
+static int mdm9625_enable_codec_ext_clk(struct snd_soc_codec *codec,
+ int enable, bool dapm);
+
+void *def_taiko_mbhc_cal(void);
+
+static struct wcd9xxx_mbhc_config mbhc_cfg = {
+ .read_fw_bin = false,
+ .calibration = NULL,
+ .micbias = MBHC_MICBIAS2,
+ .mclk_cb_fn = mdm9625_enable_codec_ext_clk,
+ .mclk_rate = MDM_MCLK_CLK_12P288MHZ,
+ .gpio = 0,
+ .gpio_irq = 0,
+ .gpio_level_insert = 1,
+ .detect_extn_cable = true,
+ .insert_detect = true,
+ .swap_gnd_mic = NULL,
+};
+
+#define WCD9XXX_MBHC_DEF_BUTTONS 8
+#define WCD9XXX_MBHC_DEF_RLOADS 5
+
+
+static bool gpio_enable;
+
+static int mdm9625_set_mi2s_gpio(void)
+{
+ int rtn = 0;
+ int i;
+ int j;
+
+ if (gpio_enable == false) {
+ for (i = 0; i < ARRAY_SIZE(mi2s_gpio); i++) {
+ rtn = gpio_request(mi2s_gpio[i].gpio_no,
+ mi2s_gpio[i].gpio_name);
+ pr_debug("%s: gpio = %d, gpio name = %s\n"
+ "rtn = %d\n", __func__,
+ mi2s_gpio[i].gpio_no,
+ mi2s_gpio[i].gpio_name,
+ rtn);
+ if (rtn) {
+ pr_err("%s: Failed to request gpio %d\n",
+ __func__, mi2s_gpio[i].gpio_no);
+ /* Release all the GPIO on failure */
+ for (j = i; j >= 0; j--)
+ gpio_free(mi2s_gpio[j].gpio_no);
+ goto err;
+ }
+ }
+ gpio_enable = true;
+ }
+err:
+ return rtn;
+}
+
+static int mdm9625_mi2s_free_gpios(void)
+{
+ int i;
+ pr_debug("%s:", __func__);
+ for (i = 0; i < ARRAY_SIZE(mi2s_gpio); i++)
+ gpio_free(mi2s_gpio[i].gpio_no);
+ gpio_enable = false;
+ return 0;
+}
+static int mdm9625_mi2s_clk_ctl(struct snd_soc_pcm_runtime *rtd, bool enable)
+{
+ struct mdm_mi2s_clk *clk = &prim_clk;
+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+ struct snd_soc_card *card = rtd->card;
+ struct mdm9625_machine_data *pdata = snd_soc_card_get_drvdata(card);
+ int ret = 0;
+
+ if (pdata == NULL) {
+ pr_err("%s:platform data is null\n", __func__);
+ return -ENODEV;
+ }
+
+ if (enable) {
+ if (clk->clk_enable == true) {
+ pr_info("%s:Device clock already enabled\n", __func__);
+ return 0;
+ }
+ /* Set up core clock. */
+ clk->cdc_cr_clk = clk_get(cpu_dai->dev, "core_clk");
+ if (IS_ERR(clk->cdc_cr_clk)) {
+ pr_err("%s: Failed to Core clk %ld\n"
+ "CPU dai name %s\n", __func__,
+ PTR_ERR(clk->cdc_cr_clk),
+ cpu_dai->dev->driver->name);
+ return -ENODEV ;
+ }
+ /* osr clock */
+ clk->cdc_osr_clk = clk_get(cpu_dai->dev, "osr_clk");
+ if (IS_ERR(clk->cdc_osr_clk)) {
+ pr_err("%s: Failed to request OSR %ld\n"
+ "CPU dai name %s\n", __func__,
+ PTR_ERR(clk->cdc_osr_clk),
+ cpu_dai->dev->driver->name);
+ clk_put(clk->cdc_cr_clk);
+ return -ENODEV ;
+ }
+ /* ibit clock */
+ clk->cdc_bit_clk = clk_get(cpu_dai->dev, "ibit_clk");
+ if (IS_ERR(clk->cdc_bit_clk)) {
+ pr_err("%s: Failed to request Bit %ld\n"
+ "CPU dai name %s\n", __func__,
+ PTR_ERR(clk->cdc_bit_clk),
+ cpu_dai->dev->driver->name);
+ clk_put(clk->cdc_cr_clk);
+ clk_put(clk->cdc_osr_clk);
+ return -ENODEV ;
+ }
+ /* Set rate core and ibit clock */
+ clk_set_rate(clk->cdc_cr_clk, pdata->mclk_freq);
+ clk_set_rate(clk->cdc_bit_clk, MDM_IBIT_CLK_DIV_1P56MHZ);
+
+ /* Enable clocks. core clock need not be enabled.
+ * Enabling branch clocks indirectly enables
+ * core clock.
+ */
+ ret = clk_prepare_enable(clk->cdc_osr_clk);
+ if (ret != 0) {
+ pr_err("Fail to enable cdc_osr_clk\n");
+ goto exit_osrclk_err;
+ }
+ ret = clk_prepare_enable(clk->cdc_bit_clk);
+ if (ret != 0) {
+ pr_err("Fail to enable cdc_bit_clk\n");
+ goto exit_bclk_err;
+ }
+ clk->clk_enable = true;
+ return ret;
+ } else {
+ clk->clk_enable = false;
+ ret = 0;
+ goto exit_bclk_err;
+ }
+exit_bclk_err:
+ clk_disable_unprepare(clk->cdc_bit_clk);
+ clk_put(clk->cdc_bit_clk);
+exit_osrclk_err:
+ clk_disable_unprepare(clk->cdc_osr_clk);
+ clk_put(clk->cdc_osr_clk);
+ clk_put(clk->cdc_cr_clk);
+ clk->cdc_cr_clk = NULL;
+ clk->cdc_bit_clk = NULL;
+ clk->cdc_osr_clk = NULL;
+ clk->clk_enable = false;
+ return ret;
+}
+
+static void mdm9625_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ int ret;
+ if (atomic_dec_return(&mi2s_ref_count) == 0) {
+ mdm9625_mi2s_free_gpios();
+ ret = mdm9625_mi2s_clk_ctl(rtd, false);
+ if (ret < 0)
+ pr_err("%s:clock disable failed\n", __func__);
+ }
+}
+
+static int mdm9625_mi2s_startup(struct snd_pcm_substream *substream)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ int ret = 0;
+
+ if (atomic_inc_return(&mi2s_ref_count) == 1) {
+ mdm9625_set_mi2s_gpio();
+ ret = mdm9625_mi2s_clk_ctl(rtd, true);
+ if (ret < 0) {
+ pr_err("set format for codec dai failed\n");
+ return ret;
+ }
+ }
+ /* This sets the CONFIG PARAMETER WS_SRC.
+ * 1 means internal clock master mode.
+ * 0 means external clock slave mode.
+ */
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0)
+ pr_err("set fmt cpu dai failed\n");
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_CBS_CFS);
+ if (ret < 0)
+ pr_err("set fmt for codec dai failed\n");
+
+ return ret;
+}
+
+static int set_codec_mclk(struct snd_soc_pcm_runtime *rtd)
+{
+ int ret = 0;
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ struct snd_soc_card *card = rtd->card;
+ struct mdm9625_machine_data *pdata = snd_soc_card_get_drvdata(card);
+
+ if (cdc_mclk_init == true)
+ return 0;
+ ret = snd_soc_dai_set_sysclk(codec_dai, TAIKO_MCLK_ID, pdata->mclk_freq,
+ SND_SOC_CLOCK_IN);
+ if (ret < 0) {
+ pr_err("%s: Set codec sys clk failed %x", __func__, ret);
+ return ret;
+ }
+ cdc_mclk_init = true;
+ return 0;
+}
+
+static int mdm9625_mi2s_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_interval *rate = hw_param_interval(params,
+ SNDRV_PCM_HW_PARAM_RATE);
+ struct snd_interval *channels = hw_param_interval(params,
+ SNDRV_PCM_HW_PARAM_CHANNELS);
+ rate->min = rate->max = 48000;
+ channels->min = channels->max = mdm9625_mi2s_rx_ch;
+ set_codec_mclk(rtd);
+ return 0;
+}
+
+static int mdm9625_mi2s_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_interval *rate = hw_param_interval(params,
+ SNDRV_PCM_HW_PARAM_RATE);
+ struct snd_interval *channels = hw_param_interval(params,
+ SNDRV_PCM_HW_PARAM_CHANNELS);
+ rate->min = rate->max = 48000;
+ channels->min = channels->max = mdm9625_mi2s_tx_ch;
+ set_codec_mclk(rtd);
+ return 0;
+}
+
+
+static int mdm9625_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ pr_debug("%s: msm9615_i2s_rx_ch = %d\n", __func__,
+ mdm9625_mi2s_rx_ch);
+ ucontrol->value.integer.value[0] = mdm9625_mi2s_rx_ch - 1;
+ return 0;
+}
+
+static int mdm9625_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ mdm9625_mi2s_rx_ch = ucontrol->value.integer.value[0] + 1;
+ pr_debug("%s: msm9615_i2s_rx_ch = %d\n", __func__,
+ mdm9625_mi2s_rx_ch);
+ return 1;
+}
+
+static int mdm9625_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ pr_debug("%s: msm9615_i2s_tx_ch = %d\n", __func__,
+ mdm9625_mi2s_tx_ch);
+ ucontrol->value.integer.value[0] = mdm9625_mi2s_tx_ch - 1;
+ return 0;
+}
+
+static int mdm9625_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ mdm9625_mi2s_tx_ch = ucontrol->value.integer.value[0] + 1;
+ pr_debug("%s: msm9615_i2s_tx_ch = %d\n", __func__,
+ mdm9625_mi2s_tx_ch);
+ return 1;
+}
+
+
+static int mdm9625_mi2s_get_spk(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ pr_debug("%s: msm_spk_control = %d", __func__, msm_spk_control);
+ ucontrol->value.integer.value[0] = msm_spk_control;
+ return 0;
+}
+
+static void mdm_ext_control(struct snd_soc_codec *codec)
+{
+ struct snd_soc_dapm_context *dapm = &codec->dapm;
+ pr_debug("%s: msm_spk_control = %d", __func__, msm_spk_control);
+ mutex_lock(&dapm->codec->mutex);
+ if (msm_spk_control == MDM9625_SPK_ON) {
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Bottom Pos");
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Bottom Neg");
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Top Pos");
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Top Neg");
+ } else {
+ snd_soc_dapm_disable_pin(dapm, "Ext Spk Bottom Pos");
+ snd_soc_dapm_disable_pin(dapm, "Ext Spk Bottom Neg");
+ snd_soc_dapm_disable_pin(dapm, "Ext Spk Top Pos");
+ snd_soc_dapm_disable_pin(dapm, "Ext Spk Top Neg");
+ }
+ snd_soc_dapm_sync(dapm);
+ mutex_unlock(&dapm->codec->mutex);
+}
+
+static int mdm9625_mi2s_set_spk(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ pr_debug("%s()\n", __func__);
+ if (msm_spk_control == ucontrol->value.integer.value[0])
+ return 0;
+ msm_spk_control = ucontrol->value.integer.value[0];
+ mdm_ext_control(codec);
+ return 1;
+}
+
+static int mdm9625_enable_codec_ext_clk(struct snd_soc_codec *codec,
+ int enable, bool dapm)
+{
+ int ret = 0;
+ pr_debug("%s: enable = %d codec name %s\n", __func__,
+ enable, codec->name);
+ mutex_lock(&cdc_mclk_mutex);
+ if (enable)
+ taiko_mclk_enable(codec, 1, dapm);
+ else
+ taiko_mclk_enable(codec, 0, dapm);
+ mutex_unlock(&cdc_mclk_mutex);
+ return ret;
+}
+
+static int mdm9625_mclk_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ pr_debug("%s: event = %d\n", __func__, event);
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ return mdm9625_enable_codec_ext_clk(w->codec, 1, true);
+ case SND_SOC_DAPM_POST_PMD:
+ return mdm9625_enable_codec_ext_clk(w->codec, 0, true);
+ }
+ return 0;
+}
+
+
+static const struct snd_soc_dapm_widget mdm9625_dapm_widgets[] = {
+
+ SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
+ mdm9625_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_SPK("Ext Spk Bottom Pos", NULL),
+ SND_SOC_DAPM_SPK("Ext Spk Bottom Neg", NULL),
+ SND_SOC_DAPM_SPK("Ext Spk Top Pos", NULL),
+ SND_SOC_DAPM_SPK("Ext Spk Top Neg", NULL),
+ SND_SOC_DAPM_MIC("Handset Mic", NULL),
+ SND_SOC_DAPM_MIC("Headset Mic", NULL),
+ SND_SOC_DAPM_MIC("ANCRight Headset Mic", NULL),
+ SND_SOC_DAPM_MIC("ANCLeft Headset Mic", NULL),
+ SND_SOC_DAPM_MIC("Digital Mic1", NULL),
+ SND_SOC_DAPM_MIC("Digital Mic2", NULL),
+ SND_SOC_DAPM_MIC("Digital Mic3", NULL),
+ SND_SOC_DAPM_MIC("Digital Mic4", NULL),
+ SND_SOC_DAPM_MIC("Digital Mic5", NULL),
+ SND_SOC_DAPM_MIC("Digital Mic6", NULL),
+};
+
+static const char *const spk_function[] = {"Off", "On"};
+static const char *const mi2s_rx_ch_text[] = {"One", "Two"};
+static const char *const mi2s_tx_ch_text[] = {"One", "Two"};
+
+static const struct soc_enum mdm9625_enum[] = {
+ SOC_ENUM_SINGLE_EXT(2, spk_function),
+ SOC_ENUM_SINGLE_EXT(2, mi2s_rx_ch_text),
+ SOC_ENUM_SINGLE_EXT(2, mi2s_tx_ch_text),
+};
+
+static const struct snd_kcontrol_new mdm_snd_controls[] = {
+ SOC_ENUM_EXT("Speaker Function", mdm9625_enum[0],
+ mdm9625_mi2s_get_spk,
+ mdm9625_mi2s_set_spk),
+ SOC_ENUM_EXT("MI2S_RX Channels", mdm9625_enum[1],
+ mdm9625_mi2s_rx_ch_get,
+ mdm9625_mi2s_rx_ch_put),
+ SOC_ENUM_EXT("MI2S_TX Channels", mdm9625_enum[2],
+ mdm9625_mi2s_tx_ch_get,
+ mdm9625_mi2s_tx_ch_put),
+};
+
+static int mdm9625_mi2s_audrx_init(struct snd_soc_pcm_runtime *rtd)
+{
+ int err;
+ struct snd_soc_codec *codec = rtd->codec;
+ struct snd_soc_dapm_context *dapm = &codec->dapm;
+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+ pr_info("%s(), dev_name%s\n", __func__, dev_name(cpu_dai->dev));
+
+ rtd->pmdown_time = 0;
+ err = snd_soc_add_codec_controls(codec, mdm_snd_controls,
+ ARRAY_SIZE(mdm_snd_controls));
+ if (err < 0)
+ return err;
+
+ snd_soc_dapm_new_controls(dapm, mdm9625_dapm_widgets,
+ ARRAY_SIZE(mdm9625_dapm_widgets));
+
+ /* After DAPM Enable pins alawys
+ * DAPM SYNC needs to be called.
+ */
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Bottom Pos");
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Bottom Neg");
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Top Pos");
+ snd_soc_dapm_enable_pin(dapm, "Ext Spk Top Neg");
+ snd_soc_dapm_sync(dapm);
+
+ /* start mbhc */
+ mdm9625_set_mi2s_gpio();
+ mdm9625_mi2s_clk_ctl(rtd, true);
+ mbhc_cfg.calibration = def_taiko_mbhc_cal();
+ if (mbhc_cfg.calibration)
+ err = taiko_hs_detect(codec, &mbhc_cfg);
+ else
+ err = -ENOMEM;
+ return err;
+}
+
+void *def_taiko_mbhc_cal(void)
+{
+ void *taiko_cal;
+ struct wcd9xxx_mbhc_btn_detect_cfg *btn_cfg;
+ u16 *btn_low, *btn_high;
+ u8 *n_ready, *n_cic, *gain;
+
+ taiko_cal = kzalloc(WCD9XXX_MBHC_CAL_SIZE(WCD9XXX_MBHC_DEF_BUTTONS,
+ WCD9XXX_MBHC_DEF_RLOADS),
+ GFP_KERNEL);
+ if (!taiko_cal) {
+ pr_err("%s: out of memory\n", __func__);
+ return NULL;
+ }
+
+#define S(X, Y) ((WCD9XXX_MBHC_CAL_GENERAL_PTR(taiko_cal)->X) = (Y))
+ S(t_ldoh, 100);
+ S(t_bg_fast_settle, 100);
+ S(t_shutdown_plug_rem, 255);
+ S(mbhc_nsa, 4);
+ S(mbhc_navg, 4);
+#undef S
+#define S(X, Y) ((WCD9XXX_MBHC_CAL_PLUG_DET_PTR(taiko_cal)->X) = (Y))
+ S(mic_current, TAIKO_PID_MIC_5_UA);
+ S(hph_current, TAIKO_PID_MIC_5_UA);
+ S(t_mic_pid, 100);
+ S(t_ins_complete, 250);
+ S(t_ins_retry, 200);
+#undef S
+#define S(X, Y) ((WCD9XXX_MBHC_CAL_PLUG_TYPE_PTR(taiko_cal)->X) = (Y))
+ S(v_no_mic, 30);
+ S(v_hs_max, 2400);
+#undef S
+#define S(X, Y) ((WCD9XXX_MBHC_CAL_BTN_DET_PTR(taiko_cal)->X) = (Y))
+ S(c[0], 62);
+ S(c[1], 124);
+ S(nc, 1);
+ S(n_meas, 3);
+ S(mbhc_nsc, 11);
+ S(n_btn_meas, 1);
+ S(n_btn_con, 2);
+ S(num_btn, WCD9XXX_MBHC_DEF_BUTTONS);
+ S(v_btn_press_delta_sta, 100);
+ S(v_btn_press_delta_cic, 50);
+#undef S
+ btn_cfg = WCD9XXX_MBHC_CAL_BTN_DET_PTR(taiko_cal);
+ btn_low = wcd9xxx_mbhc_cal_btn_det_mp(btn_cfg, MBHC_BTN_DET_V_BTN_LOW);
+ btn_high = wcd9xxx_mbhc_cal_btn_det_mp(btn_cfg,
+ MBHC_BTN_DET_V_BTN_HIGH);
+ btn_low[0] = -50;
+ btn_high[0] = 10;
+ btn_low[1] = 11;
+ btn_high[1] = 52;
+ btn_low[2] = 53;
+ btn_high[2] = 94;
+ btn_low[3] = 95;
+ btn_high[3] = 133;
+ btn_low[4] = 134;
+ btn_high[4] = 171;
+ btn_low[5] = 172;
+ btn_high[5] = 208;
+ btn_low[6] = 209;
+ btn_high[6] = 244;
+ btn_low[7] = 245;
+ btn_high[7] = 330;
+ n_ready = wcd9xxx_mbhc_cal_btn_det_mp(btn_cfg, MBHC_BTN_DET_N_READY);
+ n_ready[0] = 80;
+ n_ready[1] = 68;
+ n_cic = wcd9xxx_mbhc_cal_btn_det_mp(btn_cfg, MBHC_BTN_DET_N_CIC);
+ n_cic[0] = 60;
+ n_cic[1] = 47;
+ gain = wcd9xxx_mbhc_cal_btn_det_mp(btn_cfg, MBHC_BTN_DET_GAIN);
+ gain[0] = 11;
+ gain[1] = 9;
+
+ return taiko_cal;
+}
+
+
+static struct snd_soc_ops mdm9625_mi2s_be_ops = {
+ .startup = mdm9625_mi2s_startup,
+ .shutdown = mdm9625_mi2s_snd_shutdown,
+};
+
+/* Digital audio interface connects codec <---> CPU */
+static struct snd_soc_dai_link mdm9625_dai[] = {
+ /* FrontEnd DAI Links */
+ {
+ .name = "MDM9625 Media1",
+ .stream_name = "MultiMedia1",
+ .cpu_dai_name = "MultiMedia1",
+ .platform_name = "msm-pcm-dsp",
+ .dynamic = 1,
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ .ignore_suspend = 1,
+ /* This dainlink has playback support */
+ .ignore_pmdown_time = 1,
+ .be_id = MSM_FRONTEND_DAI_MULTIMEDIA1
+ },
+ {
+ .name = "MSM VoIP",
+ .stream_name = "VoIP",
+ .cpu_dai_name = "VoIP",
+ .platform_name = "msm-voip-dsp",
+ .dynamic = 1,
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ .ignore_suspend = 1,
+ /* This dainlink has VOIP support */
+ .ignore_pmdown_time = 1,
+ .be_id = MSM_FRONTEND_DAI_VOIP,
+ },
+ {
+ .name = "Circuit-Switch Voice",
+ .stream_name = "CS-Voice",
+ .cpu_dai_name = "CS-VOICE",
+ .platform_name = "msm-pcm-voice",
+ .dynamic = 1,
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
+ .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
+ .ignore_suspend = 1,
+ /* This dainlink has Voice support */
+ .ignore_pmdown_time = 1,
+ .be_id = MSM_FRONTEND_DAI_CS_VOICE,
+ },
+ {
+ .name = "MI2S Hostless",
+ .stream_name = "MI2S Hostless",
+ .cpu_dai_name = "MI2S_TX_HOSTLESS",
+ .platform_name = "msm-pcm-hostless",
+ .dynamic = 1,
+ .trigger = {SND_SOC_DPCM_TRIGGER_POST,
+ SND_SOC_DPCM_TRIGGER_POST},
+ .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
+ .ignore_suspend = 1,
+ .ignore_pmdown_time = 1,
+ /* This dainlink has MI2S support */
+ .codec_dai_name = "snd-soc-dummy-dai",
+ .codec_name = "snd-soc-dummy",
+ },
+ /* Backend DAI Links */
+ {
+ .name = LPASS_BE_MI2S_RX,
+ .stream_name = "MI2S Playback",
+ .cpu_dai_name = "msm-dai-q6-mi2s.0",
+ .platform_name = "msm-pcm-routing",
+ .codec_name = "taiko_codec",
+ .codec_dai_name = "taiko_i2s_rx1",
+ .no_pcm = 1,
+ .be_id = MSM_BACKEND_DAI_MI2S_RX,
+ .init = &mdm9625_mi2s_audrx_init,
+ .be_hw_params_fixup = &mdm9625_mi2s_rx_be_hw_params_fixup,
+ .ops = &mdm9625_mi2s_be_ops,
+ },
+ {
+ .name = LPASS_BE_MI2S_TX,
+ .stream_name = "MI2S Capture",
+ .cpu_dai_name = "msm-dai-q6-mi2s.0",
+ .platform_name = "msm-pcm-routing",
+ .codec_name = "taiko_codec",
+ .codec_dai_name = "taiko_i2s_tx1",
+ .no_pcm = 1,
+ .be_id = MSM_BACKEND_DAI_MI2S_TX,
+ .be_hw_params_fixup = &mdm9625_mi2s_tx_be_hw_params_fixup,
+ .ops = &mdm9625_mi2s_be_ops,
+ },
+};
+
+static struct snd_soc_card snd_soc_card_mdm9625 = {
+ .name = "mdm9625-taiko-i2s-snd-card",
+ .dai_link = mdm9625_dai,
+ .num_links = ARRAY_SIZE(mdm9625_dai),
+};
+
+static __devinit int mdm9625_asoc_machine_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct snd_soc_card *card = &snd_soc_card_mdm9625;
+ struct mdm9625_machine_data *pdata;
+
+ mutex_init(&cdc_mclk_mutex);
+ gpio_enable = false;
+ cdc_mclk_init = false;
+ if (!pdev->dev.of_node) {
+ dev_err(&pdev->dev, "No platform supplied from device tree\n");
+ return -EINVAL;
+ }
+ pdata = devm_kzalloc(&pdev->dev, sizeof(struct mdm9625_machine_data),
+ GFP_KERNEL);
+ if (!pdata) {
+ dev_err(&pdev->dev, "Can't allocate msm8974_asoc_mach_data\n");
+ ret = -ENOMEM;
+ goto err;
+ }
+ card->dev = &pdev->dev;
+ platform_set_drvdata(pdev, card);
+ snd_soc_card_set_drvdata(card, pdata);
+ ret = snd_soc_of_parse_card_name(card, "qcom,model");
+ if (ret)
+ goto err;
+ ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
+ if (ret)
+ goto err;
+ ret = of_property_read_u32(pdev->dev.of_node,
+ "qcom,taiko-mclk-clk-freq",
+ &pdata->mclk_freq);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "Looking up %s property in node %s failed",
+ "qcom,taiko-mclk-clk-freq",
+ pdev->dev.of_node->full_name);
+ goto err;
+ }
+ /* At present only 12.288MHz is supported on MDM. */
+ if (pdata->mclk_freq != MDM_MCLK_CLK_12P288MHZ) {
+ dev_err(&pdev->dev, "unsupported taiko mclk freq %u\n",
+ pdata->mclk_freq);
+ ret = -EINVAL;
+ goto err;
+ }
+ ret = snd_soc_register_card(card);
+ if (ret) {
+ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
+ ret);
+ goto err;
+ }
+ return 0;
+err:
+ devm_kfree(&pdev->dev, pdata);
+ return ret;
+}
+
+static int __devexit mdm9625_asoc_machine_remove(struct platform_device *pdev)
+{
+ struct snd_soc_card *card = platform_get_drvdata(pdev);
+ struct mdm9625_machine_data *pdata = snd_soc_card_get_drvdata(card);
+ pdata->mclk_freq = 0;
+ snd_soc_unregister_card(card);
+ return 0;
+}
+
+static const struct of_device_id msm9625_asoc_machine_of_match[] = {
+ { .compatible = "qcom,mdm9625-audio-taiko", },
+ {},
+};
+
+static struct platform_driver msm9625_asoc_machine_driver = {
+ .driver = {
+ .name = MDM9625_MACHINE_DRV_NAME,
+ .owner = THIS_MODULE,
+ .pm = &snd_soc_pm_ops,
+ .of_match_table = msm9625_asoc_machine_of_match,
+ },
+ .probe = mdm9625_asoc_machine_probe,
+ .remove = __devexit_p(mdm9625_asoc_machine_remove),
+};
+
+
+module_platform_driver(msm9625_asoc_machine_driver);
+
+MODULE_DESCRIPTION("ALSA SoC msm");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" MDM9625_MACHINE_DRV_NAME);
+MODULE_DEVICE_TABLE(of, msm9625_asoc_machine_of_match);
+