rtc: rtc-sh: SH-2A support.
Trivial support for the SH-2A on-chip RTC.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
diff --git a/drivers/rtc/rtc-sh.c b/drivers/rtc/rtc-sh.c
index a1d5d55..af9bc57 100644
--- a/drivers/rtc/rtc-sh.c
+++ b/drivers/rtc/rtc-sh.c
@@ -26,9 +26,13 @@
#include <asm/rtc.h>
#define DRV_NAME "sh-rtc"
-#define DRV_VERSION "0.1.4"
+#define DRV_VERSION "0.1.5"
-#ifdef CONFIG_CPU_SH3
+#ifdef CONFIG_CPU_SH2A
+#define rtc_reg_size sizeof(u16)
+#define RTC_BIT_INVERTED 0
+#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
+#elif defined(CONFIG_CPU_SH3)
#define rtc_reg_size sizeof(u16)
#define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */
#define RTC_DEF_CAPABILITIES 0UL
@@ -62,6 +66,18 @@
#define RCR1 RTC_REG(14) /* Control */
#define RCR2 RTC_REG(15) /* Control */
+/*
+ * Note on RYRAR and RCR3: Up until this point most of the register
+ * definitions are consistent across all of the available parts. However,
+ * the placement of the optional RYRAR and RCR3 (the RYRAR control
+ * register used to control RYRCNT/RYRAR compare) varies considerably
+ * across various parts, occasionally being mapped in to a completely
+ * unrelated address space. For proper RYRAR support a separate resource
+ * would have to be handed off, but as this is purely optional in
+ * practice, we simply opt not to support it, thereby keeping the code
+ * quite a bit more simplified.
+ */
+
/* ALARM Bits - or with BCD encoded value */
#define AR_ENB 0x80 /* Enable for alarm cmp */