ARM: gic: Add spinlocks for SGIR/AIR/EOI for 8625
On 8625 due to bug in AHB MUX on hready, back to back write followed
by read (from any CPU) on QGIC2 registers (SGIR(WO) ,IAR(RO) and
write on EOI(WO)) cause the read data to get corrupted on AHB bus.
Due to this whenever a valid irq has occurs, and dispatched to the cpu
interface but still cpu reads the IAR as 0x0 and that particular IRQ
becomes active.
But due to incorrect irq id (read as 0x0), IRQ handler will not do
proper EOI for that particular interrupt and thus it gets trapped
in the active state.
Below is the qgic register dump from CPU-1, in this particular case
we see that SGI-3 is not getting clear as cpu reads this as 0x0.
AZSD:C0000200| 00240008 00000000 00008000 00000000 00000000 00000000
00000000 00000000 ..$.............................
AZSD:C0000280| 00240008 00000000 00008000 00000000 00000000 00000000
00000000 00000000 ..$.............................
AZSD:C0000300| 00040008 00000000 00000000 00000000 00000000 00000000
00000000 00000000 ................................
AZSD:C0000380| 00040008 00000000 00000000 00000000 00000000 00000000
00000000 00000000 ................................
As the interrupt gets trapped, no other interrupt received on the core is
services any more causing the system hang.
CRs-Fixed: 349219
Change-Id: Icad2c65114377a08984b1032566cfba811bb4ca8
Signed-off-by: Taniya Das <tdas@codeaurora.org>
1 file changed