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Paul Walmsley801954d2008-08-19 11:08:44 +03001/*
2 * OMAP2/3 clockdomains
3 *
4 * Copyright (C) 2008 Texas Instruments, Inc.
5 * Copyright (C) 2008 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 */
9
10#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
11#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
12
13#include <mach/clockdomain.h>
14
15/*
16 * OMAP2/3-common clockdomains
Paul Walmsleyd37f1a12008-09-10 10:47:36 -060017 *
18 * Even though the 2420 has a single PRCM module from the
19 * interconnect's perspective, internally it does appear to have
20 * separate PRM and CM clockdomains. The usual test case is
21 * sys_clkout/sys_clkout2.
Paul Walmsley801954d2008-08-19 11:08:44 +030022 */
23
24/* This is an implicit clockdomain - it is never defined as such in TRM */
25static struct clockdomain wkup_clkdm = {
26 .name = "wkup_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -070027 .pwrdm = { .name = "wkup_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +030028 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
29};
30
Paul Walmsleyd37f1a12008-09-10 10:47:36 -060031static struct clockdomain prm_clkdm = {
32 .name = "prm_clkdm",
33 .pwrdm = { .name = "wkup_pwrdm" },
34 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
35};
36
37static struct clockdomain cm_clkdm = {
38 .name = "cm_clkdm",
39 .pwrdm = { .name = "core_pwrdm" },
40 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
41};
42
Paul Walmsley801954d2008-08-19 11:08:44 +030043/*
44 * 2420-only clockdomains
45 */
46
47#if defined(CONFIG_ARCH_OMAP2420)
48
49static struct clockdomain mpu_2420_clkdm = {
50 .name = "mpu_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -070051 .pwrdm = { .name = "mpu_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +030052 .flags = CLKDM_CAN_HWSUP,
53 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
54 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
55};
56
57static struct clockdomain iva1_2420_clkdm = {
58 .name = "iva1_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -070059 .pwrdm = { .name = "dsp_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +030060 .flags = CLKDM_CAN_HWSUP_SWSUP,
61 .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
62 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
63};
64
65#endif /* CONFIG_ARCH_OMAP2420 */
66
67
68/*
69 * 2430-only clockdomains
70 */
71
72#if defined(CONFIG_ARCH_OMAP2430)
73
74static struct clockdomain mpu_2430_clkdm = {
75 .name = "mpu_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -070076 .pwrdm = { .name = "mpu_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +030077 .flags = CLKDM_CAN_HWSUP_SWSUP,
78 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
79 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
80};
81
82static struct clockdomain mdm_clkdm = {
83 .name = "mdm_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -070084 .pwrdm = { .name = "mdm_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +030085 .flags = CLKDM_CAN_HWSUP_SWSUP,
86 .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
87 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
88};
89
90#endif /* CONFIG_ARCH_OMAP2430 */
91
92
93/*
94 * 24XX-only clockdomains
95 */
96
97#if defined(CONFIG_ARCH_OMAP24XX)
98
99static struct clockdomain dsp_clkdm = {
100 .name = "dsp_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -0700101 .pwrdm = { .name = "dsp_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +0300102 .flags = CLKDM_CAN_HWSUP_SWSUP,
103 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
104 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
105};
106
107static struct clockdomain gfx_24xx_clkdm = {
108 .name = "gfx_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -0700109 .pwrdm = { .name = "gfx_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +0300110 .flags = CLKDM_CAN_HWSUP_SWSUP,
111 .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
112 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
113};
114
115static struct clockdomain core_l3_24xx_clkdm = {
116 .name = "core_l3_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -0700117 .pwrdm = { .name = "core_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +0300118 .flags = CLKDM_CAN_HWSUP,
119 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
120 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
121};
122
123static struct clockdomain core_l4_24xx_clkdm = {
124 .name = "core_l4_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -0700125 .pwrdm = { .name = "core_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +0300126 .flags = CLKDM_CAN_HWSUP,
127 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
128 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
129};
130
131static struct clockdomain dss_24xx_clkdm = {
132 .name = "dss_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -0700133 .pwrdm = { .name = "core_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +0300134 .flags = CLKDM_CAN_HWSUP,
135 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
136 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
137};
138
139#endif /* CONFIG_ARCH_OMAP24XX */
140
141
142/*
143 * 34xx clockdomains
144 */
145
146#if defined(CONFIG_ARCH_OMAP34XX)
147
148static struct clockdomain mpu_34xx_clkdm = {
149 .name = "mpu_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -0700150 .pwrdm = { .name = "mpu_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +0300151 .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
152 .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
153 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
154};
155
156static struct clockdomain neon_clkdm = {
157 .name = "neon_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -0700158 .pwrdm = { .name = "neon_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +0300159 .flags = CLKDM_CAN_HWSUP_SWSUP,
160 .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
161 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
162};
163
164static struct clockdomain iva2_clkdm = {
165 .name = "iva2_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -0700166 .pwrdm = { .name = "iva2_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +0300167 .flags = CLKDM_CAN_HWSUP_SWSUP,
168 .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
169 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
170};
171
172static struct clockdomain gfx_3430es1_clkdm = {
173 .name = "gfx_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -0700174 .pwrdm = { .name = "gfx_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +0300175 .flags = CLKDM_CAN_HWSUP_SWSUP,
176 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
177 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
178};
179
180static struct clockdomain sgx_clkdm = {
181 .name = "sgx_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -0700182 .pwrdm = { .name = "sgx_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +0300183 .flags = CLKDM_CAN_HWSUP_SWSUP,
184 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
Paul Walmsleyd41ad522009-02-05 20:45:25 -0700185 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
Paul Walmsley801954d2008-08-19 11:08:44 +0300186};
187
Paul Walmsley333943b2008-08-19 11:08:45 +0300188/*
189 * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
190 * then that information was removed from the 34xx ES2+ TRM. It is
191 * unclear whether the core is still there, but the clockdomain logic
192 * is there, and must be programmed to an appropriate state if the
193 * CORE clockdomain is to become inactive.
194 */
Paul Walmsley801954d2008-08-19 11:08:44 +0300195static struct clockdomain d2d_clkdm = {
196 .name = "d2d_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -0700197 .pwrdm = { .name = "core_pwrdm" },
Kevin Hilman01cbd4d2008-11-25 21:48:28 -0800198 .flags = CLKDM_CAN_HWSUP_SWSUP,
Paul Walmsley801954d2008-08-19 11:08:44 +0300199 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
Paul Walmsley333943b2008-08-19 11:08:45 +0300200 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
Paul Walmsley801954d2008-08-19 11:08:44 +0300201};
202
203static struct clockdomain core_l3_34xx_clkdm = {
204 .name = "core_l3_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -0700205 .pwrdm = { .name = "core_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +0300206 .flags = CLKDM_CAN_HWSUP,
207 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
208 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
209};
210
211static struct clockdomain core_l4_34xx_clkdm = {
212 .name = "core_l4_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -0700213 .pwrdm = { .name = "core_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +0300214 .flags = CLKDM_CAN_HWSUP,
215 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
216 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
217};
218
219static struct clockdomain dss_34xx_clkdm = {
220 .name = "dss_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -0700221 .pwrdm = { .name = "dss_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +0300222 .flags = CLKDM_CAN_HWSUP_SWSUP,
223 .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
224 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
225};
226
227static struct clockdomain cam_clkdm = {
228 .name = "cam_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -0700229 .pwrdm = { .name = "cam_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +0300230 .flags = CLKDM_CAN_HWSUP_SWSUP,
231 .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
232 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
233};
234
235static struct clockdomain usbhost_clkdm = {
236 .name = "usbhost_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -0700237 .pwrdm = { .name = "usbhost_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +0300238 .flags = CLKDM_CAN_HWSUP_SWSUP,
239 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
Paul Walmsleyd41ad522009-02-05 20:45:25 -0700240 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
Paul Walmsley801954d2008-08-19 11:08:44 +0300241};
242
243static struct clockdomain per_clkdm = {
244 .name = "per_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -0700245 .pwrdm = { .name = "per_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +0300246 .flags = CLKDM_CAN_HWSUP_SWSUP,
247 .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
248 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
249};
250
Jouni Hoganderf2669502009-01-27 19:44:38 -0700251/*
252 * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
253 * switched of even if sdti is in use
254 */
Paul Walmsley801954d2008-08-19 11:08:44 +0300255static struct clockdomain emu_clkdm = {
256 .name = "emu_clkdm",
Paul Walmsley5b74c672009-02-03 02:10:03 -0700257 .pwrdm = { .name = "emu_pwrdm" },
Jouni Hoganderf2669502009-01-27 19:44:38 -0700258 .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP,
Paul Walmsley801954d2008-08-19 11:08:44 +0300259 .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
260 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
261};
262
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700263static struct clockdomain dpll1_clkdm = {
264 .name = "dpll1_clkdm",
265 .pwrdm = { .name = "dpll1_pwrdm" },
266 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
267};
268
269static struct clockdomain dpll2_clkdm = {
270 .name = "dpll2_clkdm",
271 .pwrdm = { .name = "dpll2_pwrdm" },
272 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
273};
274
275static struct clockdomain dpll3_clkdm = {
276 .name = "dpll3_clkdm",
277 .pwrdm = { .name = "dpll3_pwrdm" },
278 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
279};
280
281static struct clockdomain dpll4_clkdm = {
282 .name = "dpll4_clkdm",
283 .pwrdm = { .name = "dpll4_pwrdm" },
284 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
285};
286
287static struct clockdomain dpll5_clkdm = {
288 .name = "dpll5_clkdm",
289 .pwrdm = { .name = "dpll5_pwrdm" },
Paul Walmsleyd41ad522009-02-05 20:45:25 -0700290 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700291};
292
Paul Walmsley801954d2008-08-19 11:08:44 +0300293#endif /* CONFIG_ARCH_OMAP34XX */
294
295/*
296 * Clockdomain-powerdomain hwsup dependencies (34XX only)
297 */
298
299static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
300 {
Paul Walmsley5b74c672009-02-03 02:10:03 -0700301 .pwrdm = { .name = "mpu_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +0300302 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
303 },
304 {
Paul Walmsley5b74c672009-02-03 02:10:03 -0700305 .pwrdm = { .name = "iva2_pwrdm" },
Paul Walmsley801954d2008-08-19 11:08:44 +0300306 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
307 },
Paul Walmsley5b74c672009-02-03 02:10:03 -0700308 {
309 .pwrdm = { .name = NULL },
310 }
Paul Walmsley801954d2008-08-19 11:08:44 +0300311};
312
313/*
314 *
315 */
316
317static struct clockdomain *clockdomains_omap[] = {
318
319 &wkup_clkdm,
Paul Walmsleyd37f1a12008-09-10 10:47:36 -0600320 &cm_clkdm,
321 &prm_clkdm,
Paul Walmsley801954d2008-08-19 11:08:44 +0300322
323#ifdef CONFIG_ARCH_OMAP2420
324 &mpu_2420_clkdm,
325 &iva1_2420_clkdm,
326#endif
327
328#ifdef CONFIG_ARCH_OMAP2430
329 &mpu_2430_clkdm,
330 &mdm_clkdm,
331#endif
332
333#ifdef CONFIG_ARCH_OMAP24XX
334 &dsp_clkdm,
335 &gfx_24xx_clkdm,
336 &core_l3_24xx_clkdm,
337 &core_l4_24xx_clkdm,
338 &dss_24xx_clkdm,
339#endif
340
341#ifdef CONFIG_ARCH_OMAP34XX
342 &mpu_34xx_clkdm,
343 &neon_clkdm,
344 &iva2_clkdm,
345 &gfx_3430es1_clkdm,
346 &sgx_clkdm,
347 &d2d_clkdm,
348 &core_l3_34xx_clkdm,
349 &core_l4_34xx_clkdm,
350 &dss_34xx_clkdm,
351 &cam_clkdm,
352 &usbhost_clkdm,
353 &per_clkdm,
354 &emu_clkdm,
Paul Walmsley46e0ccf2009-01-27 19:44:18 -0700355 &dpll1_clkdm,
356 &dpll2_clkdm,
357 &dpll3_clkdm,
358 &dpll4_clkdm,
359 &dpll5_clkdm,
Paul Walmsley801954d2008-08-19 11:08:44 +0300360#endif
361
362 NULL,
363};
364
365#endif