Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1 | /* |
Gertjan van Wingerde | 9c9a0d1 | 2009-11-08 16:39:55 +0100 | [diff] [blame] | 2 | Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 3 | <http://rt2x00.serialmonkey.com> |
| 4 | |
| 5 | This program is free software; you can redistribute it and/or modify |
| 6 | it under the terms of the GNU General Public License as published by |
| 7 | the Free Software Foundation; either version 2 of the License, or |
| 8 | (at your option) any later version. |
| 9 | |
| 10 | This program is distributed in the hope that it will be useful, |
| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | GNU General Public License for more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License |
| 16 | along with this program; if not, write to the |
| 17 | Free Software Foundation, Inc., |
| 18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 19 | */ |
| 20 | |
| 21 | /* |
| 22 | Module: rt2500pci |
| 23 | Abstract: rt2500pci device specific routines. |
| 24 | Supported chipsets: RT2560. |
| 25 | */ |
| 26 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 27 | #include <linux/delay.h> |
| 28 | #include <linux/etherdevice.h> |
| 29 | #include <linux/init.h> |
| 30 | #include <linux/kernel.h> |
| 31 | #include <linux/module.h> |
| 32 | #include <linux/pci.h> |
| 33 | #include <linux/eeprom_93cx6.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 34 | #include <linux/slab.h> |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 35 | |
| 36 | #include "rt2x00.h" |
| 37 | #include "rt2x00pci.h" |
| 38 | #include "rt2500pci.h" |
| 39 | |
| 40 | /* |
| 41 | * Register access. |
| 42 | * All access to the CSR registers will go through the methods |
| 43 | * rt2x00pci_register_read and rt2x00pci_register_write. |
| 44 | * BBP and RF register require indirect register access, |
| 45 | * and use the CSR registers BBPCSR and RFCSR to achieve this. |
| 46 | * These indirect registers work with busy bits, |
| 47 | * and we will try maximal REGISTER_BUSY_COUNT times to access |
| 48 | * the register while taking a REGISTER_BUSY_DELAY us delay |
| 49 | * between each attampt. When the busy bit is still set at that time, |
| 50 | * the access attempt is considered to have failed, |
| 51 | * and we will print an error. |
| 52 | */ |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 53 | #define WAIT_FOR_BBP(__dev, __reg) \ |
| 54 | rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg)) |
| 55 | #define WAIT_FOR_RF(__dev, __reg) \ |
| 56 | rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg)) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 57 | |
Adam Baker | 0e14f6d | 2007-10-27 13:41:25 +0200 | [diff] [blame] | 58 | static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 59 | const unsigned int word, const u8 value) |
| 60 | { |
| 61 | u32 reg; |
| 62 | |
Ivo van Doorn | 8ff48a8 | 2008-11-09 23:40:46 +0100 | [diff] [blame] | 63 | mutex_lock(&rt2x00dev->csr_mutex); |
| 64 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 65 | /* |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 66 | * Wait until the BBP becomes available, afterwards we |
| 67 | * can safely write the new data into the register. |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 68 | */ |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 69 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
| 70 | reg = 0; |
| 71 | rt2x00_set_field32(®, BBPCSR_VALUE, value); |
| 72 | rt2x00_set_field32(®, BBPCSR_REGNUM, word); |
| 73 | rt2x00_set_field32(®, BBPCSR_BUSY, 1); |
| 74 | rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 75 | |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 76 | rt2x00pci_register_write(rt2x00dev, BBPCSR, reg); |
| 77 | } |
Ivo van Doorn | 8ff48a8 | 2008-11-09 23:40:46 +0100 | [diff] [blame] | 78 | |
| 79 | mutex_unlock(&rt2x00dev->csr_mutex); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 80 | } |
| 81 | |
Adam Baker | 0e14f6d | 2007-10-27 13:41:25 +0200 | [diff] [blame] | 82 | static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 83 | const unsigned int word, u8 *value) |
| 84 | { |
| 85 | u32 reg; |
| 86 | |
Ivo van Doorn | 8ff48a8 | 2008-11-09 23:40:46 +0100 | [diff] [blame] | 87 | mutex_lock(&rt2x00dev->csr_mutex); |
| 88 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 89 | /* |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 90 | * Wait until the BBP becomes available, afterwards we |
| 91 | * can safely write the read request into the register. |
| 92 | * After the data has been written, we wait until hardware |
| 93 | * returns the correct value, if at any time the register |
| 94 | * doesn't become available in time, reg will be 0xffffffff |
| 95 | * which means we return 0xff to the caller. |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 96 | */ |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 97 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
| 98 | reg = 0; |
| 99 | rt2x00_set_field32(®, BBPCSR_REGNUM, word); |
| 100 | rt2x00_set_field32(®, BBPCSR_BUSY, 1); |
| 101 | rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 102 | |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 103 | rt2x00pci_register_write(rt2x00dev, BBPCSR, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 104 | |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 105 | WAIT_FOR_BBP(rt2x00dev, ®); |
| 106 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 107 | |
| 108 | *value = rt2x00_get_field32(reg, BBPCSR_VALUE); |
Ivo van Doorn | 8ff48a8 | 2008-11-09 23:40:46 +0100 | [diff] [blame] | 109 | |
| 110 | mutex_unlock(&rt2x00dev->csr_mutex); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 111 | } |
| 112 | |
Adam Baker | 0e14f6d | 2007-10-27 13:41:25 +0200 | [diff] [blame] | 113 | static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 114 | const unsigned int word, const u32 value) |
| 115 | { |
| 116 | u32 reg; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 117 | |
Ivo van Doorn | 8ff48a8 | 2008-11-09 23:40:46 +0100 | [diff] [blame] | 118 | mutex_lock(&rt2x00dev->csr_mutex); |
| 119 | |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 120 | /* |
| 121 | * Wait until the RF becomes available, afterwards we |
| 122 | * can safely write the new data into the register. |
| 123 | */ |
| 124 | if (WAIT_FOR_RF(rt2x00dev, ®)) { |
| 125 | reg = 0; |
| 126 | rt2x00_set_field32(®, RFCSR_VALUE, value); |
| 127 | rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20); |
| 128 | rt2x00_set_field32(®, RFCSR_IF_SELECT, 0); |
| 129 | rt2x00_set_field32(®, RFCSR_BUSY, 1); |
| 130 | |
| 131 | rt2x00pci_register_write(rt2x00dev, RFCSR, reg); |
| 132 | rt2x00_rf_write(rt2x00dev, word, value); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 133 | } |
| 134 | |
Ivo van Doorn | 8ff48a8 | 2008-11-09 23:40:46 +0100 | [diff] [blame] | 135 | mutex_unlock(&rt2x00dev->csr_mutex); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom) |
| 139 | { |
| 140 | struct rt2x00_dev *rt2x00dev = eeprom->data; |
| 141 | u32 reg; |
| 142 | |
| 143 | rt2x00pci_register_read(rt2x00dev, CSR21, ®); |
| 144 | |
| 145 | eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN); |
| 146 | eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT); |
| 147 | eeprom->reg_data_clock = |
| 148 | !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK); |
| 149 | eeprom->reg_chip_select = |
| 150 | !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT); |
| 151 | } |
| 152 | |
| 153 | static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom) |
| 154 | { |
| 155 | struct rt2x00_dev *rt2x00dev = eeprom->data; |
| 156 | u32 reg = 0; |
| 157 | |
| 158 | rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in); |
| 159 | rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out); |
| 160 | rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK, |
| 161 | !!eeprom->reg_data_clock); |
| 162 | rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT, |
| 163 | !!eeprom->reg_chip_select); |
| 164 | |
| 165 | rt2x00pci_register_write(rt2x00dev, CSR21, reg); |
| 166 | } |
| 167 | |
| 168 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 169 | static const struct rt2x00debug rt2500pci_rt2x00debug = { |
| 170 | .owner = THIS_MODULE, |
| 171 | .csr = { |
Ivo van Doorn | 743b97c | 2008-10-29 19:41:03 +0100 | [diff] [blame] | 172 | .read = rt2x00pci_register_read, |
| 173 | .write = rt2x00pci_register_write, |
| 174 | .flags = RT2X00DEBUGFS_OFFSET, |
| 175 | .word_base = CSR_REG_BASE, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 176 | .word_size = sizeof(u32), |
| 177 | .word_count = CSR_REG_SIZE / sizeof(u32), |
| 178 | }, |
| 179 | .eeprom = { |
| 180 | .read = rt2x00_eeprom_read, |
| 181 | .write = rt2x00_eeprom_write, |
Ivo van Doorn | 743b97c | 2008-10-29 19:41:03 +0100 | [diff] [blame] | 182 | .word_base = EEPROM_BASE, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 183 | .word_size = sizeof(u16), |
| 184 | .word_count = EEPROM_SIZE / sizeof(u16), |
| 185 | }, |
| 186 | .bbp = { |
| 187 | .read = rt2500pci_bbp_read, |
| 188 | .write = rt2500pci_bbp_write, |
Ivo van Doorn | 743b97c | 2008-10-29 19:41:03 +0100 | [diff] [blame] | 189 | .word_base = BBP_BASE, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 190 | .word_size = sizeof(u8), |
| 191 | .word_count = BBP_SIZE / sizeof(u8), |
| 192 | }, |
| 193 | .rf = { |
| 194 | .read = rt2x00_rf_read, |
| 195 | .write = rt2500pci_rf_write, |
Ivo van Doorn | 743b97c | 2008-10-29 19:41:03 +0100 | [diff] [blame] | 196 | .word_base = RF_BASE, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 197 | .word_size = sizeof(u32), |
| 198 | .word_count = RF_SIZE / sizeof(u32), |
| 199 | }, |
| 200 | }; |
| 201 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ |
| 202 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 203 | static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) |
| 204 | { |
| 205 | u32 reg; |
| 206 | |
| 207 | rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®); |
| 208 | return rt2x00_get_field32(reg, GPIOCSR_BIT0); |
| 209 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 210 | |
Ivo van Doorn | 771fd56 | 2008-09-08 19:07:15 +0200 | [diff] [blame] | 211 | #ifdef CONFIG_RT2X00_LIB_LEDS |
Ivo van Doorn | a2e1d52 | 2008-03-31 15:53:44 +0200 | [diff] [blame] | 212 | static void rt2500pci_brightness_set(struct led_classdev *led_cdev, |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 213 | enum led_brightness brightness) |
| 214 | { |
| 215 | struct rt2x00_led *led = |
| 216 | container_of(led_cdev, struct rt2x00_led, led_dev); |
| 217 | unsigned int enabled = brightness != LED_OFF; |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 218 | u32 reg; |
| 219 | |
| 220 | rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®); |
| 221 | |
Ivo van Doorn | a2e1d52 | 2008-03-31 15:53:44 +0200 | [diff] [blame] | 222 | if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 223 | rt2x00_set_field32(®, LEDCSR_LINK, enabled); |
Ivo van Doorn | a2e1d52 | 2008-03-31 15:53:44 +0200 | [diff] [blame] | 224 | else if (led->type == LED_TYPE_ACTIVITY) |
| 225 | rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled); |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 226 | |
| 227 | rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg); |
| 228 | } |
Ivo van Doorn | a2e1d52 | 2008-03-31 15:53:44 +0200 | [diff] [blame] | 229 | |
| 230 | static int rt2500pci_blink_set(struct led_classdev *led_cdev, |
| 231 | unsigned long *delay_on, |
| 232 | unsigned long *delay_off) |
| 233 | { |
| 234 | struct rt2x00_led *led = |
| 235 | container_of(led_cdev, struct rt2x00_led, led_dev); |
| 236 | u32 reg; |
| 237 | |
| 238 | rt2x00pci_register_read(led->rt2x00dev, LEDCSR, ®); |
| 239 | rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on); |
| 240 | rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off); |
| 241 | rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg); |
| 242 | |
| 243 | return 0; |
| 244 | } |
Ivo van Doorn | 475433b | 2008-06-03 20:30:01 +0200 | [diff] [blame] | 245 | |
| 246 | static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev, |
| 247 | struct rt2x00_led *led, |
| 248 | enum led_type type) |
| 249 | { |
| 250 | led->rt2x00dev = rt2x00dev; |
| 251 | led->type = type; |
| 252 | led->led_dev.brightness_set = rt2500pci_brightness_set; |
| 253 | led->led_dev.blink_set = rt2500pci_blink_set; |
| 254 | led->flags = LED_INITIALIZED; |
| 255 | } |
Ivo van Doorn | 771fd56 | 2008-09-08 19:07:15 +0200 | [diff] [blame] | 256 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 257 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 258 | /* |
| 259 | * Configuration handlers. |
| 260 | */ |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 261 | static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev, |
| 262 | const unsigned int filter_flags) |
| 263 | { |
| 264 | u32 reg; |
| 265 | |
| 266 | /* |
| 267 | * Start configuration steps. |
| 268 | * Note that the version error will always be dropped |
| 269 | * and broadcast frames will always be accepted since |
| 270 | * there is no filter for it at this time. |
| 271 | */ |
| 272 | rt2x00pci_register_read(rt2x00dev, RXCSR0, ®); |
| 273 | rt2x00_set_field32(®, RXCSR0_DROP_CRC, |
| 274 | !(filter_flags & FIF_FCSFAIL)); |
| 275 | rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, |
| 276 | !(filter_flags & FIF_PLCPFAIL)); |
| 277 | rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, |
| 278 | !(filter_flags & FIF_CONTROL)); |
| 279 | rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME, |
| 280 | !(filter_flags & FIF_PROMISC_IN_BSS)); |
| 281 | rt2x00_set_field32(®, RXCSR0_DROP_TODS, |
Ivo van Doorn | e0b005f | 2008-03-31 15:24:53 +0200 | [diff] [blame] | 282 | !(filter_flags & FIF_PROMISC_IN_BSS) && |
| 283 | !rt2x00dev->intf_ap_count); |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 284 | rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1); |
| 285 | rt2x00_set_field32(®, RXCSR0_DROP_MCAST, |
| 286 | !(filter_flags & FIF_ALLMULTI)); |
| 287 | rt2x00_set_field32(®, RXCSR0_DROP_BCAST, 0); |
| 288 | rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); |
| 289 | } |
| 290 | |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 291 | static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev, |
| 292 | struct rt2x00_intf *intf, |
| 293 | struct rt2x00intf_conf *conf, |
| 294 | const unsigned int flags) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 295 | { |
Ivo van Doorn | e58c6ac | 2008-04-21 19:00:47 +0200 | [diff] [blame] | 296 | struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON); |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 297 | unsigned int bcn_preload; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 298 | u32 reg; |
| 299 | |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 300 | if (flags & CONFIG_UPDATE_TYPE) { |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 301 | /* |
| 302 | * Enable beacon config |
| 303 | */ |
Ivo van Doorn | bad1363 | 2008-11-09 20:47:00 +0100 | [diff] [blame] | 304 | bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20); |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 305 | rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®); |
| 306 | rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload); |
| 307 | rt2x00_set_field32(®, BCNCSR1_BEACON_CWMIN, queue->cw_min); |
| 308 | rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 309 | |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 310 | /* |
| 311 | * Enable synchronisation. |
| 312 | */ |
| 313 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); |
Ivo van Doorn | fd3c91c | 2008-03-09 22:47:43 +0100 | [diff] [blame] | 314 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 315 | rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync); |
Ivo van Doorn | fd3c91c | 2008-03-09 22:47:43 +0100 | [diff] [blame] | 316 | rt2x00_set_field32(®, CSR14_TBCN, 1); |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 317 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); |
| 318 | } |
| 319 | |
| 320 | if (flags & CONFIG_UPDATE_MAC) |
| 321 | rt2x00pci_register_multiwrite(rt2x00dev, CSR3, |
| 322 | conf->mac, sizeof(conf->mac)); |
| 323 | |
| 324 | if (flags & CONFIG_UPDATE_BSSID) |
| 325 | rt2x00pci_register_multiwrite(rt2x00dev, CSR5, |
| 326 | conf->bssid, sizeof(conf->bssid)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 327 | } |
| 328 | |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 329 | static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev, |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 330 | struct rt2x00lib_erp *erp, |
| 331 | u32 changed) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 332 | { |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 333 | int preamble_mask; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 334 | u32 reg; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 335 | |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 336 | /* |
| 337 | * When short preamble is enabled, we should set bit 0x08 |
| 338 | */ |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 339 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
| 340 | preamble_mask = erp->short_preamble << 3; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 341 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 342 | rt2x00pci_register_read(rt2x00dev, TXCSR1, ®); |
| 343 | rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x162); |
| 344 | rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0xa2); |
| 345 | rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); |
| 346 | rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1); |
| 347 | rt2x00pci_register_write(rt2x00dev, TXCSR1, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 348 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 349 | rt2x00pci_register_read(rt2x00dev, ARCSR2, ®); |
| 350 | rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00); |
| 351 | rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); |
| 352 | rt2x00_set_field32(®, ARCSR2_LENGTH, |
| 353 | GET_DURATION(ACK_SIZE, 10)); |
| 354 | rt2x00pci_register_write(rt2x00dev, ARCSR2, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 355 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 356 | rt2x00pci_register_read(rt2x00dev, ARCSR3, ®); |
| 357 | rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask); |
| 358 | rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); |
| 359 | rt2x00_set_field32(®, ARCSR2_LENGTH, |
| 360 | GET_DURATION(ACK_SIZE, 20)); |
| 361 | rt2x00pci_register_write(rt2x00dev, ARCSR3, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 362 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 363 | rt2x00pci_register_read(rt2x00dev, ARCSR4, ®); |
| 364 | rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask); |
| 365 | rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); |
| 366 | rt2x00_set_field32(®, ARCSR2_LENGTH, |
| 367 | GET_DURATION(ACK_SIZE, 55)); |
| 368 | rt2x00pci_register_write(rt2x00dev, ARCSR4, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 369 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 370 | rt2x00pci_register_read(rt2x00dev, ARCSR5, ®); |
| 371 | rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask); |
| 372 | rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); |
| 373 | rt2x00_set_field32(®, ARCSR2_LENGTH, |
| 374 | GET_DURATION(ACK_SIZE, 110)); |
| 375 | rt2x00pci_register_write(rt2x00dev, ARCSR5, reg); |
| 376 | } |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 377 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 378 | if (changed & BSS_CHANGED_BASIC_RATES) |
| 379 | rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates); |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 380 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 381 | if (changed & BSS_CHANGED_ERP_SLOT) { |
| 382 | rt2x00pci_register_read(rt2x00dev, CSR11, ®); |
| 383 | rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time); |
| 384 | rt2x00pci_register_write(rt2x00dev, CSR11, reg); |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 385 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 386 | rt2x00pci_register_read(rt2x00dev, CSR18, ®); |
| 387 | rt2x00_set_field32(®, CSR18_SIFS, erp->sifs); |
| 388 | rt2x00_set_field32(®, CSR18_PIFS, erp->pifs); |
| 389 | rt2x00pci_register_write(rt2x00dev, CSR18, reg); |
Ivo van Doorn | 8a566af | 2009-05-21 19:16:46 +0200 | [diff] [blame] | 390 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 391 | rt2x00pci_register_read(rt2x00dev, CSR19, ®); |
| 392 | rt2x00_set_field32(®, CSR19_DIFS, erp->difs); |
| 393 | rt2x00_set_field32(®, CSR19_EIFS, erp->eifs); |
| 394 | rt2x00pci_register_write(rt2x00dev, CSR19, reg); |
| 395 | } |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 396 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 397 | if (changed & BSS_CHANGED_BEACON_INT) { |
| 398 | rt2x00pci_register_read(rt2x00dev, CSR12, ®); |
| 399 | rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, |
| 400 | erp->beacon_int * 16); |
| 401 | rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, |
| 402 | erp->beacon_int * 16); |
| 403 | rt2x00pci_register_write(rt2x00dev, CSR12, reg); |
| 404 | } |
| 405 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 406 | } |
| 407 | |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 408 | static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev, |
| 409 | struct antenna_setup *ant) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 410 | { |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 411 | u32 reg; |
| 412 | u8 r14; |
| 413 | u8 r2; |
| 414 | |
| 415 | /* |
| 416 | * We should never come here because rt2x00lib is supposed |
| 417 | * to catch this and send us the correct antenna explicitely. |
| 418 | */ |
| 419 | BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY || |
| 420 | ant->tx == ANTENNA_SW_DIVERSITY); |
| 421 | |
| 422 | rt2x00pci_register_read(rt2x00dev, BBPCSR1, ®); |
| 423 | rt2500pci_bbp_read(rt2x00dev, 14, &r14); |
| 424 | rt2500pci_bbp_read(rt2x00dev, 2, &r2); |
| 425 | |
| 426 | /* |
| 427 | * Configure the TX antenna. |
| 428 | */ |
| 429 | switch (ant->tx) { |
| 430 | case ANTENNA_A: |
| 431 | rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0); |
| 432 | rt2x00_set_field32(®, BBPCSR1_CCK, 0); |
| 433 | rt2x00_set_field32(®, BBPCSR1_OFDM, 0); |
| 434 | break; |
| 435 | case ANTENNA_B: |
| 436 | default: |
| 437 | rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2); |
| 438 | rt2x00_set_field32(®, BBPCSR1_CCK, 2); |
| 439 | rt2x00_set_field32(®, BBPCSR1_OFDM, 2); |
| 440 | break; |
| 441 | } |
| 442 | |
| 443 | /* |
| 444 | * Configure the RX antenna. |
| 445 | */ |
| 446 | switch (ant->rx) { |
| 447 | case ANTENNA_A: |
| 448 | rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0); |
| 449 | break; |
| 450 | case ANTENNA_B: |
| 451 | default: |
| 452 | rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2); |
| 453 | break; |
| 454 | } |
| 455 | |
| 456 | /* |
| 457 | * RT2525E and RT5222 need to flip TX I/Q |
| 458 | */ |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 459 | if (rt2x00_rf(rt2x00dev, RF2525E) || rt2x00_rf(rt2x00dev, RF5222)) { |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 460 | rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1); |
| 461 | rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 1); |
| 462 | rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 1); |
| 463 | |
| 464 | /* |
| 465 | * RT2525E does not need RX I/Q Flip. |
| 466 | */ |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 467 | if (rt2x00_rf(rt2x00dev, RF2525E)) |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 468 | rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0); |
| 469 | } else { |
| 470 | rt2x00_set_field32(®, BBPCSR1_CCK_FLIP, 0); |
| 471 | rt2x00_set_field32(®, BBPCSR1_OFDM_FLIP, 0); |
| 472 | } |
| 473 | |
| 474 | rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg); |
| 475 | rt2500pci_bbp_write(rt2x00dev, 14, r14); |
| 476 | rt2500pci_bbp_write(rt2x00dev, 2, r2); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 477 | } |
| 478 | |
| 479 | static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 480 | struct rf_channel *rf, const int txpower) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 481 | { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 482 | u8 r70; |
| 483 | |
| 484 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 485 | * Set TXpower. |
| 486 | */ |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 487 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 488 | |
| 489 | /* |
| 490 | * Switch on tuning bits. |
| 491 | * For RT2523 devices we do not need to update the R1 register. |
| 492 | */ |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 493 | if (!rt2x00_rf(rt2x00dev, RF2523)) |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 494 | rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1); |
| 495 | rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 496 | |
| 497 | /* |
| 498 | * For RT2525 we should first set the channel to half band higher. |
| 499 | */ |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 500 | if (rt2x00_rf(rt2x00dev, RF2525)) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 501 | static const u32 vals[] = { |
| 502 | 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a, |
| 503 | 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a, |
| 504 | 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a, |
| 505 | 0x00080d2e, 0x00080d3a |
| 506 | }; |
| 507 | |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 508 | rt2500pci_rf_write(rt2x00dev, 1, rf->rf1); |
| 509 | rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]); |
| 510 | rt2500pci_rf_write(rt2x00dev, 3, rf->rf3); |
| 511 | if (rf->rf4) |
| 512 | rt2500pci_rf_write(rt2x00dev, 4, rf->rf4); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 513 | } |
| 514 | |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 515 | rt2500pci_rf_write(rt2x00dev, 1, rf->rf1); |
| 516 | rt2500pci_rf_write(rt2x00dev, 2, rf->rf2); |
| 517 | rt2500pci_rf_write(rt2x00dev, 3, rf->rf3); |
| 518 | if (rf->rf4) |
| 519 | rt2500pci_rf_write(rt2x00dev, 4, rf->rf4); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 520 | |
| 521 | /* |
| 522 | * Channel 14 requires the Japan filter bit to be set. |
| 523 | */ |
| 524 | r70 = 0x46; |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 525 | rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 526 | rt2500pci_bbp_write(rt2x00dev, 70, r70); |
| 527 | |
| 528 | msleep(1); |
| 529 | |
| 530 | /* |
| 531 | * Switch off tuning bits. |
| 532 | * For RT2523 devices we do not need to update the R1 register. |
| 533 | */ |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 534 | if (!rt2x00_rf(rt2x00dev, RF2523)) { |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 535 | rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0); |
| 536 | rt2500pci_rf_write(rt2x00dev, 1, rf->rf1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 537 | } |
| 538 | |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 539 | rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0); |
| 540 | rt2500pci_rf_write(rt2x00dev, 3, rf->rf3); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 541 | |
| 542 | /* |
| 543 | * Clear false CRC during channel switch. |
| 544 | */ |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 545 | rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 546 | } |
| 547 | |
| 548 | static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev, |
| 549 | const int txpower) |
| 550 | { |
| 551 | u32 rf3; |
| 552 | |
| 553 | rt2x00_rf_read(rt2x00dev, 3, &rf3); |
| 554 | rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); |
| 555 | rt2500pci_rf_write(rt2x00dev, 3, rf3); |
| 556 | } |
| 557 | |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 558 | static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, |
| 559 | struct rt2x00lib_conf *libconf) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 560 | { |
| 561 | u32 reg; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 562 | |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 563 | rt2x00pci_register_read(rt2x00dev, CSR11, ®); |
| 564 | rt2x00_set_field32(®, CSR11_LONG_RETRY, |
| 565 | libconf->conf->long_frame_max_tx_count); |
| 566 | rt2x00_set_field32(®, CSR11_SHORT_RETRY, |
| 567 | libconf->conf->short_frame_max_tx_count); |
| 568 | rt2x00pci_register_write(rt2x00dev, CSR11, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 569 | } |
| 570 | |
Ivo van Doorn | 7d7f19c | 2008-12-20 10:52:42 +0100 | [diff] [blame] | 571 | static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev, |
| 572 | struct rt2x00lib_conf *libconf) |
| 573 | { |
| 574 | enum dev_state state = |
| 575 | (libconf->conf->flags & IEEE80211_CONF_PS) ? |
| 576 | STATE_SLEEP : STATE_AWAKE; |
| 577 | u32 reg; |
| 578 | |
| 579 | if (state == STATE_SLEEP) { |
| 580 | rt2x00pci_register_read(rt2x00dev, CSR20, ®); |
| 581 | rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN, |
Ivo van Doorn | 6b347bf | 2009-05-23 21:09:28 +0200 | [diff] [blame] | 582 | (rt2x00dev->beacon_int - 20) * 16); |
Ivo van Doorn | 7d7f19c | 2008-12-20 10:52:42 +0100 | [diff] [blame] | 583 | rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP, |
| 584 | libconf->conf->listen_interval - 1); |
| 585 | |
| 586 | /* We must first disable autowake before it can be enabled */ |
| 587 | rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); |
| 588 | rt2x00pci_register_write(rt2x00dev, CSR20, reg); |
| 589 | |
| 590 | rt2x00_set_field32(®, CSR20_AUTOWAKE, 1); |
| 591 | rt2x00pci_register_write(rt2x00dev, CSR20, reg); |
Gertjan van Wingerde | 5731858 | 2010-03-30 23:50:23 +0200 | [diff] [blame] | 592 | } else { |
| 593 | rt2x00pci_register_read(rt2x00dev, CSR20, ®); |
| 594 | rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); |
| 595 | rt2x00pci_register_write(rt2x00dev, CSR20, reg); |
Ivo van Doorn | 7d7f19c | 2008-12-20 10:52:42 +0100 | [diff] [blame] | 596 | } |
| 597 | |
| 598 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); |
| 599 | } |
| 600 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 601 | static void rt2500pci_config(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 602 | struct rt2x00lib_conf *libconf, |
| 603 | const unsigned int flags) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 604 | { |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 605 | if (flags & IEEE80211_CONF_CHANGE_CHANNEL) |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 606 | rt2500pci_config_channel(rt2x00dev, &libconf->rf, |
| 607 | libconf->conf->power_level); |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 608 | if ((flags & IEEE80211_CONF_CHANGE_POWER) && |
| 609 | !(flags & IEEE80211_CONF_CHANGE_CHANNEL)) |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 610 | rt2500pci_config_txpower(rt2x00dev, |
| 611 | libconf->conf->power_level); |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 612 | if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) |
| 613 | rt2500pci_config_retry_limit(rt2x00dev, libconf); |
Ivo van Doorn | 7d7f19c | 2008-12-20 10:52:42 +0100 | [diff] [blame] | 614 | if (flags & IEEE80211_CONF_CHANGE_PS) |
| 615 | rt2500pci_config_ps(rt2x00dev, libconf); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 616 | } |
| 617 | |
| 618 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 619 | * Link tuning |
| 620 | */ |
Ivo van Doorn | ebcf26d | 2007-10-13 16:26:12 +0200 | [diff] [blame] | 621 | static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev, |
| 622 | struct link_qual *qual) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 623 | { |
| 624 | u32 reg; |
| 625 | |
| 626 | /* |
| 627 | * Update FCS error count from register. |
| 628 | */ |
| 629 | rt2x00pci_register_read(rt2x00dev, CNT0, ®); |
Ivo van Doorn | ebcf26d | 2007-10-13 16:26:12 +0200 | [diff] [blame] | 630 | qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 631 | |
| 632 | /* |
| 633 | * Update False CCA count from register. |
| 634 | */ |
| 635 | rt2x00pci_register_read(rt2x00dev, CNT3, ®); |
Ivo van Doorn | ebcf26d | 2007-10-13 16:26:12 +0200 | [diff] [blame] | 636 | qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 637 | } |
| 638 | |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 639 | static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev, |
| 640 | struct link_qual *qual, u8 vgc_level) |
Ivo van Doorn | eb20b4e | 2008-12-20 10:54:22 +0100 | [diff] [blame] | 641 | { |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 642 | if (qual->vgc_level_reg != vgc_level) { |
Ivo van Doorn | eb20b4e | 2008-12-20 10:54:22 +0100 | [diff] [blame] | 643 | rt2500pci_bbp_write(rt2x00dev, 17, vgc_level); |
Ivo van Doorn | 223dcc2 | 2010-07-11 12:25:17 +0200 | [diff] [blame] | 644 | qual->vgc_level = vgc_level; |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 645 | qual->vgc_level_reg = vgc_level; |
Ivo van Doorn | eb20b4e | 2008-12-20 10:54:22 +0100 | [diff] [blame] | 646 | } |
| 647 | } |
| 648 | |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 649 | static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev, |
| 650 | struct link_qual *qual) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 651 | { |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 652 | rt2500pci_set_vgc(rt2x00dev, qual, 0x48); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 653 | } |
| 654 | |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 655 | static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev, |
| 656 | struct link_qual *qual, const u32 count) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 657 | { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 658 | /* |
| 659 | * To prevent collisions with MAC ASIC on chipsets |
| 660 | * up to version C the link tuning should halt after 20 |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 661 | * seconds while being associated. |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 662 | */ |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 663 | if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D && |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 664 | rt2x00dev->intf_associated && count > 20) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 665 | return; |
| 666 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 667 | /* |
| 668 | * Chipset versions C and lower should directly continue |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 669 | * to the dynamic CCA tuning. Chipset version D and higher |
| 670 | * should go straight to dynamic CCA tuning when they |
| 671 | * are not associated. |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 672 | */ |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 673 | if (rt2x00_rev(rt2x00dev) < RT2560_VERSION_D || |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 674 | !rt2x00dev->intf_associated) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 675 | goto dynamic_cca_tune; |
| 676 | |
| 677 | /* |
| 678 | * A too low RSSI will cause too much false CCA which will |
| 679 | * then corrupt the R17 tuning. To remidy this the tuning should |
| 680 | * be stopped (While making sure the R17 value will not exceed limits) |
| 681 | */ |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 682 | if (qual->rssi < -80 && count > 20) { |
| 683 | if (qual->vgc_level_reg >= 0x41) |
| 684 | rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 685 | return; |
| 686 | } |
| 687 | |
| 688 | /* |
| 689 | * Special big-R17 for short distance |
| 690 | */ |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 691 | if (qual->rssi >= -58) { |
| 692 | rt2500pci_set_vgc(rt2x00dev, qual, 0x50); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 693 | return; |
| 694 | } |
| 695 | |
| 696 | /* |
| 697 | * Special mid-R17 for middle distance |
| 698 | */ |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 699 | if (qual->rssi >= -74) { |
| 700 | rt2500pci_set_vgc(rt2x00dev, qual, 0x41); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 701 | return; |
| 702 | } |
| 703 | |
| 704 | /* |
| 705 | * Leave short or middle distance condition, restore r17 |
| 706 | * to the dynamic tuning range. |
| 707 | */ |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 708 | if (qual->vgc_level_reg >= 0x41) { |
| 709 | rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 710 | return; |
| 711 | } |
| 712 | |
| 713 | dynamic_cca_tune: |
| 714 | |
| 715 | /* |
| 716 | * R17 is inside the dynamic tuning range, |
| 717 | * start tuning the link based on the false cca counter. |
| 718 | */ |
Ivo van Doorn | 223dcc2 | 2010-07-11 12:25:17 +0200 | [diff] [blame] | 719 | if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40) |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 720 | rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg); |
Ivo van Doorn | 223dcc2 | 2010-07-11 12:25:17 +0200 | [diff] [blame] | 721 | else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32) |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 722 | rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 723 | } |
| 724 | |
| 725 | /* |
| 726 | * Initialization functions. |
| 727 | */ |
Ivo van Doorn | 798b7ad | 2008-11-08 15:25:33 +0100 | [diff] [blame] | 728 | static bool rt2500pci_get_entry_state(struct queue_entry *entry) |
| 729 | { |
| 730 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
| 731 | u32 word; |
| 732 | |
| 733 | if (entry->queue->qid == QID_RX) { |
| 734 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
| 735 | |
| 736 | return rt2x00_get_field32(word, RXD_W0_OWNER_NIC); |
| 737 | } else { |
| 738 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
| 739 | |
| 740 | return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || |
| 741 | rt2x00_get_field32(word, TXD_W0_VALID)); |
| 742 | } |
| 743 | } |
| 744 | |
| 745 | static void rt2500pci_clear_entry(struct queue_entry *entry) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 746 | { |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 747 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
Gertjan van Wingerde | c4da004 | 2008-06-16 19:56:31 +0200 | [diff] [blame] | 748 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 749 | u32 word; |
| 750 | |
Ivo van Doorn | 798b7ad | 2008-11-08 15:25:33 +0100 | [diff] [blame] | 751 | if (entry->queue->qid == QID_RX) { |
| 752 | rt2x00_desc_read(entry_priv->desc, 1, &word); |
| 753 | rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); |
| 754 | rt2x00_desc_write(entry_priv->desc, 1, word); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 755 | |
Ivo van Doorn | 798b7ad | 2008-11-08 15:25:33 +0100 | [diff] [blame] | 756 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
| 757 | rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); |
| 758 | rt2x00_desc_write(entry_priv->desc, 0, word); |
| 759 | } else { |
| 760 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
| 761 | rt2x00_set_field32(&word, TXD_W0_VALID, 0); |
| 762 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); |
| 763 | rt2x00_desc_write(entry_priv->desc, 0, word); |
| 764 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 765 | } |
| 766 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 767 | static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 768 | { |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 769 | struct queue_entry_priv_pci *entry_priv; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 770 | u32 reg; |
| 771 | |
| 772 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 773 | * Initialize registers. |
| 774 | */ |
| 775 | rt2x00pci_register_read(rt2x00dev, TXCSR2, ®); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 776 | rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); |
| 777 | rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); |
| 778 | rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit); |
| 779 | rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 780 | rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); |
| 781 | |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 782 | entry_priv = rt2x00dev->tx[1].entries[0].priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 783 | rt2x00pci_register_read(rt2x00dev, TXCSR3, ®); |
Ivo van Doorn | 30b3a23 | 2008-02-17 17:33:24 +0100 | [diff] [blame] | 784 | rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 785 | entry_priv->desc_dma); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 786 | rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); |
| 787 | |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 788 | entry_priv = rt2x00dev->tx[0].entries[0].priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 789 | rt2x00pci_register_read(rt2x00dev, TXCSR5, ®); |
Ivo van Doorn | 30b3a23 | 2008-02-17 17:33:24 +0100 | [diff] [blame] | 790 | rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 791 | entry_priv->desc_dma); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 792 | rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); |
| 793 | |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 794 | entry_priv = rt2x00dev->bcn[1].entries[0].priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 795 | rt2x00pci_register_read(rt2x00dev, TXCSR4, ®); |
Ivo van Doorn | 30b3a23 | 2008-02-17 17:33:24 +0100 | [diff] [blame] | 796 | rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 797 | entry_priv->desc_dma); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 798 | rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); |
| 799 | |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 800 | entry_priv = rt2x00dev->bcn[0].entries[0].priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 801 | rt2x00pci_register_read(rt2x00dev, TXCSR6, ®); |
Ivo van Doorn | 30b3a23 | 2008-02-17 17:33:24 +0100 | [diff] [blame] | 802 | rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 803 | entry_priv->desc_dma); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 804 | rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); |
| 805 | |
| 806 | rt2x00pci_register_read(rt2x00dev, RXCSR1, ®); |
| 807 | rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 808 | rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 809 | rt2x00pci_register_write(rt2x00dev, RXCSR1, reg); |
| 810 | |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 811 | entry_priv = rt2x00dev->rx->entries[0].priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 812 | rt2x00pci_register_read(rt2x00dev, RXCSR2, ®); |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 813 | rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, |
| 814 | entry_priv->desc_dma); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 815 | rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); |
| 816 | |
| 817 | return 0; |
| 818 | } |
| 819 | |
| 820 | static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev) |
| 821 | { |
| 822 | u32 reg; |
| 823 | |
| 824 | rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002); |
| 825 | rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002); |
| 826 | rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002); |
| 827 | rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002); |
| 828 | |
| 829 | rt2x00pci_register_read(rt2x00dev, TIMECSR, ®); |
| 830 | rt2x00_set_field32(®, TIMECSR_US_COUNT, 33); |
| 831 | rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63); |
| 832 | rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0); |
| 833 | rt2x00pci_register_write(rt2x00dev, TIMECSR, reg); |
| 834 | |
| 835 | rt2x00pci_register_read(rt2x00dev, CSR9, ®); |
| 836 | rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT, |
| 837 | rt2x00dev->rx->data_size / 128); |
| 838 | rt2x00pci_register_write(rt2x00dev, CSR9, reg); |
| 839 | |
| 840 | /* |
| 841 | * Always use CWmin and CWmax set in descriptor. |
| 842 | */ |
| 843 | rt2x00pci_register_read(rt2x00dev, CSR11, ®); |
| 844 | rt2x00_set_field32(®, CSR11_CW_SELECT, 0); |
| 845 | rt2x00pci_register_write(rt2x00dev, CSR11, reg); |
| 846 | |
Ivo van Doorn | 1f90916 | 2008-07-08 13:45:20 +0200 | [diff] [blame] | 847 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); |
| 848 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); |
| 849 | rt2x00_set_field32(®, CSR14_TSF_SYNC, 0); |
| 850 | rt2x00_set_field32(®, CSR14_TBCN, 0); |
| 851 | rt2x00_set_field32(®, CSR14_TCFP, 0); |
| 852 | rt2x00_set_field32(®, CSR14_TATIMW, 0); |
| 853 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); |
| 854 | rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0); |
| 855 | rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0); |
| 856 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); |
| 857 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 858 | rt2x00pci_register_write(rt2x00dev, CNT3, 0); |
| 859 | |
| 860 | rt2x00pci_register_read(rt2x00dev, TXCSR8, ®); |
| 861 | rt2x00_set_field32(®, TXCSR8_BBP_ID0, 10); |
| 862 | rt2x00_set_field32(®, TXCSR8_BBP_ID0_VALID, 1); |
| 863 | rt2x00_set_field32(®, TXCSR8_BBP_ID1, 11); |
| 864 | rt2x00_set_field32(®, TXCSR8_BBP_ID1_VALID, 1); |
| 865 | rt2x00_set_field32(®, TXCSR8_BBP_ID2, 13); |
| 866 | rt2x00_set_field32(®, TXCSR8_BBP_ID2_VALID, 1); |
| 867 | rt2x00_set_field32(®, TXCSR8_BBP_ID3, 12); |
| 868 | rt2x00_set_field32(®, TXCSR8_BBP_ID3_VALID, 1); |
| 869 | rt2x00pci_register_write(rt2x00dev, TXCSR8, reg); |
| 870 | |
| 871 | rt2x00pci_register_read(rt2x00dev, ARTCSR0, ®); |
| 872 | rt2x00_set_field32(®, ARTCSR0_ACK_CTS_1MBS, 112); |
| 873 | rt2x00_set_field32(®, ARTCSR0_ACK_CTS_2MBS, 56); |
| 874 | rt2x00_set_field32(®, ARTCSR0_ACK_CTS_5_5MBS, 20); |
| 875 | rt2x00_set_field32(®, ARTCSR0_ACK_CTS_11MBS, 10); |
| 876 | rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg); |
| 877 | |
| 878 | rt2x00pci_register_read(rt2x00dev, ARTCSR1, ®); |
| 879 | rt2x00_set_field32(®, ARTCSR1_ACK_CTS_6MBS, 45); |
| 880 | rt2x00_set_field32(®, ARTCSR1_ACK_CTS_9MBS, 37); |
| 881 | rt2x00_set_field32(®, ARTCSR1_ACK_CTS_12MBS, 33); |
| 882 | rt2x00_set_field32(®, ARTCSR1_ACK_CTS_18MBS, 29); |
| 883 | rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg); |
| 884 | |
| 885 | rt2x00pci_register_read(rt2x00dev, ARTCSR2, ®); |
| 886 | rt2x00_set_field32(®, ARTCSR2_ACK_CTS_24MBS, 29); |
| 887 | rt2x00_set_field32(®, ARTCSR2_ACK_CTS_36MBS, 25); |
| 888 | rt2x00_set_field32(®, ARTCSR2_ACK_CTS_48MBS, 25); |
| 889 | rt2x00_set_field32(®, ARTCSR2_ACK_CTS_54MBS, 25); |
| 890 | rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg); |
| 891 | |
| 892 | rt2x00pci_register_read(rt2x00dev, RXCSR3, ®); |
| 893 | rt2x00_set_field32(®, RXCSR3_BBP_ID0, 47); /* CCK Signal */ |
| 894 | rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1); |
| 895 | rt2x00_set_field32(®, RXCSR3_BBP_ID1, 51); /* Rssi */ |
| 896 | rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1); |
| 897 | rt2x00_set_field32(®, RXCSR3_BBP_ID2, 42); /* OFDM Rate */ |
| 898 | rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1); |
| 899 | rt2x00_set_field32(®, RXCSR3_BBP_ID3, 51); /* RSSI */ |
| 900 | rt2x00_set_field32(®, RXCSR3_BBP_ID3_VALID, 1); |
| 901 | rt2x00pci_register_write(rt2x00dev, RXCSR3, reg); |
| 902 | |
| 903 | rt2x00pci_register_read(rt2x00dev, PCICSR, ®); |
| 904 | rt2x00_set_field32(®, PCICSR_BIG_ENDIAN, 0); |
| 905 | rt2x00_set_field32(®, PCICSR_RX_TRESHOLD, 0); |
| 906 | rt2x00_set_field32(®, PCICSR_TX_TRESHOLD, 3); |
| 907 | rt2x00_set_field32(®, PCICSR_BURST_LENTH, 1); |
| 908 | rt2x00_set_field32(®, PCICSR_ENABLE_CLK, 1); |
| 909 | rt2x00_set_field32(®, PCICSR_READ_MULTIPLE, 1); |
| 910 | rt2x00_set_field32(®, PCICSR_WRITE_INVALID, 1); |
| 911 | rt2x00pci_register_write(rt2x00dev, PCICSR, reg); |
| 912 | |
| 913 | rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100); |
| 914 | |
| 915 | rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00); |
| 916 | rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0); |
| 917 | |
| 918 | if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) |
| 919 | return -EBUSY; |
| 920 | |
| 921 | rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223); |
| 922 | rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518); |
| 923 | |
| 924 | rt2x00pci_register_read(rt2x00dev, MACCSR2, ®); |
| 925 | rt2x00_set_field32(®, MACCSR2_DELAY, 64); |
| 926 | rt2x00pci_register_write(rt2x00dev, MACCSR2, reg); |
| 927 | |
| 928 | rt2x00pci_register_read(rt2x00dev, RALINKCSR, ®); |
| 929 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17); |
| 930 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 26); |
| 931 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID0, 1); |
| 932 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0); |
| 933 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 26); |
| 934 | rt2x00_set_field32(®, RALINKCSR_AR_BBP_VALID1, 1); |
| 935 | rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg); |
| 936 | |
| 937 | rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200); |
| 938 | |
| 939 | rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020); |
| 940 | |
| 941 | rt2x00pci_register_read(rt2x00dev, CSR1, ®); |
| 942 | rt2x00_set_field32(®, CSR1_SOFT_RESET, 1); |
| 943 | rt2x00_set_field32(®, CSR1_BBP_RESET, 0); |
| 944 | rt2x00_set_field32(®, CSR1_HOST_READY, 0); |
| 945 | rt2x00pci_register_write(rt2x00dev, CSR1, reg); |
| 946 | |
| 947 | rt2x00pci_register_read(rt2x00dev, CSR1, ®); |
| 948 | rt2x00_set_field32(®, CSR1_SOFT_RESET, 0); |
| 949 | rt2x00_set_field32(®, CSR1_HOST_READY, 1); |
| 950 | rt2x00pci_register_write(rt2x00dev, CSR1, reg); |
| 951 | |
| 952 | /* |
| 953 | * We must clear the FCS and FIFO error count. |
| 954 | * These registers are cleared on read, |
| 955 | * so we may pass a useless variable to store the value. |
| 956 | */ |
| 957 | rt2x00pci_register_read(rt2x00dev, CNT0, ®); |
| 958 | rt2x00pci_register_read(rt2x00dev, CNT4, ®); |
| 959 | |
| 960 | return 0; |
| 961 | } |
| 962 | |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 963 | static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) |
| 964 | { |
| 965 | unsigned int i; |
| 966 | u8 value; |
| 967 | |
| 968 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
| 969 | rt2500pci_bbp_read(rt2x00dev, 0, &value); |
| 970 | if ((value != 0xff) && (value != 0x00)) |
| 971 | return 0; |
| 972 | udelay(REGISTER_BUSY_DELAY); |
| 973 | } |
| 974 | |
| 975 | ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); |
| 976 | return -EACCES; |
| 977 | } |
| 978 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 979 | static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev) |
| 980 | { |
| 981 | unsigned int i; |
| 982 | u16 eeprom; |
| 983 | u8 reg_id; |
| 984 | u8 value; |
| 985 | |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 986 | if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev))) |
| 987 | return -EACCES; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 988 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 989 | rt2500pci_bbp_write(rt2x00dev, 3, 0x02); |
| 990 | rt2500pci_bbp_write(rt2x00dev, 4, 0x19); |
| 991 | rt2500pci_bbp_write(rt2x00dev, 14, 0x1c); |
| 992 | rt2500pci_bbp_write(rt2x00dev, 15, 0x30); |
| 993 | rt2500pci_bbp_write(rt2x00dev, 16, 0xac); |
| 994 | rt2500pci_bbp_write(rt2x00dev, 18, 0x18); |
| 995 | rt2500pci_bbp_write(rt2x00dev, 19, 0xff); |
| 996 | rt2500pci_bbp_write(rt2x00dev, 20, 0x1e); |
| 997 | rt2500pci_bbp_write(rt2x00dev, 21, 0x08); |
| 998 | rt2500pci_bbp_write(rt2x00dev, 22, 0x08); |
| 999 | rt2500pci_bbp_write(rt2x00dev, 23, 0x08); |
| 1000 | rt2500pci_bbp_write(rt2x00dev, 24, 0x70); |
| 1001 | rt2500pci_bbp_write(rt2x00dev, 25, 0x40); |
| 1002 | rt2500pci_bbp_write(rt2x00dev, 26, 0x08); |
| 1003 | rt2500pci_bbp_write(rt2x00dev, 27, 0x23); |
| 1004 | rt2500pci_bbp_write(rt2x00dev, 30, 0x10); |
| 1005 | rt2500pci_bbp_write(rt2x00dev, 31, 0x2b); |
| 1006 | rt2500pci_bbp_write(rt2x00dev, 32, 0xb9); |
| 1007 | rt2500pci_bbp_write(rt2x00dev, 34, 0x12); |
| 1008 | rt2500pci_bbp_write(rt2x00dev, 35, 0x50); |
| 1009 | rt2500pci_bbp_write(rt2x00dev, 39, 0xc4); |
| 1010 | rt2500pci_bbp_write(rt2x00dev, 40, 0x02); |
| 1011 | rt2500pci_bbp_write(rt2x00dev, 41, 0x60); |
| 1012 | rt2500pci_bbp_write(rt2x00dev, 53, 0x10); |
| 1013 | rt2500pci_bbp_write(rt2x00dev, 54, 0x18); |
| 1014 | rt2500pci_bbp_write(rt2x00dev, 56, 0x08); |
| 1015 | rt2500pci_bbp_write(rt2x00dev, 57, 0x10); |
| 1016 | rt2500pci_bbp_write(rt2x00dev, 58, 0x08); |
| 1017 | rt2500pci_bbp_write(rt2x00dev, 61, 0x6d); |
| 1018 | rt2500pci_bbp_write(rt2x00dev, 62, 0x10); |
| 1019 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1020 | for (i = 0; i < EEPROM_BBP_SIZE; i++) { |
| 1021 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); |
| 1022 | |
| 1023 | if (eeprom != 0xffff && eeprom != 0x0000) { |
| 1024 | reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); |
| 1025 | value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1026 | rt2500pci_bbp_write(rt2x00dev, reg_id, value); |
| 1027 | } |
| 1028 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1029 | |
| 1030 | return 0; |
| 1031 | } |
| 1032 | |
| 1033 | /* |
| 1034 | * Device state switch handlers. |
| 1035 | */ |
| 1036 | static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev, |
| 1037 | enum dev_state state) |
| 1038 | { |
| 1039 | u32 reg; |
| 1040 | |
| 1041 | rt2x00pci_register_read(rt2x00dev, RXCSR0, ®); |
| 1042 | rt2x00_set_field32(®, RXCSR0_DISABLE_RX, |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 1043 | (state == STATE_RADIO_RX_OFF) || |
| 1044 | (state == STATE_RADIO_RX_OFF_LINK)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1045 | rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); |
| 1046 | } |
| 1047 | |
| 1048 | static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev, |
| 1049 | enum dev_state state) |
| 1050 | { |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 1051 | int mask = (state == STATE_RADIO_IRQ_OFF) || |
| 1052 | (state == STATE_RADIO_IRQ_OFF_ISR); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1053 | u32 reg; |
| 1054 | |
| 1055 | /* |
| 1056 | * When interrupts are being enabled, the interrupt registers |
| 1057 | * should clear the register to assure a clean state. |
| 1058 | */ |
| 1059 | if (state == STATE_RADIO_IRQ_ON) { |
| 1060 | rt2x00pci_register_read(rt2x00dev, CSR7, ®); |
| 1061 | rt2x00pci_register_write(rt2x00dev, CSR7, reg); |
| 1062 | } |
| 1063 | |
| 1064 | /* |
| 1065 | * Only toggle the interrupts bits we are going to use. |
| 1066 | * Non-checked interrupt bits are disabled by default. |
| 1067 | */ |
| 1068 | rt2x00pci_register_read(rt2x00dev, CSR8, ®); |
| 1069 | rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); |
| 1070 | rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); |
| 1071 | rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask); |
| 1072 | rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); |
| 1073 | rt2x00_set_field32(®, CSR8_RXDONE, mask); |
| 1074 | rt2x00pci_register_write(rt2x00dev, CSR8, reg); |
| 1075 | } |
| 1076 | |
| 1077 | static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev) |
| 1078 | { |
| 1079 | /* |
| 1080 | * Initialize all registers. |
| 1081 | */ |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 1082 | if (unlikely(rt2500pci_init_queues(rt2x00dev) || |
| 1083 | rt2500pci_init_registers(rt2x00dev) || |
| 1084 | rt2500pci_init_bbp(rt2x00dev))) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1085 | return -EIO; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1086 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1087 | return 0; |
| 1088 | } |
| 1089 | |
| 1090 | static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev) |
| 1091 | { |
Ivo van Doorn | a2c9b65 | 2009-01-28 00:32:33 +0100 | [diff] [blame] | 1092 | /* |
| 1093 | * Disable power |
| 1094 | */ |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1095 | rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1096 | } |
| 1097 | |
| 1098 | static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev, |
| 1099 | enum dev_state state) |
| 1100 | { |
Gertjan van Wingerde | 9655a6e | 2010-05-13 21:16:03 +0200 | [diff] [blame] | 1101 | u32 reg, reg2; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1102 | unsigned int i; |
| 1103 | char put_to_sleep; |
| 1104 | char bbp_state; |
| 1105 | char rf_state; |
| 1106 | |
| 1107 | put_to_sleep = (state != STATE_AWAKE); |
| 1108 | |
| 1109 | rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®); |
| 1110 | rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1); |
| 1111 | rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state); |
| 1112 | rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state); |
| 1113 | rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep); |
| 1114 | rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg); |
| 1115 | |
| 1116 | /* |
| 1117 | * Device is not guaranteed to be in the requested state yet. |
| 1118 | * We must wait until the register indicates that the |
| 1119 | * device has entered the correct state. |
| 1120 | */ |
| 1121 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
Gertjan van Wingerde | 9655a6e | 2010-05-13 21:16:03 +0200 | [diff] [blame] | 1122 | rt2x00pci_register_read(rt2x00dev, PWRCSR1, ®2); |
| 1123 | bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE); |
| 1124 | rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1125 | if (bbp_state == state && rf_state == state) |
| 1126 | return 0; |
Gertjan van Wingerde | 9655a6e | 2010-05-13 21:16:03 +0200 | [diff] [blame] | 1127 | rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1128 | msleep(10); |
| 1129 | } |
| 1130 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1131 | return -EBUSY; |
| 1132 | } |
| 1133 | |
| 1134 | static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev, |
| 1135 | enum dev_state state) |
| 1136 | { |
| 1137 | int retval = 0; |
| 1138 | |
| 1139 | switch (state) { |
| 1140 | case STATE_RADIO_ON: |
| 1141 | retval = rt2500pci_enable_radio(rt2x00dev); |
| 1142 | break; |
| 1143 | case STATE_RADIO_OFF: |
| 1144 | rt2500pci_disable_radio(rt2x00dev); |
| 1145 | break; |
| 1146 | case STATE_RADIO_RX_ON: |
Ivo van Doorn | 61667d8 | 2008-02-25 23:15:05 +0100 | [diff] [blame] | 1147 | case STATE_RADIO_RX_ON_LINK: |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1148 | case STATE_RADIO_RX_OFF: |
Ivo van Doorn | 61667d8 | 2008-02-25 23:15:05 +0100 | [diff] [blame] | 1149 | case STATE_RADIO_RX_OFF_LINK: |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 1150 | rt2500pci_toggle_rx(rt2x00dev, state); |
| 1151 | break; |
| 1152 | case STATE_RADIO_IRQ_ON: |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 1153 | case STATE_RADIO_IRQ_ON_ISR: |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 1154 | case STATE_RADIO_IRQ_OFF: |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 1155 | case STATE_RADIO_IRQ_OFF_ISR: |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 1156 | rt2500pci_toggle_irq(rt2x00dev, state); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1157 | break; |
| 1158 | case STATE_DEEP_SLEEP: |
| 1159 | case STATE_SLEEP: |
| 1160 | case STATE_STANDBY: |
| 1161 | case STATE_AWAKE: |
| 1162 | retval = rt2500pci_set_state(rt2x00dev, state); |
| 1163 | break; |
| 1164 | default: |
| 1165 | retval = -ENOTSUPP; |
| 1166 | break; |
| 1167 | } |
| 1168 | |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 1169 | if (unlikely(retval)) |
| 1170 | ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n", |
| 1171 | state, retval); |
| 1172 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1173 | return retval; |
| 1174 | } |
| 1175 | |
| 1176 | /* |
| 1177 | * TX descriptor initialization |
| 1178 | */ |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1179 | static void rt2500pci_write_tx_desc(struct queue_entry *entry, |
Ivo van Doorn | 61486e0 | 2008-05-10 13:42:31 +0200 | [diff] [blame] | 1180 | struct txentry_desc *txdesc) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1181 | { |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1182 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
| 1183 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
Gertjan van Wingerde | 85b7a8b | 2010-05-11 23:51:40 +0200 | [diff] [blame] | 1184 | __le32 *txd = entry_priv->desc; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1185 | u32 word; |
| 1186 | |
| 1187 | /* |
| 1188 | * Start writing the descriptor words. |
| 1189 | */ |
Gertjan van Wingerde | 85b7a8b | 2010-05-11 23:51:40 +0200 | [diff] [blame] | 1190 | rt2x00_desc_read(txd, 1, &word); |
Gertjan van Wingerde | c4da004 | 2008-06-16 19:56:31 +0200 | [diff] [blame] | 1191 | rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); |
Gertjan van Wingerde | 85b7a8b | 2010-05-11 23:51:40 +0200 | [diff] [blame] | 1192 | rt2x00_desc_write(txd, 1, word); |
Gertjan van Wingerde | 4de36fe | 2008-05-10 13:44:14 +0200 | [diff] [blame] | 1193 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1194 | rt2x00_desc_read(txd, 2, &word); |
| 1195 | rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1196 | rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs); |
| 1197 | rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min); |
| 1198 | rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1199 | rt2x00_desc_write(txd, 2, word); |
| 1200 | |
| 1201 | rt2x00_desc_read(txd, 3, &word); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1202 | rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal); |
| 1203 | rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service); |
| 1204 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low); |
| 1205 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1206 | rt2x00_desc_write(txd, 3, word); |
| 1207 | |
| 1208 | rt2x00_desc_read(txd, 10, &word); |
| 1209 | rt2x00_set_field32(&word, TXD_W10_RTS, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1210 | test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1211 | rt2x00_desc_write(txd, 10, word); |
| 1212 | |
Gertjan van Wingerde | e01f1ec | 2010-05-11 23:51:39 +0200 | [diff] [blame] | 1213 | /* |
| 1214 | * Writing TXD word 0 must the last to prevent a race condition with |
| 1215 | * the device, whereby the device may take hold of the TXD before we |
| 1216 | * finished updating it. |
| 1217 | */ |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1218 | rt2x00_desc_read(txd, 0, &word); |
| 1219 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); |
| 1220 | rt2x00_set_field32(&word, TXD_W0_VALID, 1); |
| 1221 | rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1222 | test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1223 | rt2x00_set_field32(&word, TXD_W0_ACK, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1224 | test_bit(ENTRY_TXD_ACK, &txdesc->flags)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1225 | rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1226 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1227 | rt2x00_set_field32(&word, TXD_W0_OFDM, |
Ivo van Doorn | 076f958 | 2008-12-20 10:59:02 +0100 | [diff] [blame] | 1228 | (txdesc->rate_mode == RATE_MODE_OFDM)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1229 | rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1230 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1231 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, |
Ivo van Doorn | 61486e0 | 2008-05-10 13:42:31 +0200 | [diff] [blame] | 1232 | test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); |
Gertjan van Wingerde | df624ca | 2010-05-03 22:43:05 +0200 | [diff] [blame] | 1233 | rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1234 | rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE); |
| 1235 | rt2x00_desc_write(txd, 0, word); |
Gertjan van Wingerde | 85b7a8b | 2010-05-11 23:51:40 +0200 | [diff] [blame] | 1236 | |
| 1237 | /* |
| 1238 | * Register descriptor details in skb frame descriptor. |
| 1239 | */ |
| 1240 | skbdesc->desc = txd; |
| 1241 | skbdesc->desc_len = TXD_DESC_SIZE; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1242 | } |
| 1243 | |
| 1244 | /* |
| 1245 | * TX data initialization |
| 1246 | */ |
Gertjan van Wingerde | f224f4e | 2010-05-08 23:40:25 +0200 | [diff] [blame] | 1247 | static void rt2500pci_write_beacon(struct queue_entry *entry, |
| 1248 | struct txentry_desc *txdesc) |
Ivo van Doorn | bd88a78 | 2008-07-09 15:12:44 +0200 | [diff] [blame] | 1249 | { |
| 1250 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
Ivo van Doorn | bd88a78 | 2008-07-09 15:12:44 +0200 | [diff] [blame] | 1251 | u32 reg; |
| 1252 | |
| 1253 | /* |
| 1254 | * Disable beaconing while we are reloading the beacon data, |
| 1255 | * otherwise we might be sending out invalid data. |
| 1256 | */ |
| 1257 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); |
Ivo van Doorn | bd88a78 | 2008-07-09 15:12:44 +0200 | [diff] [blame] | 1258 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); |
| 1259 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); |
| 1260 | |
Ivo van Doorn | bd88a78 | 2008-07-09 15:12:44 +0200 | [diff] [blame] | 1261 | rt2x00queue_map_txskb(rt2x00dev, entry->skb); |
| 1262 | |
Gertjan van Wingerde | 5c3b685 | 2010-06-03 10:51:41 +0200 | [diff] [blame] | 1263 | /* |
| 1264 | * Write the TX descriptor for the beacon. |
| 1265 | */ |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1266 | rt2500pci_write_tx_desc(entry, txdesc); |
Gertjan van Wingerde | 5c3b685 | 2010-06-03 10:51:41 +0200 | [diff] [blame] | 1267 | |
| 1268 | /* |
| 1269 | * Dump beacon to userspace through debugfs. |
| 1270 | */ |
| 1271 | rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); |
Gertjan van Wingerde | d61cb26 | 2010-05-08 23:40:24 +0200 | [diff] [blame] | 1272 | |
| 1273 | /* |
| 1274 | * Enable beaconing again. |
| 1275 | */ |
| 1276 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); |
| 1277 | rt2x00_set_field32(®, CSR14_TBCN, 1); |
| 1278 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); |
| 1279 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); |
Ivo van Doorn | bd88a78 | 2008-07-09 15:12:44 +0200 | [diff] [blame] | 1280 | } |
| 1281 | |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1282 | static void rt2500pci_kick_tx_queue(struct data_queue *queue) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1283 | { |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1284 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1285 | u32 reg; |
| 1286 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1287 | rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1288 | rt2x00_set_field32(®, TXCSR0_KICK_PRIO, (queue->qid == QID_AC_BE)); |
| 1289 | rt2x00_set_field32(®, TXCSR0_KICK_TX, (queue->qid == QID_AC_BK)); |
| 1290 | rt2x00_set_field32(®, TXCSR0_KICK_ATIM, (queue->qid == QID_ATIM)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1291 | rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); |
| 1292 | } |
| 1293 | |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1294 | static void rt2500pci_kill_tx_queue(struct data_queue *queue) |
Ivo van Doorn | a2c9b65 | 2009-01-28 00:32:33 +0100 | [diff] [blame] | 1295 | { |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1296 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; |
Ivo van Doorn | a2c9b65 | 2009-01-28 00:32:33 +0100 | [diff] [blame] | 1297 | u32 reg; |
| 1298 | |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1299 | if (queue->qid == QID_BEACON) { |
Ivo van Doorn | a2c9b65 | 2009-01-28 00:32:33 +0100 | [diff] [blame] | 1300 | rt2x00pci_register_write(rt2x00dev, CSR14, 0); |
| 1301 | } else { |
| 1302 | rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); |
| 1303 | rt2x00_set_field32(®, TXCSR0_ABORT, 1); |
| 1304 | rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); |
| 1305 | } |
| 1306 | } |
| 1307 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1308 | /* |
| 1309 | * RX control handlers |
| 1310 | */ |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1311 | static void rt2500pci_fill_rxdone(struct queue_entry *entry, |
| 1312 | struct rxdone_entry_desc *rxdesc) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1313 | { |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1314 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1315 | u32 word0; |
| 1316 | u32 word2; |
| 1317 | |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1318 | rt2x00_desc_read(entry_priv->desc, 0, &word0); |
| 1319 | rt2x00_desc_read(entry_priv->desc, 2, &word2); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1320 | |
Johannes Berg | 4150c57 | 2007-09-17 01:29:23 -0400 | [diff] [blame] | 1321 | if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1322 | rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; |
Johannes Berg | 4150c57 | 2007-09-17 01:29:23 -0400 | [diff] [blame] | 1323 | if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1324 | rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1325 | |
Ivo van Doorn | 8999389 | 2008-03-09 22:49:04 +0100 | [diff] [blame] | 1326 | /* |
| 1327 | * Obtain the status about this packet. |
| 1328 | * When frame was received with an OFDM bitrate, |
| 1329 | * the signal is the PLCP value. If it was received with |
| 1330 | * a CCK bitrate the signal is the rate in 100kbit/s. |
| 1331 | */ |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1332 | rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL); |
| 1333 | rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) - |
| 1334 | entry->queue->rt2x00dev->rssi_offset; |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1335 | rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); |
Ivo van Doorn | 19d30e0 | 2008-03-15 21:38:07 +0100 | [diff] [blame] | 1336 | |
Ivo van Doorn | 19d30e0 | 2008-03-15 21:38:07 +0100 | [diff] [blame] | 1337 | if (rt2x00_get_field32(word0, RXD_W0_OFDM)) |
| 1338 | rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; |
Ivo van Doorn | 6c6aa3c | 2008-08-29 21:07:16 +0200 | [diff] [blame] | 1339 | else |
| 1340 | rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE; |
Ivo van Doorn | 19d30e0 | 2008-03-15 21:38:07 +0100 | [diff] [blame] | 1341 | if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) |
| 1342 | rxdesc->dev_flags |= RXDONE_MY_BSS; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1343 | } |
| 1344 | |
| 1345 | /* |
| 1346 | * Interrupt functions. |
| 1347 | */ |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1348 | static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | e58c6ac | 2008-04-21 19:00:47 +0200 | [diff] [blame] | 1349 | const enum data_queue_qid queue_idx) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1350 | { |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1351 | struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1352 | struct queue_entry_priv_pci *entry_priv; |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1353 | struct queue_entry *entry; |
| 1354 | struct txdone_entry_desc txdesc; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1355 | u32 word; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1356 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1357 | while (!rt2x00queue_empty(queue)) { |
| 1358 | entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1359 | entry_priv = entry->priv_data; |
| 1360 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1361 | |
| 1362 | if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || |
| 1363 | !rt2x00_get_field32(word, TXD_W0_VALID)) |
| 1364 | break; |
| 1365 | |
| 1366 | /* |
| 1367 | * Obtain the status about this packet. |
| 1368 | */ |
Ivo van Doorn | fb55f4d | 2008-05-10 13:42:06 +0200 | [diff] [blame] | 1369 | txdesc.flags = 0; |
| 1370 | switch (rt2x00_get_field32(word, TXD_W0_RESULT)) { |
| 1371 | case 0: /* Success */ |
| 1372 | case 1: /* Success with retry */ |
| 1373 | __set_bit(TXDONE_SUCCESS, &txdesc.flags); |
| 1374 | break; |
| 1375 | case 2: /* Failure, excessive retries */ |
| 1376 | __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags); |
| 1377 | /* Don't break, this is a failed frame! */ |
| 1378 | default: /* Failure */ |
| 1379 | __set_bit(TXDONE_FAILURE, &txdesc.flags); |
| 1380 | } |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1381 | txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1382 | |
Gertjan van Wingerde | e513a0b | 2010-06-29 21:41:40 +0200 | [diff] [blame] | 1383 | rt2x00lib_txdone(entry, &txdesc); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1384 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1385 | } |
| 1386 | |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 1387 | static irqreturn_t rt2500pci_interrupt_thread(int irq, void *dev_instance) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1388 | { |
| 1389 | struct rt2x00_dev *rt2x00dev = dev_instance; |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 1390 | u32 reg = rt2x00dev->irqvalue[0]; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1391 | |
| 1392 | /* |
| 1393 | * Handle interrupts, walk through all bits |
| 1394 | * and run the tasks, the bits are checked in order of |
| 1395 | * priority. |
| 1396 | */ |
| 1397 | |
| 1398 | /* |
| 1399 | * 1 - Beacon timer expired interrupt. |
| 1400 | */ |
| 1401 | if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE)) |
| 1402 | rt2x00lib_beacondone(rt2x00dev); |
| 1403 | |
| 1404 | /* |
| 1405 | * 2 - Rx ring done interrupt. |
| 1406 | */ |
| 1407 | if (rt2x00_get_field32(reg, CSR7_RXDONE)) |
| 1408 | rt2x00pci_rxdone(rt2x00dev); |
| 1409 | |
| 1410 | /* |
| 1411 | * 3 - Atim ring transmit done interrupt. |
| 1412 | */ |
| 1413 | if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING)) |
Ivo van Doorn | e58c6ac | 2008-04-21 19:00:47 +0200 | [diff] [blame] | 1414 | rt2500pci_txdone(rt2x00dev, QID_ATIM); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1415 | |
| 1416 | /* |
| 1417 | * 4 - Priority ring transmit done interrupt. |
| 1418 | */ |
| 1419 | if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING)) |
Ivo van Doorn | e58c6ac | 2008-04-21 19:00:47 +0200 | [diff] [blame] | 1420 | rt2500pci_txdone(rt2x00dev, QID_AC_BE); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1421 | |
| 1422 | /* |
| 1423 | * 5 - Tx ring transmit done interrupt. |
| 1424 | */ |
| 1425 | if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) |
Ivo van Doorn | e58c6ac | 2008-04-21 19:00:47 +0200 | [diff] [blame] | 1426 | rt2500pci_txdone(rt2x00dev, QID_AC_BK); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1427 | |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 1428 | /* Enable interrupts again. */ |
| 1429 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, |
| 1430 | STATE_RADIO_IRQ_ON_ISR); |
| 1431 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1432 | return IRQ_HANDLED; |
| 1433 | } |
| 1434 | |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 1435 | static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance) |
| 1436 | { |
| 1437 | struct rt2x00_dev *rt2x00dev = dev_instance; |
| 1438 | u32 reg; |
| 1439 | |
| 1440 | /* |
| 1441 | * Get the interrupt sources & saved to local variable. |
| 1442 | * Write register value back to clear pending interrupts. |
| 1443 | */ |
| 1444 | rt2x00pci_register_read(rt2x00dev, CSR7, ®); |
| 1445 | rt2x00pci_register_write(rt2x00dev, CSR7, reg); |
| 1446 | |
| 1447 | if (!reg) |
| 1448 | return IRQ_NONE; |
| 1449 | |
| 1450 | if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) |
| 1451 | return IRQ_HANDLED; |
| 1452 | |
| 1453 | /* Store irqvalues for use in the interrupt thread. */ |
| 1454 | rt2x00dev->irqvalue[0] = reg; |
| 1455 | |
| 1456 | /* Disable interrupts, will be enabled again in the interrupt thread. */ |
| 1457 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, |
| 1458 | STATE_RADIO_IRQ_OFF_ISR); |
| 1459 | |
| 1460 | return IRQ_WAKE_THREAD; |
| 1461 | } |
| 1462 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1463 | /* |
| 1464 | * Device probe functions. |
| 1465 | */ |
| 1466 | static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) |
| 1467 | { |
| 1468 | struct eeprom_93cx6 eeprom; |
| 1469 | u32 reg; |
| 1470 | u16 word; |
| 1471 | u8 *mac; |
| 1472 | |
| 1473 | rt2x00pci_register_read(rt2x00dev, CSR21, ®); |
| 1474 | |
| 1475 | eeprom.data = rt2x00dev; |
| 1476 | eeprom.register_read = rt2500pci_eepromregister_read; |
| 1477 | eeprom.register_write = rt2500pci_eepromregister_write; |
| 1478 | eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ? |
| 1479 | PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66; |
| 1480 | eeprom.reg_data_in = 0; |
| 1481 | eeprom.reg_data_out = 0; |
| 1482 | eeprom.reg_data_clock = 0; |
| 1483 | eeprom.reg_chip_select = 0; |
| 1484 | |
| 1485 | eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, |
| 1486 | EEPROM_SIZE / sizeof(u16)); |
| 1487 | |
| 1488 | /* |
| 1489 | * Start validation of the data that has been read. |
| 1490 | */ |
| 1491 | mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); |
| 1492 | if (!is_valid_ether_addr(mac)) { |
| 1493 | random_ether_addr(mac); |
Johannes Berg | e174961 | 2008-10-27 15:59:26 -0700 | [diff] [blame] | 1494 | EEPROM(rt2x00dev, "MAC: %pM\n", mac); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1495 | } |
| 1496 | |
| 1497 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); |
| 1498 | if (word == 0xffff) { |
| 1499 | rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2); |
Ivo van Doorn | 362f3b6 | 2007-10-13 16:26:18 +0200 | [diff] [blame] | 1500 | rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, |
| 1501 | ANTENNA_SW_DIVERSITY); |
| 1502 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, |
| 1503 | ANTENNA_SW_DIVERSITY); |
| 1504 | rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE, |
| 1505 | LED_MODE_DEFAULT); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1506 | rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0); |
| 1507 | rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0); |
| 1508 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522); |
| 1509 | rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); |
| 1510 | EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word); |
| 1511 | } |
| 1512 | |
| 1513 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); |
| 1514 | if (word == 0xffff) { |
| 1515 | rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0); |
| 1516 | rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0); |
| 1517 | rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0); |
| 1518 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); |
| 1519 | EEPROM(rt2x00dev, "NIC: 0x%04x\n", word); |
| 1520 | } |
| 1521 | |
| 1522 | rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word); |
| 1523 | if (word == 0xffff) { |
| 1524 | rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI, |
| 1525 | DEFAULT_RSSI_OFFSET); |
| 1526 | rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word); |
| 1527 | EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word); |
| 1528 | } |
| 1529 | |
| 1530 | return 0; |
| 1531 | } |
| 1532 | |
| 1533 | static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev) |
| 1534 | { |
| 1535 | u32 reg; |
| 1536 | u16 value; |
| 1537 | u16 eeprom; |
| 1538 | |
| 1539 | /* |
| 1540 | * Read EEPROM word for configuration. |
| 1541 | */ |
| 1542 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); |
| 1543 | |
| 1544 | /* |
| 1545 | * Identify RF chipset. |
| 1546 | */ |
| 1547 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); |
| 1548 | rt2x00pci_register_read(rt2x00dev, CSR0, ®); |
Gertjan van Wingerde | 49e721e | 2010-02-13 20:55:49 +0100 | [diff] [blame] | 1549 | rt2x00_set_chip(rt2x00dev, RT2560, value, |
| 1550 | rt2x00_get_field32(reg, CSR0_REVISION)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1551 | |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 1552 | if (!rt2x00_rf(rt2x00dev, RF2522) && |
| 1553 | !rt2x00_rf(rt2x00dev, RF2523) && |
| 1554 | !rt2x00_rf(rt2x00dev, RF2524) && |
| 1555 | !rt2x00_rf(rt2x00dev, RF2525) && |
| 1556 | !rt2x00_rf(rt2x00dev, RF2525E) && |
| 1557 | !rt2x00_rf(rt2x00dev, RF5222)) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1558 | ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); |
| 1559 | return -ENODEV; |
| 1560 | } |
| 1561 | |
| 1562 | /* |
| 1563 | * Identify default antenna configuration. |
| 1564 | */ |
Ivo van Doorn | addc81b | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 1565 | rt2x00dev->default_ant.tx = |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1566 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT); |
Ivo van Doorn | addc81b | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 1567 | rt2x00dev->default_ant.rx = |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1568 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT); |
| 1569 | |
| 1570 | /* |
| 1571 | * Store led mode, for correct led behaviour. |
| 1572 | */ |
Ivo van Doorn | 771fd56 | 2008-09-08 19:07:15 +0200 | [diff] [blame] | 1573 | #ifdef CONFIG_RT2X00_LIB_LEDS |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 1574 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE); |
| 1575 | |
Ivo van Doorn | 475433b | 2008-06-03 20:30:01 +0200 | [diff] [blame] | 1576 | rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); |
Ivo van Doorn | 3d3e451 | 2009-01-17 20:44:08 +0100 | [diff] [blame] | 1577 | if (value == LED_MODE_TXRX_ACTIVITY || |
| 1578 | value == LED_MODE_DEFAULT || |
| 1579 | value == LED_MODE_ASUS) |
Ivo van Doorn | 475433b | 2008-06-03 20:30:01 +0200 | [diff] [blame] | 1580 | rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual, |
| 1581 | LED_TYPE_ACTIVITY); |
Ivo van Doorn | 771fd56 | 2008-09-08 19:07:15 +0200 | [diff] [blame] | 1582 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1583 | |
| 1584 | /* |
| 1585 | * Detect if this device has an hardware controlled radio. |
| 1586 | */ |
| 1587 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) |
Ivo van Doorn | 066cb63 | 2007-09-25 20:55:39 +0200 | [diff] [blame] | 1588 | __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1589 | |
| 1590 | /* |
| 1591 | * Check if the BBP tuning should be enabled. |
| 1592 | */ |
| 1593 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); |
Ivo van Doorn | 27df2a9 | 2010-07-11 12:24:22 +0200 | [diff] [blame] | 1594 | if (!rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE)) |
| 1595 | __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1596 | |
| 1597 | /* |
| 1598 | * Read the RSSI <-> dBm offset information. |
| 1599 | */ |
| 1600 | rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom); |
| 1601 | rt2x00dev->rssi_offset = |
| 1602 | rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI); |
| 1603 | |
| 1604 | return 0; |
| 1605 | } |
| 1606 | |
| 1607 | /* |
| 1608 | * RF value list for RF2522 |
| 1609 | * Supports: 2.4 GHz |
| 1610 | */ |
| 1611 | static const struct rf_channel rf_vals_bg_2522[] = { |
| 1612 | { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 }, |
| 1613 | { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 }, |
| 1614 | { 3, 0x00002050, 0x000c2002, 0x00000101, 0 }, |
| 1615 | { 4, 0x00002050, 0x000c2016, 0x00000101, 0 }, |
| 1616 | { 5, 0x00002050, 0x000c202a, 0x00000101, 0 }, |
| 1617 | { 6, 0x00002050, 0x000c203e, 0x00000101, 0 }, |
| 1618 | { 7, 0x00002050, 0x000c2052, 0x00000101, 0 }, |
| 1619 | { 8, 0x00002050, 0x000c2066, 0x00000101, 0 }, |
| 1620 | { 9, 0x00002050, 0x000c207a, 0x00000101, 0 }, |
| 1621 | { 10, 0x00002050, 0x000c208e, 0x00000101, 0 }, |
| 1622 | { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 }, |
| 1623 | { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 }, |
| 1624 | { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 }, |
| 1625 | { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 }, |
| 1626 | }; |
| 1627 | |
| 1628 | /* |
| 1629 | * RF value list for RF2523 |
| 1630 | * Supports: 2.4 GHz |
| 1631 | */ |
| 1632 | static const struct rf_channel rf_vals_bg_2523[] = { |
| 1633 | { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b }, |
| 1634 | { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b }, |
| 1635 | { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b }, |
| 1636 | { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b }, |
| 1637 | { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b }, |
| 1638 | { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b }, |
| 1639 | { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b }, |
| 1640 | { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b }, |
| 1641 | { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b }, |
| 1642 | { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b }, |
| 1643 | { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b }, |
| 1644 | { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b }, |
| 1645 | { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b }, |
| 1646 | { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 }, |
| 1647 | }; |
| 1648 | |
| 1649 | /* |
| 1650 | * RF value list for RF2524 |
| 1651 | * Supports: 2.4 GHz |
| 1652 | */ |
| 1653 | static const struct rf_channel rf_vals_bg_2524[] = { |
| 1654 | { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b }, |
| 1655 | { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b }, |
| 1656 | { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b }, |
| 1657 | { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b }, |
| 1658 | { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b }, |
| 1659 | { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b }, |
| 1660 | { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b }, |
| 1661 | { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b }, |
| 1662 | { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b }, |
| 1663 | { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b }, |
| 1664 | { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b }, |
| 1665 | { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b }, |
| 1666 | { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b }, |
| 1667 | { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 }, |
| 1668 | }; |
| 1669 | |
| 1670 | /* |
| 1671 | * RF value list for RF2525 |
| 1672 | * Supports: 2.4 GHz |
| 1673 | */ |
| 1674 | static const struct rf_channel rf_vals_bg_2525[] = { |
| 1675 | { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b }, |
| 1676 | { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b }, |
| 1677 | { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b }, |
| 1678 | { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b }, |
| 1679 | { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b }, |
| 1680 | { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b }, |
| 1681 | { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b }, |
| 1682 | { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b }, |
| 1683 | { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b }, |
| 1684 | { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b }, |
| 1685 | { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b }, |
| 1686 | { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b }, |
| 1687 | { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b }, |
| 1688 | { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 }, |
| 1689 | }; |
| 1690 | |
| 1691 | /* |
| 1692 | * RF value list for RF2525e |
| 1693 | * Supports: 2.4 GHz |
| 1694 | */ |
| 1695 | static const struct rf_channel rf_vals_bg_2525e[] = { |
| 1696 | { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b }, |
| 1697 | { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b }, |
| 1698 | { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b }, |
| 1699 | { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b }, |
| 1700 | { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b }, |
| 1701 | { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b }, |
| 1702 | { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b }, |
| 1703 | { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b }, |
| 1704 | { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b }, |
| 1705 | { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b }, |
| 1706 | { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b }, |
| 1707 | { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b }, |
| 1708 | { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b }, |
| 1709 | { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b }, |
| 1710 | }; |
| 1711 | |
| 1712 | /* |
| 1713 | * RF value list for RF5222 |
| 1714 | * Supports: 2.4 GHz & 5.2 GHz |
| 1715 | */ |
| 1716 | static const struct rf_channel rf_vals_5222[] = { |
| 1717 | { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b }, |
| 1718 | { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b }, |
| 1719 | { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b }, |
| 1720 | { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b }, |
| 1721 | { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b }, |
| 1722 | { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b }, |
| 1723 | { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b }, |
| 1724 | { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b }, |
| 1725 | { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b }, |
| 1726 | { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b }, |
| 1727 | { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b }, |
| 1728 | { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b }, |
| 1729 | { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b }, |
| 1730 | { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b }, |
| 1731 | |
| 1732 | /* 802.11 UNI / HyperLan 2 */ |
| 1733 | { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f }, |
| 1734 | { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f }, |
| 1735 | { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f }, |
| 1736 | { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f }, |
| 1737 | { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f }, |
| 1738 | { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f }, |
| 1739 | { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f }, |
| 1740 | { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f }, |
| 1741 | |
| 1742 | /* 802.11 HyperLan 2 */ |
| 1743 | { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f }, |
| 1744 | { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f }, |
| 1745 | { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f }, |
| 1746 | { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f }, |
| 1747 | { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f }, |
| 1748 | { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f }, |
| 1749 | { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f }, |
| 1750 | { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f }, |
| 1751 | { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f }, |
| 1752 | { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f }, |
| 1753 | |
| 1754 | /* 802.11 UNII */ |
| 1755 | { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f }, |
| 1756 | { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 }, |
| 1757 | { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 }, |
| 1758 | { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 }, |
| 1759 | { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 }, |
| 1760 | }; |
| 1761 | |
Ivo van Doorn | 8c5e7a5 | 2008-08-04 16:38:47 +0200 | [diff] [blame] | 1762 | static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1763 | { |
| 1764 | struct hw_mode_spec *spec = &rt2x00dev->spec; |
Ivo van Doorn | 8c5e7a5 | 2008-08-04 16:38:47 +0200 | [diff] [blame] | 1765 | struct channel_info *info; |
| 1766 | char *tx_power; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1767 | unsigned int i; |
| 1768 | |
| 1769 | /* |
| 1770 | * Initialize all hw fields. |
| 1771 | */ |
Bruno Randolf | 566bfe5 | 2008-05-08 19:15:40 +0200 | [diff] [blame] | 1772 | rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | |
Johannes Berg | 4be8c38 | 2009-01-07 18:28:20 +0100 | [diff] [blame] | 1773 | IEEE80211_HW_SIGNAL_DBM | |
| 1774 | IEEE80211_HW_SUPPORTS_PS | |
| 1775 | IEEE80211_HW_PS_NULLFUNC_STACK; |
Bruno Randolf | 566bfe5 | 2008-05-08 19:15:40 +0200 | [diff] [blame] | 1776 | |
Gertjan van Wingerde | 14a3bf8 | 2008-06-16 19:55:43 +0200 | [diff] [blame] | 1777 | SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1778 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, |
| 1779 | rt2x00_eeprom_addr(rt2x00dev, |
| 1780 | EEPROM_MAC_ADDR_0)); |
| 1781 | |
| 1782 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1783 | * Initialize hw_mode information. |
| 1784 | */ |
Ivo van Doorn | 31562e8 | 2008-02-17 17:35:05 +0100 | [diff] [blame] | 1785 | spec->supported_bands = SUPPORT_BAND_2GHZ; |
| 1786 | spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1787 | |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 1788 | if (rt2x00_rf(rt2x00dev, RF2522)) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1789 | spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522); |
| 1790 | spec->channels = rf_vals_bg_2522; |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 1791 | } else if (rt2x00_rf(rt2x00dev, RF2523)) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1792 | spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523); |
| 1793 | spec->channels = rf_vals_bg_2523; |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 1794 | } else if (rt2x00_rf(rt2x00dev, RF2524)) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1795 | spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524); |
| 1796 | spec->channels = rf_vals_bg_2524; |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 1797 | } else if (rt2x00_rf(rt2x00dev, RF2525)) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1798 | spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525); |
| 1799 | spec->channels = rf_vals_bg_2525; |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 1800 | } else if (rt2x00_rf(rt2x00dev, RF2525E)) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1801 | spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e); |
| 1802 | spec->channels = rf_vals_bg_2525e; |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 1803 | } else if (rt2x00_rf(rt2x00dev, RF5222)) { |
Ivo van Doorn | 31562e8 | 2008-02-17 17:35:05 +0100 | [diff] [blame] | 1804 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1805 | spec->num_channels = ARRAY_SIZE(rf_vals_5222); |
| 1806 | spec->channels = rf_vals_5222; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1807 | } |
Ivo van Doorn | 8c5e7a5 | 2008-08-04 16:38:47 +0200 | [diff] [blame] | 1808 | |
| 1809 | /* |
| 1810 | * Create channel information array |
| 1811 | */ |
| 1812 | info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL); |
| 1813 | if (!info) |
| 1814 | return -ENOMEM; |
| 1815 | |
| 1816 | spec->channels_info = info; |
| 1817 | |
| 1818 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START); |
Ivo van Doorn | 8d1331b | 2010-08-23 19:56:07 +0200 | [diff] [blame] | 1819 | for (i = 0; i < 14; i++) { |
| 1820 | info[i].max_power = MAX_TXPOWER; |
| 1821 | info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]); |
| 1822 | } |
Ivo van Doorn | 8c5e7a5 | 2008-08-04 16:38:47 +0200 | [diff] [blame] | 1823 | |
| 1824 | if (spec->num_channels > 14) { |
Ivo van Doorn | 8d1331b | 2010-08-23 19:56:07 +0200 | [diff] [blame] | 1825 | for (i = 14; i < spec->num_channels; i++) { |
| 1826 | info[i].max_power = MAX_TXPOWER; |
| 1827 | info[i].default_power1 = DEFAULT_TXPOWER; |
| 1828 | } |
Ivo van Doorn | 8c5e7a5 | 2008-08-04 16:38:47 +0200 | [diff] [blame] | 1829 | } |
| 1830 | |
| 1831 | return 0; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1832 | } |
| 1833 | |
| 1834 | static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev) |
| 1835 | { |
| 1836 | int retval; |
| 1837 | |
| 1838 | /* |
| 1839 | * Allocate eeprom data. |
| 1840 | */ |
| 1841 | retval = rt2500pci_validate_eeprom(rt2x00dev); |
| 1842 | if (retval) |
| 1843 | return retval; |
| 1844 | |
| 1845 | retval = rt2500pci_init_eeprom(rt2x00dev); |
| 1846 | if (retval) |
| 1847 | return retval; |
| 1848 | |
| 1849 | /* |
| 1850 | * Initialize hw specifications. |
| 1851 | */ |
Ivo van Doorn | 8c5e7a5 | 2008-08-04 16:38:47 +0200 | [diff] [blame] | 1852 | retval = rt2500pci_probe_hw_mode(rt2x00dev); |
| 1853 | if (retval) |
| 1854 | return retval; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1855 | |
| 1856 | /* |
Gertjan van Wingerde | c4da004 | 2008-06-16 19:56:31 +0200 | [diff] [blame] | 1857 | * This device requires the atim queue and DMA-mapped skbs. |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1858 | */ |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1859 | __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); |
Gertjan van Wingerde | c4da004 | 2008-06-16 19:56:31 +0200 | [diff] [blame] | 1860 | __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1861 | |
| 1862 | /* |
| 1863 | * Set the rssi offset. |
| 1864 | */ |
| 1865 | rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; |
| 1866 | |
| 1867 | return 0; |
| 1868 | } |
| 1869 | |
| 1870 | /* |
| 1871 | * IEEE80211 stack callback functions. |
| 1872 | */ |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1873 | static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw) |
| 1874 | { |
| 1875 | struct rt2x00_dev *rt2x00dev = hw->priv; |
| 1876 | u64 tsf; |
| 1877 | u32 reg; |
| 1878 | |
| 1879 | rt2x00pci_register_read(rt2x00dev, CSR17, ®); |
| 1880 | tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32; |
| 1881 | rt2x00pci_register_read(rt2x00dev, CSR16, ®); |
| 1882 | tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER); |
| 1883 | |
| 1884 | return tsf; |
| 1885 | } |
| 1886 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1887 | static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw) |
| 1888 | { |
| 1889 | struct rt2x00_dev *rt2x00dev = hw->priv; |
| 1890 | u32 reg; |
| 1891 | |
| 1892 | rt2x00pci_register_read(rt2x00dev, CSR15, ®); |
| 1893 | return rt2x00_get_field32(reg, CSR15_BEACON_SENT); |
| 1894 | } |
| 1895 | |
| 1896 | static const struct ieee80211_ops rt2500pci_mac80211_ops = { |
| 1897 | .tx = rt2x00mac_tx, |
Johannes Berg | 4150c57 | 2007-09-17 01:29:23 -0400 | [diff] [blame] | 1898 | .start = rt2x00mac_start, |
| 1899 | .stop = rt2x00mac_stop, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1900 | .add_interface = rt2x00mac_add_interface, |
| 1901 | .remove_interface = rt2x00mac_remove_interface, |
| 1902 | .config = rt2x00mac_config, |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 1903 | .configure_filter = rt2x00mac_configure_filter, |
Ivo van Doorn | d8147f9 | 2010-07-11 12:24:47 +0200 | [diff] [blame] | 1904 | .sw_scan_start = rt2x00mac_sw_scan_start, |
| 1905 | .sw_scan_complete = rt2x00mac_sw_scan_complete, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1906 | .get_stats = rt2x00mac_get_stats, |
Johannes Berg | 471b3ef | 2007-12-28 14:32:58 +0100 | [diff] [blame] | 1907 | .bss_info_changed = rt2x00mac_bss_info_changed, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1908 | .conf_tx = rt2x00mac_conf_tx, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1909 | .get_tsf = rt2500pci_get_tsf, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1910 | .tx_last_beacon = rt2500pci_tx_last_beacon, |
Ivo van Doorn | e47a5cd | 2009-07-01 15:17:35 +0200 | [diff] [blame] | 1911 | .rfkill_poll = rt2x00mac_rfkill_poll, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1912 | }; |
| 1913 | |
| 1914 | static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = { |
| 1915 | .irq_handler = rt2500pci_interrupt, |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 1916 | .irq_handler_thread = rt2500pci_interrupt_thread, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1917 | .probe_hw = rt2500pci_probe_hw, |
| 1918 | .initialize = rt2x00pci_initialize, |
| 1919 | .uninitialize = rt2x00pci_uninitialize, |
Ivo van Doorn | 798b7ad | 2008-11-08 15:25:33 +0100 | [diff] [blame] | 1920 | .get_entry_state = rt2500pci_get_entry_state, |
| 1921 | .clear_entry = rt2500pci_clear_entry, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1922 | .set_device_state = rt2500pci_set_device_state, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1923 | .rfkill_poll = rt2500pci_rfkill_poll, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1924 | .link_stats = rt2500pci_link_stats, |
| 1925 | .reset_tuner = rt2500pci_reset_tuner, |
| 1926 | .link_tuner = rt2500pci_link_tuner, |
| 1927 | .write_tx_desc = rt2500pci_write_tx_desc, |
Ivo van Doorn | bd88a78 | 2008-07-09 15:12:44 +0200 | [diff] [blame] | 1928 | .write_beacon = rt2500pci_write_beacon, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1929 | .kick_tx_queue = rt2500pci_kick_tx_queue, |
Ivo van Doorn | a2c9b65 | 2009-01-28 00:32:33 +0100 | [diff] [blame] | 1930 | .kill_tx_queue = rt2500pci_kill_tx_queue, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1931 | .fill_rxdone = rt2500pci_fill_rxdone, |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 1932 | .config_filter = rt2500pci_config_filter, |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 1933 | .config_intf = rt2500pci_config_intf, |
Ivo van Doorn | 7281037 | 2008-03-09 22:46:18 +0100 | [diff] [blame] | 1934 | .config_erp = rt2500pci_config_erp, |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 1935 | .config_ant = rt2500pci_config_ant, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1936 | .config = rt2500pci_config, |
| 1937 | }; |
| 1938 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1939 | static const struct data_queue_desc rt2500pci_queue_rx = { |
| 1940 | .entry_num = RX_ENTRIES, |
| 1941 | .data_size = DATA_FRAME_SIZE, |
| 1942 | .desc_size = RXD_DESC_SIZE, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1943 | .priv_size = sizeof(struct queue_entry_priv_pci), |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1944 | }; |
| 1945 | |
| 1946 | static const struct data_queue_desc rt2500pci_queue_tx = { |
| 1947 | .entry_num = TX_ENTRIES, |
| 1948 | .data_size = DATA_FRAME_SIZE, |
| 1949 | .desc_size = TXD_DESC_SIZE, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1950 | .priv_size = sizeof(struct queue_entry_priv_pci), |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1951 | }; |
| 1952 | |
| 1953 | static const struct data_queue_desc rt2500pci_queue_bcn = { |
| 1954 | .entry_num = BEACON_ENTRIES, |
| 1955 | .data_size = MGMT_FRAME_SIZE, |
| 1956 | .desc_size = TXD_DESC_SIZE, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1957 | .priv_size = sizeof(struct queue_entry_priv_pci), |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1958 | }; |
| 1959 | |
| 1960 | static const struct data_queue_desc rt2500pci_queue_atim = { |
| 1961 | .entry_num = ATIM_ENTRIES, |
| 1962 | .data_size = DATA_FRAME_SIZE, |
| 1963 | .desc_size = TXD_DESC_SIZE, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1964 | .priv_size = sizeof(struct queue_entry_priv_pci), |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1965 | }; |
| 1966 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1967 | static const struct rt2x00_ops rt2500pci_ops = { |
Gertjan van Wingerde | 04d0362 | 2009-11-23 22:44:51 +0100 | [diff] [blame] | 1968 | .name = KBUILD_MODNAME, |
| 1969 | .max_sta_intf = 1, |
| 1970 | .max_ap_intf = 1, |
| 1971 | .eeprom_size = EEPROM_SIZE, |
| 1972 | .rf_size = RF_SIZE, |
| 1973 | .tx_queues = NUM_TX_QUEUES, |
Gertjan van Wingerde | e6218cc | 2009-11-23 22:44:52 +0100 | [diff] [blame] | 1974 | .extra_tx_headroom = 0, |
Gertjan van Wingerde | 04d0362 | 2009-11-23 22:44:51 +0100 | [diff] [blame] | 1975 | .rx = &rt2500pci_queue_rx, |
| 1976 | .tx = &rt2500pci_queue_tx, |
| 1977 | .bcn = &rt2500pci_queue_bcn, |
| 1978 | .atim = &rt2500pci_queue_atim, |
| 1979 | .lib = &rt2500pci_rt2x00_ops, |
| 1980 | .hw = &rt2500pci_mac80211_ops, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1981 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
Gertjan van Wingerde | 04d0362 | 2009-11-23 22:44:51 +0100 | [diff] [blame] | 1982 | .debugfs = &rt2500pci_rt2x00debug, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1983 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ |
| 1984 | }; |
| 1985 | |
| 1986 | /* |
| 1987 | * RT2500pci module information. |
| 1988 | */ |
Alexey Dobriyan | a3aa188 | 2010-01-07 11:58:11 +0000 | [diff] [blame] | 1989 | static DEFINE_PCI_DEVICE_TABLE(rt2500pci_device_table) = { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1990 | { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) }, |
| 1991 | { 0, } |
| 1992 | }; |
| 1993 | |
| 1994 | MODULE_AUTHOR(DRV_PROJECT); |
| 1995 | MODULE_VERSION(DRV_VERSION); |
| 1996 | MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver."); |
| 1997 | MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards"); |
| 1998 | MODULE_DEVICE_TABLE(pci, rt2500pci_device_table); |
| 1999 | MODULE_LICENSE("GPL"); |
| 2000 | |
| 2001 | static struct pci_driver rt2500pci_driver = { |
Ivo van Doorn | 2360157 | 2007-11-27 21:47:34 +0100 | [diff] [blame] | 2002 | .name = KBUILD_MODNAME, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2003 | .id_table = rt2500pci_device_table, |
| 2004 | .probe = rt2x00pci_probe, |
| 2005 | .remove = __devexit_p(rt2x00pci_remove), |
| 2006 | .suspend = rt2x00pci_suspend, |
| 2007 | .resume = rt2x00pci_resume, |
| 2008 | }; |
| 2009 | |
| 2010 | static int __init rt2500pci_init(void) |
| 2011 | { |
| 2012 | return pci_register_driver(&rt2500pci_driver); |
| 2013 | } |
| 2014 | |
| 2015 | static void __exit rt2500pci_exit(void) |
| 2016 | { |
| 2017 | pci_unregister_driver(&rt2500pci_driver); |
| 2018 | } |
| 2019 | |
| 2020 | module_init(rt2500pci_init); |
| 2021 | module_exit(rt2500pci_exit); |