Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1 | /* |
Gertjan van Wingerde | 9c9a0d1 | 2009-11-08 16:39:55 +0100 | [diff] [blame] | 2 | Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 3 | <http://rt2x00.serialmonkey.com> |
| 4 | |
| 5 | This program is free software; you can redistribute it and/or modify |
| 6 | it under the terms of the GNU General Public License as published by |
| 7 | the Free Software Foundation; either version 2 of the License, or |
| 8 | (at your option) any later version. |
| 9 | |
| 10 | This program is distributed in the hope that it will be useful, |
| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | GNU General Public License for more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License |
| 16 | along with this program; if not, write to the |
| 17 | Free Software Foundation, Inc., |
| 18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 19 | */ |
| 20 | |
| 21 | /* |
| 22 | Module: rt61pci |
| 23 | Abstract: rt61pci device specific routines. |
| 24 | Supported chipsets: RT2561, RT2561s, RT2661. |
| 25 | */ |
| 26 | |
Ivo van Doorn | a7f3a06 | 2008-03-09 22:44:54 +0100 | [diff] [blame] | 27 | #include <linux/crc-itu-t.h> |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 28 | #include <linux/delay.h> |
| 29 | #include <linux/etherdevice.h> |
| 30 | #include <linux/init.h> |
| 31 | #include <linux/kernel.h> |
| 32 | #include <linux/module.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 33 | #include <linux/slab.h> |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 34 | #include <linux/pci.h> |
| 35 | #include <linux/eeprom_93cx6.h> |
| 36 | |
| 37 | #include "rt2x00.h" |
| 38 | #include "rt2x00pci.h" |
| 39 | #include "rt61pci.h" |
| 40 | |
| 41 | /* |
Ivo van Doorn | 008c448 | 2008-08-06 17:27:31 +0200 | [diff] [blame] | 42 | * Allow hardware encryption to be disabled. |
| 43 | */ |
| 44 | static int modparam_nohwcrypt = 0; |
| 45 | module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); |
| 46 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); |
| 47 | |
| 48 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 49 | * Register access. |
| 50 | * BBP and RF register require indirect register access, |
| 51 | * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this. |
| 52 | * These indirect registers work with busy bits, |
| 53 | * and we will try maximal REGISTER_BUSY_COUNT times to access |
| 54 | * the register while taking a REGISTER_BUSY_DELAY us delay |
Thadeu Lima de Souza Cascardo | b34e620 | 2009-11-09 09:45:50 +0100 | [diff] [blame] | 55 | * between each attempt. When the busy bit is still set at that time, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 56 | * the access attempt is considered to have failed, |
| 57 | * and we will print an error. |
| 58 | */ |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 59 | #define WAIT_FOR_BBP(__dev, __reg) \ |
| 60 | rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg)) |
| 61 | #define WAIT_FOR_RF(__dev, __reg) \ |
| 62 | rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg)) |
| 63 | #define WAIT_FOR_MCU(__dev, __reg) \ |
| 64 | rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \ |
| 65 | H2M_MAILBOX_CSR_OWNER, (__reg)) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 66 | |
Adam Baker | 0e14f6d | 2007-10-27 13:41:25 +0200 | [diff] [blame] | 67 | static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 68 | const unsigned int word, const u8 value) |
| 69 | { |
| 70 | u32 reg; |
| 71 | |
Ivo van Doorn | 8ff48a8 | 2008-11-09 23:40:46 +0100 | [diff] [blame] | 72 | mutex_lock(&rt2x00dev->csr_mutex); |
| 73 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 74 | /* |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 75 | * Wait until the BBP becomes available, afterwards we |
| 76 | * can safely write the new data into the register. |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 77 | */ |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 78 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
| 79 | reg = 0; |
| 80 | rt2x00_set_field32(®, PHY_CSR3_VALUE, value); |
| 81 | rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); |
| 82 | rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); |
| 83 | rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 84 | |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 85 | rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg); |
| 86 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 87 | |
Ivo van Doorn | 8ff48a8 | 2008-11-09 23:40:46 +0100 | [diff] [blame] | 88 | mutex_unlock(&rt2x00dev->csr_mutex); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 89 | } |
| 90 | |
Adam Baker | 0e14f6d | 2007-10-27 13:41:25 +0200 | [diff] [blame] | 91 | static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 92 | const unsigned int word, u8 *value) |
| 93 | { |
| 94 | u32 reg; |
| 95 | |
Ivo van Doorn | 8ff48a8 | 2008-11-09 23:40:46 +0100 | [diff] [blame] | 96 | mutex_lock(&rt2x00dev->csr_mutex); |
| 97 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 98 | /* |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 99 | * Wait until the BBP becomes available, afterwards we |
| 100 | * can safely write the read request into the register. |
| 101 | * After the data has been written, we wait until hardware |
| 102 | * returns the correct value, if at any time the register |
| 103 | * doesn't become available in time, reg will be 0xffffffff |
| 104 | * which means we return 0xff to the caller. |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 105 | */ |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 106 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
| 107 | reg = 0; |
| 108 | rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); |
| 109 | rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); |
| 110 | rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 111 | |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 112 | rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 113 | |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 114 | WAIT_FOR_BBP(rt2x00dev, ®); |
| 115 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 116 | |
| 117 | *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 118 | |
Ivo van Doorn | 8ff48a8 | 2008-11-09 23:40:46 +0100 | [diff] [blame] | 119 | mutex_unlock(&rt2x00dev->csr_mutex); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 120 | } |
| 121 | |
Adam Baker | 0e14f6d | 2007-10-27 13:41:25 +0200 | [diff] [blame] | 122 | static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 123 | const unsigned int word, const u32 value) |
| 124 | { |
| 125 | u32 reg; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 126 | |
Ivo van Doorn | 8ff48a8 | 2008-11-09 23:40:46 +0100 | [diff] [blame] | 127 | mutex_lock(&rt2x00dev->csr_mutex); |
| 128 | |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 129 | /* |
| 130 | * Wait until the RF becomes available, afterwards we |
| 131 | * can safely write the new data into the register. |
| 132 | */ |
| 133 | if (WAIT_FOR_RF(rt2x00dev, ®)) { |
| 134 | reg = 0; |
| 135 | rt2x00_set_field32(®, PHY_CSR4_VALUE, value); |
| 136 | rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21); |
| 137 | rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0); |
| 138 | rt2x00_set_field32(®, PHY_CSR4_BUSY, 1); |
| 139 | |
| 140 | rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg); |
| 141 | rt2x00_rf_write(rt2x00dev, word, value); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 142 | } |
| 143 | |
Ivo van Doorn | 8ff48a8 | 2008-11-09 23:40:46 +0100 | [diff] [blame] | 144 | mutex_unlock(&rt2x00dev->csr_mutex); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 145 | } |
| 146 | |
Adam Baker | 0e14f6d | 2007-10-27 13:41:25 +0200 | [diff] [blame] | 147 | static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 148 | const u8 command, const u8 token, |
| 149 | const u8 arg0, const u8 arg1) |
| 150 | { |
| 151 | u32 reg; |
| 152 | |
Ivo van Doorn | 8ff48a8 | 2008-11-09 23:40:46 +0100 | [diff] [blame] | 153 | mutex_lock(&rt2x00dev->csr_mutex); |
| 154 | |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 155 | /* |
| 156 | * Wait until the MCU becomes available, afterwards we |
| 157 | * can safely write the new data into the register. |
| 158 | */ |
| 159 | if (WAIT_FOR_MCU(rt2x00dev, ®)) { |
| 160 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); |
| 161 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); |
| 162 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); |
| 163 | rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); |
| 164 | rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 165 | |
Ivo van Doorn | c9c3b1a | 2008-11-10 19:41:40 +0100 | [diff] [blame] | 166 | rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, ®); |
| 167 | rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); |
| 168 | rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1); |
| 169 | rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg); |
| 170 | } |
Ivo van Doorn | 8ff48a8 | 2008-11-09 23:40:46 +0100 | [diff] [blame] | 171 | |
| 172 | mutex_unlock(&rt2x00dev->csr_mutex); |
| 173 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 174 | } |
| 175 | |
| 176 | static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom) |
| 177 | { |
| 178 | struct rt2x00_dev *rt2x00dev = eeprom->data; |
| 179 | u32 reg; |
| 180 | |
| 181 | rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®); |
| 182 | |
| 183 | eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); |
| 184 | eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); |
| 185 | eeprom->reg_data_clock = |
| 186 | !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK); |
| 187 | eeprom->reg_chip_select = |
| 188 | !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT); |
| 189 | } |
| 190 | |
| 191 | static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom) |
| 192 | { |
| 193 | struct rt2x00_dev *rt2x00dev = eeprom->data; |
| 194 | u32 reg = 0; |
| 195 | |
| 196 | rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in); |
| 197 | rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out); |
| 198 | rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, |
| 199 | !!eeprom->reg_data_clock); |
| 200 | rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT, |
| 201 | !!eeprom->reg_chip_select); |
| 202 | |
| 203 | rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg); |
| 204 | } |
| 205 | |
| 206 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 207 | static const struct rt2x00debug rt61pci_rt2x00debug = { |
| 208 | .owner = THIS_MODULE, |
| 209 | .csr = { |
Ivo van Doorn | 743b97c | 2008-10-29 19:41:03 +0100 | [diff] [blame] | 210 | .read = rt2x00pci_register_read, |
| 211 | .write = rt2x00pci_register_write, |
| 212 | .flags = RT2X00DEBUGFS_OFFSET, |
| 213 | .word_base = CSR_REG_BASE, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 214 | .word_size = sizeof(u32), |
| 215 | .word_count = CSR_REG_SIZE / sizeof(u32), |
| 216 | }, |
| 217 | .eeprom = { |
| 218 | .read = rt2x00_eeprom_read, |
| 219 | .write = rt2x00_eeprom_write, |
Ivo van Doorn | 743b97c | 2008-10-29 19:41:03 +0100 | [diff] [blame] | 220 | .word_base = EEPROM_BASE, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 221 | .word_size = sizeof(u16), |
| 222 | .word_count = EEPROM_SIZE / sizeof(u16), |
| 223 | }, |
| 224 | .bbp = { |
| 225 | .read = rt61pci_bbp_read, |
| 226 | .write = rt61pci_bbp_write, |
Ivo van Doorn | 743b97c | 2008-10-29 19:41:03 +0100 | [diff] [blame] | 227 | .word_base = BBP_BASE, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 228 | .word_size = sizeof(u8), |
| 229 | .word_count = BBP_SIZE / sizeof(u8), |
| 230 | }, |
| 231 | .rf = { |
| 232 | .read = rt2x00_rf_read, |
| 233 | .write = rt61pci_rf_write, |
Ivo van Doorn | 743b97c | 2008-10-29 19:41:03 +0100 | [diff] [blame] | 234 | .word_base = RF_BASE, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 235 | .word_size = sizeof(u32), |
| 236 | .word_count = RF_SIZE / sizeof(u32), |
| 237 | }, |
| 238 | }; |
| 239 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ |
| 240 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 241 | static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) |
| 242 | { |
| 243 | u32 reg; |
| 244 | |
| 245 | rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 246 | return rt2x00_get_field32(reg, MAC_CSR13_BIT5); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 247 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 248 | |
Ivo van Doorn | 771fd56 | 2008-09-08 19:07:15 +0200 | [diff] [blame] | 249 | #ifdef CONFIG_RT2X00_LIB_LEDS |
Ivo van Doorn | a2e1d52 | 2008-03-31 15:53:44 +0200 | [diff] [blame] | 250 | static void rt61pci_brightness_set(struct led_classdev *led_cdev, |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 251 | enum led_brightness brightness) |
| 252 | { |
| 253 | struct rt2x00_led *led = |
| 254 | container_of(led_cdev, struct rt2x00_led, led_dev); |
| 255 | unsigned int enabled = brightness != LED_OFF; |
| 256 | unsigned int a_mode = |
| 257 | (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); |
| 258 | unsigned int bg_mode = |
| 259 | (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); |
| 260 | |
| 261 | if (led->type == LED_TYPE_RADIO) { |
| 262 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, |
| 263 | MCU_LEDCS_RADIO_STATUS, enabled); |
| 264 | |
| 265 | rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, |
| 266 | (led->rt2x00dev->led_mcu_reg & 0xff), |
| 267 | ((led->rt2x00dev->led_mcu_reg >> 8))); |
| 268 | } else if (led->type == LED_TYPE_ASSOC) { |
| 269 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, |
| 270 | MCU_LEDCS_LINK_BG_STATUS, bg_mode); |
| 271 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, |
| 272 | MCU_LEDCS_LINK_A_STATUS, a_mode); |
| 273 | |
| 274 | rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, |
| 275 | (led->rt2x00dev->led_mcu_reg & 0xff), |
| 276 | ((led->rt2x00dev->led_mcu_reg >> 8))); |
| 277 | } else if (led->type == LED_TYPE_QUALITY) { |
| 278 | /* |
| 279 | * The brightness is divided into 6 levels (0 - 5), |
| 280 | * this means we need to convert the brightness |
| 281 | * argument into the matching level within that range. |
| 282 | */ |
| 283 | rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, |
| 284 | brightness / (LED_FULL / 6), 0); |
| 285 | } |
| 286 | } |
Ivo van Doorn | a2e1d52 | 2008-03-31 15:53:44 +0200 | [diff] [blame] | 287 | |
| 288 | static int rt61pci_blink_set(struct led_classdev *led_cdev, |
| 289 | unsigned long *delay_on, |
| 290 | unsigned long *delay_off) |
| 291 | { |
| 292 | struct rt2x00_led *led = |
| 293 | container_of(led_cdev, struct rt2x00_led, led_dev); |
| 294 | u32 reg; |
| 295 | |
| 296 | rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, ®); |
| 297 | rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on); |
| 298 | rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off); |
| 299 | rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg); |
| 300 | |
| 301 | return 0; |
| 302 | } |
Ivo van Doorn | 475433b | 2008-06-03 20:30:01 +0200 | [diff] [blame] | 303 | |
| 304 | static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev, |
| 305 | struct rt2x00_led *led, |
| 306 | enum led_type type) |
| 307 | { |
| 308 | led->rt2x00dev = rt2x00dev; |
| 309 | led->type = type; |
| 310 | led->led_dev.brightness_set = rt61pci_brightness_set; |
| 311 | led->led_dev.blink_set = rt61pci_blink_set; |
| 312 | led->flags = LED_INITIALIZED; |
| 313 | } |
Ivo van Doorn | 771fd56 | 2008-09-08 19:07:15 +0200 | [diff] [blame] | 314 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 315 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 316 | /* |
| 317 | * Configuration handlers. |
| 318 | */ |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 319 | static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev, |
| 320 | struct rt2x00lib_crypto *crypto, |
| 321 | struct ieee80211_key_conf *key) |
| 322 | { |
| 323 | struct hw_key_entry key_entry; |
| 324 | struct rt2x00_field32 field; |
| 325 | u32 mask; |
| 326 | u32 reg; |
| 327 | |
| 328 | if (crypto->cmd == SET_KEY) { |
| 329 | /* |
| 330 | * rt2x00lib can't determine the correct free |
| 331 | * key_idx for shared keys. We have 1 register |
| 332 | * with key valid bits. The goal is simple, read |
| 333 | * the register, if that is full we have no slots |
| 334 | * left. |
| 335 | * Note that each BSS is allowed to have up to 4 |
| 336 | * shared keys, so put a mask over the allowed |
| 337 | * entries. |
| 338 | */ |
| 339 | mask = (0xf << crypto->bssidx); |
| 340 | |
| 341 | rt2x00pci_register_read(rt2x00dev, SEC_CSR0, ®); |
| 342 | reg &= mask; |
| 343 | |
| 344 | if (reg && reg == mask) |
| 345 | return -ENOSPC; |
| 346 | |
Ivo van Doorn | acaf908d | 2008-09-22 19:40:04 +0200 | [diff] [blame] | 347 | key->hw_key_idx += reg ? ffz(reg) : 0; |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 348 | |
| 349 | /* |
| 350 | * Upload key to hardware |
| 351 | */ |
| 352 | memcpy(key_entry.key, crypto->key, |
| 353 | sizeof(key_entry.key)); |
| 354 | memcpy(key_entry.tx_mic, crypto->tx_mic, |
| 355 | sizeof(key_entry.tx_mic)); |
| 356 | memcpy(key_entry.rx_mic, crypto->rx_mic, |
| 357 | sizeof(key_entry.rx_mic)); |
| 358 | |
| 359 | reg = SHARED_KEY_ENTRY(key->hw_key_idx); |
| 360 | rt2x00pci_register_multiwrite(rt2x00dev, reg, |
| 361 | &key_entry, sizeof(key_entry)); |
| 362 | |
| 363 | /* |
| 364 | * The cipher types are stored over 2 registers. |
| 365 | * bssidx 0 and 1 keys are stored in SEC_CSR1 and |
| 366 | * bssidx 1 and 2 keys are stored in SEC_CSR5. |
| 367 | * Using the correct defines correctly will cause overhead, |
| 368 | * so just calculate the correct offset. |
| 369 | */ |
| 370 | if (key->hw_key_idx < 8) { |
| 371 | field.bit_offset = (3 * key->hw_key_idx); |
| 372 | field.bit_mask = 0x7 << field.bit_offset; |
| 373 | |
| 374 | rt2x00pci_register_read(rt2x00dev, SEC_CSR1, ®); |
| 375 | rt2x00_set_field32(®, field, crypto->cipher); |
| 376 | rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg); |
| 377 | } else { |
| 378 | field.bit_offset = (3 * (key->hw_key_idx - 8)); |
| 379 | field.bit_mask = 0x7 << field.bit_offset; |
| 380 | |
| 381 | rt2x00pci_register_read(rt2x00dev, SEC_CSR5, ®); |
| 382 | rt2x00_set_field32(®, field, crypto->cipher); |
| 383 | rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg); |
| 384 | } |
| 385 | |
| 386 | /* |
| 387 | * The driver does not support the IV/EIV generation |
| 388 | * in hardware. However it doesn't support the IV/EIV |
| 389 | * inside the ieee80211 frame either, but requires it |
Thadeu Lima de Souza Cascardo | b34e620 | 2009-11-09 09:45:50 +0100 | [diff] [blame] | 390 | * to be provided separately for the descriptor. |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 391 | * rt2x00lib will cut the IV/EIV data out of all frames |
| 392 | * given to us by mac80211, but we must tell mac80211 |
| 393 | * to generate the IV/EIV data. |
| 394 | */ |
| 395 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; |
| 396 | } |
| 397 | |
| 398 | /* |
| 399 | * SEC_CSR0 contains only single-bit fields to indicate |
| 400 | * a particular key is valid. Because using the FIELD32() |
Thadeu Lima de Souza Cascardo | b34e620 | 2009-11-09 09:45:50 +0100 | [diff] [blame] | 401 | * defines directly will cause a lot of overhead, we use |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 402 | * a calculation to determine the correct bit directly. |
| 403 | */ |
| 404 | mask = 1 << key->hw_key_idx; |
| 405 | |
| 406 | rt2x00pci_register_read(rt2x00dev, SEC_CSR0, ®); |
| 407 | if (crypto->cmd == SET_KEY) |
| 408 | reg |= mask; |
| 409 | else if (crypto->cmd == DISABLE_KEY) |
| 410 | reg &= ~mask; |
| 411 | rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg); |
| 412 | |
| 413 | return 0; |
| 414 | } |
| 415 | |
| 416 | static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev, |
| 417 | struct rt2x00lib_crypto *crypto, |
| 418 | struct ieee80211_key_conf *key) |
| 419 | { |
| 420 | struct hw_pairwise_ta_entry addr_entry; |
| 421 | struct hw_key_entry key_entry; |
| 422 | u32 mask; |
| 423 | u32 reg; |
| 424 | |
| 425 | if (crypto->cmd == SET_KEY) { |
| 426 | /* |
| 427 | * rt2x00lib can't determine the correct free |
| 428 | * key_idx for pairwise keys. We have 2 registers |
Thadeu Lima de Souza Cascardo | b34e620 | 2009-11-09 09:45:50 +0100 | [diff] [blame] | 429 | * with key valid bits. The goal is simple: read |
| 430 | * the first register. If that is full, move to |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 431 | * the next register. |
Thadeu Lima de Souza Cascardo | b34e620 | 2009-11-09 09:45:50 +0100 | [diff] [blame] | 432 | * When both registers are full, we drop the key. |
| 433 | * Otherwise, we use the first invalid entry. |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 434 | */ |
| 435 | rt2x00pci_register_read(rt2x00dev, SEC_CSR2, ®); |
| 436 | if (reg && reg == ~0) { |
| 437 | key->hw_key_idx = 32; |
| 438 | rt2x00pci_register_read(rt2x00dev, SEC_CSR3, ®); |
| 439 | if (reg && reg == ~0) |
| 440 | return -ENOSPC; |
| 441 | } |
| 442 | |
Ivo van Doorn | acaf908d | 2008-09-22 19:40:04 +0200 | [diff] [blame] | 443 | key->hw_key_idx += reg ? ffz(reg) : 0; |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 444 | |
| 445 | /* |
| 446 | * Upload key to hardware |
| 447 | */ |
| 448 | memcpy(key_entry.key, crypto->key, |
| 449 | sizeof(key_entry.key)); |
| 450 | memcpy(key_entry.tx_mic, crypto->tx_mic, |
| 451 | sizeof(key_entry.tx_mic)); |
| 452 | memcpy(key_entry.rx_mic, crypto->rx_mic, |
| 453 | sizeof(key_entry.rx_mic)); |
| 454 | |
| 455 | memset(&addr_entry, 0, sizeof(addr_entry)); |
| 456 | memcpy(&addr_entry, crypto->address, ETH_ALEN); |
| 457 | addr_entry.cipher = crypto->cipher; |
| 458 | |
| 459 | reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx); |
| 460 | rt2x00pci_register_multiwrite(rt2x00dev, reg, |
| 461 | &key_entry, sizeof(key_entry)); |
| 462 | |
| 463 | reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); |
| 464 | rt2x00pci_register_multiwrite(rt2x00dev, reg, |
| 465 | &addr_entry, sizeof(addr_entry)); |
| 466 | |
| 467 | /* |
Thadeu Lima de Souza Cascardo | b34e620 | 2009-11-09 09:45:50 +0100 | [diff] [blame] | 468 | * Enable pairwise lookup table for given BSS idx. |
| 469 | * Without this, received frames will not be decrypted |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 470 | * by the hardware. |
| 471 | */ |
| 472 | rt2x00pci_register_read(rt2x00dev, SEC_CSR4, ®); |
| 473 | reg |= (1 << crypto->bssidx); |
| 474 | rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg); |
| 475 | |
| 476 | /* |
| 477 | * The driver does not support the IV/EIV generation |
| 478 | * in hardware. However it doesn't support the IV/EIV |
| 479 | * inside the ieee80211 frame either, but requires it |
Daniel Mack | 3ad2f3f | 2010-02-03 08:01:28 +0800 | [diff] [blame] | 480 | * to be provided separately for the descriptor. |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 481 | * rt2x00lib will cut the IV/EIV data out of all frames |
| 482 | * given to us by mac80211, but we must tell mac80211 |
| 483 | * to generate the IV/EIV data. |
| 484 | */ |
| 485 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; |
| 486 | } |
| 487 | |
| 488 | /* |
| 489 | * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate |
| 490 | * a particular key is valid. Because using the FIELD32() |
Thadeu Lima de Souza Cascardo | b34e620 | 2009-11-09 09:45:50 +0100 | [diff] [blame] | 491 | * defines directly will cause a lot of overhead, we use |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 492 | * a calculation to determine the correct bit directly. |
| 493 | */ |
| 494 | if (key->hw_key_idx < 32) { |
| 495 | mask = 1 << key->hw_key_idx; |
| 496 | |
| 497 | rt2x00pci_register_read(rt2x00dev, SEC_CSR2, ®); |
| 498 | if (crypto->cmd == SET_KEY) |
| 499 | reg |= mask; |
| 500 | else if (crypto->cmd == DISABLE_KEY) |
| 501 | reg &= ~mask; |
| 502 | rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg); |
| 503 | } else { |
| 504 | mask = 1 << (key->hw_key_idx - 32); |
| 505 | |
| 506 | rt2x00pci_register_read(rt2x00dev, SEC_CSR3, ®); |
| 507 | if (crypto->cmd == SET_KEY) |
| 508 | reg |= mask; |
| 509 | else if (crypto->cmd == DISABLE_KEY) |
| 510 | reg &= ~mask; |
| 511 | rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg); |
| 512 | } |
| 513 | |
| 514 | return 0; |
| 515 | } |
| 516 | |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 517 | static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev, |
| 518 | const unsigned int filter_flags) |
| 519 | { |
| 520 | u32 reg; |
| 521 | |
| 522 | /* |
| 523 | * Start configuration steps. |
| 524 | * Note that the version error will always be dropped |
| 525 | * and broadcast frames will always be accepted since |
| 526 | * there is no filter for it at this time. |
| 527 | */ |
| 528 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®); |
| 529 | rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC, |
| 530 | !(filter_flags & FIF_FCSFAIL)); |
| 531 | rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL, |
| 532 | !(filter_flags & FIF_PLCPFAIL)); |
| 533 | rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL, |
Igor Perminov | 1afcfd54 | 2009-08-08 23:55:55 +0200 | [diff] [blame] | 534 | !(filter_flags & (FIF_CONTROL | FIF_PSPOLL))); |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 535 | rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME, |
| 536 | !(filter_flags & FIF_PROMISC_IN_BSS)); |
| 537 | rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS, |
Ivo van Doorn | e0b005f | 2008-03-31 15:24:53 +0200 | [diff] [blame] | 538 | !(filter_flags & FIF_PROMISC_IN_BSS) && |
| 539 | !rt2x00dev->intf_ap_count); |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 540 | rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1); |
| 541 | rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST, |
| 542 | !(filter_flags & FIF_ALLMULTI)); |
| 543 | rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0); |
| 544 | rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, |
| 545 | !(filter_flags & FIF_CONTROL)); |
| 546 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); |
| 547 | } |
| 548 | |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 549 | static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev, |
| 550 | struct rt2x00_intf *intf, |
| 551 | struct rt2x00intf_conf *conf, |
| 552 | const unsigned int flags) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 553 | { |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 554 | unsigned int beacon_base; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 555 | u32 reg; |
| 556 | |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 557 | if (flags & CONFIG_UPDATE_TYPE) { |
| 558 | /* |
| 559 | * Clear current synchronisation setup. |
Thadeu Lima de Souza Cascardo | b34e620 | 2009-11-09 09:45:50 +0100 | [diff] [blame] | 560 | * For the Beacon base registers, we only need to clear |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 561 | * the first byte since that byte contains the VALID and OWNER |
| 562 | * bits which (when set to 0) will invalidate the entire beacon. |
| 563 | */ |
| 564 | beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx); |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 565 | rt2x00pci_register_write(rt2x00dev, beacon_base, 0); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 566 | |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 567 | /* |
| 568 | * Enable synchronisation. |
| 569 | */ |
| 570 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®); |
Ivo van Doorn | fd3c91c | 2008-03-09 22:47:43 +0100 | [diff] [blame] | 571 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 572 | rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync); |
Ivo van Doorn | fd3c91c | 2008-03-09 22:47:43 +0100 | [diff] [blame] | 573 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 574 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); |
| 575 | } |
| 576 | |
| 577 | if (flags & CONFIG_UPDATE_MAC) { |
| 578 | reg = le32_to_cpu(conf->mac[1]); |
| 579 | rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); |
| 580 | conf->mac[1] = cpu_to_le32(reg); |
| 581 | |
| 582 | rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, |
| 583 | conf->mac, sizeof(conf->mac)); |
| 584 | } |
| 585 | |
| 586 | if (flags & CONFIG_UPDATE_BSSID) { |
| 587 | reg = le32_to_cpu(conf->bssid[1]); |
| 588 | rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3); |
| 589 | conf->bssid[1] = cpu_to_le32(reg); |
| 590 | |
| 591 | rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, |
| 592 | conf->bssid, sizeof(conf->bssid)); |
| 593 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 594 | } |
| 595 | |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 596 | static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev, |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 597 | struct rt2x00lib_erp *erp, |
| 598 | u32 changed) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 599 | { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 600 | u32 reg; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 601 | |
| 602 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®); |
Ivo van Doorn | 4789666 | 2009-09-06 15:14:23 +0200 | [diff] [blame] | 603 | rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32); |
Ivo van Doorn | 8a566af | 2009-05-21 19:16:46 +0200 | [diff] [blame] | 604 | rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 605 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); |
| 606 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 607 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
| 608 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®); |
| 609 | rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1); |
| 610 | rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, |
| 611 | !!erp->short_preamble); |
| 612 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg); |
| 613 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 614 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 615 | if (changed & BSS_CHANGED_BASIC_RATES) |
| 616 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, |
| 617 | erp->basic_rates); |
Ivo van Doorn | ba2ab47 | 2008-08-06 16:22:17 +0200 | [diff] [blame] | 618 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 619 | if (changed & BSS_CHANGED_BEACON_INT) { |
| 620 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®); |
| 621 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, |
| 622 | erp->beacon_int * 16); |
| 623 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); |
| 624 | } |
Ivo van Doorn | 8a566af | 2009-05-21 19:16:46 +0200 | [diff] [blame] | 625 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 626 | if (changed & BSS_CHANGED_ERP_SLOT) { |
| 627 | rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®); |
| 628 | rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time); |
| 629 | rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg); |
Ivo van Doorn | ba2ab47 | 2008-08-06 16:22:17 +0200 | [diff] [blame] | 630 | |
Helmut Schaa | 0204464 | 2010-09-08 20:56:32 +0200 | [diff] [blame^] | 631 | rt2x00pci_register_read(rt2x00dev, MAC_CSR8, ®); |
| 632 | rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs); |
| 633 | rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); |
| 634 | rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs); |
| 635 | rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg); |
| 636 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 637 | } |
| 638 | |
| 639 | static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | addc81b | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 640 | struct antenna_setup *ant) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 641 | { |
| 642 | u8 r3; |
| 643 | u8 r4; |
| 644 | u8 r77; |
| 645 | |
| 646 | rt61pci_bbp_read(rt2x00dev, 3, &r3); |
| 647 | rt61pci_bbp_read(rt2x00dev, 4, &r4); |
| 648 | rt61pci_bbp_read(rt2x00dev, 77, &r77); |
| 649 | |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 650 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325)); |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 651 | |
| 652 | /* |
| 653 | * Configure the RX antenna. |
| 654 | */ |
Ivo van Doorn | addc81b | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 655 | switch (ant->rx) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 656 | case ANTENNA_HW_DIVERSITY: |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 657 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 658 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 659 | (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 660 | break; |
| 661 | case ANTENNA_A: |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 662 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 663 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 664 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 665 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); |
| 666 | else |
| 667 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 668 | break; |
| 669 | case ANTENNA_B: |
Ivo van Doorn | a4fe07d | 2008-03-09 22:45:21 +0100 | [diff] [blame] | 670 | default: |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 671 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 672 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 673 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 674 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); |
| 675 | else |
| 676 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 677 | break; |
| 678 | } |
| 679 | |
| 680 | rt61pci_bbp_write(rt2x00dev, 77, r77); |
| 681 | rt61pci_bbp_write(rt2x00dev, 3, r3); |
| 682 | rt61pci_bbp_write(rt2x00dev, 4, r4); |
| 683 | } |
| 684 | |
| 685 | static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | addc81b | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 686 | struct antenna_setup *ant) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 687 | { |
| 688 | u8 r3; |
| 689 | u8 r4; |
| 690 | u8 r77; |
| 691 | |
| 692 | rt61pci_bbp_read(rt2x00dev, 3, &r3); |
| 693 | rt61pci_bbp_read(rt2x00dev, 4, &r4); |
| 694 | rt61pci_bbp_read(rt2x00dev, 77, &r77); |
| 695 | |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 696 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 697 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, |
| 698 | !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)); |
| 699 | |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 700 | /* |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 701 | * Configure the RX antenna. |
| 702 | */ |
Ivo van Doorn | addc81b | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 703 | switch (ant->rx) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 704 | case ANTENNA_HW_DIVERSITY: |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 705 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 706 | break; |
| 707 | case ANTENNA_A: |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 708 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
| 709 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 710 | break; |
| 711 | case ANTENNA_B: |
Ivo van Doorn | a4fe07d | 2008-03-09 22:45:21 +0100 | [diff] [blame] | 712 | default: |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 713 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
| 714 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 715 | break; |
| 716 | } |
| 717 | |
| 718 | rt61pci_bbp_write(rt2x00dev, 77, r77); |
| 719 | rt61pci_bbp_write(rt2x00dev, 3, r3); |
| 720 | rt61pci_bbp_write(rt2x00dev, 4, r4); |
| 721 | } |
| 722 | |
| 723 | static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev, |
| 724 | const int p1, const int p2) |
| 725 | { |
| 726 | u32 reg; |
| 727 | |
| 728 | rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®); |
| 729 | |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 730 | rt2x00_set_field32(®, MAC_CSR13_BIT4, p1); |
| 731 | rt2x00_set_field32(®, MAC_CSR13_BIT12, 0); |
| 732 | |
| 733 | rt2x00_set_field32(®, MAC_CSR13_BIT3, !p2); |
| 734 | rt2x00_set_field32(®, MAC_CSR13_BIT11, 0); |
| 735 | |
| 736 | rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 737 | } |
| 738 | |
| 739 | static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | addc81b | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 740 | struct antenna_setup *ant) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 741 | { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 742 | u8 r3; |
| 743 | u8 r4; |
| 744 | u8 r77; |
| 745 | |
| 746 | rt61pci_bbp_read(rt2x00dev, 3, &r3); |
| 747 | rt61pci_bbp_read(rt2x00dev, 4, &r4); |
| 748 | rt61pci_bbp_read(rt2x00dev, 77, &r77); |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 749 | |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 750 | /* |
| 751 | * Configure the RX antenna. |
| 752 | */ |
| 753 | switch (ant->rx) { |
| 754 | case ANTENNA_A: |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 755 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
| 756 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); |
| 757 | rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0); |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 758 | break; |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 759 | case ANTENNA_HW_DIVERSITY: |
| 760 | /* |
Ivo van Doorn | a4fe07d | 2008-03-09 22:45:21 +0100 | [diff] [blame] | 761 | * FIXME: Antenna selection for the rf 2529 is very confusing |
| 762 | * in the legacy driver. Just default to antenna B until the |
| 763 | * legacy code can be properly translated into rt2x00 code. |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 764 | */ |
| 765 | case ANTENNA_B: |
Ivo van Doorn | a4fe07d | 2008-03-09 22:45:21 +0100 | [diff] [blame] | 766 | default: |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 767 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
| 768 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); |
| 769 | rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1); |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 770 | break; |
| 771 | } |
| 772 | |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 773 | rt61pci_bbp_write(rt2x00dev, 77, r77); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 774 | rt61pci_bbp_write(rt2x00dev, 3, r3); |
| 775 | rt61pci_bbp_write(rt2x00dev, 4, r4); |
| 776 | } |
| 777 | |
| 778 | struct antenna_sel { |
| 779 | u8 word; |
| 780 | /* |
| 781 | * value[0] -> non-LNA |
| 782 | * value[1] -> LNA |
| 783 | */ |
| 784 | u8 value[2]; |
| 785 | }; |
| 786 | |
| 787 | static const struct antenna_sel antenna_sel_a[] = { |
| 788 | { 96, { 0x58, 0x78 } }, |
| 789 | { 104, { 0x38, 0x48 } }, |
| 790 | { 75, { 0xfe, 0x80 } }, |
| 791 | { 86, { 0xfe, 0x80 } }, |
| 792 | { 88, { 0xfe, 0x80 } }, |
| 793 | { 35, { 0x60, 0x60 } }, |
| 794 | { 97, { 0x58, 0x58 } }, |
| 795 | { 98, { 0x58, 0x58 } }, |
| 796 | }; |
| 797 | |
| 798 | static const struct antenna_sel antenna_sel_bg[] = { |
| 799 | { 96, { 0x48, 0x68 } }, |
| 800 | { 104, { 0x2c, 0x3c } }, |
| 801 | { 75, { 0xfe, 0x80 } }, |
| 802 | { 86, { 0xfe, 0x80 } }, |
| 803 | { 88, { 0xfe, 0x80 } }, |
| 804 | { 35, { 0x50, 0x50 } }, |
| 805 | { 97, { 0x48, 0x48 } }, |
| 806 | { 98, { 0x48, 0x48 } }, |
| 807 | }; |
| 808 | |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 809 | static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev, |
| 810 | struct antenna_setup *ant) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 811 | { |
| 812 | const struct antenna_sel *sel; |
| 813 | unsigned int lna; |
| 814 | unsigned int i; |
| 815 | u32 reg; |
| 816 | |
Ivo van Doorn | a4fe07d | 2008-03-09 22:45:21 +0100 | [diff] [blame] | 817 | /* |
| 818 | * We should never come here because rt2x00lib is supposed |
| 819 | * to catch this and send us the correct antenna explicitely. |
| 820 | */ |
| 821 | BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY || |
| 822 | ant->tx == ANTENNA_SW_DIVERSITY); |
| 823 | |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 824 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 825 | sel = antenna_sel_a; |
| 826 | lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 827 | } else { |
| 828 | sel = antenna_sel_bg; |
| 829 | lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 830 | } |
| 831 | |
Mattias Nissler | acaa410 | 2007-10-27 13:41:53 +0200 | [diff] [blame] | 832 | for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) |
| 833 | rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); |
| 834 | |
| 835 | rt2x00pci_register_read(rt2x00dev, PHY_CSR0, ®); |
| 836 | |
Ivo van Doorn | ddc827f | 2007-10-13 16:26:42 +0200 | [diff] [blame] | 837 | rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 838 | rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); |
Ivo van Doorn | ddc827f | 2007-10-13 16:26:42 +0200 | [diff] [blame] | 839 | rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, |
Johannes Berg | 8318d78 | 2008-01-24 19:38:38 +0100 | [diff] [blame] | 840 | rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); |
Ivo van Doorn | ddc827f | 2007-10-13 16:26:42 +0200 | [diff] [blame] | 841 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 842 | rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg); |
| 843 | |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 844 | if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) |
Ivo van Doorn | addc81b | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 845 | rt61pci_config_antenna_5x(rt2x00dev, ant); |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 846 | else if (rt2x00_rf(rt2x00dev, RF2527)) |
Ivo van Doorn | addc81b | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 847 | rt61pci_config_antenna_2x(rt2x00dev, ant); |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 848 | else if (rt2x00_rf(rt2x00dev, RF2529)) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 849 | if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) |
Ivo van Doorn | addc81b | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 850 | rt61pci_config_antenna_2x(rt2x00dev, ant); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 851 | else |
Ivo van Doorn | addc81b | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 852 | rt61pci_config_antenna_2529(rt2x00dev, ant); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 853 | } |
| 854 | } |
| 855 | |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 856 | static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev, |
| 857 | struct rt2x00lib_conf *libconf) |
| 858 | { |
| 859 | u16 eeprom; |
| 860 | short lna_gain = 0; |
| 861 | |
| 862 | if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) { |
| 863 | if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) |
| 864 | lna_gain += 14; |
| 865 | |
| 866 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom); |
| 867 | lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1); |
| 868 | } else { |
| 869 | if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) |
| 870 | lna_gain += 14; |
| 871 | |
| 872 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom); |
| 873 | lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1); |
| 874 | } |
| 875 | |
| 876 | rt2x00dev->lna_gain = lna_gain; |
| 877 | } |
| 878 | |
| 879 | static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev, |
| 880 | struct rf_channel *rf, const int txpower) |
| 881 | { |
| 882 | u8 r3; |
| 883 | u8 r94; |
| 884 | u8 smart; |
| 885 | |
| 886 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); |
| 887 | rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); |
| 888 | |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 889 | smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527)); |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 890 | |
| 891 | rt61pci_bbp_read(rt2x00dev, 3, &r3); |
| 892 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart); |
| 893 | rt61pci_bbp_write(rt2x00dev, 3, r3); |
| 894 | |
| 895 | r94 = 6; |
| 896 | if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94)) |
| 897 | r94 += txpower - MAX_TXPOWER; |
| 898 | else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94)) |
| 899 | r94 += txpower; |
| 900 | rt61pci_bbp_write(rt2x00dev, 94, r94); |
| 901 | |
| 902 | rt61pci_rf_write(rt2x00dev, 1, rf->rf1); |
| 903 | rt61pci_rf_write(rt2x00dev, 2, rf->rf2); |
| 904 | rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); |
| 905 | rt61pci_rf_write(rt2x00dev, 4, rf->rf4); |
| 906 | |
| 907 | udelay(200); |
| 908 | |
| 909 | rt61pci_rf_write(rt2x00dev, 1, rf->rf1); |
| 910 | rt61pci_rf_write(rt2x00dev, 2, rf->rf2); |
| 911 | rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); |
| 912 | rt61pci_rf_write(rt2x00dev, 4, rf->rf4); |
| 913 | |
| 914 | udelay(200); |
| 915 | |
| 916 | rt61pci_rf_write(rt2x00dev, 1, rf->rf1); |
| 917 | rt61pci_rf_write(rt2x00dev, 2, rf->rf2); |
| 918 | rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); |
| 919 | rt61pci_rf_write(rt2x00dev, 4, rf->rf4); |
| 920 | |
| 921 | msleep(1); |
| 922 | } |
| 923 | |
| 924 | static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev, |
| 925 | const int txpower) |
| 926 | { |
| 927 | struct rf_channel rf; |
| 928 | |
| 929 | rt2x00_rf_read(rt2x00dev, 1, &rf.rf1); |
| 930 | rt2x00_rf_read(rt2x00dev, 2, &rf.rf2); |
| 931 | rt2x00_rf_read(rt2x00dev, 3, &rf.rf3); |
| 932 | rt2x00_rf_read(rt2x00dev, 4, &rf.rf4); |
| 933 | |
| 934 | rt61pci_config_channel(rt2x00dev, &rf, txpower); |
| 935 | } |
| 936 | |
| 937 | static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 938 | struct rt2x00lib_conf *libconf) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 939 | { |
| 940 | u32 reg; |
| 941 | |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 942 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®); |
Ivo van Doorn | e1b4d7b | 2010-06-14 22:12:54 +0200 | [diff] [blame] | 943 | rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1); |
| 944 | rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_STEP, 0); |
| 945 | rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0); |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 946 | rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, |
| 947 | libconf->conf->long_frame_max_tx_count); |
| 948 | rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, |
| 949 | libconf->conf->short_frame_max_tx_count); |
| 950 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg); |
| 951 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 952 | |
Ivo van Doorn | 7d7f19c | 2008-12-20 10:52:42 +0100 | [diff] [blame] | 953 | static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev, |
| 954 | struct rt2x00lib_conf *libconf) |
| 955 | { |
| 956 | enum dev_state state = |
| 957 | (libconf->conf->flags & IEEE80211_CONF_PS) ? |
| 958 | STATE_SLEEP : STATE_AWAKE; |
| 959 | u32 reg; |
| 960 | |
| 961 | if (state == STATE_SLEEP) { |
| 962 | rt2x00pci_register_read(rt2x00dev, MAC_CSR11, ®); |
| 963 | rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, |
Ivo van Doorn | 6b347bf | 2009-05-23 21:09:28 +0200 | [diff] [blame] | 964 | rt2x00dev->beacon_int - 10); |
Ivo van Doorn | 7d7f19c | 2008-12-20 10:52:42 +0100 | [diff] [blame] | 965 | rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, |
| 966 | libconf->conf->listen_interval - 1); |
| 967 | rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 5); |
| 968 | |
| 969 | /* We must first disable autowake before it can be enabled */ |
| 970 | rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); |
| 971 | rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg); |
| 972 | |
| 973 | rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 1); |
| 974 | rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg); |
| 975 | |
| 976 | rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005); |
| 977 | rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c); |
| 978 | rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060); |
| 979 | |
| 980 | rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0); |
| 981 | } else { |
| 982 | rt2x00pci_register_read(rt2x00dev, MAC_CSR11, ®); |
| 983 | rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 0); |
| 984 | rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0); |
| 985 | rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); |
| 986 | rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 0); |
| 987 | rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg); |
| 988 | |
| 989 | rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007); |
| 990 | rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018); |
| 991 | rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020); |
| 992 | |
| 993 | rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0); |
| 994 | } |
| 995 | } |
| 996 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 997 | static void rt61pci_config(struct rt2x00_dev *rt2x00dev, |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 998 | struct rt2x00lib_conf *libconf, |
| 999 | const unsigned int flags) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1000 | { |
Ivo van Doorn | ba2ab47 | 2008-08-06 16:22:17 +0200 | [diff] [blame] | 1001 | /* Always recalculate LNA gain before changing configuration */ |
| 1002 | rt61pci_config_lna_gain(rt2x00dev, libconf); |
| 1003 | |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 1004 | if (flags & IEEE80211_CONF_CHANGE_CHANNEL) |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 1005 | rt61pci_config_channel(rt2x00dev, &libconf->rf, |
| 1006 | libconf->conf->power_level); |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 1007 | if ((flags & IEEE80211_CONF_CHANGE_POWER) && |
| 1008 | !(flags & IEEE80211_CONF_CHANGE_CHANNEL)) |
Ivo van Doorn | 5c58ee5 | 2007-10-06 13:34:52 +0200 | [diff] [blame] | 1009 | rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level); |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 1010 | if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) |
| 1011 | rt61pci_config_retry_limit(rt2x00dev, libconf); |
Ivo van Doorn | 7d7f19c | 2008-12-20 10:52:42 +0100 | [diff] [blame] | 1012 | if (flags & IEEE80211_CONF_CHANGE_PS) |
| 1013 | rt61pci_config_ps(rt2x00dev, libconf); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1014 | } |
| 1015 | |
| 1016 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1017 | * Link tuning |
| 1018 | */ |
Ivo van Doorn | ebcf26d | 2007-10-13 16:26:12 +0200 | [diff] [blame] | 1019 | static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev, |
| 1020 | struct link_qual *qual) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1021 | { |
| 1022 | u32 reg; |
| 1023 | |
| 1024 | /* |
| 1025 | * Update FCS error count from register. |
| 1026 | */ |
| 1027 | rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®); |
Ivo van Doorn | ebcf26d | 2007-10-13 16:26:12 +0200 | [diff] [blame] | 1028 | qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1029 | |
| 1030 | /* |
| 1031 | * Update False CCA count from register. |
| 1032 | */ |
| 1033 | rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®); |
Ivo van Doorn | ebcf26d | 2007-10-13 16:26:12 +0200 | [diff] [blame] | 1034 | qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1035 | } |
| 1036 | |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 1037 | static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev, |
| 1038 | struct link_qual *qual, u8 vgc_level) |
Ivo van Doorn | eb20b4e | 2008-12-20 10:54:22 +0100 | [diff] [blame] | 1039 | { |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 1040 | if (qual->vgc_level != vgc_level) { |
Ivo van Doorn | eb20b4e | 2008-12-20 10:54:22 +0100 | [diff] [blame] | 1041 | rt61pci_bbp_write(rt2x00dev, 17, vgc_level); |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 1042 | qual->vgc_level = vgc_level; |
| 1043 | qual->vgc_level_reg = vgc_level; |
Ivo van Doorn | eb20b4e | 2008-12-20 10:54:22 +0100 | [diff] [blame] | 1044 | } |
| 1045 | } |
| 1046 | |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 1047 | static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev, |
| 1048 | struct link_qual *qual) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1049 | { |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 1050 | rt61pci_set_vgc(rt2x00dev, qual, 0x20); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1051 | } |
| 1052 | |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 1053 | static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev, |
| 1054 | struct link_qual *qual, const u32 count) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1055 | { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1056 | u8 up_bound; |
| 1057 | u8 low_bound; |
| 1058 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1059 | /* |
| 1060 | * Determine r17 bounds. |
| 1061 | */ |
Ivo van Doorn | e5ef5ba | 2010-08-06 20:49:27 +0200 | [diff] [blame] | 1062 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1063 | low_bound = 0x28; |
| 1064 | up_bound = 0x48; |
| 1065 | if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) { |
| 1066 | low_bound += 0x10; |
| 1067 | up_bound += 0x10; |
| 1068 | } |
| 1069 | } else { |
| 1070 | low_bound = 0x20; |
| 1071 | up_bound = 0x40; |
| 1072 | if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) { |
| 1073 | low_bound += 0x10; |
| 1074 | up_bound += 0x10; |
| 1075 | } |
| 1076 | } |
| 1077 | |
| 1078 | /* |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 1079 | * If we are not associated, we should go straight to the |
| 1080 | * dynamic CCA tuning. |
| 1081 | */ |
| 1082 | if (!rt2x00dev->intf_associated) |
| 1083 | goto dynamic_cca_tune; |
| 1084 | |
| 1085 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1086 | * Special big-R17 for very short distance |
| 1087 | */ |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 1088 | if (qual->rssi >= -35) { |
| 1089 | rt61pci_set_vgc(rt2x00dev, qual, 0x60); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1090 | return; |
| 1091 | } |
| 1092 | |
| 1093 | /* |
| 1094 | * Special big-R17 for short distance |
| 1095 | */ |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 1096 | if (qual->rssi >= -58) { |
| 1097 | rt61pci_set_vgc(rt2x00dev, qual, up_bound); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1098 | return; |
| 1099 | } |
| 1100 | |
| 1101 | /* |
| 1102 | * Special big-R17 for middle-short distance |
| 1103 | */ |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 1104 | if (qual->rssi >= -66) { |
| 1105 | rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1106 | return; |
| 1107 | } |
| 1108 | |
| 1109 | /* |
| 1110 | * Special mid-R17 for middle distance |
| 1111 | */ |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 1112 | if (qual->rssi >= -74) { |
| 1113 | rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1114 | return; |
| 1115 | } |
| 1116 | |
| 1117 | /* |
| 1118 | * Special case: Change up_bound based on the rssi. |
| 1119 | * Lower up_bound when rssi is weaker then -74 dBm. |
| 1120 | */ |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 1121 | up_bound -= 2 * (-74 - qual->rssi); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1122 | if (low_bound > up_bound) |
| 1123 | up_bound = low_bound; |
| 1124 | |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 1125 | if (qual->vgc_level > up_bound) { |
| 1126 | rt61pci_set_vgc(rt2x00dev, qual, up_bound); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1127 | return; |
| 1128 | } |
| 1129 | |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 1130 | dynamic_cca_tune: |
| 1131 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1132 | /* |
| 1133 | * r17 does not yet exceed upper limit, continue and base |
| 1134 | * the r17 tuning on the false CCA count. |
| 1135 | */ |
Ivo van Doorn | 5352ff6 | 2008-12-20 10:54:54 +0100 | [diff] [blame] | 1136 | if ((qual->false_cca > 512) && (qual->vgc_level < up_bound)) |
| 1137 | rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level); |
| 1138 | else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound)) |
| 1139 | rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1140 | } |
| 1141 | |
| 1142 | /* |
Ivo van Doorn | a7f3a06 | 2008-03-09 22:44:54 +0100 | [diff] [blame] | 1143 | * Firmware functions |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1144 | */ |
| 1145 | static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev) |
| 1146 | { |
Gertjan van Wingerde | 49e721e | 2010-02-13 20:55:49 +0100 | [diff] [blame] | 1147 | u16 chip; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1148 | char *fw_name; |
| 1149 | |
Gertjan van Wingerde | 49e721e | 2010-02-13 20:55:49 +0100 | [diff] [blame] | 1150 | pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip); |
| 1151 | switch (chip) { |
| 1152 | case RT2561_PCI_ID: |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1153 | fw_name = FIRMWARE_RT2561; |
| 1154 | break; |
Gertjan van Wingerde | 49e721e | 2010-02-13 20:55:49 +0100 | [diff] [blame] | 1155 | case RT2561s_PCI_ID: |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1156 | fw_name = FIRMWARE_RT2561s; |
| 1157 | break; |
Gertjan van Wingerde | 49e721e | 2010-02-13 20:55:49 +0100 | [diff] [blame] | 1158 | case RT2661_PCI_ID: |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1159 | fw_name = FIRMWARE_RT2661; |
| 1160 | break; |
| 1161 | default: |
| 1162 | fw_name = NULL; |
| 1163 | break; |
| 1164 | } |
| 1165 | |
| 1166 | return fw_name; |
| 1167 | } |
| 1168 | |
Ivo van Doorn | 0cbe006 | 2009-01-28 00:33:47 +0100 | [diff] [blame] | 1169 | static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev, |
| 1170 | const u8 *data, const size_t len) |
Ivo van Doorn | a7f3a06 | 2008-03-09 22:44:54 +0100 | [diff] [blame] | 1171 | { |
Ivo van Doorn | 0cbe006 | 2009-01-28 00:33:47 +0100 | [diff] [blame] | 1172 | u16 fw_crc; |
Ivo van Doorn | a7f3a06 | 2008-03-09 22:44:54 +0100 | [diff] [blame] | 1173 | u16 crc; |
| 1174 | |
| 1175 | /* |
Ivo van Doorn | 0cbe006 | 2009-01-28 00:33:47 +0100 | [diff] [blame] | 1176 | * Only support 8kb firmware files. |
| 1177 | */ |
| 1178 | if (len != 8192) |
| 1179 | return FW_BAD_LENGTH; |
| 1180 | |
| 1181 | /* |
Thadeu Lima de Souza Cascardo | b34e620 | 2009-11-09 09:45:50 +0100 | [diff] [blame] | 1182 | * The last 2 bytes in the firmware array are the crc checksum itself. |
| 1183 | * This means that we should never pass those 2 bytes to the crc |
Ivo van Doorn | a7f3a06 | 2008-03-09 22:44:54 +0100 | [diff] [blame] | 1184 | * algorithm. |
| 1185 | */ |
Ivo van Doorn | 0cbe006 | 2009-01-28 00:33:47 +0100 | [diff] [blame] | 1186 | fw_crc = (data[len - 2] << 8 | data[len - 1]); |
| 1187 | |
| 1188 | /* |
| 1189 | * Use the crc itu-t algorithm. |
| 1190 | */ |
Ivo van Doorn | a7f3a06 | 2008-03-09 22:44:54 +0100 | [diff] [blame] | 1191 | crc = crc_itu_t(0, data, len - 2); |
| 1192 | crc = crc_itu_t_byte(crc, 0); |
| 1193 | crc = crc_itu_t_byte(crc, 0); |
| 1194 | |
Ivo van Doorn | 0cbe006 | 2009-01-28 00:33:47 +0100 | [diff] [blame] | 1195 | return (fw_crc == crc) ? FW_OK : FW_BAD_CRC; |
Ivo van Doorn | a7f3a06 | 2008-03-09 22:44:54 +0100 | [diff] [blame] | 1196 | } |
| 1197 | |
Ivo van Doorn | 0cbe006 | 2009-01-28 00:33:47 +0100 | [diff] [blame] | 1198 | static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, |
| 1199 | const u8 *data, const size_t len) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1200 | { |
| 1201 | int i; |
| 1202 | u32 reg; |
| 1203 | |
| 1204 | /* |
| 1205 | * Wait for stable hardware. |
| 1206 | */ |
| 1207 | for (i = 0; i < 100; i++) { |
| 1208 | rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®); |
| 1209 | if (reg) |
| 1210 | break; |
| 1211 | msleep(1); |
| 1212 | } |
| 1213 | |
| 1214 | if (!reg) { |
| 1215 | ERROR(rt2x00dev, "Unstable hardware.\n"); |
| 1216 | return -EBUSY; |
| 1217 | } |
| 1218 | |
| 1219 | /* |
| 1220 | * Prepare MCU and mailbox for firmware loading. |
| 1221 | */ |
| 1222 | reg = 0; |
| 1223 | rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); |
| 1224 | rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg); |
| 1225 | rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); |
| 1226 | rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); |
| 1227 | rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0); |
| 1228 | |
| 1229 | /* |
| 1230 | * Write firmware to device. |
| 1231 | */ |
| 1232 | reg = 0; |
| 1233 | rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); |
| 1234 | rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1); |
| 1235 | rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg); |
| 1236 | |
| 1237 | rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, |
| 1238 | data, len); |
| 1239 | |
| 1240 | rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0); |
| 1241 | rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg); |
| 1242 | |
| 1243 | rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0); |
| 1244 | rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg); |
| 1245 | |
| 1246 | for (i = 0; i < 100; i++) { |
| 1247 | rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, ®); |
| 1248 | if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY)) |
| 1249 | break; |
| 1250 | msleep(1); |
| 1251 | } |
| 1252 | |
| 1253 | if (i == 100) { |
| 1254 | ERROR(rt2x00dev, "MCU Control register not ready.\n"); |
| 1255 | return -EBUSY; |
| 1256 | } |
| 1257 | |
| 1258 | /* |
Ivo van Doorn | e6d3e90 | 2008-07-27 15:06:50 +0200 | [diff] [blame] | 1259 | * Hardware needs another millisecond before it is ready. |
| 1260 | */ |
| 1261 | msleep(1); |
| 1262 | |
| 1263 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1264 | * Reset MAC and BBP registers. |
| 1265 | */ |
| 1266 | reg = 0; |
| 1267 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); |
| 1268 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); |
| 1269 | rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); |
| 1270 | |
| 1271 | rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®); |
| 1272 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); |
| 1273 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); |
| 1274 | rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); |
| 1275 | |
| 1276 | rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®); |
| 1277 | rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); |
| 1278 | rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); |
| 1279 | |
| 1280 | return 0; |
| 1281 | } |
| 1282 | |
Ivo van Doorn | a7f3a06 | 2008-03-09 22:44:54 +0100 | [diff] [blame] | 1283 | /* |
| 1284 | * Initialization functions. |
| 1285 | */ |
Ivo van Doorn | 798b7ad | 2008-11-08 15:25:33 +0100 | [diff] [blame] | 1286 | static bool rt61pci_get_entry_state(struct queue_entry *entry) |
| 1287 | { |
| 1288 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
| 1289 | u32 word; |
| 1290 | |
| 1291 | if (entry->queue->qid == QID_RX) { |
| 1292 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
| 1293 | |
| 1294 | return rt2x00_get_field32(word, RXD_W0_OWNER_NIC); |
| 1295 | } else { |
| 1296 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
| 1297 | |
| 1298 | return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || |
| 1299 | rt2x00_get_field32(word, TXD_W0_VALID)); |
| 1300 | } |
| 1301 | } |
| 1302 | |
| 1303 | static void rt61pci_clear_entry(struct queue_entry *entry) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1304 | { |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1305 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
Gertjan van Wingerde | c4da004 | 2008-06-16 19:56:31 +0200 | [diff] [blame] | 1306 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1307 | u32 word; |
| 1308 | |
Ivo van Doorn | 798b7ad | 2008-11-08 15:25:33 +0100 | [diff] [blame] | 1309 | if (entry->queue->qid == QID_RX) { |
| 1310 | rt2x00_desc_read(entry_priv->desc, 5, &word); |
| 1311 | rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, |
| 1312 | skbdesc->skb_dma); |
| 1313 | rt2x00_desc_write(entry_priv->desc, 5, word); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1314 | |
Ivo van Doorn | 798b7ad | 2008-11-08 15:25:33 +0100 | [diff] [blame] | 1315 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
| 1316 | rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); |
| 1317 | rt2x00_desc_write(entry_priv->desc, 0, word); |
| 1318 | } else { |
| 1319 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
| 1320 | rt2x00_set_field32(&word, TXD_W0_VALID, 0); |
| 1321 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); |
| 1322 | rt2x00_desc_write(entry_priv->desc, 0, word); |
| 1323 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1324 | } |
| 1325 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1326 | static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1327 | { |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1328 | struct queue_entry_priv_pci *entry_priv; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1329 | u32 reg; |
| 1330 | |
| 1331 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1332 | * Initialize registers. |
| 1333 | */ |
| 1334 | rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, ®); |
| 1335 | rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1336 | rt2x00dev->tx[0].limit); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1337 | rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1338 | rt2x00dev->tx[1].limit); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1339 | rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1340 | rt2x00dev->tx[2].limit); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1341 | rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1342 | rt2x00dev->tx[3].limit); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1343 | rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg); |
| 1344 | |
| 1345 | rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, ®); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1346 | rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1347 | rt2x00dev->tx[0].desc_size / 4); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1348 | rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg); |
| 1349 | |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1350 | entry_priv = rt2x00dev->tx[0].entries[0].priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1351 | rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, ®); |
Ivo van Doorn | 30b3a23 | 2008-02-17 17:33:24 +0100 | [diff] [blame] | 1352 | rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1353 | entry_priv->desc_dma); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1354 | rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg); |
| 1355 | |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1356 | entry_priv = rt2x00dev->tx[1].entries[0].priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1357 | rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, ®); |
Ivo van Doorn | 30b3a23 | 2008-02-17 17:33:24 +0100 | [diff] [blame] | 1358 | rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1359 | entry_priv->desc_dma); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1360 | rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg); |
| 1361 | |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1362 | entry_priv = rt2x00dev->tx[2].entries[0].priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1363 | rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, ®); |
Ivo van Doorn | 30b3a23 | 2008-02-17 17:33:24 +0100 | [diff] [blame] | 1364 | rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1365 | entry_priv->desc_dma); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1366 | rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg); |
| 1367 | |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1368 | entry_priv = rt2x00dev->tx[3].entries[0].priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1369 | rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, ®); |
Ivo van Doorn | 30b3a23 | 2008-02-17 17:33:24 +0100 | [diff] [blame] | 1370 | rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1371 | entry_priv->desc_dma); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1372 | rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg); |
| 1373 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1374 | rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, ®); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1375 | rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1376 | rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE, |
| 1377 | rt2x00dev->rx->desc_size / 4); |
| 1378 | rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4); |
| 1379 | rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg); |
| 1380 | |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1381 | entry_priv = rt2x00dev->rx->entries[0].priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1382 | rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, ®); |
Ivo van Doorn | 30b3a23 | 2008-02-17 17:33:24 +0100 | [diff] [blame] | 1383 | rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1384 | entry_priv->desc_dma); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1385 | rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg); |
| 1386 | |
| 1387 | rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, ®); |
| 1388 | rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2); |
| 1389 | rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2); |
| 1390 | rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2); |
| 1391 | rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1392 | rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg); |
| 1393 | |
| 1394 | rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®); |
| 1395 | rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1); |
| 1396 | rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1); |
| 1397 | rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1); |
| 1398 | rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1399 | rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg); |
| 1400 | |
| 1401 | rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®); |
| 1402 | rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1); |
| 1403 | rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg); |
| 1404 | |
| 1405 | return 0; |
| 1406 | } |
| 1407 | |
| 1408 | static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev) |
| 1409 | { |
| 1410 | u32 reg; |
| 1411 | |
| 1412 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®); |
| 1413 | rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1); |
| 1414 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); |
| 1415 | rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0); |
| 1416 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); |
| 1417 | |
| 1418 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, ®); |
| 1419 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ |
| 1420 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1); |
| 1421 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ |
| 1422 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1); |
| 1423 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ |
| 1424 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1); |
| 1425 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ |
| 1426 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1); |
| 1427 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg); |
| 1428 | |
| 1429 | /* |
| 1430 | * CCK TXD BBP registers |
| 1431 | */ |
| 1432 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, ®); |
| 1433 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13); |
| 1434 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1); |
| 1435 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12); |
| 1436 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1); |
| 1437 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11); |
| 1438 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1); |
| 1439 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10); |
| 1440 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1); |
| 1441 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg); |
| 1442 | |
| 1443 | /* |
| 1444 | * OFDM TXD BBP registers |
| 1445 | */ |
| 1446 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, ®); |
| 1447 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7); |
| 1448 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1); |
| 1449 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6); |
| 1450 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1); |
| 1451 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5); |
| 1452 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1); |
| 1453 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg); |
| 1454 | |
| 1455 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, ®); |
| 1456 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59); |
| 1457 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53); |
| 1458 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49); |
| 1459 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46); |
| 1460 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg); |
| 1461 | |
| 1462 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, ®); |
| 1463 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44); |
| 1464 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42); |
| 1465 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42); |
| 1466 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42); |
| 1467 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg); |
| 1468 | |
Ivo van Doorn | 1f90916 | 2008-07-08 13:45:20 +0200 | [diff] [blame] | 1469 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®); |
| 1470 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0); |
| 1471 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); |
| 1472 | rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0); |
| 1473 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); |
| 1474 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); |
| 1475 | rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); |
| 1476 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); |
| 1477 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1478 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); |
| 1479 | |
| 1480 | rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff); |
| 1481 | |
| 1482 | rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®); |
| 1483 | rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0); |
| 1484 | rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg); |
| 1485 | |
| 1486 | rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c); |
| 1487 | |
| 1488 | if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) |
| 1489 | return -EBUSY; |
| 1490 | |
| 1491 | rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000); |
| 1492 | |
| 1493 | /* |
| 1494 | * Invalidate all Shared Keys (SEC_CSR0), |
| 1495 | * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5) |
| 1496 | */ |
| 1497 | rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000); |
| 1498 | rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000); |
| 1499 | rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000); |
| 1500 | |
| 1501 | rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0); |
| 1502 | rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c); |
| 1503 | rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606); |
| 1504 | rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08); |
| 1505 | |
| 1506 | rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404); |
| 1507 | |
| 1508 | rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200); |
| 1509 | |
| 1510 | rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); |
| 1511 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1512 | /* |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 1513 | * Clear all beacons |
| 1514 | * For the Beacon base registers we only need to clear |
| 1515 | * the first byte since that byte contains the VALID and OWNER |
| 1516 | * bits which (when set to 0) will invalidate the entire beacon. |
| 1517 | */ |
| 1518 | rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0); |
| 1519 | rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0); |
| 1520 | rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0); |
| 1521 | rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0); |
| 1522 | |
| 1523 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1524 | * We must clear the error counters. |
| 1525 | * These registers are cleared on read, |
| 1526 | * so we may pass a useless variable to store the value. |
| 1527 | */ |
| 1528 | rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®); |
| 1529 | rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®); |
| 1530 | rt2x00pci_register_read(rt2x00dev, STA_CSR2, ®); |
| 1531 | |
| 1532 | /* |
| 1533 | * Reset MAC and BBP registers. |
| 1534 | */ |
| 1535 | rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®); |
| 1536 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); |
| 1537 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); |
| 1538 | rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); |
| 1539 | |
| 1540 | rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®); |
| 1541 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); |
| 1542 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); |
| 1543 | rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); |
| 1544 | |
| 1545 | rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®); |
| 1546 | rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); |
| 1547 | rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg); |
| 1548 | |
| 1549 | return 0; |
| 1550 | } |
| 1551 | |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 1552 | static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) |
| 1553 | { |
| 1554 | unsigned int i; |
| 1555 | u8 value; |
| 1556 | |
| 1557 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
| 1558 | rt61pci_bbp_read(rt2x00dev, 0, &value); |
| 1559 | if ((value != 0xff) && (value != 0x00)) |
| 1560 | return 0; |
| 1561 | udelay(REGISTER_BUSY_DELAY); |
| 1562 | } |
| 1563 | |
| 1564 | ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); |
| 1565 | return -EACCES; |
| 1566 | } |
| 1567 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1568 | static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev) |
| 1569 | { |
| 1570 | unsigned int i; |
| 1571 | u16 eeprom; |
| 1572 | u8 reg_id; |
| 1573 | u8 value; |
| 1574 | |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 1575 | if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev))) |
| 1576 | return -EACCES; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1577 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1578 | rt61pci_bbp_write(rt2x00dev, 3, 0x00); |
| 1579 | rt61pci_bbp_write(rt2x00dev, 15, 0x30); |
| 1580 | rt61pci_bbp_write(rt2x00dev, 21, 0xc8); |
| 1581 | rt61pci_bbp_write(rt2x00dev, 22, 0x38); |
| 1582 | rt61pci_bbp_write(rt2x00dev, 23, 0x06); |
| 1583 | rt61pci_bbp_write(rt2x00dev, 24, 0xfe); |
| 1584 | rt61pci_bbp_write(rt2x00dev, 25, 0x0a); |
| 1585 | rt61pci_bbp_write(rt2x00dev, 26, 0x0d); |
| 1586 | rt61pci_bbp_write(rt2x00dev, 34, 0x12); |
| 1587 | rt61pci_bbp_write(rt2x00dev, 37, 0x07); |
| 1588 | rt61pci_bbp_write(rt2x00dev, 39, 0xf8); |
| 1589 | rt61pci_bbp_write(rt2x00dev, 41, 0x60); |
| 1590 | rt61pci_bbp_write(rt2x00dev, 53, 0x10); |
| 1591 | rt61pci_bbp_write(rt2x00dev, 54, 0x18); |
| 1592 | rt61pci_bbp_write(rt2x00dev, 60, 0x10); |
| 1593 | rt61pci_bbp_write(rt2x00dev, 61, 0x04); |
| 1594 | rt61pci_bbp_write(rt2x00dev, 62, 0x04); |
| 1595 | rt61pci_bbp_write(rt2x00dev, 75, 0xfe); |
| 1596 | rt61pci_bbp_write(rt2x00dev, 86, 0xfe); |
| 1597 | rt61pci_bbp_write(rt2x00dev, 88, 0xfe); |
| 1598 | rt61pci_bbp_write(rt2x00dev, 90, 0x0f); |
| 1599 | rt61pci_bbp_write(rt2x00dev, 99, 0x00); |
| 1600 | rt61pci_bbp_write(rt2x00dev, 102, 0x16); |
| 1601 | rt61pci_bbp_write(rt2x00dev, 107, 0x04); |
| 1602 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1603 | for (i = 0; i < EEPROM_BBP_SIZE; i++) { |
| 1604 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); |
| 1605 | |
| 1606 | if (eeprom != 0xffff && eeprom != 0x0000) { |
| 1607 | reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); |
| 1608 | value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1609 | rt61pci_bbp_write(rt2x00dev, reg_id, value); |
| 1610 | } |
| 1611 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1612 | |
| 1613 | return 0; |
| 1614 | } |
| 1615 | |
| 1616 | /* |
| 1617 | * Device state switch handlers. |
| 1618 | */ |
| 1619 | static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev, |
| 1620 | enum dev_state state) |
| 1621 | { |
| 1622 | u32 reg; |
| 1623 | |
| 1624 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®); |
| 1625 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 1626 | (state == STATE_RADIO_RX_OFF) || |
| 1627 | (state == STATE_RADIO_RX_OFF_LINK)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1628 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); |
| 1629 | } |
| 1630 | |
| 1631 | static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev, |
| 1632 | enum dev_state state) |
| 1633 | { |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 1634 | int mask = (state == STATE_RADIO_IRQ_OFF) || |
| 1635 | (state == STATE_RADIO_IRQ_OFF_ISR); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1636 | u32 reg; |
| 1637 | |
| 1638 | /* |
| 1639 | * When interrupts are being enabled, the interrupt registers |
| 1640 | * should clear the register to assure a clean state. |
| 1641 | */ |
| 1642 | if (state == STATE_RADIO_IRQ_ON) { |
| 1643 | rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®); |
| 1644 | rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); |
| 1645 | |
| 1646 | rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®); |
| 1647 | rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg); |
| 1648 | } |
| 1649 | |
| 1650 | /* |
| 1651 | * Only toggle the interrupts bits we are going to use. |
| 1652 | * Non-checked interrupt bits are disabled by default. |
| 1653 | */ |
| 1654 | rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®); |
| 1655 | rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask); |
| 1656 | rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask); |
| 1657 | rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask); |
| 1658 | rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff); |
| 1659 | rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg); |
| 1660 | |
| 1661 | rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); |
| 1662 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask); |
| 1663 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask); |
| 1664 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask); |
| 1665 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask); |
| 1666 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask); |
| 1667 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask); |
| 1668 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask); |
| 1669 | rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask); |
| 1670 | rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); |
| 1671 | } |
| 1672 | |
| 1673 | static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev) |
| 1674 | { |
| 1675 | u32 reg; |
| 1676 | |
| 1677 | /* |
| 1678 | * Initialize all registers. |
| 1679 | */ |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 1680 | if (unlikely(rt61pci_init_queues(rt2x00dev) || |
| 1681 | rt61pci_init_registers(rt2x00dev) || |
| 1682 | rt61pci_init_bbp(rt2x00dev))) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1683 | return -EIO; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1684 | |
| 1685 | /* |
| 1686 | * Enable RX. |
| 1687 | */ |
| 1688 | rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®); |
| 1689 | rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1); |
| 1690 | rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg); |
| 1691 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1692 | return 0; |
| 1693 | } |
| 1694 | |
| 1695 | static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev) |
| 1696 | { |
Ivo van Doorn | a2c9b65 | 2009-01-28 00:32:33 +0100 | [diff] [blame] | 1697 | /* |
| 1698 | * Disable power |
| 1699 | */ |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1700 | rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1701 | } |
| 1702 | |
| 1703 | static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) |
| 1704 | { |
Gertjan van Wingerde | 9655a6e | 2010-05-13 21:16:03 +0200 | [diff] [blame] | 1705 | u32 reg, reg2; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1706 | unsigned int i; |
| 1707 | char put_to_sleep; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1708 | |
| 1709 | put_to_sleep = (state != STATE_AWAKE); |
| 1710 | |
| 1711 | rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®); |
| 1712 | rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); |
| 1713 | rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); |
| 1714 | rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg); |
| 1715 | |
| 1716 | /* |
| 1717 | * Device is not guaranteed to be in the requested state yet. |
| 1718 | * We must wait until the register indicates that the |
| 1719 | * device has entered the correct state. |
| 1720 | */ |
| 1721 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
Gertjan van Wingerde | 9655a6e | 2010-05-13 21:16:03 +0200 | [diff] [blame] | 1722 | rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®2); |
| 1723 | state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE); |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 1724 | if (state == !put_to_sleep) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1725 | return 0; |
Gertjan van Wingerde | 9655a6e | 2010-05-13 21:16:03 +0200 | [diff] [blame] | 1726 | rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1727 | msleep(10); |
| 1728 | } |
| 1729 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1730 | return -EBUSY; |
| 1731 | } |
| 1732 | |
| 1733 | static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev, |
| 1734 | enum dev_state state) |
| 1735 | { |
| 1736 | int retval = 0; |
| 1737 | |
| 1738 | switch (state) { |
| 1739 | case STATE_RADIO_ON: |
| 1740 | retval = rt61pci_enable_radio(rt2x00dev); |
| 1741 | break; |
| 1742 | case STATE_RADIO_OFF: |
| 1743 | rt61pci_disable_radio(rt2x00dev); |
| 1744 | break; |
| 1745 | case STATE_RADIO_RX_ON: |
Ivo van Doorn | 61667d8 | 2008-02-25 23:15:05 +0100 | [diff] [blame] | 1746 | case STATE_RADIO_RX_ON_LINK: |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1747 | case STATE_RADIO_RX_OFF: |
Ivo van Doorn | 61667d8 | 2008-02-25 23:15:05 +0100 | [diff] [blame] | 1748 | case STATE_RADIO_RX_OFF_LINK: |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 1749 | rt61pci_toggle_rx(rt2x00dev, state); |
| 1750 | break; |
| 1751 | case STATE_RADIO_IRQ_ON: |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 1752 | case STATE_RADIO_IRQ_ON_ISR: |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 1753 | case STATE_RADIO_IRQ_OFF: |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 1754 | case STATE_RADIO_IRQ_OFF_ISR: |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 1755 | rt61pci_toggle_irq(rt2x00dev, state); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1756 | break; |
| 1757 | case STATE_DEEP_SLEEP: |
| 1758 | case STATE_SLEEP: |
| 1759 | case STATE_STANDBY: |
| 1760 | case STATE_AWAKE: |
| 1761 | retval = rt61pci_set_state(rt2x00dev, state); |
| 1762 | break; |
| 1763 | default: |
| 1764 | retval = -ENOTSUPP; |
| 1765 | break; |
| 1766 | } |
| 1767 | |
Ivo van Doorn | 2b08da3 | 2008-06-03 18:58:56 +0200 | [diff] [blame] | 1768 | if (unlikely(retval)) |
| 1769 | ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n", |
| 1770 | state, retval); |
| 1771 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1772 | return retval; |
| 1773 | } |
| 1774 | |
| 1775 | /* |
| 1776 | * TX descriptor initialization |
| 1777 | */ |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1778 | static void rt61pci_write_tx_desc(struct queue_entry *entry, |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 1779 | struct txentry_desc *txdesc) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1780 | { |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1781 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
| 1782 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
Gertjan van Wingerde | 85b7a8b | 2010-05-11 23:51:40 +0200 | [diff] [blame] | 1783 | __le32 *txd = entry_priv->desc; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1784 | u32 word; |
| 1785 | |
| 1786 | /* |
| 1787 | * Start writing the descriptor words. |
| 1788 | */ |
| 1789 | rt2x00_desc_read(txd, 1, &word); |
Helmut Schaa | a908a74 | 2010-08-30 21:12:24 +0200 | [diff] [blame] | 1790 | rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->qid); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1791 | rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs); |
| 1792 | rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min); |
| 1793 | rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max); |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 1794 | rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset); |
Ivo van Doorn | 5adf6d6 | 2008-07-20 18:03:38 +0200 | [diff] [blame] | 1795 | rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, |
| 1796 | test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); |
Gertjan van Wingerde | 4de36fe | 2008-05-10 13:44:14 +0200 | [diff] [blame] | 1797 | rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1798 | rt2x00_desc_write(txd, 1, word); |
| 1799 | |
| 1800 | rt2x00_desc_read(txd, 2, &word); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1801 | rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal); |
| 1802 | rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service); |
| 1803 | rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low); |
| 1804 | rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1805 | rt2x00_desc_write(txd, 2, word); |
| 1806 | |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 1807 | if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) { |
Ivo van Doorn | 1ce9cda | 2008-12-02 18:19:48 +0100 | [diff] [blame] | 1808 | _rt2x00_desc_write(txd, 3, skbdesc->iv[0]); |
| 1809 | _rt2x00_desc_write(txd, 4, skbdesc->iv[1]); |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 1810 | } |
| 1811 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1812 | rt2x00_desc_read(txd, 5, &word); |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1813 | rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid); |
Gertjan van Wingerde | 4de36fe | 2008-05-10 13:44:14 +0200 | [diff] [blame] | 1814 | rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, |
| 1815 | skbdesc->entry->entry_idx); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1816 | rt2x00_set_field32(&word, TXD_W5_TX_POWER, |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1817 | TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1818 | rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); |
| 1819 | rt2x00_desc_write(txd, 5, word); |
| 1820 | |
Helmut Schaa | a908a74 | 2010-08-30 21:12:24 +0200 | [diff] [blame] | 1821 | if (txdesc->qid != QID_BEACON) { |
Gertjan van Wingerde | 6b97cb0 | 2010-05-11 23:51:38 +0200 | [diff] [blame] | 1822 | rt2x00_desc_read(txd, 6, &word); |
| 1823 | rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, |
| 1824 | skbdesc->skb_dma); |
| 1825 | rt2x00_desc_write(txd, 6, word); |
Gertjan van Wingerde | 4de36fe | 2008-05-10 13:44:14 +0200 | [diff] [blame] | 1826 | |
Adam Baker | d7bafff | 2008-02-03 15:46:24 +0100 | [diff] [blame] | 1827 | rt2x00_desc_read(txd, 11, &word); |
Gertjan van Wingerde | df624ca | 2010-05-03 22:43:05 +0200 | [diff] [blame] | 1828 | rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, |
| 1829 | txdesc->length); |
Adam Baker | d7bafff | 2008-02-03 15:46:24 +0100 | [diff] [blame] | 1830 | rt2x00_desc_write(txd, 11, word); |
| 1831 | } |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1832 | |
Gertjan van Wingerde | e01f1ec | 2010-05-11 23:51:39 +0200 | [diff] [blame] | 1833 | /* |
| 1834 | * Writing TXD word 0 must the last to prevent a race condition with |
| 1835 | * the device, whereby the device may take hold of the TXD before we |
| 1836 | * finished updating it. |
| 1837 | */ |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1838 | rt2x00_desc_read(txd, 0, &word); |
| 1839 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); |
| 1840 | rt2x00_set_field32(&word, TXD_W0_VALID, 1); |
| 1841 | rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1842 | test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1843 | rt2x00_set_field32(&word, TXD_W0_ACK, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1844 | test_bit(ENTRY_TXD_ACK, &txdesc->flags)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1845 | rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1846 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1847 | rt2x00_set_field32(&word, TXD_W0_OFDM, |
Ivo van Doorn | 076f958 | 2008-12-20 10:59:02 +0100 | [diff] [blame] | 1848 | (txdesc->rate_mode == RATE_MODE_OFDM)); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1849 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1850 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, |
Ivo van Doorn | 61486e0 | 2008-05-10 13:42:31 +0200 | [diff] [blame] | 1851 | test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 1852 | rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, |
| 1853 | test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags)); |
| 1854 | rt2x00_set_field32(&word, TXD_W0_KEY_TABLE, |
| 1855 | test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags)); |
| 1856 | rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx); |
Gertjan van Wingerde | df624ca | 2010-05-03 22:43:05 +0200 | [diff] [blame] | 1857 | rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1858 | rt2x00_set_field32(&word, TXD_W0_BURST, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1859 | test_bit(ENTRY_TXD_BURST, &txdesc->flags)); |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 1860 | rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1861 | rt2x00_desc_write(txd, 0, word); |
Gertjan van Wingerde | 85b7a8b | 2010-05-11 23:51:40 +0200 | [diff] [blame] | 1862 | |
| 1863 | /* |
| 1864 | * Register descriptor details in skb frame descriptor. |
| 1865 | */ |
| 1866 | skbdesc->desc = txd; |
| 1867 | skbdesc->desc_len = |
Helmut Schaa | a908a74 | 2010-08-30 21:12:24 +0200 | [diff] [blame] | 1868 | (txdesc->qid == QID_BEACON) ? TXINFO_SIZE : TXD_DESC_SIZE; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1869 | } |
| 1870 | |
| 1871 | /* |
| 1872 | * TX data initialization |
| 1873 | */ |
Gertjan van Wingerde | f224f4e | 2010-05-08 23:40:25 +0200 | [diff] [blame] | 1874 | static void rt61pci_write_beacon(struct queue_entry *entry, |
| 1875 | struct txentry_desc *txdesc) |
Ivo van Doorn | bd88a78 | 2008-07-09 15:12:44 +0200 | [diff] [blame] | 1876 | { |
| 1877 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
Gertjan van Wingerde | 85b7a8b | 2010-05-11 23:51:40 +0200 | [diff] [blame] | 1878 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
Ivo van Doorn | bd88a78 | 2008-07-09 15:12:44 +0200 | [diff] [blame] | 1879 | unsigned int beacon_base; |
| 1880 | u32 reg; |
| 1881 | |
| 1882 | /* |
| 1883 | * Disable beaconing while we are reloading the beacon data, |
| 1884 | * otherwise we might be sending out invalid data. |
| 1885 | */ |
| 1886 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®); |
Ivo van Doorn | bd88a78 | 2008-07-09 15:12:44 +0200 | [diff] [blame] | 1887 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); |
| 1888 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); |
| 1889 | |
| 1890 | /* |
Gertjan van Wingerde | 5c3b685 | 2010-06-03 10:51:41 +0200 | [diff] [blame] | 1891 | * Write the TX descriptor for the beacon. |
| 1892 | */ |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1893 | rt61pci_write_tx_desc(entry, txdesc); |
Gertjan van Wingerde | 5c3b685 | 2010-06-03 10:51:41 +0200 | [diff] [blame] | 1894 | |
| 1895 | /* |
| 1896 | * Dump beacon to userspace through debugfs. |
| 1897 | */ |
| 1898 | rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); |
| 1899 | |
| 1900 | /* |
Ivo van Doorn | bd88a78 | 2008-07-09 15:12:44 +0200 | [diff] [blame] | 1901 | * Write entire beacon with descriptor to register. |
| 1902 | */ |
| 1903 | beacon_base = HW_BEACON_OFFSET(entry->entry_idx); |
Gertjan van Wingerde | 85b7a8b | 2010-05-11 23:51:40 +0200 | [diff] [blame] | 1904 | rt2x00pci_register_multiwrite(rt2x00dev, beacon_base, |
| 1905 | entry_priv->desc, TXINFO_SIZE); |
| 1906 | rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE, |
Ivo van Doorn | bd88a78 | 2008-07-09 15:12:44 +0200 | [diff] [blame] | 1907 | entry->skb->data, entry->skb->len); |
| 1908 | |
| 1909 | /* |
Gertjan van Wingerde | d61cb26 | 2010-05-08 23:40:24 +0200 | [diff] [blame] | 1910 | * Enable beaconing again. |
| 1911 | * |
| 1912 | * For Wi-Fi faily generated beacons between participating |
| 1913 | * stations. Set TBTT phase adaptive adjustment step to 8us. |
| 1914 | */ |
| 1915 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); |
| 1916 | |
| 1917 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); |
| 1918 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); |
| 1919 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); |
| 1920 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); |
| 1921 | |
| 1922 | /* |
Ivo van Doorn | bd88a78 | 2008-07-09 15:12:44 +0200 | [diff] [blame] | 1923 | * Clean up beacon skb. |
| 1924 | */ |
| 1925 | dev_kfree_skb_any(entry->skb); |
| 1926 | entry->skb = NULL; |
| 1927 | } |
| 1928 | |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1929 | static void rt61pci_kick_tx_queue(struct data_queue *queue) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1930 | { |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1931 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1932 | u32 reg; |
| 1933 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1934 | rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®); |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1935 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, (queue->qid == QID_AC_BE)); |
| 1936 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, (queue->qid == QID_AC_BK)); |
| 1937 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, (queue->qid == QID_AC_VI)); |
| 1938 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, (queue->qid == QID_AC_VO)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1939 | rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); |
| 1940 | } |
| 1941 | |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1942 | static void rt61pci_kill_tx_queue(struct data_queue *queue) |
Ivo van Doorn | a2c9b65 | 2009-01-28 00:32:33 +0100 | [diff] [blame] | 1943 | { |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1944 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; |
Ivo van Doorn | a2c9b65 | 2009-01-28 00:32:33 +0100 | [diff] [blame] | 1945 | u32 reg; |
| 1946 | |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1947 | if (queue->qid == QID_BEACON) { |
Ivo van Doorn | a2c9b65 | 2009-01-28 00:32:33 +0100 | [diff] [blame] | 1948 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0); |
| 1949 | return; |
| 1950 | } |
| 1951 | |
| 1952 | rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®); |
Ivo van Doorn | 9333145 | 2010-08-23 19:53:39 +0200 | [diff] [blame] | 1953 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, (queue->qid == QID_AC_BE)); |
| 1954 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, (queue->qid == QID_AC_BK)); |
| 1955 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, (queue->qid == QID_AC_VI)); |
| 1956 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, (queue->qid == QID_AC_VO)); |
Ivo van Doorn | a2c9b65 | 2009-01-28 00:32:33 +0100 | [diff] [blame] | 1957 | rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); |
| 1958 | } |
| 1959 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1960 | /* |
| 1961 | * RX control handlers |
| 1962 | */ |
| 1963 | static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1) |
| 1964 | { |
Ivo van Doorn | ba2ab47 | 2008-08-06 16:22:17 +0200 | [diff] [blame] | 1965 | u8 offset = rt2x00dev->lna_gain; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1966 | u8 lna; |
| 1967 | |
| 1968 | lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA); |
| 1969 | switch (lna) { |
| 1970 | case 3: |
Ivo van Doorn | ba2ab47 | 2008-08-06 16:22:17 +0200 | [diff] [blame] | 1971 | offset += 90; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1972 | break; |
| 1973 | case 2: |
Ivo van Doorn | ba2ab47 | 2008-08-06 16:22:17 +0200 | [diff] [blame] | 1974 | offset += 74; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1975 | break; |
| 1976 | case 1: |
Ivo van Doorn | ba2ab47 | 2008-08-06 16:22:17 +0200 | [diff] [blame] | 1977 | offset += 64; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1978 | break; |
| 1979 | default: |
| 1980 | return 0; |
| 1981 | } |
| 1982 | |
Ivo van Doorn | e5ef5ba | 2010-08-06 20:49:27 +0200 | [diff] [blame] | 1983 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1984 | if (lna == 3 || lna == 2) |
| 1985 | offset += 10; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1986 | } |
| 1987 | |
| 1988 | return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset; |
| 1989 | } |
| 1990 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 1991 | static void rt61pci_fill_rxdone(struct queue_entry *entry, |
John Daiker | 5588751 | 2008-10-17 12:16:17 -0700 | [diff] [blame] | 1992 | struct rxdone_entry_desc *rxdesc) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1993 | { |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 1994 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1995 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 1996 | u32 word0; |
| 1997 | u32 word1; |
| 1998 | |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 1999 | rt2x00_desc_read(entry_priv->desc, 0, &word0); |
| 2000 | rt2x00_desc_read(entry_priv->desc, 1, &word1); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2001 | |
Johannes Berg | 4150c57 | 2007-09-17 01:29:23 -0400 | [diff] [blame] | 2002 | if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2003 | rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2004 | |
Gertjan van Wingerde | 78b8f3b | 2010-05-08 23:40:20 +0200 | [diff] [blame] | 2005 | rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG); |
| 2006 | rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR); |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 2007 | |
| 2008 | if (rxdesc->cipher != CIPHER_NONE) { |
Ivo van Doorn | 1ce9cda | 2008-12-02 18:19:48 +0100 | [diff] [blame] | 2009 | _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]); |
| 2010 | _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]); |
Ivo van Doorn | 74415ed | 2008-12-02 22:50:33 +0100 | [diff] [blame] | 2011 | rxdesc->dev_flags |= RXDONE_CRYPTO_IV; |
| 2012 | |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 2013 | _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv); |
Ivo van Doorn | 74415ed | 2008-12-02 22:50:33 +0100 | [diff] [blame] | 2014 | rxdesc->dev_flags |= RXDONE_CRYPTO_ICV; |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 2015 | |
| 2016 | /* |
| 2017 | * Hardware has stripped IV/EIV data from 802.11 frame during |
Thadeu Lima de Souza Cascardo | b34e620 | 2009-11-09 09:45:50 +0100 | [diff] [blame] | 2018 | * decryption. It has provided the data separately but rt2x00lib |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 2019 | * should decide if it should be reinserted. |
| 2020 | */ |
| 2021 | rxdesc->flags |= RX_FLAG_IV_STRIPPED; |
| 2022 | |
| 2023 | /* |
| 2024 | * FIXME: Legacy driver indicates that the frame does |
| 2025 | * contain the Michael Mic. Unfortunately, in rt2x00 |
| 2026 | * the MIC seems to be missing completely... |
| 2027 | */ |
| 2028 | rxdesc->flags |= RX_FLAG_MMIC_STRIPPED; |
| 2029 | |
| 2030 | if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS) |
| 2031 | rxdesc->flags |= RX_FLAG_DECRYPTED; |
| 2032 | else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC) |
| 2033 | rxdesc->flags |= RX_FLAG_MMIC_ERROR; |
| 2034 | } |
| 2035 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2036 | /* |
| 2037 | * Obtain the status about this packet. |
Ivo van Doorn | 8999389 | 2008-03-09 22:49:04 +0100 | [diff] [blame] | 2038 | * When frame was received with an OFDM bitrate, |
| 2039 | * the signal is the PLCP value. If it was received with |
| 2040 | * a CCK bitrate the signal is the rate in 100kbit/s. |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2041 | */ |
Ivo van Doorn | 8999389 | 2008-03-09 22:49:04 +0100 | [diff] [blame] | 2042 | rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL); |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 2043 | rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2044 | rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); |
Ivo van Doorn | 19d30e0 | 2008-03-15 21:38:07 +0100 | [diff] [blame] | 2045 | |
Ivo van Doorn | 19d30e0 | 2008-03-15 21:38:07 +0100 | [diff] [blame] | 2046 | if (rt2x00_get_field32(word0, RXD_W0_OFDM)) |
| 2047 | rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; |
Ivo van Doorn | 6c6aa3c | 2008-08-29 21:07:16 +0200 | [diff] [blame] | 2048 | else |
| 2049 | rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE; |
Ivo van Doorn | 19d30e0 | 2008-03-15 21:38:07 +0100 | [diff] [blame] | 2050 | if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) |
| 2051 | rxdesc->dev_flags |= RXDONE_MY_BSS; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2052 | } |
| 2053 | |
| 2054 | /* |
| 2055 | * Interrupt functions. |
| 2056 | */ |
| 2057 | static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev) |
| 2058 | { |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2059 | struct data_queue *queue; |
| 2060 | struct queue_entry *entry; |
| 2061 | struct queue_entry *entry_done; |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 2062 | struct queue_entry_priv_pci *entry_priv; |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2063 | struct txdone_entry_desc txdesc; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2064 | u32 word; |
| 2065 | u32 reg; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2066 | int type; |
| 2067 | int index; |
Ivo van Doorn | e6474c3 | 2010-06-14 22:13:37 +0200 | [diff] [blame] | 2068 | int i; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2069 | |
| 2070 | /* |
Ivo van Doorn | e6474c3 | 2010-06-14 22:13:37 +0200 | [diff] [blame] | 2071 | * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO |
| 2072 | * at most X times and also stop processing once the TX_STA_FIFO_VALID |
| 2073 | * flag is not set anymore. |
| 2074 | * |
| 2075 | * The legacy drivers use X=TX_RING_SIZE but state in a comment |
| 2076 | * that the TX_STA_FIFO stack has a size of 16. We stick to our |
| 2077 | * tx ring size for now. |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2078 | */ |
Ivo van Doorn | e6474c3 | 2010-06-14 22:13:37 +0200 | [diff] [blame] | 2079 | for (i = 0; i < TX_ENTRIES; i++) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2080 | rt2x00pci_register_read(rt2x00dev, STA_CSR4, ®); |
| 2081 | if (!rt2x00_get_field32(reg, STA_CSR4_VALID)) |
| 2082 | break; |
| 2083 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2084 | /* |
| 2085 | * Skip this entry when it contains an invalid |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2086 | * queue identication number. |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2087 | */ |
| 2088 | type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2089 | queue = rt2x00queue_get_queue(rt2x00dev, type); |
| 2090 | if (unlikely(!queue)) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2091 | continue; |
| 2092 | |
| 2093 | /* |
| 2094 | * Skip this entry when it contains an invalid |
| 2095 | * index number. |
| 2096 | */ |
| 2097 | index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2098 | if (unlikely(index >= queue->limit)) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2099 | continue; |
| 2100 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2101 | entry = &queue->entries[index]; |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 2102 | entry_priv = entry->priv_data; |
| 2103 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2104 | |
| 2105 | if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || |
| 2106 | !rt2x00_get_field32(word, TXD_W0_VALID)) |
| 2107 | return; |
| 2108 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2109 | entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE); |
Mattias Nissler | 62bc060 | 2007-11-12 15:03:12 +0100 | [diff] [blame] | 2110 | while (entry != entry_done) { |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2111 | /* Catch up. |
| 2112 | * Just report any entries we missed as failed. |
| 2113 | */ |
Mattias Nissler | 62bc060 | 2007-11-12 15:03:12 +0100 | [diff] [blame] | 2114 | WARNING(rt2x00dev, |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2115 | "TX status report missed for entry %d\n", |
| 2116 | entry_done->entry_idx); |
| 2117 | |
Ivo van Doorn | 3392bec | 2010-08-06 20:46:53 +0200 | [diff] [blame] | 2118 | rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN); |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2119 | entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE); |
Mattias Nissler | 62bc060 | 2007-11-12 15:03:12 +0100 | [diff] [blame] | 2120 | } |
| 2121 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2122 | /* |
| 2123 | * Obtain the status about this packet. |
| 2124 | */ |
Ivo van Doorn | fb55f4d | 2008-05-10 13:42:06 +0200 | [diff] [blame] | 2125 | txdesc.flags = 0; |
| 2126 | switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) { |
| 2127 | case 0: /* Success, maybe with retry */ |
| 2128 | __set_bit(TXDONE_SUCCESS, &txdesc.flags); |
| 2129 | break; |
| 2130 | case 6: /* Failure, excessive retries */ |
| 2131 | __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags); |
| 2132 | /* Don't break, this is a failed frame! */ |
| 2133 | default: /* Failure */ |
| 2134 | __set_bit(TXDONE_FAILURE, &txdesc.flags); |
| 2135 | } |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2136 | txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2137 | |
Ivo van Doorn | e1b4d7b | 2010-06-14 22:12:54 +0200 | [diff] [blame] | 2138 | /* |
| 2139 | * the frame was retried at least once |
| 2140 | * -> hw used fallback rates |
| 2141 | */ |
| 2142 | if (txdesc.retry) |
| 2143 | __set_bit(TXDONE_FALLBACK, &txdesc.flags); |
| 2144 | |
Gertjan van Wingerde | e513a0b | 2010-06-29 21:41:40 +0200 | [diff] [blame] | 2145 | rt2x00lib_txdone(entry, &txdesc); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2146 | } |
| 2147 | } |
| 2148 | |
Gertjan van Wingerde | 9e18944 | 2010-03-30 23:50:25 +0200 | [diff] [blame] | 2149 | static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev) |
| 2150 | { |
| 2151 | struct ieee80211_conf conf = { .flags = 0 }; |
| 2152 | struct rt2x00lib_conf libconf = { .conf = &conf }; |
| 2153 | |
| 2154 | rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS); |
| 2155 | } |
| 2156 | |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 2157 | static irqreturn_t rt61pci_interrupt_thread(int irq, void *dev_instance) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2158 | { |
| 2159 | struct rt2x00_dev *rt2x00dev = dev_instance; |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 2160 | u32 reg = rt2x00dev->irqvalue[0]; |
| 2161 | u32 reg_mcu = rt2x00dev->irqvalue[1]; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2162 | |
| 2163 | /* |
| 2164 | * Handle interrupts, walk through all bits |
| 2165 | * and run the tasks, the bits are checked in order of |
| 2166 | * priority. |
| 2167 | */ |
| 2168 | |
| 2169 | /* |
| 2170 | * 1 - Rx ring done interrupt. |
| 2171 | */ |
| 2172 | if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE)) |
| 2173 | rt2x00pci_rxdone(rt2x00dev); |
| 2174 | |
| 2175 | /* |
| 2176 | * 2 - Tx ring done interrupt. |
| 2177 | */ |
| 2178 | if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE)) |
| 2179 | rt61pci_txdone(rt2x00dev); |
| 2180 | |
| 2181 | /* |
| 2182 | * 3 - Handle MCU command done. |
| 2183 | */ |
| 2184 | if (reg_mcu) |
| 2185 | rt2x00pci_register_write(rt2x00dev, |
| 2186 | M2H_CMD_DONE_CSR, 0xffffffff); |
| 2187 | |
Gertjan van Wingerde | 9e18944 | 2010-03-30 23:50:25 +0200 | [diff] [blame] | 2188 | /* |
| 2189 | * 4 - MCU Autowakeup interrupt. |
| 2190 | */ |
| 2191 | if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP)) |
| 2192 | rt61pci_wakeup(rt2x00dev); |
| 2193 | |
Helmut Schaa | fa43750 | 2010-06-29 21:47:10 +0200 | [diff] [blame] | 2194 | /* |
| 2195 | * 5 - Beacon done interrupt. |
| 2196 | */ |
| 2197 | if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE)) |
| 2198 | rt2x00lib_beacondone(rt2x00dev); |
| 2199 | |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 2200 | /* Enable interrupts again. */ |
| 2201 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, |
| 2202 | STATE_RADIO_IRQ_ON_ISR); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2203 | return IRQ_HANDLED; |
| 2204 | } |
| 2205 | |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 2206 | |
| 2207 | static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance) |
| 2208 | { |
| 2209 | struct rt2x00_dev *rt2x00dev = dev_instance; |
| 2210 | u32 reg_mcu; |
| 2211 | u32 reg; |
| 2212 | |
| 2213 | /* |
| 2214 | * Get the interrupt sources & saved to local variable. |
| 2215 | * Write register value back to clear pending interrupts. |
| 2216 | */ |
| 2217 | rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu); |
| 2218 | rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu); |
| 2219 | |
| 2220 | rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®); |
| 2221 | rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); |
| 2222 | |
| 2223 | if (!reg && !reg_mcu) |
| 2224 | return IRQ_NONE; |
| 2225 | |
| 2226 | if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) |
| 2227 | return IRQ_HANDLED; |
| 2228 | |
| 2229 | /* Store irqvalues for use in the interrupt thread. */ |
| 2230 | rt2x00dev->irqvalue[0] = reg; |
| 2231 | rt2x00dev->irqvalue[1] = reg_mcu; |
| 2232 | |
| 2233 | /* Disable interrupts, will be enabled again in the interrupt thread. */ |
| 2234 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, |
| 2235 | STATE_RADIO_IRQ_OFF_ISR); |
| 2236 | return IRQ_WAKE_THREAD; |
| 2237 | } |
| 2238 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2239 | /* |
| 2240 | * Device probe functions. |
| 2241 | */ |
| 2242 | static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) |
| 2243 | { |
| 2244 | struct eeprom_93cx6 eeprom; |
| 2245 | u32 reg; |
| 2246 | u16 word; |
| 2247 | u8 *mac; |
| 2248 | s8 value; |
| 2249 | |
| 2250 | rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®); |
| 2251 | |
| 2252 | eeprom.data = rt2x00dev; |
| 2253 | eeprom.register_read = rt61pci_eepromregister_read; |
| 2254 | eeprom.register_write = rt61pci_eepromregister_write; |
| 2255 | eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ? |
| 2256 | PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66; |
| 2257 | eeprom.reg_data_in = 0; |
| 2258 | eeprom.reg_data_out = 0; |
| 2259 | eeprom.reg_data_clock = 0; |
| 2260 | eeprom.reg_chip_select = 0; |
| 2261 | |
| 2262 | eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, |
| 2263 | EEPROM_SIZE / sizeof(u16)); |
| 2264 | |
| 2265 | /* |
| 2266 | * Start validation of the data that has been read. |
| 2267 | */ |
| 2268 | mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); |
| 2269 | if (!is_valid_ether_addr(mac)) { |
| 2270 | random_ether_addr(mac); |
Johannes Berg | e174961 | 2008-10-27 15:59:26 -0700 | [diff] [blame] | 2271 | EEPROM(rt2x00dev, "MAC: %pM\n", mac); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2272 | } |
| 2273 | |
| 2274 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); |
| 2275 | if (word == 0xffff) { |
| 2276 | rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2); |
Ivo van Doorn | 362f3b6 | 2007-10-13 16:26:18 +0200 | [diff] [blame] | 2277 | rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, |
| 2278 | ANTENNA_B); |
| 2279 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, |
| 2280 | ANTENNA_B); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2281 | rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0); |
| 2282 | rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0); |
| 2283 | rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0); |
| 2284 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225); |
| 2285 | rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); |
| 2286 | EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word); |
| 2287 | } |
| 2288 | |
| 2289 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); |
| 2290 | if (word == 0xffff) { |
| 2291 | rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0); |
| 2292 | rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0); |
Ivo van Doorn | 91581b6 | 2008-12-20 10:57:47 +0100 | [diff] [blame] | 2293 | rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0); |
| 2294 | rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2295 | rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0); |
| 2296 | rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0); |
| 2297 | rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0); |
| 2298 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); |
| 2299 | EEPROM(rt2x00dev, "NIC: 0x%04x\n", word); |
| 2300 | } |
| 2301 | |
| 2302 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word); |
| 2303 | if (word == 0xffff) { |
| 2304 | rt2x00_set_field16(&word, EEPROM_LED_LED_MODE, |
| 2305 | LED_MODE_DEFAULT); |
| 2306 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word); |
| 2307 | EEPROM(rt2x00dev, "Led: 0x%04x\n", word); |
| 2308 | } |
| 2309 | |
| 2310 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); |
| 2311 | if (word == 0xffff) { |
| 2312 | rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); |
| 2313 | rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0); |
| 2314 | rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); |
| 2315 | EEPROM(rt2x00dev, "Freq: 0x%04x\n", word); |
| 2316 | } |
| 2317 | |
| 2318 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word); |
| 2319 | if (word == 0xffff) { |
| 2320 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); |
| 2321 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); |
| 2322 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); |
| 2323 | EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word); |
| 2324 | } else { |
| 2325 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1); |
| 2326 | if (value < -10 || value > 10) |
| 2327 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); |
| 2328 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2); |
| 2329 | if (value < -10 || value > 10) |
| 2330 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); |
| 2331 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); |
| 2332 | } |
| 2333 | |
| 2334 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word); |
| 2335 | if (word == 0xffff) { |
| 2336 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); |
| 2337 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); |
| 2338 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); |
Ivo van Doorn | 417f412 | 2008-02-10 22:50:58 +0100 | [diff] [blame] | 2339 | EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2340 | } else { |
| 2341 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1); |
| 2342 | if (value < -10 || value > 10) |
| 2343 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); |
| 2344 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2); |
| 2345 | if (value < -10 || value > 10) |
| 2346 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); |
| 2347 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); |
| 2348 | } |
| 2349 | |
| 2350 | return 0; |
| 2351 | } |
| 2352 | |
| 2353 | static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev) |
| 2354 | { |
| 2355 | u32 reg; |
| 2356 | u16 value; |
| 2357 | u16 eeprom; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2358 | |
| 2359 | /* |
| 2360 | * Read EEPROM word for configuration. |
| 2361 | */ |
| 2362 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); |
| 2363 | |
| 2364 | /* |
| 2365 | * Identify RF chipset. |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2366 | */ |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2367 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); |
| 2368 | rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®); |
Gertjan van Wingerde | 49e721e | 2010-02-13 20:55:49 +0100 | [diff] [blame] | 2369 | rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), |
| 2370 | value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2371 | |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 2372 | if (!rt2x00_rf(rt2x00dev, RF5225) && |
| 2373 | !rt2x00_rf(rt2x00dev, RF5325) && |
| 2374 | !rt2x00_rf(rt2x00dev, RF2527) && |
| 2375 | !rt2x00_rf(rt2x00dev, RF2529)) { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2376 | ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); |
| 2377 | return -ENODEV; |
| 2378 | } |
| 2379 | |
| 2380 | /* |
Luis Correia | 4951348 | 2009-07-17 21:39:19 +0200 | [diff] [blame] | 2381 | * Determine number of antennas. |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 2382 | */ |
| 2383 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2) |
| 2384 | __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags); |
| 2385 | |
| 2386 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2387 | * Identify default antenna configuration. |
| 2388 | */ |
Ivo van Doorn | addc81b | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 2389 | rt2x00dev->default_ant.tx = |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2390 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT); |
Ivo van Doorn | addc81b | 2007-10-13 16:26:23 +0200 | [diff] [blame] | 2391 | rt2x00dev->default_ant.rx = |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2392 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT); |
| 2393 | |
| 2394 | /* |
| 2395 | * Read the Frame type. |
| 2396 | */ |
| 2397 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE)) |
| 2398 | __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags); |
| 2399 | |
| 2400 | /* |
Thadeu Lima de Souza Cascardo | b34e620 | 2009-11-09 09:45:50 +0100 | [diff] [blame] | 2401 | * Detect if this device has a hardware controlled radio. |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2402 | */ |
| 2403 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO)) |
Ivo van Doorn | 066cb63 | 2007-09-25 20:55:39 +0200 | [diff] [blame] | 2404 | __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2405 | |
| 2406 | /* |
| 2407 | * Read frequency offset and RF programming sequence. |
| 2408 | */ |
| 2409 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); |
| 2410 | if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ)) |
| 2411 | __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags); |
| 2412 | |
| 2413 | rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); |
| 2414 | |
| 2415 | /* |
| 2416 | * Read external LNA informations. |
| 2417 | */ |
| 2418 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); |
| 2419 | |
| 2420 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A)) |
| 2421 | __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); |
| 2422 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG)) |
| 2423 | __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); |
| 2424 | |
| 2425 | /* |
Thadeu Lima de Souza Cascardo | b34e620 | 2009-11-09 09:45:50 +0100 | [diff] [blame] | 2426 | * When working with a RF2529 chip without double antenna, |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 2427 | * the antenna settings should be gathered from the NIC |
| 2428 | * eeprom word. |
| 2429 | */ |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 2430 | if (rt2x00_rf(rt2x00dev, RF2529) && |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 2431 | !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) { |
Ivo van Doorn | 91581b6 | 2008-12-20 10:57:47 +0100 | [diff] [blame] | 2432 | rt2x00dev->default_ant.rx = |
| 2433 | ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED); |
| 2434 | rt2x00dev->default_ant.tx = |
| 2435 | ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED); |
Ivo van Doorn | e4cd2ff | 2007-10-27 13:39:57 +0200 | [diff] [blame] | 2436 | |
| 2437 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) |
| 2438 | rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY; |
| 2439 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY)) |
| 2440 | rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY; |
| 2441 | } |
| 2442 | |
| 2443 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2444 | * Store led settings, for correct led behaviour. |
| 2445 | * If the eeprom value is invalid, |
| 2446 | * switch to default led mode. |
| 2447 | */ |
Ivo van Doorn | 771fd56 | 2008-09-08 19:07:15 +0200 | [diff] [blame] | 2448 | #ifdef CONFIG_RT2X00_LIB_LEDS |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2449 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom); |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 2450 | value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2451 | |
Ivo van Doorn | 475433b | 2008-06-03 20:30:01 +0200 | [diff] [blame] | 2452 | rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); |
| 2453 | rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); |
| 2454 | if (value == LED_MODE_SIGNAL_STRENGTH) |
| 2455 | rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual, |
| 2456 | LED_TYPE_QUALITY); |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 2457 | |
| 2458 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value); |
| 2459 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2460 | rt2x00_get_field16(eeprom, |
| 2461 | EEPROM_LED_POLARITY_GPIO_0)); |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 2462 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2463 | rt2x00_get_field16(eeprom, |
| 2464 | EEPROM_LED_POLARITY_GPIO_1)); |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 2465 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2466 | rt2x00_get_field16(eeprom, |
| 2467 | EEPROM_LED_POLARITY_GPIO_2)); |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 2468 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2469 | rt2x00_get_field16(eeprom, |
| 2470 | EEPROM_LED_POLARITY_GPIO_3)); |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 2471 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2472 | rt2x00_get_field16(eeprom, |
| 2473 | EEPROM_LED_POLARITY_GPIO_4)); |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 2474 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2475 | rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT)); |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 2476 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2477 | rt2x00_get_field16(eeprom, |
| 2478 | EEPROM_LED_POLARITY_RDY_G)); |
Ivo van Doorn | a9450b7 | 2008-02-03 15:53:40 +0100 | [diff] [blame] | 2479 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2480 | rt2x00_get_field16(eeprom, |
| 2481 | EEPROM_LED_POLARITY_RDY_A)); |
Ivo van Doorn | 771fd56 | 2008-09-08 19:07:15 +0200 | [diff] [blame] | 2482 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2483 | |
| 2484 | return 0; |
| 2485 | } |
| 2486 | |
| 2487 | /* |
| 2488 | * RF value list for RF5225 & RF5325 |
| 2489 | * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled |
| 2490 | */ |
| 2491 | static const struct rf_channel rf_vals_noseq[] = { |
| 2492 | { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b }, |
| 2493 | { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f }, |
| 2494 | { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b }, |
| 2495 | { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f }, |
| 2496 | { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b }, |
| 2497 | { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f }, |
| 2498 | { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b }, |
| 2499 | { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f }, |
| 2500 | { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b }, |
| 2501 | { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f }, |
| 2502 | { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b }, |
| 2503 | { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f }, |
| 2504 | { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b }, |
| 2505 | { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 }, |
| 2506 | |
| 2507 | /* 802.11 UNI / HyperLan 2 */ |
| 2508 | { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 }, |
| 2509 | { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 }, |
| 2510 | { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b }, |
| 2511 | { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 }, |
| 2512 | { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b }, |
| 2513 | { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 }, |
| 2514 | { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 }, |
| 2515 | { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b }, |
| 2516 | |
| 2517 | /* 802.11 HyperLan 2 */ |
| 2518 | { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 }, |
| 2519 | { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b }, |
| 2520 | { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 }, |
| 2521 | { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b }, |
| 2522 | { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 }, |
| 2523 | { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 }, |
| 2524 | { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b }, |
| 2525 | { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 }, |
| 2526 | { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b }, |
| 2527 | { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 }, |
| 2528 | |
| 2529 | /* 802.11 UNII */ |
| 2530 | { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 }, |
| 2531 | { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f }, |
| 2532 | { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 }, |
| 2533 | { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 }, |
| 2534 | { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f }, |
| 2535 | { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 }, |
| 2536 | |
| 2537 | /* MMAC(Japan)J52 ch 34,38,42,46 */ |
| 2538 | { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b }, |
| 2539 | { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 }, |
| 2540 | { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b }, |
| 2541 | { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 }, |
| 2542 | }; |
| 2543 | |
| 2544 | /* |
| 2545 | * RF value list for RF5225 & RF5325 |
| 2546 | * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled |
| 2547 | */ |
| 2548 | static const struct rf_channel rf_vals_seq[] = { |
| 2549 | { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b }, |
| 2550 | { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f }, |
| 2551 | { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b }, |
| 2552 | { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f }, |
| 2553 | { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b }, |
| 2554 | { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f }, |
| 2555 | { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b }, |
| 2556 | { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f }, |
| 2557 | { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b }, |
| 2558 | { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f }, |
| 2559 | { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b }, |
| 2560 | { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f }, |
| 2561 | { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b }, |
| 2562 | { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 }, |
| 2563 | |
| 2564 | /* 802.11 UNI / HyperLan 2 */ |
| 2565 | { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 }, |
| 2566 | { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 }, |
| 2567 | { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b }, |
| 2568 | { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b }, |
| 2569 | { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 }, |
| 2570 | { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 }, |
| 2571 | { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 }, |
| 2572 | { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b }, |
| 2573 | |
| 2574 | /* 802.11 HyperLan 2 */ |
| 2575 | { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 }, |
| 2576 | { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 }, |
| 2577 | { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 }, |
| 2578 | { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 }, |
| 2579 | { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 }, |
| 2580 | { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 }, |
| 2581 | { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b }, |
| 2582 | { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b }, |
| 2583 | { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 }, |
| 2584 | { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 }, |
| 2585 | |
| 2586 | /* 802.11 UNII */ |
| 2587 | { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 }, |
| 2588 | { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b }, |
| 2589 | { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b }, |
| 2590 | { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 }, |
| 2591 | { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 }, |
| 2592 | { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 }, |
| 2593 | |
| 2594 | /* MMAC(Japan)J52 ch 34,38,42,46 */ |
| 2595 | { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b }, |
| 2596 | { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 }, |
| 2597 | { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b }, |
| 2598 | { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 }, |
| 2599 | }; |
| 2600 | |
Ivo van Doorn | 8c5e7a5 | 2008-08-04 16:38:47 +0200 | [diff] [blame] | 2601 | static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2602 | { |
| 2603 | struct hw_mode_spec *spec = &rt2x00dev->spec; |
Ivo van Doorn | 8c5e7a5 | 2008-08-04 16:38:47 +0200 | [diff] [blame] | 2604 | struct channel_info *info; |
| 2605 | char *tx_power; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2606 | unsigned int i; |
| 2607 | |
| 2608 | /* |
Gertjan van Wingerde | 93b6bd2 | 2009-12-14 20:33:55 +0100 | [diff] [blame] | 2609 | * Disable powersaving as default. |
| 2610 | */ |
| 2611 | rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; |
| 2612 | |
| 2613 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2614 | * Initialize all hw fields. |
| 2615 | */ |
| 2616 | rt2x00dev->hw->flags = |
Bruno Randolf | 566bfe5 | 2008-05-08 19:15:40 +0200 | [diff] [blame] | 2617 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | |
Johannes Berg | 4be8c38 | 2009-01-07 18:28:20 +0100 | [diff] [blame] | 2618 | IEEE80211_HW_SIGNAL_DBM | |
| 2619 | IEEE80211_HW_SUPPORTS_PS | |
| 2620 | IEEE80211_HW_PS_NULLFUNC_STACK; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2621 | |
Gertjan van Wingerde | 14a3bf8 | 2008-06-16 19:55:43 +0200 | [diff] [blame] | 2622 | SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2623 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, |
| 2624 | rt2x00_eeprom_addr(rt2x00dev, |
| 2625 | EEPROM_MAC_ADDR_0)); |
| 2626 | |
| 2627 | /* |
Ivo van Doorn | e1b4d7b | 2010-06-14 22:12:54 +0200 | [diff] [blame] | 2628 | * As rt61 has a global fallback table we cannot specify |
| 2629 | * more then one tx rate per frame but since the hw will |
| 2630 | * try several rates (based on the fallback table) we should |
| 2631 | * still initialize max_rates to the maximum number of rates |
| 2632 | * we are going to try. Otherwise mac80211 will truncate our |
| 2633 | * reported tx rates and the rc algortihm will end up with |
| 2634 | * incorrect data. |
| 2635 | */ |
| 2636 | rt2x00dev->hw->max_rates = 7; |
| 2637 | rt2x00dev->hw->max_rate_tries = 1; |
| 2638 | |
| 2639 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2640 | * Initialize hw_mode information. |
| 2641 | */ |
Ivo van Doorn | 31562e8 | 2008-02-17 17:35:05 +0100 | [diff] [blame] | 2642 | spec->supported_bands = SUPPORT_BAND_2GHZ; |
| 2643 | spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2644 | |
| 2645 | if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) { |
| 2646 | spec->num_channels = 14; |
| 2647 | spec->channels = rf_vals_noseq; |
| 2648 | } else { |
| 2649 | spec->num_channels = 14; |
| 2650 | spec->channels = rf_vals_seq; |
| 2651 | } |
| 2652 | |
Gertjan van Wingerde | 5122d89 | 2009-12-23 00:03:25 +0100 | [diff] [blame] | 2653 | if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) { |
Ivo van Doorn | 31562e8 | 2008-02-17 17:35:05 +0100 | [diff] [blame] | 2654 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2655 | spec->num_channels = ARRAY_SIZE(rf_vals_seq); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2656 | } |
Ivo van Doorn | 8c5e7a5 | 2008-08-04 16:38:47 +0200 | [diff] [blame] | 2657 | |
| 2658 | /* |
| 2659 | * Create channel information array |
| 2660 | */ |
| 2661 | info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL); |
| 2662 | if (!info) |
| 2663 | return -ENOMEM; |
| 2664 | |
| 2665 | spec->channels_info = info; |
| 2666 | |
| 2667 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START); |
Ivo van Doorn | 8d1331b | 2010-08-23 19:56:07 +0200 | [diff] [blame] | 2668 | for (i = 0; i < 14; i++) { |
| 2669 | info[i].max_power = MAX_TXPOWER; |
| 2670 | info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]); |
| 2671 | } |
Ivo van Doorn | 8c5e7a5 | 2008-08-04 16:38:47 +0200 | [diff] [blame] | 2672 | |
| 2673 | if (spec->num_channels > 14) { |
| 2674 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); |
Ivo van Doorn | 8d1331b | 2010-08-23 19:56:07 +0200 | [diff] [blame] | 2675 | for (i = 14; i < spec->num_channels; i++) { |
| 2676 | info[i].max_power = MAX_TXPOWER; |
| 2677 | info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]); |
| 2678 | } |
Ivo van Doorn | 8c5e7a5 | 2008-08-04 16:38:47 +0200 | [diff] [blame] | 2679 | } |
| 2680 | |
| 2681 | return 0; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2682 | } |
| 2683 | |
| 2684 | static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev) |
| 2685 | { |
| 2686 | int retval; |
| 2687 | |
| 2688 | /* |
Pavel Roskin | 117839b | 2009-08-02 14:30:02 -0400 | [diff] [blame] | 2689 | * Disable power saving. |
| 2690 | */ |
| 2691 | rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007); |
| 2692 | |
| 2693 | /* |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2694 | * Allocate eeprom data. |
| 2695 | */ |
| 2696 | retval = rt61pci_validate_eeprom(rt2x00dev); |
| 2697 | if (retval) |
| 2698 | return retval; |
| 2699 | |
| 2700 | retval = rt61pci_init_eeprom(rt2x00dev); |
| 2701 | if (retval) |
| 2702 | return retval; |
| 2703 | |
| 2704 | /* |
| 2705 | * Initialize hw specifications. |
| 2706 | */ |
Ivo van Doorn | 8c5e7a5 | 2008-08-04 16:38:47 +0200 | [diff] [blame] | 2707 | retval = rt61pci_probe_hw_mode(rt2x00dev); |
| 2708 | if (retval) |
| 2709 | return retval; |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2710 | |
| 2711 | /* |
Igor Perminov | 1afcfd54 | 2009-08-08 23:55:55 +0200 | [diff] [blame] | 2712 | * This device has multiple filters for control frames, |
| 2713 | * but has no a separate filter for PS Poll frames. |
| 2714 | */ |
| 2715 | __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags); |
| 2716 | |
| 2717 | /* |
Gertjan van Wingerde | c4da004 | 2008-06-16 19:56:31 +0200 | [diff] [blame] | 2718 | * This device requires firmware and DMA mapped skbs. |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2719 | */ |
Ivo van Doorn | 066cb63 | 2007-09-25 20:55:39 +0200 | [diff] [blame] | 2720 | __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags); |
Gertjan van Wingerde | c4da004 | 2008-06-16 19:56:31 +0200 | [diff] [blame] | 2721 | __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); |
Ivo van Doorn | 008c448 | 2008-08-06 17:27:31 +0200 | [diff] [blame] | 2722 | if (!modparam_nohwcrypt) |
| 2723 | __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags); |
Ivo van Doorn | 27df2a9 | 2010-07-11 12:24:22 +0200 | [diff] [blame] | 2724 | __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags); |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2725 | |
| 2726 | /* |
| 2727 | * Set the rssi offset. |
| 2728 | */ |
| 2729 | rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; |
| 2730 | |
| 2731 | return 0; |
| 2732 | } |
| 2733 | |
| 2734 | /* |
| 2735 | * IEEE80211 stack callback functions. |
| 2736 | */ |
Ivo van Doorn | 2af0a57 | 2008-08-29 21:05:45 +0200 | [diff] [blame] | 2737 | static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx, |
| 2738 | const struct ieee80211_tx_queue_params *params) |
| 2739 | { |
| 2740 | struct rt2x00_dev *rt2x00dev = hw->priv; |
| 2741 | struct data_queue *queue; |
| 2742 | struct rt2x00_field32 field; |
| 2743 | int retval; |
| 2744 | u32 reg; |
Ivo van Doorn | 5e79002 | 2009-01-17 20:42:58 +0100 | [diff] [blame] | 2745 | u32 offset; |
Ivo van Doorn | 2af0a57 | 2008-08-29 21:05:45 +0200 | [diff] [blame] | 2746 | |
| 2747 | /* |
| 2748 | * First pass the configuration through rt2x00lib, that will |
| 2749 | * update the queue settings and validate the input. After that |
| 2750 | * we are free to update the registers based on the value |
| 2751 | * in the queue parameter. |
| 2752 | */ |
| 2753 | retval = rt2x00mac_conf_tx(hw, queue_idx, params); |
| 2754 | if (retval) |
| 2755 | return retval; |
| 2756 | |
Ivo van Doorn | 5e79002 | 2009-01-17 20:42:58 +0100 | [diff] [blame] | 2757 | /* |
| 2758 | * We only need to perform additional register initialization |
Thadeu Lima de Souza Cascardo | b34e620 | 2009-11-09 09:45:50 +0100 | [diff] [blame] | 2759 | * for WMM queues. |
Ivo van Doorn | 5e79002 | 2009-01-17 20:42:58 +0100 | [diff] [blame] | 2760 | */ |
| 2761 | if (queue_idx >= 4) |
| 2762 | return 0; |
| 2763 | |
Ivo van Doorn | 2af0a57 | 2008-08-29 21:05:45 +0200 | [diff] [blame] | 2764 | queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); |
| 2765 | |
| 2766 | /* Update WMM TXOP register */ |
Ivo van Doorn | 5e79002 | 2009-01-17 20:42:58 +0100 | [diff] [blame] | 2767 | offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2))); |
| 2768 | field.bit_offset = (queue_idx & 1) * 16; |
| 2769 | field.bit_mask = 0xffff << field.bit_offset; |
Ivo van Doorn | 2af0a57 | 2008-08-29 21:05:45 +0200 | [diff] [blame] | 2770 | |
Ivo van Doorn | 5e79002 | 2009-01-17 20:42:58 +0100 | [diff] [blame] | 2771 | rt2x00pci_register_read(rt2x00dev, offset, ®); |
| 2772 | rt2x00_set_field32(®, field, queue->txop); |
| 2773 | rt2x00pci_register_write(rt2x00dev, offset, reg); |
Ivo van Doorn | 2af0a57 | 2008-08-29 21:05:45 +0200 | [diff] [blame] | 2774 | |
| 2775 | /* Update WMM registers */ |
| 2776 | field.bit_offset = queue_idx * 4; |
| 2777 | field.bit_mask = 0xf << field.bit_offset; |
| 2778 | |
| 2779 | rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, ®); |
| 2780 | rt2x00_set_field32(®, field, queue->aifs); |
| 2781 | rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg); |
| 2782 | |
| 2783 | rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, ®); |
| 2784 | rt2x00_set_field32(®, field, queue->cw_min); |
| 2785 | rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg); |
| 2786 | |
| 2787 | rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, ®); |
| 2788 | rt2x00_set_field32(®, field, queue->cw_max); |
| 2789 | rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg); |
| 2790 | |
| 2791 | return 0; |
| 2792 | } |
| 2793 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2794 | static u64 rt61pci_get_tsf(struct ieee80211_hw *hw) |
| 2795 | { |
| 2796 | struct rt2x00_dev *rt2x00dev = hw->priv; |
| 2797 | u64 tsf; |
| 2798 | u32 reg; |
| 2799 | |
| 2800 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, ®); |
| 2801 | tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; |
| 2802 | rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, ®); |
| 2803 | tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); |
| 2804 | |
| 2805 | return tsf; |
| 2806 | } |
| 2807 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2808 | static const struct ieee80211_ops rt61pci_mac80211_ops = { |
| 2809 | .tx = rt2x00mac_tx, |
Johannes Berg | 4150c57 | 2007-09-17 01:29:23 -0400 | [diff] [blame] | 2810 | .start = rt2x00mac_start, |
| 2811 | .stop = rt2x00mac_stop, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2812 | .add_interface = rt2x00mac_add_interface, |
| 2813 | .remove_interface = rt2x00mac_remove_interface, |
| 2814 | .config = rt2x00mac_config, |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 2815 | .configure_filter = rt2x00mac_configure_filter, |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 2816 | .set_key = rt2x00mac_set_key, |
Ivo van Doorn | d8147f9 | 2010-07-11 12:24:47 +0200 | [diff] [blame] | 2817 | .sw_scan_start = rt2x00mac_sw_scan_start, |
| 2818 | .sw_scan_complete = rt2x00mac_sw_scan_complete, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2819 | .get_stats = rt2x00mac_get_stats, |
Johannes Berg | 471b3ef | 2007-12-28 14:32:58 +0100 | [diff] [blame] | 2820 | .bss_info_changed = rt2x00mac_bss_info_changed, |
Ivo van Doorn | 2af0a57 | 2008-08-29 21:05:45 +0200 | [diff] [blame] | 2821 | .conf_tx = rt61pci_conf_tx, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2822 | .get_tsf = rt61pci_get_tsf, |
Ivo van Doorn | e47a5cd | 2009-07-01 15:17:35 +0200 | [diff] [blame] | 2823 | .rfkill_poll = rt2x00mac_rfkill_poll, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2824 | }; |
| 2825 | |
| 2826 | static const struct rt2x00lib_ops rt61pci_rt2x00_ops = { |
| 2827 | .irq_handler = rt61pci_interrupt, |
Helmut Schaa | 78e256c | 2010-07-11 12:26:48 +0200 | [diff] [blame] | 2828 | .irq_handler_thread = rt61pci_interrupt_thread, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2829 | .probe_hw = rt61pci_probe_hw, |
| 2830 | .get_firmware_name = rt61pci_get_firmware_name, |
Ivo van Doorn | 0cbe006 | 2009-01-28 00:33:47 +0100 | [diff] [blame] | 2831 | .check_firmware = rt61pci_check_firmware, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2832 | .load_firmware = rt61pci_load_firmware, |
| 2833 | .initialize = rt2x00pci_initialize, |
| 2834 | .uninitialize = rt2x00pci_uninitialize, |
Ivo van Doorn | 798b7ad | 2008-11-08 15:25:33 +0100 | [diff] [blame] | 2835 | .get_entry_state = rt61pci_get_entry_state, |
| 2836 | .clear_entry = rt61pci_clear_entry, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2837 | .set_device_state = rt61pci_set_device_state, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2838 | .rfkill_poll = rt61pci_rfkill_poll, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2839 | .link_stats = rt61pci_link_stats, |
| 2840 | .reset_tuner = rt61pci_reset_tuner, |
| 2841 | .link_tuner = rt61pci_link_tuner, |
| 2842 | .write_tx_desc = rt61pci_write_tx_desc, |
Ivo van Doorn | bd88a78 | 2008-07-09 15:12:44 +0200 | [diff] [blame] | 2843 | .write_beacon = rt61pci_write_beacon, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2844 | .kick_tx_queue = rt61pci_kick_tx_queue, |
Ivo van Doorn | a2c9b65 | 2009-01-28 00:32:33 +0100 | [diff] [blame] | 2845 | .kill_tx_queue = rt61pci_kill_tx_queue, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2846 | .fill_rxdone = rt61pci_fill_rxdone, |
Ivo van Doorn | 61e754f | 2008-08-04 16:38:02 +0200 | [diff] [blame] | 2847 | .config_shared_key = rt61pci_config_shared_key, |
| 2848 | .config_pairwise_key = rt61pci_config_pairwise_key, |
Ivo van Doorn | 3a643d2 | 2008-03-25 14:13:18 +0100 | [diff] [blame] | 2849 | .config_filter = rt61pci_config_filter, |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 2850 | .config_intf = rt61pci_config_intf, |
Ivo van Doorn | 7281037 | 2008-03-09 22:46:18 +0100 | [diff] [blame] | 2851 | .config_erp = rt61pci_config_erp, |
Ivo van Doorn | e4ea1c4 | 2008-10-29 17:17:57 +0100 | [diff] [blame] | 2852 | .config_ant = rt61pci_config_ant, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2853 | .config = rt61pci_config, |
| 2854 | }; |
| 2855 | |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2856 | static const struct data_queue_desc rt61pci_queue_rx = { |
| 2857 | .entry_num = RX_ENTRIES, |
| 2858 | .data_size = DATA_FRAME_SIZE, |
| 2859 | .desc_size = RXD_DESC_SIZE, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 2860 | .priv_size = sizeof(struct queue_entry_priv_pci), |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2861 | }; |
| 2862 | |
| 2863 | static const struct data_queue_desc rt61pci_queue_tx = { |
| 2864 | .entry_num = TX_ENTRIES, |
| 2865 | .data_size = DATA_FRAME_SIZE, |
| 2866 | .desc_size = TXD_DESC_SIZE, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 2867 | .priv_size = sizeof(struct queue_entry_priv_pci), |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2868 | }; |
| 2869 | |
| 2870 | static const struct data_queue_desc rt61pci_queue_bcn = { |
Ivo van Doorn | 6bb40dd | 2008-02-03 15:49:59 +0100 | [diff] [blame] | 2871 | .entry_num = 4 * BEACON_ENTRIES, |
Ivo van Doorn | 7872089 | 2008-05-05 17:23:31 +0200 | [diff] [blame] | 2872 | .data_size = 0, /* No DMA required for beacons */ |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2873 | .desc_size = TXINFO_SIZE, |
Ivo van Doorn | b8be63f | 2008-05-10 13:46:03 +0200 | [diff] [blame] | 2874 | .priv_size = sizeof(struct queue_entry_priv_pci), |
Ivo van Doorn | 181d690 | 2008-02-05 16:42:23 -0500 | [diff] [blame] | 2875 | }; |
| 2876 | |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2877 | static const struct rt2x00_ops rt61pci_ops = { |
Gertjan van Wingerde | 04d0362 | 2009-11-23 22:44:51 +0100 | [diff] [blame] | 2878 | .name = KBUILD_MODNAME, |
| 2879 | .max_sta_intf = 1, |
| 2880 | .max_ap_intf = 4, |
| 2881 | .eeprom_size = EEPROM_SIZE, |
| 2882 | .rf_size = RF_SIZE, |
| 2883 | .tx_queues = NUM_TX_QUEUES, |
Gertjan van Wingerde | e6218cc | 2009-11-23 22:44:52 +0100 | [diff] [blame] | 2884 | .extra_tx_headroom = 0, |
Gertjan van Wingerde | 04d0362 | 2009-11-23 22:44:51 +0100 | [diff] [blame] | 2885 | .rx = &rt61pci_queue_rx, |
| 2886 | .tx = &rt61pci_queue_tx, |
| 2887 | .bcn = &rt61pci_queue_bcn, |
| 2888 | .lib = &rt61pci_rt2x00_ops, |
| 2889 | .hw = &rt61pci_mac80211_ops, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2890 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |
Gertjan van Wingerde | 04d0362 | 2009-11-23 22:44:51 +0100 | [diff] [blame] | 2891 | .debugfs = &rt61pci_rt2x00debug, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2892 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ |
| 2893 | }; |
| 2894 | |
| 2895 | /* |
| 2896 | * RT61pci module information. |
| 2897 | */ |
Alexey Dobriyan | a3aa188 | 2010-01-07 11:58:11 +0000 | [diff] [blame] | 2898 | static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = { |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2899 | /* RT2561s */ |
| 2900 | { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) }, |
| 2901 | /* RT2561 v2 */ |
| 2902 | { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) }, |
| 2903 | /* RT2661 */ |
| 2904 | { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) }, |
| 2905 | { 0, } |
| 2906 | }; |
| 2907 | |
| 2908 | MODULE_AUTHOR(DRV_PROJECT); |
| 2909 | MODULE_VERSION(DRV_VERSION); |
| 2910 | MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver."); |
| 2911 | MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 " |
| 2912 | "PCI & PCMCIA chipset based cards"); |
| 2913 | MODULE_DEVICE_TABLE(pci, rt61pci_device_table); |
| 2914 | MODULE_FIRMWARE(FIRMWARE_RT2561); |
| 2915 | MODULE_FIRMWARE(FIRMWARE_RT2561s); |
| 2916 | MODULE_FIRMWARE(FIRMWARE_RT2661); |
| 2917 | MODULE_LICENSE("GPL"); |
| 2918 | |
| 2919 | static struct pci_driver rt61pci_driver = { |
Ivo van Doorn | 2360157 | 2007-11-27 21:47:34 +0100 | [diff] [blame] | 2920 | .name = KBUILD_MODNAME, |
Ivo van Doorn | 95ea362 | 2007-09-25 17:57:13 -0700 | [diff] [blame] | 2921 | .id_table = rt61pci_device_table, |
| 2922 | .probe = rt2x00pci_probe, |
| 2923 | .remove = __devexit_p(rt2x00pci_remove), |
| 2924 | .suspend = rt2x00pci_suspend, |
| 2925 | .resume = rt2x00pci_resume, |
| 2926 | }; |
| 2927 | |
| 2928 | static int __init rt61pci_init(void) |
| 2929 | { |
| 2930 | return pci_register_driver(&rt61pci_driver); |
| 2931 | } |
| 2932 | |
| 2933 | static void __exit rt61pci_exit(void) |
| 2934 | { |
| 2935 | pci_unregister_driver(&rt61pci_driver); |
| 2936 | } |
| 2937 | |
| 2938 | module_init(rt61pci_init); |
| 2939 | module_exit(rt61pci_exit); |