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Clemens Ladischd0ce9942007-12-23 19:50:57 +01001/*
2 * C-Media CMI8788 driver - PCM code
3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 *
6 *
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
9 *
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
Clemens Ladischd0ce9942007-12-23 19:50:57 +010020#include <linux/pci.h>
21#include <sound/control.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include "oxygen.h"
26
Clemens Ladischd55d7a12008-05-13 09:25:39 +020027/* most DMA channels have a 16-bit counter for 32-bit words */
28#define BUFFER_BYTES_MAX ((1 << 16) * 4)
29/* the multichannel DMA channel has a 24-bit counter */
30#define BUFFER_BYTES_MAX_MULTICH ((1 << 24) * 4)
31
32#define PERIOD_BYTES_MIN 64
33
34#define DEFAULT_BUFFER_BYTES (BUFFER_BYTES_MAX / 2)
35#define DEFAULT_BUFFER_BYTES_MULTICH (1024 * 1024)
36
Clemens Ladischc57cccc2008-01-21 08:54:06 +010037static const struct snd_pcm_hardware oxygen_stereo_hardware = {
38 .info = SNDRV_PCM_INFO_MMAP |
39 SNDRV_PCM_INFO_MMAP_VALID |
40 SNDRV_PCM_INFO_INTERLEAVED |
41 SNDRV_PCM_INFO_PAUSE |
Clemens Ladisch075140e2010-11-15 10:50:37 +010042 SNDRV_PCM_INFO_SYNC_START |
43 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
Clemens Ladischc57cccc2008-01-21 08:54:06 +010044 .formats = SNDRV_PCM_FMTBIT_S16_LE |
45 SNDRV_PCM_FMTBIT_S32_LE,
46 .rates = SNDRV_PCM_RATE_32000 |
47 SNDRV_PCM_RATE_44100 |
48 SNDRV_PCM_RATE_48000 |
49 SNDRV_PCM_RATE_64000 |
50 SNDRV_PCM_RATE_88200 |
51 SNDRV_PCM_RATE_96000 |
52 SNDRV_PCM_RATE_176400 |
53 SNDRV_PCM_RATE_192000,
54 .rate_min = 32000,
55 .rate_max = 192000,
56 .channels_min = 2,
57 .channels_max = 2,
Clemens Ladischd55d7a12008-05-13 09:25:39 +020058 .buffer_bytes_max = BUFFER_BYTES_MAX,
59 .period_bytes_min = PERIOD_BYTES_MIN,
Clemens Ladisch93943be2010-10-06 10:57:11 +020060 .period_bytes_max = BUFFER_BYTES_MAX,
61 .periods_min = 1,
Clemens Ladischd55d7a12008-05-13 09:25:39 +020062 .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
Clemens Ladischc57cccc2008-01-21 08:54:06 +010063};
64static const struct snd_pcm_hardware oxygen_multichannel_hardware = {
65 .info = SNDRV_PCM_INFO_MMAP |
66 SNDRV_PCM_INFO_MMAP_VALID |
67 SNDRV_PCM_INFO_INTERLEAVED |
68 SNDRV_PCM_INFO_PAUSE |
Clemens Ladisch075140e2010-11-15 10:50:37 +010069 SNDRV_PCM_INFO_SYNC_START |
70 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
Clemens Ladischc57cccc2008-01-21 08:54:06 +010071 .formats = SNDRV_PCM_FMTBIT_S16_LE |
72 SNDRV_PCM_FMTBIT_S32_LE,
73 .rates = SNDRV_PCM_RATE_32000 |
74 SNDRV_PCM_RATE_44100 |
75 SNDRV_PCM_RATE_48000 |
76 SNDRV_PCM_RATE_64000 |
77 SNDRV_PCM_RATE_88200 |
78 SNDRV_PCM_RATE_96000 |
79 SNDRV_PCM_RATE_176400 |
80 SNDRV_PCM_RATE_192000,
81 .rate_min = 32000,
82 .rate_max = 192000,
83 .channels_min = 2,
84 .channels_max = 8,
Clemens Ladischd55d7a12008-05-13 09:25:39 +020085 .buffer_bytes_max = BUFFER_BYTES_MAX_MULTICH,
86 .period_bytes_min = PERIOD_BYTES_MIN,
Clemens Ladisch93943be2010-10-06 10:57:11 +020087 .period_bytes_max = BUFFER_BYTES_MAX_MULTICH,
88 .periods_min = 1,
Clemens Ladischd55d7a12008-05-13 09:25:39 +020089 .periods_max = BUFFER_BYTES_MAX_MULTICH / PERIOD_BYTES_MIN,
Clemens Ladischc57cccc2008-01-21 08:54:06 +010090};
91static const struct snd_pcm_hardware oxygen_ac97_hardware = {
92 .info = SNDRV_PCM_INFO_MMAP |
93 SNDRV_PCM_INFO_MMAP_VALID |
94 SNDRV_PCM_INFO_INTERLEAVED |
95 SNDRV_PCM_INFO_PAUSE |
Clemens Ladisch075140e2010-11-15 10:50:37 +010096 SNDRV_PCM_INFO_SYNC_START |
97 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
Clemens Ladischc57cccc2008-01-21 08:54:06 +010098 .formats = SNDRV_PCM_FMTBIT_S16_LE,
99 .rates = SNDRV_PCM_RATE_48000,
100 .rate_min = 48000,
101 .rate_max = 48000,
102 .channels_min = 2,
103 .channels_max = 2,
Clemens Ladischd55d7a12008-05-13 09:25:39 +0200104 .buffer_bytes_max = BUFFER_BYTES_MAX,
105 .period_bytes_min = PERIOD_BYTES_MIN,
Clemens Ladisch93943be2010-10-06 10:57:11 +0200106 .period_bytes_max = BUFFER_BYTES_MAX,
107 .periods_min = 1,
Clemens Ladischd55d7a12008-05-13 09:25:39 +0200108 .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
Clemens Ladischc57cccc2008-01-21 08:54:06 +0100109};
110
111static const struct snd_pcm_hardware *const oxygen_hardware[PCM_COUNT] = {
112 [PCM_A] = &oxygen_stereo_hardware,
113 [PCM_B] = &oxygen_stereo_hardware,
114 [PCM_C] = &oxygen_stereo_hardware,
115 [PCM_SPDIF] = &oxygen_stereo_hardware,
116 [PCM_MULTICH] = &oxygen_multichannel_hardware,
117 [PCM_AC97] = &oxygen_ac97_hardware,
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100118};
119
Clemens Ladisch740eb832008-01-04 09:22:20 +0100120static inline unsigned int
121oxygen_substream_channel(struct snd_pcm_substream *substream)
122{
123 return (unsigned int)(uintptr_t)substream->runtime->private_data;
124}
125
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100126static int oxygen_open(struct snd_pcm_substream *substream,
127 unsigned int channel)
128{
129 struct oxygen *chip = snd_pcm_substream_chip(substream);
130 struct snd_pcm_runtime *runtime = substream->runtime;
131 int err;
132
Clemens Ladisch740eb832008-01-04 09:22:20 +0100133 runtime->private_data = (void *)(uintptr_t)channel;
Clemens Ladisch5f7b9b42008-01-28 08:35:47 +0100134 if (channel == PCM_B && chip->has_ac97_1 &&
Clemens Ladischd76596b2008-09-22 09:02:08 +0200135 (chip->model.device_config & CAPTURE_2_FROM_AC97_1))
Clemens Ladisch5f7b9b42008-01-28 08:35:47 +0100136 runtime->hw = oxygen_ac97_hardware;
137 else
138 runtime->hw = *oxygen_hardware[channel];
Clemens Ladisch976cd622008-01-25 08:37:49 +0100139 switch (channel) {
140 case PCM_C:
Clemens Ladisch33c646e2008-01-24 08:43:16 +0100141 runtime->hw.rates &= ~(SNDRV_PCM_RATE_32000 |
142 SNDRV_PCM_RATE_64000);
143 runtime->hw.rate_min = 44100;
Clemens Ladisch976cd622008-01-25 08:37:49 +0100144 break;
145 case PCM_MULTICH:
Clemens Ladisch9bd6a732008-09-22 08:55:19 +0200146 runtime->hw.channels_max = chip->model.dac_channels;
Clemens Ladisch976cd622008-01-25 08:37:49 +0100147 break;
Clemens Ladisch33c646e2008-01-24 08:43:16 +0100148 }
Clemens Ladisch9bd6a732008-09-22 08:55:19 +0200149 if (chip->model.pcm_hardware_filter)
150 chip->model.pcm_hardware_filter(channel, &runtime->hw);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100151 err = snd_pcm_hw_constraint_step(runtime, 0,
152 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
153 if (err < 0)
154 return err;
155 err = snd_pcm_hw_constraint_step(runtime, 0,
156 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
157 if (err < 0)
158 return err;
159 if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) {
160 err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
161 if (err < 0)
162 return err;
163 }
164 if (runtime->hw.channels_max > 2) {
165 err = snd_pcm_hw_constraint_step(runtime, 0,
166 SNDRV_PCM_HW_PARAM_CHANNELS,
167 2);
168 if (err < 0)
169 return err;
170 }
Clemens Ladischca1f30a2008-05-13 09:26:01 +0200171 if (channel == PCM_MULTICH) {
172 err = snd_pcm_hw_constraint_minmax
173 (runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 0, 8192000);
174 if (err < 0)
175 return err;
176 }
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100177 snd_pcm_set_sync(substream);
178 chip->streams[channel] = substream;
179
180 mutex_lock(&chip->mutex);
181 chip->pcm_active |= 1 << channel;
182 if (channel == PCM_SPDIF) {
183 chip->spdif_pcm_bits = chip->spdif_bits;
Clemens Ladisch01a3aff2008-01-14 08:56:01 +0100184 chip->controls[CONTROL_SPDIF_PCM]->vd[0].access &=
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100185 ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
186 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
187 SNDRV_CTL_EVENT_MASK_INFO,
Clemens Ladisch01a3aff2008-01-14 08:56:01 +0100188 &chip->controls[CONTROL_SPDIF_PCM]->id);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100189 }
190 mutex_unlock(&chip->mutex);
191
192 return 0;
193}
194
195static int oxygen_rec_a_open(struct snd_pcm_substream *substream)
196{
197 return oxygen_open(substream, PCM_A);
198}
199
200static int oxygen_rec_b_open(struct snd_pcm_substream *substream)
201{
202 return oxygen_open(substream, PCM_B);
203}
204
205static int oxygen_rec_c_open(struct snd_pcm_substream *substream)
206{
207 return oxygen_open(substream, PCM_C);
208}
209
210static int oxygen_spdif_open(struct snd_pcm_substream *substream)
211{
212 return oxygen_open(substream, PCM_SPDIF);
213}
214
215static int oxygen_multich_open(struct snd_pcm_substream *substream)
216{
217 return oxygen_open(substream, PCM_MULTICH);
218}
219
220static int oxygen_ac97_open(struct snd_pcm_substream *substream)
221{
222 return oxygen_open(substream, PCM_AC97);
223}
224
225static int oxygen_close(struct snd_pcm_substream *substream)
226{
227 struct oxygen *chip = snd_pcm_substream_chip(substream);
Clemens Ladisch740eb832008-01-04 09:22:20 +0100228 unsigned int channel = oxygen_substream_channel(substream);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100229
230 mutex_lock(&chip->mutex);
231 chip->pcm_active &= ~(1 << channel);
232 if (channel == PCM_SPDIF) {
Clemens Ladisch01a3aff2008-01-14 08:56:01 +0100233 chip->controls[CONTROL_SPDIF_PCM]->vd[0].access |=
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100234 SNDRV_CTL_ELEM_ACCESS_INACTIVE;
235 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
236 SNDRV_CTL_EVENT_MASK_INFO,
Clemens Ladisch01a3aff2008-01-14 08:56:01 +0100237 &chip->controls[CONTROL_SPDIF_PCM]->id);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100238 }
239 if (channel == PCM_SPDIF || channel == PCM_MULTICH)
240 oxygen_update_spdif_source(chip);
241 mutex_unlock(&chip->mutex);
242
243 chip->streams[channel] = NULL;
244 return 0;
245}
246
247static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params)
248{
249 if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
250 return OXYGEN_FORMAT_24;
251 else
252 return OXYGEN_FORMAT_16;
253}
254
255static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
256{
257 switch (params_rate(hw_params)) {
258 case 32000:
259 return OXYGEN_RATE_32000;
260 case 44100:
261 return OXYGEN_RATE_44100;
262 default: /* 48000 */
263 return OXYGEN_RATE_48000;
264 case 64000:
265 return OXYGEN_RATE_64000;
266 case 88200:
267 return OXYGEN_RATE_88200;
268 case 96000:
269 return OXYGEN_RATE_96000;
270 case 176400:
271 return OXYGEN_RATE_176400;
272 case 192000:
273 return OXYGEN_RATE_192000;
274 }
275}
276
Clemens Ladisch76ffe1e2009-09-28 11:20:11 +0200277unsigned int oxygen_default_i2s_mclk(struct oxygen *chip,
278 unsigned int channel,
279 struct snd_pcm_hw_params *hw_params)
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100280{
Clemens Ladischb78e3db2008-01-25 08:39:26 +0100281 if (params_rate(hw_params) <= 96000)
282 return OXYGEN_I2S_MCLK_256;
283 else
284 return OXYGEN_I2S_MCLK_128;
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100285}
Clemens Ladisch76ffe1e2009-09-28 11:20:11 +0200286EXPORT_SYMBOL(oxygen_default_i2s_mclk);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100287
Clemens Ladisch05855ba2008-01-17 09:05:09 +0100288static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params)
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100289{
290 if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
Clemens Ladisch05855ba2008-01-17 09:05:09 +0100291 return OXYGEN_I2S_BITS_24;
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100292 else
Clemens Ladisch05855ba2008-01-17 09:05:09 +0100293 return OXYGEN_I2S_BITS_16;
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100294}
295
296static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params)
297{
298 switch (params_channels(hw_params)) {
299 default: /* 2 */
300 return OXYGEN_PLAY_CHANNELS_2;
301 case 4:
302 return OXYGEN_PLAY_CHANNELS_4;
303 case 6:
304 return OXYGEN_PLAY_CHANNELS_6;
305 case 8:
306 return OXYGEN_PLAY_CHANNELS_8;
307 }
308}
309
310static const unsigned int channel_base_registers[PCM_COUNT] = {
311 [PCM_A] = OXYGEN_DMA_A_ADDRESS,
312 [PCM_B] = OXYGEN_DMA_B_ADDRESS,
313 [PCM_C] = OXYGEN_DMA_C_ADDRESS,
314 [PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS,
315 [PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS,
316 [PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS,
317};
318
319static int oxygen_hw_params(struct snd_pcm_substream *substream,
320 struct snd_pcm_hw_params *hw_params)
321{
322 struct oxygen *chip = snd_pcm_substream_chip(substream);
Clemens Ladisch740eb832008-01-04 09:22:20 +0100323 unsigned int channel = oxygen_substream_channel(substream);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100324 int err;
325
326 err = snd_pcm_lib_malloc_pages(substream,
327 params_buffer_bytes(hw_params));
328 if (err < 0)
329 return err;
330
331 oxygen_write32(chip, channel_base_registers[channel],
332 (u32)substream->runtime->dma_addr);
333 if (channel == PCM_MULTICH) {
334 oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT,
335 params_buffer_bytes(hw_params) / 4 - 1);
336 oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT,
337 params_period_bytes(hw_params) / 4 - 1);
338 } else {
339 oxygen_write16(chip, channel_base_registers[channel] + 4,
340 params_buffer_bytes(hw_params) / 4 - 1);
341 oxygen_write16(chip, channel_base_registers[channel] + 6,
342 params_period_bytes(hw_params) / 4 - 1);
343 }
344 return 0;
345}
346
347static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
348 struct snd_pcm_hw_params *hw_params)
349{
350 struct oxygen *chip = snd_pcm_substream_chip(substream);
351 int err;
352
353 err = oxygen_hw_params(substream, hw_params);
354 if (err < 0)
355 return err;
356
357 spin_lock_irq(&chip->reg_lock);
358 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
359 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT,
360 OXYGEN_REC_FORMAT_A_MASK);
Clemens Ladisch05855ba2008-01-17 09:05:09 +0100361 oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT,
362 oxygen_rate(hw_params) |
Clemens Ladisch76ffe1e2009-09-28 11:20:11 +0200363 chip->model.get_i2s_mclk(chip, PCM_A, hw_params) |
Clemens Ladisch9bd6a732008-09-22 08:55:19 +0200364 chip->model.adc_i2s_format |
Clemens Ladisch05855ba2008-01-17 09:05:09 +0100365 oxygen_i2s_bits(hw_params),
366 OXYGEN_I2S_RATE_MASK |
367 OXYGEN_I2S_FORMAT_MASK |
Clemens Ladischc2353a02008-01-18 09:17:53 +0100368 OXYGEN_I2S_MCLK_MASK |
Clemens Ladisch05855ba2008-01-17 09:05:09 +0100369 OXYGEN_I2S_BITS_MASK);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100370 spin_unlock_irq(&chip->reg_lock);
371
372 mutex_lock(&chip->mutex);
Clemens Ladisch9bd6a732008-09-22 08:55:19 +0200373 chip->model.set_adc_params(chip, hw_params);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100374 mutex_unlock(&chip->mutex);
375 return 0;
376}
377
378static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
379 struct snd_pcm_hw_params *hw_params)
380{
381 struct oxygen *chip = snd_pcm_substream_chip(substream);
Clemens Ladisch5f7b9b42008-01-28 08:35:47 +0100382 int is_ac97;
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100383 int err;
384
385 err = oxygen_hw_params(substream, hw_params);
386 if (err < 0)
387 return err;
388
Clemens Ladisch5f7b9b42008-01-28 08:35:47 +0100389 is_ac97 = chip->has_ac97_1 &&
Clemens Ladischd76596b2008-09-22 09:02:08 +0200390 (chip->model.device_config & CAPTURE_2_FROM_AC97_1);
Clemens Ladisch5f7b9b42008-01-28 08:35:47 +0100391
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100392 spin_lock_irq(&chip->reg_lock);
393 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
394 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT,
395 OXYGEN_REC_FORMAT_B_MASK);
Clemens Ladisch5f7b9b42008-01-28 08:35:47 +0100396 if (!is_ac97)
397 oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT,
398 oxygen_rate(hw_params) |
Clemens Ladisch76ffe1e2009-09-28 11:20:11 +0200399 chip->model.get_i2s_mclk(chip, PCM_B,
400 hw_params) |
Clemens Ladisch9bd6a732008-09-22 08:55:19 +0200401 chip->model.adc_i2s_format |
Clemens Ladisch5f7b9b42008-01-28 08:35:47 +0100402 oxygen_i2s_bits(hw_params),
403 OXYGEN_I2S_RATE_MASK |
404 OXYGEN_I2S_FORMAT_MASK |
405 OXYGEN_I2S_MCLK_MASK |
406 OXYGEN_I2S_BITS_MASK);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100407 spin_unlock_irq(&chip->reg_lock);
408
Clemens Ladisch5f7b9b42008-01-28 08:35:47 +0100409 if (!is_ac97) {
410 mutex_lock(&chip->mutex);
Clemens Ladisch9bd6a732008-09-22 08:55:19 +0200411 chip->model.set_adc_params(chip, hw_params);
Clemens Ladisch5f7b9b42008-01-28 08:35:47 +0100412 mutex_unlock(&chip->mutex);
413 }
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100414 return 0;
415}
416
417static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream,
418 struct snd_pcm_hw_params *hw_params)
419{
420 struct oxygen *chip = snd_pcm_substream_chip(substream);
421 int err;
422
423 err = oxygen_hw_params(substream, hw_params);
424 if (err < 0)
425 return err;
426
427 spin_lock_irq(&chip->reg_lock);
428 oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
429 oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
430 OXYGEN_REC_FORMAT_C_MASK);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100431 spin_unlock_irq(&chip->reg_lock);
432 return 0;
433}
434
435static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream,
436 struct snd_pcm_hw_params *hw_params)
437{
438 struct oxygen *chip = snd_pcm_substream_chip(substream);
439 int err;
440
441 err = oxygen_hw_params(substream, hw_params);
442 if (err < 0)
443 return err;
444
Clemens Ladisch3d8bb452009-09-28 11:16:41 +0200445 mutex_lock(&chip->mutex);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100446 spin_lock_irq(&chip->reg_lock);
447 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
448 OXYGEN_SPDIF_OUT_ENABLE);
449 oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
450 oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT,
451 OXYGEN_SPDIF_FORMAT_MASK);
452 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
453 oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT,
454 OXYGEN_SPDIF_OUT_RATE_MASK);
455 oxygen_update_spdif_source(chip);
456 spin_unlock_irq(&chip->reg_lock);
Clemens Ladisch3d8bb452009-09-28 11:16:41 +0200457 mutex_unlock(&chip->mutex);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100458 return 0;
459}
460
461static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
462 struct snd_pcm_hw_params *hw_params)
463{
464 struct oxygen *chip = snd_pcm_substream_chip(substream);
465 int err;
466
467 err = oxygen_hw_params(substream, hw_params);
468 if (err < 0)
469 return err;
470
Clemens Ladisch3d8bb452009-09-28 11:16:41 +0200471 mutex_lock(&chip->mutex);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100472 spin_lock_irq(&chip->reg_lock);
473 oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS,
474 oxygen_play_channels(hw_params),
475 OXYGEN_PLAY_CHANNELS_MASK);
476 oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
477 oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT,
478 OXYGEN_MULTICH_FORMAT_MASK);
479 oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT,
Clemens Ladisch05855ba2008-01-17 09:05:09 +0100480 oxygen_rate(hw_params) |
Clemens Ladisch9bd6a732008-09-22 08:55:19 +0200481 chip->model.dac_i2s_format |
Clemens Ladisch76ffe1e2009-09-28 11:20:11 +0200482 chip->model.get_i2s_mclk(chip, PCM_MULTICH,
483 hw_params) |
Clemens Ladisch05855ba2008-01-17 09:05:09 +0100484 oxygen_i2s_bits(hw_params),
485 OXYGEN_I2S_RATE_MASK |
486 OXYGEN_I2S_FORMAT_MASK |
Clemens Ladischb91ab722009-09-01 08:23:58 +0200487 OXYGEN_I2S_MCLK_MASK |
Clemens Ladisch05855ba2008-01-17 09:05:09 +0100488 OXYGEN_I2S_BITS_MASK);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100489 oxygen_update_spdif_source(chip);
490 spin_unlock_irq(&chip->reg_lock);
491
Clemens Ladisch9bd6a732008-09-22 08:55:19 +0200492 chip->model.set_dac_params(chip, hw_params);
Clemens Ladisch3d8bb452009-09-28 11:16:41 +0200493 oxygen_update_dac_routing(chip);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100494 mutex_unlock(&chip->mutex);
495 return 0;
496}
497
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100498static int oxygen_hw_free(struct snd_pcm_substream *substream)
499{
500 struct oxygen *chip = snd_pcm_substream_chip(substream);
Clemens Ladisch740eb832008-01-04 09:22:20 +0100501 unsigned int channel = oxygen_substream_channel(substream);
Clemens Ladisch345c03e2009-05-25 10:05:00 +0200502 unsigned int channel_mask = 1 << channel;
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100503
504 spin_lock_irq(&chip->reg_lock);
Clemens Ladisch345c03e2009-05-25 10:05:00 +0200505 chip->interrupt_mask &= ~channel_mask;
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100506 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
Clemens Ladisch345c03e2009-05-25 10:05:00 +0200507
508 oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
509 oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100510 spin_unlock_irq(&chip->reg_lock);
511
512 return snd_pcm_lib_free_pages(substream);
513}
514
515static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream)
516{
517 struct oxygen *chip = snd_pcm_substream_chip(substream);
518
519 spin_lock_irq(&chip->reg_lock);
520 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
521 OXYGEN_SPDIF_OUT_ENABLE);
522 spin_unlock_irq(&chip->reg_lock);
523 return oxygen_hw_free(substream);
524}
525
526static int oxygen_prepare(struct snd_pcm_substream *substream)
527{
528 struct oxygen *chip = snd_pcm_substream_chip(substream);
Clemens Ladisch740eb832008-01-04 09:22:20 +0100529 unsigned int channel = oxygen_substream_channel(substream);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100530 unsigned int channel_mask = 1 << channel;
531
532 spin_lock_irq(&chip->reg_lock);
533 oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
534 oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
535
Clemens Ladisch075140e2010-11-15 10:50:37 +0100536 if (substream->runtime->no_period_wakeup)
537 chip->interrupt_mask &= ~channel_mask;
538 else
539 chip->interrupt_mask |= channel_mask;
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100540 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
541 spin_unlock_irq(&chip->reg_lock);
542 return 0;
543}
544
545static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd)
546{
547 struct oxygen *chip = snd_pcm_substream_chip(substream);
548 struct snd_pcm_substream *s;
549 unsigned int mask = 0;
Clemens Ladischdb2396d2008-01-21 08:44:52 +0100550 int pausing;
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100551
552 switch (cmd) {
553 case SNDRV_PCM_TRIGGER_STOP:
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100554 case SNDRV_PCM_TRIGGER_START:
Clemens Ladisch4a4bc532008-05-13 09:24:39 +0200555 case SNDRV_PCM_TRIGGER_SUSPEND:
Clemens Ladischdb2396d2008-01-21 08:44:52 +0100556 pausing = 0;
557 break;
558 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100559 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Clemens Ladischdb2396d2008-01-21 08:44:52 +0100560 pausing = 1;
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100561 break;
562 default:
563 return -EINVAL;
564 }
565
566 snd_pcm_group_for_each_entry(s, substream) {
567 if (snd_pcm_substream_chip(s) == chip) {
Clemens Ladisch740eb832008-01-04 09:22:20 +0100568 mask |= 1 << oxygen_substream_channel(s);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100569 snd_pcm_trigger_done(s, substream);
570 }
571 }
572
573 spin_lock(&chip->reg_lock);
Clemens Ladischdb2396d2008-01-21 08:44:52 +0100574 if (!pausing) {
575 if (cmd == SNDRV_PCM_TRIGGER_START)
576 chip->pcm_running |= mask;
577 else
578 chip->pcm_running &= ~mask;
579 oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running);
580 } else {
581 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
582 oxygen_set_bits8(chip, OXYGEN_DMA_PAUSE, mask);
583 else
584 oxygen_clear_bits8(chip, OXYGEN_DMA_PAUSE, mask);
585 }
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100586 spin_unlock(&chip->reg_lock);
587 return 0;
588}
589
590static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream)
591{
592 struct oxygen *chip = snd_pcm_substream_chip(substream);
593 struct snd_pcm_runtime *runtime = substream->runtime;
Clemens Ladisch740eb832008-01-04 09:22:20 +0100594 unsigned int channel = oxygen_substream_channel(substream);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100595 u32 curr_addr;
596
597 /* no spinlock, this read should be atomic */
598 curr_addr = oxygen_read32(chip, channel_base_registers[channel]);
599 return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr);
600}
601
602static struct snd_pcm_ops oxygen_rec_a_ops = {
603 .open = oxygen_rec_a_open,
604 .close = oxygen_close,
605 .ioctl = snd_pcm_lib_ioctl,
606 .hw_params = oxygen_rec_a_hw_params,
607 .hw_free = oxygen_hw_free,
608 .prepare = oxygen_prepare,
609 .trigger = oxygen_trigger,
610 .pointer = oxygen_pointer,
611};
612
613static struct snd_pcm_ops oxygen_rec_b_ops = {
614 .open = oxygen_rec_b_open,
615 .close = oxygen_close,
616 .ioctl = snd_pcm_lib_ioctl,
617 .hw_params = oxygen_rec_b_hw_params,
618 .hw_free = oxygen_hw_free,
619 .prepare = oxygen_prepare,
620 .trigger = oxygen_trigger,
621 .pointer = oxygen_pointer,
622};
623
624static struct snd_pcm_ops oxygen_rec_c_ops = {
625 .open = oxygen_rec_c_open,
626 .close = oxygen_close,
627 .ioctl = snd_pcm_lib_ioctl,
628 .hw_params = oxygen_rec_c_hw_params,
629 .hw_free = oxygen_hw_free,
630 .prepare = oxygen_prepare,
631 .trigger = oxygen_trigger,
632 .pointer = oxygen_pointer,
633};
634
635static struct snd_pcm_ops oxygen_spdif_ops = {
636 .open = oxygen_spdif_open,
637 .close = oxygen_close,
638 .ioctl = snd_pcm_lib_ioctl,
639 .hw_params = oxygen_spdif_hw_params,
640 .hw_free = oxygen_spdif_hw_free,
641 .prepare = oxygen_prepare,
642 .trigger = oxygen_trigger,
643 .pointer = oxygen_pointer,
644};
645
646static struct snd_pcm_ops oxygen_multich_ops = {
647 .open = oxygen_multich_open,
648 .close = oxygen_close,
649 .ioctl = snd_pcm_lib_ioctl,
650 .hw_params = oxygen_multich_hw_params,
651 .hw_free = oxygen_hw_free,
652 .prepare = oxygen_prepare,
653 .trigger = oxygen_trigger,
654 .pointer = oxygen_pointer,
655};
656
657static struct snd_pcm_ops oxygen_ac97_ops = {
658 .open = oxygen_ac97_open,
659 .close = oxygen_close,
660 .ioctl = snd_pcm_lib_ioctl,
Clemens Ladischc2353a02008-01-18 09:17:53 +0100661 .hw_params = oxygen_hw_params,
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100662 .hw_free = oxygen_hw_free,
663 .prepare = oxygen_prepare,
664 .trigger = oxygen_trigger,
665 .pointer = oxygen_pointer,
666};
667
668static void oxygen_pcm_free(struct snd_pcm *pcm)
669{
670 snd_pcm_lib_preallocate_free_for_all(pcm);
671}
672
Takashi Iwaif007dc02008-02-22 18:35:22 +0100673int oxygen_pcm_init(struct oxygen *chip)
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100674{
675 struct snd_pcm *pcm;
Clemens Ladische85e0922008-01-16 08:30:38 +0100676 int outs, ins;
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100677 int err;
678
Clemens Ladischd76596b2008-09-22 09:02:08 +0200679 outs = !!(chip->model.device_config & PLAYBACK_0_TO_I2S);
680 ins = !!(chip->model.device_config & (CAPTURE_0_FROM_I2S_1 |
681 CAPTURE_0_FROM_I2S_2));
Clemens Ladischf009ad92008-03-19 08:19:41 +0100682 if (outs | ins) {
Clemens Ladisch79c50e22008-09-22 09:07:53 +0200683 err = snd_pcm_new(chip->card, "Multichannel",
684 0, outs, ins, &pcm);
Clemens Ladischf009ad92008-03-19 08:19:41 +0100685 if (err < 0)
686 return err;
687 if (outs)
688 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
689 &oxygen_multich_ops);
Clemens Ladischd76596b2008-09-22 09:02:08 +0200690 if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
Clemens Ladischf009ad92008-03-19 08:19:41 +0100691 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
692 &oxygen_rec_a_ops);
Clemens Ladischd76596b2008-09-22 09:02:08 +0200693 else if (chip->model.device_config & CAPTURE_0_FROM_I2S_2)
Clemens Ladischf009ad92008-03-19 08:19:41 +0100694 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
695 &oxygen_rec_b_ops);
696 pcm->private_data = chip;
697 pcm->private_free = oxygen_pcm_free;
Clemens Ladisch79c50e22008-09-22 09:07:53 +0200698 strcpy(pcm->name, "Multichannel");
Clemens Ladischf009ad92008-03-19 08:19:41 +0100699 if (outs)
700 snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
701 SNDRV_DMA_TYPE_DEV,
702 snd_dma_pci_data(chip->pci),
Clemens Ladischd55d7a12008-05-13 09:25:39 +0200703 DEFAULT_BUFFER_BYTES_MULTICH,
704 BUFFER_BYTES_MAX_MULTICH);
Clemens Ladischf009ad92008-03-19 08:19:41 +0100705 if (ins)
706 snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
707 SNDRV_DMA_TYPE_DEV,
708 snd_dma_pci_data(chip->pci),
Clemens Ladischd55d7a12008-05-13 09:25:39 +0200709 DEFAULT_BUFFER_BYTES,
710 BUFFER_BYTES_MAX);
Clemens Ladischf009ad92008-03-19 08:19:41 +0100711 }
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100712
Clemens Ladischd76596b2008-09-22 09:02:08 +0200713 outs = !!(chip->model.device_config & PLAYBACK_1_TO_SPDIF);
714 ins = !!(chip->model.device_config & CAPTURE_1_FROM_SPDIF);
Clemens Ladische85e0922008-01-16 08:30:38 +0100715 if (outs | ins) {
716 err = snd_pcm_new(chip->card, "Digital", 1, outs, ins, &pcm);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100717 if (err < 0)
718 return err;
Clemens Ladische85e0922008-01-16 08:30:38 +0100719 if (outs)
720 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
721 &oxygen_spdif_ops);
722 if (ins)
723 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
724 &oxygen_rec_c_ops);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100725 pcm->private_data = chip;
726 pcm->private_free = oxygen_pcm_free;
Clemens Ladische85e0922008-01-16 08:30:38 +0100727 strcpy(pcm->name, "Digital");
728 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
729 snd_dma_pci_data(chip->pci),
Clemens Ladischd55d7a12008-05-13 09:25:39 +0200730 DEFAULT_BUFFER_BYTES,
731 BUFFER_BYTES_MAX);
Clemens Ladische85e0922008-01-16 08:30:38 +0100732 }
733
Clemens Ladischf009ad92008-03-19 08:19:41 +0100734 if (chip->has_ac97_1) {
Clemens Ladischd76596b2008-09-22 09:02:08 +0200735 outs = !!(chip->model.device_config & PLAYBACK_2_TO_AC97_1);
736 ins = !!(chip->model.device_config & CAPTURE_2_FROM_AC97_1);
Clemens Ladischf009ad92008-03-19 08:19:41 +0100737 } else {
738 outs = 0;
Clemens Ladischd76596b2008-09-22 09:02:08 +0200739 ins = !!(chip->model.device_config & CAPTURE_2_FROM_I2S_2);
Clemens Ladischf009ad92008-03-19 08:19:41 +0100740 }
Clemens Ladische85e0922008-01-16 08:30:38 +0100741 if (outs | ins) {
Clemens Ladisch5f7b9b42008-01-28 08:35:47 +0100742 err = snd_pcm_new(chip->card, outs ? "AC97" : "Analog2",
Clemens Ladische85e0922008-01-16 08:30:38 +0100743 2, outs, ins, &pcm);
744 if (err < 0)
745 return err;
Clemens Ladisch5f7b9b42008-01-28 08:35:47 +0100746 if (outs) {
Clemens Ladische85e0922008-01-16 08:30:38 +0100747 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
748 &oxygen_ac97_ops);
Clemens Ladisch5f7b9b42008-01-28 08:35:47 +0100749 oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
750 OXYGEN_REC_B_ROUTE_AC97_1,
751 OXYGEN_REC_B_ROUTE_MASK);
752 }
Clemens Ladische85e0922008-01-16 08:30:38 +0100753 if (ins)
754 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
755 &oxygen_rec_b_ops);
756 pcm->private_data = chip;
757 pcm->private_free = oxygen_pcm_free;
Clemens Ladisch5f7b9b42008-01-28 08:35:47 +0100758 strcpy(pcm->name, outs ? "Front Panel" : "Analog 2");
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100759 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
760 snd_dma_pci_data(chip->pci),
Clemens Ladischd55d7a12008-05-13 09:25:39 +0200761 DEFAULT_BUFFER_BYTES,
762 BUFFER_BYTES_MAX);
Clemens Ladischd0ce9942007-12-23 19:50:57 +0100763 }
764 return 0;
765}