blob: 7f669a997aa6ca8b1646cd456e5a0d1991e5e0cc [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Support for IDE interfaces on PowerMacs.
Bartlomiej Zolnierkiewicz58f189f2008-02-01 23:09:33 +01003 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * These IDE interfaces are memory-mapped and have a DBDMA channel
5 * for doing DMA.
6 *
7 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +02008 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 * Some code taken from drivers/ide/ide-dma.c:
16 *
17 * Copyright (c) 1995-1998 Mark Lord
18 *
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
22 * big table
23 *
24 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070025#include <linux/types.h>
26#include <linux/kernel.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/ide.h>
30#include <linux/notifier.h>
31#include <linux/reboot.h>
32#include <linux/pci.h>
33#include <linux/adb.h>
34#include <linux/pmu.h>
35#include <linux/scatterlist.h>
36
37#include <asm/prom.h>
38#include <asm/io.h>
39#include <asm/dbdma.h>
40#include <asm/ide.h>
41#include <asm/pci-bridge.h>
42#include <asm/machdep.h>
43#include <asm/pmac_feature.h>
44#include <asm/sections.h>
45#include <asm/irq.h>
46
47#ifndef CONFIG_PPC64
48#include <asm/mediabay.h>
49#endif
50
Andrew Morton9e5755b2007-03-03 17:48:54 +010051#include "../ide-timing.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
53#undef IDE_PMAC_DEBUG
54
55#define DMA_WAIT_TIMEOUT 50
56
57typedef struct pmac_ide_hwif {
58 unsigned long regbase;
59 int irq;
60 int kind;
61 int aapl_bus_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -070062 unsigned mediabay : 1;
63 unsigned broken_dma : 1;
64 unsigned broken_dma_warn : 1;
65 struct device_node* node;
66 struct macio_dev *mdev;
67 u32 timings[4];
68 volatile u32 __iomem * *kauai_fcr;
69#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
70 /* Those fields are duplicating what is in hwif. We currently
71 * can't use the hwif ones because of some assumptions that are
72 * beeing done by the generic code about the kind of dma controller
73 * and format of the dma table. This will have to be fixed though.
74 */
75 volatile struct dbdma_regs __iomem * dma_regs;
76 struct dbdma_cmd* dma_table_cpu;
77#endif
78
79} pmac_ide_hwif_t;
80
Linus Torvalds1da177e2005-04-16 15:20:36 -070081enum {
82 controller_ohare, /* OHare based */
83 controller_heathrow, /* Heathrow/Paddington */
84 controller_kl_ata3, /* KeyLargo ATA-3 */
85 controller_kl_ata4, /* KeyLargo ATA-4 */
86 controller_un_ata6, /* UniNorth2 ATA-6 */
87 controller_k2_ata6, /* K2 ATA-6 */
88 controller_sh_ata6, /* Shasta ATA-6 */
89};
90
91static const char* model_name[] = {
92 "OHare ATA", /* OHare based */
93 "Heathrow ATA", /* Heathrow/Paddington */
94 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
95 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
96 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
97 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
98 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
99};
100
101/*
102 * Extra registers, both 32-bit little-endian
103 */
104#define IDE_TIMING_CONFIG 0x200
105#define IDE_INTERRUPT 0x300
106
107/* Kauai (U2) ATA has different register setup */
108#define IDE_KAUAI_PIO_CONFIG 0x200
109#define IDE_KAUAI_ULTRA_CONFIG 0x210
110#define IDE_KAUAI_POLL_CONFIG 0x220
111
112/*
113 * Timing configuration register definitions
114 */
115
116/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
117#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
118#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
119#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
120#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
121
122/* 133Mhz cell, found in shasta.
123 * See comments about 100 Mhz Uninorth 2...
124 * Note that PIO_MASK and MDMA_MASK seem to overlap
125 */
126#define TR_133_PIOREG_PIO_MASK 0xff000fff
127#define TR_133_PIOREG_MDMA_MASK 0x00fff800
128#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
129#define TR_133_UDMAREG_UDMA_EN 0x00000001
130
131/* 100Mhz cell, found in Uninorth 2. I don't have much infos about
132 * this one yet, it appears as a pci device (106b/0033) on uninorth
133 * internal PCI bus and it's clock is controlled like gem or fw. It
134 * appears to be an evolution of keylargo ATA4 with a timing register
135 * extended to 2 32bits registers and a similar DBDMA channel. Other
136 * registers seem to exist but I can't tell much about them.
137 *
138 * So far, I'm using pre-calculated tables for this extracted from
139 * the values used by the MacOS X driver.
140 *
141 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
142 * register controls the UDMA timings. At least, it seems bit 0
143 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
144 * cycle time in units of 10ns. Bits 8..15 are used by I don't
145 * know their meaning yet
146 */
147#define TR_100_PIOREG_PIO_MASK 0xff000fff
148#define TR_100_PIOREG_MDMA_MASK 0x00fff000
149#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
150#define TR_100_UDMAREG_UDMA_EN 0x00000001
151
152
153/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
154 * 40 connector cable and to 4 on 80 connector one.
155 * Clock unit is 15ns (66Mhz)
156 *
157 * 3 Values can be programmed:
158 * - Write data setup, which appears to match the cycle time. They
159 * also call it DIOW setup.
160 * - Ready to pause time (from spec)
161 * - Address setup. That one is weird. I don't see where exactly
162 * it fits in UDMA cycles, I got it's name from an obscure piece
163 * of commented out code in Darwin. They leave it to 0, we do as
164 * well, despite a comment that would lead to think it has a
165 * min value of 45ns.
166 * Apple also add 60ns to the write data setup (or cycle time ?) on
167 * reads.
168 */
169#define TR_66_UDMA_MASK 0xfff00000
170#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
171#define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
172#define TR_66_UDMA_ADDRSETUP_SHIFT 29
173#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
174#define TR_66_UDMA_RDY2PAUS_SHIFT 25
175#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
176#define TR_66_UDMA_WRDATASETUP_SHIFT 21
177#define TR_66_MDMA_MASK 0x000ffc00
178#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
179#define TR_66_MDMA_RECOVERY_SHIFT 15
180#define TR_66_MDMA_ACCESS_MASK 0x00007c00
181#define TR_66_MDMA_ACCESS_SHIFT 10
182#define TR_66_PIO_MASK 0x000003ff
183#define TR_66_PIO_RECOVERY_MASK 0x000003e0
184#define TR_66_PIO_RECOVERY_SHIFT 5
185#define TR_66_PIO_ACCESS_MASK 0x0000001f
186#define TR_66_PIO_ACCESS_SHIFT 0
187
188/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
189 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
190 *
191 * The access time and recovery time can be programmed. Some older
192 * Darwin code base limit OHare to 150ns cycle time. I decided to do
193 * the same here fore safety against broken old hardware ;)
194 * The HalfTick bit, when set, adds half a clock (15ns) to the access
195 * time and removes one from recovery. It's not supported on KeyLargo
196 * implementation afaik. The E bit appears to be set for PIO mode 0 and
197 * is used to reach long timings used in this mode.
198 */
199#define TR_33_MDMA_MASK 0x003ff800
200#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
201#define TR_33_MDMA_RECOVERY_SHIFT 16
202#define TR_33_MDMA_ACCESS_MASK 0x0000f800
203#define TR_33_MDMA_ACCESS_SHIFT 11
204#define TR_33_MDMA_HALFTICK 0x00200000
205#define TR_33_PIO_MASK 0x000007ff
206#define TR_33_PIO_E 0x00000400
207#define TR_33_PIO_RECOVERY_MASK 0x000003e0
208#define TR_33_PIO_RECOVERY_SHIFT 5
209#define TR_33_PIO_ACCESS_MASK 0x0000001f
210#define TR_33_PIO_ACCESS_SHIFT 0
211
212/*
213 * Interrupt register definitions
214 */
215#define IDE_INTR_DMA 0x80000000
216#define IDE_INTR_DEVICE 0x40000000
217
218/*
219 * FCR Register on Kauai. Not sure what bit 0x4 is ...
220 */
221#define KAUAI_FCR_UATA_MAGIC 0x00000004
222#define KAUAI_FCR_UATA_RESET_N 0x00000002
223#define KAUAI_FCR_UATA_ENABLE 0x00000001
224
225#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
226
227/* Rounded Multiword DMA timings
228 *
229 * I gave up finding a generic formula for all controller
230 * types and instead, built tables based on timing values
231 * used by Apple in Darwin's implementation.
232 */
233struct mdma_timings_t {
234 int accessTime;
235 int recoveryTime;
236 int cycleTime;
237};
238
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500239struct mdma_timings_t mdma_timings_33[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240{
241 { 240, 240, 480 },
242 { 180, 180, 360 },
243 { 135, 135, 270 },
244 { 120, 120, 240 },
245 { 105, 105, 210 },
246 { 90, 90, 180 },
247 { 75, 75, 150 },
248 { 75, 45, 120 },
249 { 0, 0, 0 }
250};
251
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500252struct mdma_timings_t mdma_timings_33k[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253{
254 { 240, 240, 480 },
255 { 180, 180, 360 },
256 { 150, 150, 300 },
257 { 120, 120, 240 },
258 { 90, 120, 210 },
259 { 90, 90, 180 },
260 { 90, 60, 150 },
261 { 90, 30, 120 },
262 { 0, 0, 0 }
263};
264
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500265struct mdma_timings_t mdma_timings_66[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700266{
267 { 240, 240, 480 },
268 { 180, 180, 360 },
269 { 135, 135, 270 },
270 { 120, 120, 240 },
271 { 105, 105, 210 },
272 { 90, 90, 180 },
273 { 90, 75, 165 },
274 { 75, 45, 120 },
275 { 0, 0, 0 }
276};
277
278/* KeyLargo ATA-4 Ultra DMA timings (rounded) */
279struct {
280 int addrSetup; /* ??? */
281 int rdy2pause;
282 int wrDataSetup;
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500283} kl66_udma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700284{
285 { 0, 180, 120 }, /* Mode 0 */
286 { 0, 150, 90 }, /* 1 */
287 { 0, 120, 60 }, /* 2 */
288 { 0, 90, 45 }, /* 3 */
289 { 0, 90, 30 } /* 4 */
290};
291
292/* UniNorth 2 ATA/100 timings */
293struct kauai_timing {
294 int cycle_time;
295 u32 timing_reg;
296};
297
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500298static struct kauai_timing kauai_pio_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299{
300 { 930 , 0x08000fff },
301 { 600 , 0x08000a92 },
302 { 383 , 0x0800060f },
303 { 360 , 0x08000492 },
304 { 330 , 0x0800048f },
305 { 300 , 0x080003cf },
306 { 270 , 0x080003cc },
307 { 240 , 0x0800038b },
308 { 239 , 0x0800030c },
309 { 180 , 0x05000249 },
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +0200310 { 120 , 0x04000148 },
311 { 0 , 0 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312};
313
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500314static struct kauai_timing kauai_mdma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315{
316 { 1260 , 0x00fff000 },
317 { 480 , 0x00618000 },
318 { 360 , 0x00492000 },
319 { 270 , 0x0038e000 },
320 { 240 , 0x0030c000 },
321 { 210 , 0x002cb000 },
322 { 180 , 0x00249000 },
323 { 150 , 0x00209000 },
324 { 120 , 0x00148000 },
325 { 0 , 0 },
326};
327
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500328static struct kauai_timing kauai_udma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329{
330 { 120 , 0x000070c0 },
331 { 90 , 0x00005d80 },
332 { 60 , 0x00004a60 },
333 { 45 , 0x00003a50 },
334 { 30 , 0x00002a30 },
335 { 20 , 0x00002921 },
336 { 0 , 0 },
337};
338
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500339static struct kauai_timing shasta_pio_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340{
341 { 930 , 0x08000fff },
342 { 600 , 0x0A000c97 },
343 { 383 , 0x07000712 },
344 { 360 , 0x040003cd },
345 { 330 , 0x040003cd },
346 { 300 , 0x040003cd },
347 { 270 , 0x040003cd },
348 { 240 , 0x040003cd },
349 { 239 , 0x040003cd },
350 { 180 , 0x0400028b },
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +0200351 { 120 , 0x0400010a },
352 { 0 , 0 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353};
354
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500355static struct kauai_timing shasta_mdma_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356{
357 { 1260 , 0x00fff000 },
358 { 480 , 0x00820800 },
359 { 360 , 0x00820800 },
360 { 270 , 0x00820800 },
361 { 240 , 0x00820800 },
362 { 210 , 0x00820800 },
363 { 180 , 0x00820800 },
364 { 150 , 0x0028b000 },
365 { 120 , 0x001ca000 },
366 { 0 , 0 },
367};
368
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500369static struct kauai_timing shasta_udma133_timings[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370{
371 { 120 , 0x00035901, },
372 { 90 , 0x000348b1, },
373 { 60 , 0x00033881, },
374 { 45 , 0x00033861, },
375 { 30 , 0x00033841, },
376 { 20 , 0x00033031, },
377 { 15 , 0x00033021, },
378 { 0 , 0 },
379};
380
381
382static inline u32
383kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
384{
385 int i;
386
387 for (i=0; table[i].cycle_time; i++)
388 if (cycle_time > table[i+1].cycle_time)
389 return table[i].timing_reg;
Bartlomiej Zolnierkiewicz90a87ea2007-10-13 17:47:48 +0200390 BUG();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391 return 0;
392}
393
394/* allow up to 256 DBDMA commands per xfer */
395#define MAX_DCMDS 256
396
397/*
398 * Wait 1s for disk to answer on IDE bus after a hard reset
399 * of the device (via GPIO/FCR).
400 *
401 * Some devices seem to "pollute" the bus even after dropping
402 * the BSY bit (typically some combo drives slave on the UDMA
403 * bus) after a hard reset. Since we hard reset all drives on
404 * KeyLargo ATA66, we have to keep that delay around. I may end
405 * up not hard resetting anymore on these and keep the delay only
406 * for older interfaces instead (we have to reset when coming
407 * from MacOS...) --BenH.
408 */
409#define IDE_WAKEUP_DELAY (1*HZ)
410
Bartlomiej Zolnierkiewicz0d071922008-04-26 22:25:22 +0200411static int pmac_ide_init_dma(ide_hwif_t *, const struct ide_port_info *);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413static void pmac_ide_selectproc(ide_drive_t *drive);
414static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
415
416#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
417
Bartlomiej Zolnierkiewicz23579a22008-04-18 00:46:26 +0200418#define PMAC_IDE_REG(x) \
Bartlomiej Zolnierkiewicz4c3032d2008-04-27 15:38:32 +0200419 ((void __iomem *)((drive)->hwif->io_ports.data_addr + (x)))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420
421/*
422 * Apply the timings of the proper unit (master/slave) to the shared
423 * timing register when selecting that unit. This version is for
424 * ASICs with a single timing register
425 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500426static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700427pmac_ide_selectproc(ide_drive_t *drive)
428{
429 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
430
431 if (pmif == NULL)
432 return;
433
434 if (drive->select.b.unit & 0x01)
435 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
436 else
437 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
438 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
439}
440
441/*
442 * Apply the timings of the proper unit (master/slave) to the shared
443 * timing register when selecting that unit. This version is for
444 * ASICs with a dual timing register (Kauai)
445 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500446static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447pmac_ide_kauai_selectproc(ide_drive_t *drive)
448{
449 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
450
451 if (pmif == NULL)
452 return;
453
454 if (drive->select.b.unit & 0x01) {
455 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
456 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
457 } else {
458 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
459 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
460 }
461 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
462}
463
464/*
465 * Force an update of controller timing values for a given drive
466 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500467static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700468pmac_ide_do_update_timings(ide_drive_t *drive)
469{
470 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
471
472 if (pmif == NULL)
473 return;
474
475 if (pmif->kind == controller_sh_ata6 ||
476 pmif->kind == controller_un_ata6 ||
477 pmif->kind == controller_k2_ata6)
478 pmac_ide_kauai_selectproc(drive);
479 else
480 pmac_ide_selectproc(drive);
481}
482
483static void
484pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port)
485{
486 u32 tmp;
487
488 writeb(value, (void __iomem *) port);
489 tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
490}
491
492/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700493 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
494 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500495static void
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200496pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700497{
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200498 u32 *timings, t;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700499 unsigned accessTicks, recTicks;
500 unsigned accessTime, recTime;
501 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200502 unsigned int cycle_time;
503
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504 if (pmif == NULL)
505 return;
506
507 /* which drive is it ? */
508 timings = &pmif->timings[drive->select.b.unit & 0x01];
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200509 t = *timings;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700510
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200511 cycle_time = ide_pio_cycle_time(drive, pio);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700512
513 switch (pmif->kind) {
514 case controller_sh_ata6: {
515 /* 133Mhz cell */
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200516 u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200517 t = (t & ~TR_133_PIOREG_PIO_MASK) | tr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700518 break;
519 }
520 case controller_un_ata6:
521 case controller_k2_ata6: {
522 /* 100Mhz cell */
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200523 u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200524 t = (t & ~TR_100_PIOREG_PIO_MASK) | tr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525 break;
526 }
527 case controller_kl_ata4:
528 /* 66Mhz cell */
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200529 recTime = cycle_time - ide_pio_timings[pio].active_time
Linus Torvalds1da177e2005-04-16 15:20:36 -0700530 - ide_pio_timings[pio].setup_time;
531 recTime = max(recTime, 150U);
532 accessTime = ide_pio_timings[pio].active_time;
533 accessTime = max(accessTime, 150U);
534 accessTicks = SYSCLK_TICKS_66(accessTime);
535 accessTicks = min(accessTicks, 0x1fU);
536 recTicks = SYSCLK_TICKS_66(recTime);
537 recTicks = min(recTicks, 0x1fU);
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200538 t = (t & ~TR_66_PIO_MASK) |
539 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
540 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541 break;
542 default: {
543 /* 33Mhz cell */
544 int ebit = 0;
Bartlomiej Zolnierkiewicz7dd00082007-07-20 01:11:56 +0200545 recTime = cycle_time - ide_pio_timings[pio].active_time
Linus Torvalds1da177e2005-04-16 15:20:36 -0700546 - ide_pio_timings[pio].setup_time;
547 recTime = max(recTime, 150U);
548 accessTime = ide_pio_timings[pio].active_time;
549 accessTime = max(accessTime, 150U);
550 accessTicks = SYSCLK_TICKS(accessTime);
551 accessTicks = min(accessTicks, 0x1fU);
552 accessTicks = max(accessTicks, 4U);
553 recTicks = SYSCLK_TICKS(recTime);
554 recTicks = min(recTicks, 0x1fU);
555 recTicks = max(recTicks, 5U) - 4;
556 if (recTicks > 9) {
557 recTicks--; /* guess, but it's only for PIO0, so... */
558 ebit = 1;
559 }
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200560 t = (t & ~TR_33_PIO_MASK) |
Linus Torvalds1da177e2005-04-16 15:20:36 -0700561 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
562 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
563 if (ebit)
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200564 t |= TR_33_PIO_E;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565 break;
566 }
567 }
568
569#ifdef IDE_PMAC_DEBUG
570 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
571 drive->name, pio, *timings);
572#endif
573
Benjamin Herrenschmidt0b46ff22007-10-13 17:47:50 +0200574 *timings = t;
Bartlomiej Zolnierkiewiczc15d5d42007-10-11 23:54:01 +0200575 pmac_ide_do_update_timings(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700576}
577
578#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
579
580/*
581 * Calculate KeyLargo ATA/66 UDMA timings
582 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500583static int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584set_timings_udma_ata4(u32 *timings, u8 speed)
585{
586 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
587
588 if (speed > XFER_UDMA_4)
589 return 1;
590
591 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
592 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
593 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
594
595 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
596 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
597 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
598 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
599 TR_66_UDMA_EN;
600#ifdef IDE_PMAC_DEBUG
601 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
602 speed & 0xf, *timings);
603#endif
604
605 return 0;
606}
607
608/*
609 * Calculate Kauai ATA/100 UDMA timings
610 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500611static int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700612set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
613{
614 struct ide_timing *t = ide_timing_find_mode(speed);
615 u32 tr;
616
617 if (speed > XFER_UDMA_5 || t == NULL)
618 return 1;
619 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
621 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
622
623 return 0;
624}
625
626/*
627 * Calculate Shasta ATA/133 UDMA timings
628 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500629static int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700630set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
631{
632 struct ide_timing *t = ide_timing_find_mode(speed);
633 u32 tr;
634
635 if (speed > XFER_UDMA_6 || t == NULL)
636 return 1;
637 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700638 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
639 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
640
641 return 0;
642}
643
644/*
645 * Calculate MDMA timings for all cells
646 */
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200647static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200649 u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700650{
651 int cycleTime, accessTime = 0, recTime = 0;
652 unsigned accessTicks, recTicks;
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200653 struct hd_driveid *id = drive->id;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700654 struct mdma_timings_t* tm = NULL;
655 int i;
656
657 /* Get default cycle time for mode */
658 switch(speed & 0xf) {
659 case 0: cycleTime = 480; break;
660 case 1: cycleTime = 150; break;
661 case 2: cycleTime = 120; break;
662 default:
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200663 BUG();
664 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665 }
Bartlomiej Zolnierkiewicz90f72ec2007-10-13 17:47:48 +0200666
667 /* Check if drive provides explicit DMA cycle time */
668 if ((id->field_valid & 2) && id->eide_dma_time)
669 cycleTime = max_t(int, id->eide_dma_time, cycleTime);
670
Linus Torvalds1da177e2005-04-16 15:20:36 -0700671 /* OHare limits according to some old Apple sources */
672 if ((intf_type == controller_ohare) && (cycleTime < 150))
673 cycleTime = 150;
674 /* Get the proper timing array for this controller */
675 switch(intf_type) {
676 case controller_sh_ata6:
677 case controller_un_ata6:
678 case controller_k2_ata6:
679 break;
680 case controller_kl_ata4:
681 tm = mdma_timings_66;
682 break;
683 case controller_kl_ata3:
684 tm = mdma_timings_33k;
685 break;
686 default:
687 tm = mdma_timings_33;
688 break;
689 }
690 if (tm != NULL) {
691 /* Lookup matching access & recovery times */
692 i = -1;
693 for (;;) {
694 if (tm[i+1].cycleTime < cycleTime)
695 break;
696 i++;
697 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700698 cycleTime = tm[i].cycleTime;
699 accessTime = tm[i].accessTime;
700 recTime = tm[i].recoveryTime;
701
702#ifdef IDE_PMAC_DEBUG
703 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
704 drive->name, cycleTime, accessTime, recTime);
705#endif
706 }
707 switch(intf_type) {
708 case controller_sh_ata6: {
709 /* 133Mhz cell */
710 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700711 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
712 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
713 }
714 case controller_un_ata6:
715 case controller_k2_ata6: {
716 /* 100Mhz cell */
717 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
719 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
720 }
721 break;
722 case controller_kl_ata4:
723 /* 66Mhz cell */
724 accessTicks = SYSCLK_TICKS_66(accessTime);
725 accessTicks = min(accessTicks, 0x1fU);
726 accessTicks = max(accessTicks, 0x1U);
727 recTicks = SYSCLK_TICKS_66(recTime);
728 recTicks = min(recTicks, 0x1fU);
729 recTicks = max(recTicks, 0x3U);
730 /* Clear out mdma bits and disable udma */
731 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
732 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
733 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
734 break;
735 case controller_kl_ata3:
736 /* 33Mhz cell on KeyLargo */
737 accessTicks = SYSCLK_TICKS(accessTime);
738 accessTicks = max(accessTicks, 1U);
739 accessTicks = min(accessTicks, 0x1fU);
740 accessTime = accessTicks * IDE_SYSCLK_NS;
741 recTicks = SYSCLK_TICKS(recTime);
742 recTicks = max(recTicks, 1U);
743 recTicks = min(recTicks, 0x1fU);
744 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
745 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
746 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
747 break;
748 default: {
749 /* 33Mhz cell on others */
750 int halfTick = 0;
751 int origAccessTime = accessTime;
752 int origRecTime = recTime;
753
754 accessTicks = SYSCLK_TICKS(accessTime);
755 accessTicks = max(accessTicks, 1U);
756 accessTicks = min(accessTicks, 0x1fU);
757 accessTime = accessTicks * IDE_SYSCLK_NS;
758 recTicks = SYSCLK_TICKS(recTime);
759 recTicks = max(recTicks, 2U) - 1;
760 recTicks = min(recTicks, 0x1fU);
761 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
762 if ((accessTicks > 1) &&
763 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
764 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
765 halfTick = 1;
766 accessTicks--;
767 }
768 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
769 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
770 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
771 if (halfTick)
772 *timings |= TR_33_MDMA_HALFTICK;
773 }
774 }
775#ifdef IDE_PMAC_DEBUG
776 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
777 drive->name, speed & 0xf, *timings);
778#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700779}
780#endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
781
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200782static void pmac_ide_set_dma_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700783{
784 int unit = (drive->select.b.unit & 0x01);
785 int ret = 0;
786 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200787 u32 *timings, *timings2, tl[2];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700788
Linus Torvalds1da177e2005-04-16 15:20:36 -0700789 timings = &pmif->timings[unit];
790 timings2 = &pmif->timings[unit+2];
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200791
792 /* Copy timings to local image */
793 tl[0] = *timings;
794 tl[1] = *timings2;
795
Linus Torvalds1da177e2005-04-16 15:20:36 -0700796#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +0100797 if (speed >= XFER_UDMA_0) {
798 if (pmif->kind == controller_kl_ata4)
799 ret = set_timings_udma_ata4(&tl[0], speed);
800 else if (pmif->kind == controller_un_ata6
801 || pmif->kind == controller_k2_ata6)
802 ret = set_timings_udma_ata6(&tl[0], &tl[1], speed);
803 else if (pmif->kind == controller_sh_ata6)
804 ret = set_timings_udma_shasta(&tl[0], &tl[1], speed);
805 else
806 ret = -1;
807 } else
808 set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700809#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810 if (ret)
Bartlomiej Zolnierkiewicz88b2b322007-10-13 17:47:51 +0200811 return;
Bartlomiej Zolnierkiewicz085798b2007-10-13 17:47:48 +0200812
813 /* Apply timings to controller */
814 *timings = tl[0];
815 *timings2 = tl[1];
816
Linus Torvalds1da177e2005-04-16 15:20:36 -0700817 pmac_ide_do_update_timings(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700818}
819
820/*
821 * Blast some well known "safe" values to the timing registers at init or
822 * wakeup from sleep time, before we do real calculation
823 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -0500824static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825sanitize_timings(pmac_ide_hwif_t *pmif)
826{
827 unsigned int value, value2 = 0;
828
829 switch(pmif->kind) {
830 case controller_sh_ata6:
831 value = 0x0a820c97;
832 value2 = 0x00033031;
833 break;
834 case controller_un_ata6:
835 case controller_k2_ata6:
836 value = 0x08618a92;
837 value2 = 0x00002921;
838 break;
839 case controller_kl_ata4:
840 value = 0x0008438c;
841 break;
842 case controller_kl_ata3:
843 value = 0x00084526;
844 break;
845 case controller_heathrow:
846 case controller_ohare:
847 default:
848 value = 0x00074526;
849 break;
850 }
851 pmif->timings[0] = pmif->timings[1] = value;
852 pmif->timings[2] = pmif->timings[3] = value2;
853}
854
Linus Torvalds1da177e2005-04-16 15:20:36 -0700855/* Suspend call back, should be called after the child devices
856 * have actually been suspended
857 */
858static int
859pmac_ide_do_suspend(ide_hwif_t *hwif)
860{
861 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
862
863 /* We clear the timings */
864 pmif->timings[0] = 0;
865 pmif->timings[1] = 0;
866
Benjamin Herrenschmidt616299a2005-05-01 08:58:41 -0700867 disable_irq(pmif->irq);
868
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869 /* The media bay will handle itself just fine */
870 if (pmif->mediabay)
871 return 0;
872
873 /* Kauai has bus control FCRs directly here */
874 if (pmif->kauai_fcr) {
875 u32 fcr = readl(pmif->kauai_fcr);
876 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
877 writel(fcr, pmif->kauai_fcr);
878 }
879
880 /* Disable the bus on older machines and the cell on kauai */
881 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
882 0);
883
884 return 0;
885}
886
887/* Resume call back, should be called before the child devices
888 * are resumed
889 */
890static int
891pmac_ide_do_resume(ide_hwif_t *hwif)
892{
893 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
894
895 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
896 if (!pmif->mediabay) {
897 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
898 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
899 msleep(10);
900 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700901
902 /* Kauai has it different */
903 if (pmif->kauai_fcr) {
904 u32 fcr = readl(pmif->kauai_fcr);
905 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
906 writel(fcr, pmif->kauai_fcr);
907 }
Benjamin Herrenschmidt616299a2005-05-01 08:58:41 -0700908
909 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700910 }
911
912 /* Sanitize drive timings */
913 sanitize_timings(pmif);
914
Benjamin Herrenschmidt616299a2005-05-01 08:58:41 -0700915 enable_irq(pmif->irq);
916
Linus Torvalds1da177e2005-04-16 15:20:36 -0700917 return 0;
918}
919
Bartlomiej Zolnierkiewicz07a6c662008-06-15 21:00:23 +0200920static u8 pmac_ide_cable_detect(ide_hwif_t *hwif)
921{
922 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)ide_get_hwifdata(hwif);
923 struct device_node *np = pmif->node;
924 const char *cable = of_get_property(np, "cable-type", NULL);
925
926 /* Get cable type from device-tree. */
927 if (cable && !strncmp(cable, "80-", 3))
928 return ATA_CBL_PATA80;
929
930 /*
931 * G5's seem to have incorrect cable type in device-tree.
932 * Let's assume they have a 80 conductor cable, this seem
933 * to be always the case unless the user mucked around.
934 */
935 if (of_device_is_compatible(np, "K2-UATA") ||
936 of_device_is_compatible(np, "shasta-ata"))
937 return ATA_CBL_PATA80;
938
939 return ATA_CBL_PATA40;
940}
941
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200942static const struct ide_port_ops pmac_ide_ata6_port_ops = {
943 .set_pio_mode = pmac_ide_set_pio_mode,
944 .set_dma_mode = pmac_ide_set_dma_mode,
945 .selectproc = pmac_ide_kauai_selectproc,
Bartlomiej Zolnierkiewicz07a6c662008-06-15 21:00:23 +0200946 .cable_detect = pmac_ide_cable_detect,
947};
948
949static const struct ide_port_ops pmac_ide_ata4_port_ops = {
950 .set_pio_mode = pmac_ide_set_pio_mode,
951 .set_dma_mode = pmac_ide_set_dma_mode,
952 .selectproc = pmac_ide_selectproc,
953 .cable_detect = pmac_ide_cable_detect,
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200954};
955
956static const struct ide_port_ops pmac_ide_port_ops = {
957 .set_pio_mode = pmac_ide_set_pio_mode,
958 .set_dma_mode = pmac_ide_set_dma_mode,
959 .selectproc = pmac_ide_selectproc,
960};
961
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +0200962static const struct ide_dma_ops pmac_dma_ops;
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200963
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100964static const struct ide_port_info pmac_port_info = {
Bartlomiej Zolnierkiewicz0d071922008-04-26 22:25:22 +0200965 .init_dma = pmac_ide_init_dma,
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100966 .chipset = ide_pmac,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200967#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
968 .dma_ops = &pmac_dma_ops,
969#endif
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200970 .port_ops = &pmac_ide_port_ops,
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100971 .host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA |
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100972 IDE_HFLAG_POST_SET_MODE |
Bartlomiej Zolnierkiewiczc5dd43e2008-04-28 23:44:37 +0200973 IDE_HFLAG_MMIO |
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100974 IDE_HFLAG_UNMASK_IRQS,
975 .pio_mask = ATA_PIO4,
976 .mwdma_mask = ATA_MWDMA2,
977};
978
Linus Torvalds1da177e2005-04-16 15:20:36 -0700979/*
980 * Setup, register & probe an IDE channel driven by this driver, this is
981 * called by one of the 2 probe functions (macio or PCI). Note that a channel
982 * that ends up beeing free of any device is not kept around by this driver
983 * (it is kept in 2.4). This introduce an interface numbering change on some
984 * rare machines unfortunately, but it's better this way.
985 */
Adrian Bunk468e4682008-02-01 23:09:16 +0100986static int __devinit
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +0100987pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700988{
989 struct device_node *np = pmif->node;
Jeremy Kerr018a3d12006-07-12 15:40:29 +1000990 const int *bidp;
Bartlomiej Zolnierkiewicz8447d9d2007-10-20 00:32:31 +0200991 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100992 struct ide_port_info d = pmac_port_info;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700993
Linus Torvalds1da177e2005-04-16 15:20:36 -0700994 pmif->broken_dma = pmif->broken_dma_warn = 0;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100995 if (of_device_is_compatible(np, "shasta-ata")) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700996 pmif->kind = controller_sh_ata6;
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +0200997 d.port_ops = &pmac_ide_ata6_port_ops;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +0100998 d.udma_mask = ATA_UDMA6;
999 } else if (of_device_is_compatible(np, "kauai-ata")) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001000 pmif->kind = controller_un_ata6;
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001001 d.port_ops = &pmac_ide_ata6_port_ops;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001002 d.udma_mask = ATA_UDMA5;
1003 } else if (of_device_is_compatible(np, "K2-UATA")) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001004 pmif->kind = controller_k2_ata6;
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001005 d.port_ops = &pmac_ide_ata6_port_ops;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001006 d.udma_mask = ATA_UDMA5;
1007 } else if (of_device_is_compatible(np, "keylargo-ata")) {
1008 if (strcmp(np->name, "ata-4") == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001009 pmif->kind = controller_kl_ata4;
Bartlomiej Zolnierkiewicz07a6c662008-06-15 21:00:23 +02001010 d.port_ops = &pmac_ide_ata4_port_ops;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001011 d.udma_mask = ATA_UDMA4;
1012 } else
Linus Torvalds1da177e2005-04-16 15:20:36 -07001013 pmif->kind = controller_kl_ata3;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001014 } else if (of_device_is_compatible(np, "heathrow-ata")) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001015 pmif->kind = controller_heathrow;
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001016 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001017 pmif->kind = controller_ohare;
1018 pmif->broken_dma = 1;
1019 }
1020
Stephen Rothwell40cd3a42007-05-01 13:54:02 +10001021 bidp = of_get_property(np, "AAPL,bus-id", NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001022 pmif->aapl_bus_id = bidp ? *bidp : 0;
1023
Linus Torvalds1da177e2005-04-16 15:20:36 -07001024 /* On Kauai-type controllers, we make sure the FCR is correct */
1025 if (pmif->kauai_fcr)
1026 writel(KAUAI_FCR_UATA_MAGIC |
1027 KAUAI_FCR_UATA_RESET_N |
1028 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1029
1030 pmif->mediabay = 0;
1031
1032 /* Make sure we have sane timings */
1033 sanitize_timings(pmif);
1034
1035#ifndef CONFIG_PPC64
1036 /* XXX FIXME: Media bay stuff need re-organizing */
1037 if (np->parent && np->parent->name
1038 && strcasecmp(np->parent->name, "media-bay") == 0) {
Benjamin Herrenschmidt8c870932005-06-27 14:36:34 -07001039#ifdef CONFIG_PMAC_MEDIABAY
Bartlomiej Zolnierkiewicz2dde7862008-04-18 00:46:23 +02001040 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq,
1041 hwif);
Benjamin Herrenschmidt8c870932005-06-27 14:36:34 -07001042#endif /* CONFIG_PMAC_MEDIABAY */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001043 pmif->mediabay = 1;
1044 if (!bidp)
1045 pmif->aapl_bus_id = 1;
1046 } else if (pmif->kind == controller_ohare) {
1047 /* The code below is having trouble on some ohare machines
1048 * (timing related ?). Until I can put my hand on one of these
1049 * units, I keep the old way
1050 */
1051 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1052 } else
1053#endif
1054 {
1055 /* This is necessary to enable IDE when net-booting */
1056 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1057 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1058 msleep(10);
1059 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1060 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1061 }
1062
1063 /* Setup MMIO ops */
1064 default_hwif_mmiops(hwif);
1065 hwif->OUTBSYNC = pmac_outbsync;
1066
Linus Torvalds1da177e2005-04-16 15:20:36 -07001067 hwif->hwif_data = pmif;
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001068 ide_init_port_hw(hwif, hw);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001069
Linus Torvalds1da177e2005-04-16 15:20:36 -07001070 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1071 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
1072 pmif->mediabay ? " (mediabay)" : "", hwif->irq);
Bartlomiej Zolnierkiewicze53cd452008-04-26 22:25:16 +02001073
1074 if (pmif->mediabay) {
Benjamin Herrenschmidt8c870932005-06-27 14:36:34 -07001075#ifdef CONFIG_PMAC_MEDIABAY
Bartlomiej Zolnierkiewicze53cd452008-04-26 22:25:16 +02001076 if (check_media_bay_by_base(pmif->regbase, MB_CD)) {
1077#else
1078 if (1) {
1079#endif
1080 hwif->drives[0].noprobe = 1;
1081 hwif->drives[1].noprobe = 1;
1082 }
1083 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001084
Bartlomiej Zolnierkiewicz8447d9d2007-10-20 00:32:31 +02001085 idx[0] = hwif->index;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001086
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001087 ide_device_add(idx, &d);
Bartlomiej Zolnierkiewicz5cbf79c2007-05-10 00:01:11 +02001088
Linus Torvalds1da177e2005-04-16 15:20:36 -07001089 return 0;
1090}
1091
Bartlomiej Zolnierkiewicz5c586662008-04-18 00:46:29 +02001092static void __devinit pmac_ide_init_ports(hw_regs_t *hw, unsigned long base)
1093{
1094 int i;
1095
1096 for (i = 0; i < 8; ++i)
Bartlomiej Zolnierkiewicz4c3032d2008-04-27 15:38:32 +02001097 hw->io_ports_array[i] = base + i * 0x10;
1098
1099 hw->io_ports.ctl_addr = base + 0x160;
Bartlomiej Zolnierkiewicz5c586662008-04-18 00:46:29 +02001100}
1101
Linus Torvalds1da177e2005-04-16 15:20:36 -07001102/*
1103 * Attach to a macio probed interface
1104 */
1105static int __devinit
Jeff Mahoney5e655772005-07-06 15:44:41 -04001106pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001107{
1108 void __iomem *base;
1109 unsigned long regbase;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001110 ide_hwif_t *hwif;
1111 pmac_ide_hwif_t *pmif;
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001112 int irq, rc;
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001113 hw_regs_t hw;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001114
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001115 pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
1116 if (pmif == NULL)
1117 return -ENOMEM;
1118
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001119 hwif = ide_find_port();
1120 if (hwif == NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001121 printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n");
1122 printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001123 rc = -ENODEV;
1124 goto out_free_pmif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001125 }
1126
Benjamin Herrenschmidtcc5d0182005-12-13 18:01:21 +11001127 if (macio_resource_count(mdev) == 0) {
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001128 printk(KERN_WARNING "ide-pmac: no address for %s\n",
1129 mdev->ofdev.node->full_name);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001130 rc = -ENXIO;
1131 goto out_free_pmif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001132 }
1133
1134 /* Request memory resource for IO ports */
1135 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001136 printk(KERN_ERR "ide-pmac: can't request MMIO resource for "
1137 "%s!\n", mdev->ofdev.node->full_name);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001138 rc = -EBUSY;
1139 goto out_free_pmif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001140 }
1141
1142 /* XXX This is bogus. Should be fixed in the registry by checking
1143 * the kind of host interrupt controller, a bit like gatwick
1144 * fixes in irq.c. That works well enough for the single case
1145 * where that happens though...
1146 */
1147 if (macio_irq_count(mdev) == 0) {
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001148 printk(KERN_WARNING "ide-pmac: no intrs for device %s, using "
1149 "13\n", mdev->ofdev.node->full_name);
Benjamin Herrenschmidt69917c22006-09-22 12:56:30 +10001150 irq = irq_create_mapping(NULL, 13);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001151 } else
1152 irq = macio_irq(mdev, 0);
1153
1154 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1155 regbase = (unsigned long) base;
1156
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001157 hwif->dev = &mdev->bus->pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001158
1159 pmif->mdev = mdev;
1160 pmif->node = mdev->ofdev.node;
1161 pmif->regbase = regbase;
1162 pmif->irq = irq;
1163 pmif->kauai_fcr = NULL;
1164#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1165 if (macio_resource_count(mdev) >= 2) {
1166 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001167 printk(KERN_WARNING "ide-pmac: can't request DMA "
1168 "resource for %s!\n",
1169 mdev->ofdev.node->full_name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001170 else
1171 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1172 } else
1173 pmif->dma_regs = NULL;
1174#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1175 dev_set_drvdata(&mdev->ofdev.dev, hwif);
1176
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001177 memset(&hw, 0, sizeof(hw));
Bartlomiej Zolnierkiewicz5c586662008-04-18 00:46:29 +02001178 pmac_ide_init_ports(&hw, pmif->regbase);
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001179 hw.irq = irq;
1180 hw.dev = &mdev->ofdev.dev;
1181
1182 rc = pmac_ide_setup_device(pmif, hwif, &hw);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001183 if (rc != 0) {
1184 /* The inteface is released to the common IDE layer */
1185 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1186 iounmap(base);
Bartlomiej Zolnierkiewiczed908fa2008-02-01 23:09:32 +01001187 if (pmif->dma_regs) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001188 iounmap(pmif->dma_regs);
Bartlomiej Zolnierkiewiczed908fa2008-02-01 23:09:32 +01001189 macio_release_resource(mdev, 1);
1190 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001191 macio_release_resource(mdev, 0);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001192 kfree(pmif);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001193 }
1194
1195 return rc;
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001196
1197out_free_pmif:
1198 kfree(pmif);
1199 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001200}
1201
1202static int
David Brownell8b4b8a22006-08-14 23:11:03 -07001203pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001204{
1205 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1206 int rc = 0;
1207
David Brownell8b4b8a22006-08-14 23:11:03 -07001208 if (mesg.event != mdev->ofdev.dev.power.power_state.event
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +01001209 && (mesg.event & PM_EVENT_SLEEP)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001210 rc = pmac_ide_do_suspend(hwif);
1211 if (rc == 0)
David Brownell8b4b8a22006-08-14 23:11:03 -07001212 mdev->ofdev.dev.power.power_state = mesg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001213 }
1214
1215 return rc;
1216}
1217
1218static int
1219pmac_ide_macio_resume(struct macio_dev *mdev)
1220{
1221 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1222 int rc = 0;
1223
Pavel Machekca078ba2005-09-03 15:56:57 -07001224 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001225 rc = pmac_ide_do_resume(hwif);
1226 if (rc == 0)
Pavel Machek829ca9a2005-09-03 15:56:56 -07001227 mdev->ofdev.dev.power.power_state = PMSG_ON;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001228 }
1229
1230 return rc;
1231}
1232
1233/*
1234 * Attach to a PCI probed interface
1235 */
1236static int __devinit
1237pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1238{
1239 ide_hwif_t *hwif;
1240 struct device_node *np;
1241 pmac_ide_hwif_t *pmif;
1242 void __iomem *base;
1243 unsigned long rbase, rlen;
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001244 int rc;
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001245 hw_regs_t hw;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001246
1247 np = pci_device_to_OF_node(pdev);
1248 if (np == NULL) {
1249 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1250 return -ENODEV;
1251 }
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001252
1253 pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
1254 if (pmif == NULL)
1255 return -ENOMEM;
1256
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001257 hwif = ide_find_port();
1258 if (hwif == NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001259 printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n");
1260 printk(KERN_ERR " %s\n", np->full_name);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001261 rc = -ENODEV;
1262 goto out_free_pmif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001263 }
1264
Linus Torvalds1da177e2005-04-16 15:20:36 -07001265 if (pci_enable_device(pdev)) {
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001266 printk(KERN_WARNING "ide-pmac: Can't enable PCI device for "
1267 "%s\n", np->full_name);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001268 rc = -ENXIO;
1269 goto out_free_pmif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001270 }
1271 pci_set_master(pdev);
1272
1273 if (pci_request_regions(pdev, "Kauai ATA")) {
Bartlomiej Zolnierkiewicz939b0f12008-04-26 17:36:33 +02001274 printk(KERN_ERR "ide-pmac: Cannot obtain PCI resources for "
1275 "%s\n", np->full_name);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001276 rc = -ENXIO;
1277 goto out_free_pmif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001278 }
1279
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001280 hwif->dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001281 pmif->mdev = NULL;
1282 pmif->node = np;
1283
1284 rbase = pci_resource_start(pdev, 0);
1285 rlen = pci_resource_len(pdev, 0);
1286
1287 base = ioremap(rbase, rlen);
1288 pmif->regbase = (unsigned long) base + 0x2000;
1289#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1290 pmif->dma_regs = base + 0x1000;
1291#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1292 pmif->kauai_fcr = base;
1293 pmif->irq = pdev->irq;
1294
1295 pci_set_drvdata(pdev, hwif);
1296
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001297 memset(&hw, 0, sizeof(hw));
Bartlomiej Zolnierkiewicz5c586662008-04-18 00:46:29 +02001298 pmac_ide_init_ports(&hw, pmif->regbase);
Bartlomiej Zolnierkiewicz57c802e2008-01-26 20:13:05 +01001299 hw.irq = pdev->irq;
1300 hw.dev = &pdev->dev;
1301
1302 rc = pmac_ide_setup_device(pmif, hwif, &hw);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001303 if (rc != 0) {
1304 /* The inteface is released to the common IDE layer */
1305 pci_set_drvdata(pdev, NULL);
1306 iounmap(base);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001307 pci_release_regions(pdev);
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001308 kfree(pmif);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001309 }
1310
1311 return rc;
Bartlomiej Zolnierkiewicz5297a3e2008-04-26 17:36:32 +02001312
1313out_free_pmif:
1314 kfree(pmif);
1315 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001316}
1317
1318static int
David Brownell8b4b8a22006-08-14 23:11:03 -07001319pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001320{
1321 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1322 int rc = 0;
1323
David Brownell8b4b8a22006-08-14 23:11:03 -07001324 if (mesg.event != pdev->dev.power.power_state.event
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +01001325 && (mesg.event & PM_EVENT_SLEEP)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001326 rc = pmac_ide_do_suspend(hwif);
1327 if (rc == 0)
David Brownell8b4b8a22006-08-14 23:11:03 -07001328 pdev->dev.power.power_state = mesg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001329 }
1330
1331 return rc;
1332}
1333
1334static int
1335pmac_ide_pci_resume(struct pci_dev *pdev)
1336{
1337 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1338 int rc = 0;
1339
Pavel Machekca078ba2005-09-03 15:56:57 -07001340 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001341 rc = pmac_ide_do_resume(hwif);
1342 if (rc == 0)
Pavel Machek829ca9a2005-09-03 15:56:56 -07001343 pdev->dev.power.power_state = PMSG_ON;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001344 }
1345
1346 return rc;
1347}
1348
Jeff Mahoney5e655772005-07-06 15:44:41 -04001349static struct of_device_id pmac_ide_macio_match[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001350{
1351 {
1352 .name = "IDE",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001353 },
1354 {
1355 .name = "ATA",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001356 },
1357 {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001358 .type = "ide",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001359 },
1360 {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001361 .type = "ata",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001362 },
1363 {},
1364};
1365
1366static struct macio_driver pmac_ide_macio_driver =
1367{
1368 .name = "ide-pmac",
1369 .match_table = pmac_ide_macio_match,
1370 .probe = pmac_ide_macio_attach,
1371 .suspend = pmac_ide_macio_suspend,
1372 .resume = pmac_ide_macio_resume,
1373};
1374
Bartlomiej Zolnierkiewicz9cbcc5e2007-10-16 22:29:56 +02001375static const struct pci_device_id pmac_ide_pci_match[] = {
1376 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },
1377 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },
1378 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },
1379 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },
1380 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },
Benjamin Herrenschmidt71e4eda2007-10-06 18:52:27 +10001381 {},
Linus Torvalds1da177e2005-04-16 15:20:36 -07001382};
1383
1384static struct pci_driver pmac_ide_pci_driver = {
1385 .name = "ide-pmac",
1386 .id_table = pmac_ide_pci_match,
1387 .probe = pmac_ide_pci_attach,
1388 .suspend = pmac_ide_pci_suspend,
1389 .resume = pmac_ide_pci_resume,
1390};
1391MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1392
Andrew Morton9e5755b2007-03-03 17:48:54 +01001393int __init pmac_ide_probe(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001394{
Andrew Morton9e5755b2007-03-03 17:48:54 +01001395 int error;
1396
Benjamin Herrenschmidte8222502006-03-28 23:15:54 +11001397 if (!machine_is(powermac))
Andrew Morton9e5755b2007-03-03 17:48:54 +01001398 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001399
1400#ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
Andrew Morton9e5755b2007-03-03 17:48:54 +01001401 error = pci_register_driver(&pmac_ide_pci_driver);
1402 if (error)
1403 goto out;
1404 error = macio_register_driver(&pmac_ide_macio_driver);
1405 if (error) {
1406 pci_unregister_driver(&pmac_ide_pci_driver);
1407 goto out;
1408 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001409#else
Andrew Morton9e5755b2007-03-03 17:48:54 +01001410 error = macio_register_driver(&pmac_ide_macio_driver);
1411 if (error)
1412 goto out;
1413 error = pci_register_driver(&pmac_ide_pci_driver);
1414 if (error) {
1415 macio_unregister_driver(&pmac_ide_macio_driver);
1416 goto out;
1417 }
Benjamin Herrenschmidt1beb6a72005-12-14 13:10:10 +11001418#endif
Andrew Morton9e5755b2007-03-03 17:48:54 +01001419out:
1420 return error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001421}
1422
1423#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1424
1425/*
1426 * pmac_ide_build_dmatable builds the DBDMA command list
1427 * for a transfer and sets the DBDMA channel to point to it.
1428 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001429static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001430pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1431{
1432 struct dbdma_cmd *table;
1433 int i, count = 0;
1434 ide_hwif_t *hwif = HWIF(drive);
1435 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1436 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1437 struct scatterlist *sg;
1438 int wr = (rq_data_dir(rq) == WRITE);
1439
1440 /* DMA table is already aligned */
1441 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1442
1443 /* Make sure DMA controller is stopped (necessary ?) */
1444 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1445 while (readl(&dma->status) & RUN)
1446 udelay(1);
1447
1448 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1449
1450 if (!i)
1451 return 0;
1452
1453 /* Build DBDMA commands list */
1454 sg = hwif->sg_table;
1455 while (i && sg_dma_len(sg)) {
1456 u32 cur_addr;
1457 u32 cur_len;
1458
1459 cur_addr = sg_dma_address(sg);
1460 cur_len = sg_dma_len(sg);
1461
1462 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1463 if (pmif->broken_dma_warn == 0) {
Joe Perchesaca38a52007-11-27 21:35:55 +01001464 printk(KERN_WARNING "%s: DMA on non aligned address, "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001465 "switching to PIO on Ohare chipset\n", drive->name);
1466 pmif->broken_dma_warn = 1;
1467 }
1468 goto use_pio_instead;
1469 }
1470 while (cur_len) {
1471 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1472
1473 if (count++ >= MAX_DCMDS) {
1474 printk(KERN_WARNING "%s: DMA table too small\n",
1475 drive->name);
1476 goto use_pio_instead;
1477 }
1478 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1479 st_le16(&table->req_count, tc);
1480 st_le32(&table->phy_addr, cur_addr);
1481 table->cmd_dep = 0;
1482 table->xfer_status = 0;
1483 table->res_count = 0;
1484 cur_addr += tc;
1485 cur_len -= tc;
1486 ++table;
1487 }
Jens Axboe55c16a72007-07-25 08:13:56 +02001488 sg = sg_next(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001489 i--;
1490 }
1491
1492 /* convert the last command to an input/output last command */
1493 if (count) {
1494 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1495 /* add the stop command to the end of the list */
1496 memset(table, 0, sizeof(struct dbdma_cmd));
1497 st_le16(&table->command, DBDMA_STOP);
1498 mb();
1499 writel(hwif->dmatable_dma, &dma->cmdptr);
1500 return 1;
1501 }
1502
1503 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
Bartlomiej Zolnierkiewiczf6fb7862008-02-01 23:09:31 +01001504
1505use_pio_instead:
1506 ide_destroy_dmatable(drive);
1507
Linus Torvalds1da177e2005-04-16 15:20:36 -07001508 return 0; /* revert to PIO for this request */
1509}
1510
1511/* Teardown mappings after DMA has completed. */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001512static void
Linus Torvalds1da177e2005-04-16 15:20:36 -07001513pmac_ide_destroy_dmatable (ide_drive_t *drive)
1514{
1515 ide_hwif_t *hwif = drive->hwif;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001516
Bartlomiej Zolnierkiewiczf6fb7862008-02-01 23:09:31 +01001517 if (hwif->sg_nents) {
1518 ide_destroy_dmatable(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001519 hwif->sg_nents = 0;
1520 }
1521}
1522
1523/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001524 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1525 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1526 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001527static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001528pmac_ide_dma_setup(ide_drive_t *drive)
1529{
1530 ide_hwif_t *hwif = HWIF(drive);
1531 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1532 struct request *rq = HWGROUP(drive)->rq;
1533 u8 unit = (drive->select.b.unit & 0x01);
1534 u8 ata4;
1535
1536 if (pmif == NULL)
1537 return 1;
1538 ata4 = (pmif->kind == controller_kl_ata4);
1539
1540 if (!pmac_ide_build_dmatable(drive, rq)) {
1541 ide_map_sg(drive, rq);
1542 return 1;
1543 }
1544
1545 /* Apple adds 60ns to wrDataSetup on reads */
1546 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1547 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1548 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1549 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1550 }
1551
1552 drive->waiting_for_dma = 1;
1553
1554 return 0;
1555}
1556
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001557static void
Linus Torvalds1da177e2005-04-16 15:20:36 -07001558pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
1559{
1560 /* issue cmd to drive */
1561 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
1562}
1563
1564/*
1565 * Kick the DMA controller into life after the DMA command has been issued
1566 * to the drive.
1567 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001568static void
Linus Torvalds1da177e2005-04-16 15:20:36 -07001569pmac_ide_dma_start(ide_drive_t *drive)
1570{
1571 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1572 volatile struct dbdma_regs __iomem *dma;
1573
1574 dma = pmif->dma_regs;
1575
1576 writel((RUN << 16) | RUN, &dma->control);
1577 /* Make sure it gets to the controller right now */
1578 (void)readl(&dma->control);
1579}
1580
1581/*
1582 * After a DMA transfer, make sure the controller is stopped
1583 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001584static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001585pmac_ide_dma_end (ide_drive_t *drive)
1586{
1587 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1588 volatile struct dbdma_regs __iomem *dma;
1589 u32 dstat;
1590
1591 if (pmif == NULL)
1592 return 0;
1593 dma = pmif->dma_regs;
1594
1595 drive->waiting_for_dma = 0;
1596 dstat = readl(&dma->status);
1597 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1598 pmac_ide_destroy_dmatable(drive);
1599 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1600 * in theory, but with ATAPI decices doing buffer underruns, that would
1601 * cause us to disable DMA, which isn't what we want
1602 */
1603 return (dstat & (RUN|DEAD)) != RUN;
1604}
1605
1606/*
1607 * Check out that the interrupt we got was for us. We can't always know this
1608 * for sure with those Apple interfaces (well, we could on the recent ones but
1609 * that's not implemented yet), on the other hand, we don't have shared interrupts
1610 * so it's not really a problem
1611 */
Jon Loeligeraacaf9b2005-09-17 10:36:54 -05001612static int
Linus Torvalds1da177e2005-04-16 15:20:36 -07001613pmac_ide_dma_test_irq (ide_drive_t *drive)
1614{
1615 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1616 volatile struct dbdma_regs __iomem *dma;
1617 unsigned long status, timeout;
1618
1619 if (pmif == NULL)
1620 return 0;
1621 dma = pmif->dma_regs;
1622
1623 /* We have to things to deal with here:
1624 *
1625 * - The dbdma won't stop if the command was started
1626 * but completed with an error without transferring all
1627 * datas. This happens when bad blocks are met during
1628 * a multi-block transfer.
1629 *
1630 * - The dbdma fifo hasn't yet finished flushing to
1631 * to system memory when the disk interrupt occurs.
1632 *
1633 */
1634
1635 /* If ACTIVE is cleared, the STOP command have passed and
1636 * transfer is complete.
1637 */
1638 status = readl(&dma->status);
1639 if (!(status & ACTIVE))
1640 return 1;
1641 if (!drive->waiting_for_dma)
1642 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1643 called while not waiting\n", HWIF(drive)->index);
1644
1645 /* If dbdma didn't execute the STOP command yet, the
1646 * active bit is still set. We consider that we aren't
1647 * sharing interrupts (which is hopefully the case with
1648 * those controllers) and so we just try to flush the
1649 * channel for pending data in the fifo
1650 */
1651 udelay(1);
1652 writel((FLUSH << 16) | FLUSH, &dma->control);
1653 timeout = 0;
1654 for (;;) {
1655 udelay(1);
1656 status = readl(&dma->status);
1657 if ((status & FLUSH) == 0)
1658 break;
1659 if (++timeout > 100) {
1660 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1661 timeout flushing channel\n", HWIF(drive)->index);
1662 break;
1663 }
1664 }
1665 return 1;
1666}
1667
Bartlomiej Zolnierkiewicz15ce9262008-01-26 20:13:03 +01001668static void pmac_ide_dma_host_set(ide_drive_t *drive, int on)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001669{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001670}
1671
Sergei Shtylyov841d2a92007-07-09 23:17:54 +02001672static void
1673pmac_ide_dma_lost_irq (ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001674{
1675 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1676 volatile struct dbdma_regs __iomem *dma;
1677 unsigned long status;
1678
1679 if (pmif == NULL)
Sergei Shtylyov841d2a92007-07-09 23:17:54 +02001680 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001681 dma = pmif->dma_regs;
1682
1683 status = readl(&dma->status);
1684 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001685}
1686
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001687static const struct ide_dma_ops pmac_dma_ops = {
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001688 .dma_host_set = pmac_ide_dma_host_set,
1689 .dma_setup = pmac_ide_dma_setup,
1690 .dma_exec_cmd = pmac_ide_dma_exec_cmd,
1691 .dma_start = pmac_ide_dma_start,
1692 .dma_end = pmac_ide_dma_end,
1693 .dma_test_irq = pmac_ide_dma_test_irq,
1694 .dma_timeout = ide_dma_timeout,
1695 .dma_lost_irq = pmac_ide_dma_lost_irq,
1696};
1697
Linus Torvalds1da177e2005-04-16 15:20:36 -07001698/*
1699 * Allocate the data structures needed for using DMA with an interface
1700 * and fill the proper list of functions pointers
1701 */
Bartlomiej Zolnierkiewicz0d071922008-04-26 22:25:22 +02001702static int __devinit pmac_ide_init_dma(ide_hwif_t *hwif,
1703 const struct ide_port_info *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001704{
Bartlomiej Zolnierkiewicz0d071922008-04-26 22:25:22 +02001705 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001706 struct pci_dev *dev = to_pci_dev(hwif->dev);
1707
Linus Torvalds1da177e2005-04-16 15:20:36 -07001708 /* We won't need pci_dev if we switch to generic consistent
1709 * DMA routines ...
1710 */
Bartlomiej Zolnierkiewicz0d071922008-04-26 22:25:22 +02001711 if (dev == NULL || pmif->dma_regs == 0)
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001712 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001713 /*
1714 * Allocate space for the DBDMA commands.
1715 * The +2 is +1 for the stop command and +1 to allow for
1716 * aligning the start address to a multiple of 16 bytes.
1717 */
1718 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001719 dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001720 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
1721 &hwif->dmatable_dma);
1722 if (pmif->dma_table_cpu == NULL) {
1723 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
1724 hwif->name);
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001725 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001726 }
1727
Bartlomiej Zolnierkiewicz4f52a322008-01-26 20:13:08 +01001728 hwif->sg_max_nents = MAX_DCMDS;
1729
Bartlomiej Zolnierkiewiczc413b9b2008-02-02 19:56:31 +01001730 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001731}
Bartlomiej Zolnierkiewicz0d071922008-04-26 22:25:22 +02001732#else
1733static int __devinit pmac_ide_init_dma(ide_hwif_t *hwif,
1734 const struct ide_port_info *d)
1735{
1736 return -EOPNOTSUPP;
1737}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001738#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
Bartlomiej Zolnierkiewiczade2daf2008-01-26 20:13:07 +01001739
1740module_init(pmac_ide_probe);
Adrian Bunkde9facb2008-04-02 21:22:03 +02001741
1742MODULE_LICENSE("GPL");