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Pierre Ossman5c4e6f12007-05-21 20:23:20 +02001/*
2 * include/linux/mmc/sdio.h
3 *
4 * Copyright 2006-2007 Pierre Ossman
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 */
11
Robert P. J. Day100e9182011-05-27 16:04:03 -040012#ifndef LINUX_MMC_SDIO_H
13#define LINUX_MMC_SDIO_H
Pierre Ossman5c4e6f12007-05-21 20:23:20 +020014
15/* SDIO commands type argument response */
16#define SD_IO_SEND_OP_COND 5 /* bcr [23:0] OCR R4 */
Pierre Ossmanb2bcc792007-05-22 20:25:21 +020017#define SD_IO_RW_DIRECT 52 /* ac [31:0] See below R5 */
Pierre Ossman112c9db2007-07-06 13:35:01 +020018#define SD_IO_RW_EXTENDED 53 /* adtc [31:0] See below R5 */
Pierre Ossmanb2bcc792007-05-22 20:25:21 +020019
20/*
21 * SD_IO_RW_DIRECT argument format:
22 *
23 * [31] R/W flag
24 * [30:28] Function number
25 * [27] RAW flag
26 * [25:9] Register address
27 * [7:0] Data
28 */
29
30/*
Pierre Ossman112c9db2007-07-06 13:35:01 +020031 * SD_IO_RW_EXTENDED argument format:
32 *
33 * [31] R/W flag
34 * [30:28] Function number
35 * [27] Block mode
36 * [26] Increment address
37 * [25:9] Register address
38 * [8:0] Byte/block count
39 */
40
Philip Rakitya303c532011-11-14 19:14:38 -080041#define R4_18V_PRESENT (1<<24)
David Vrabelf3c65b22010-09-09 16:37:24 -070042#define R4_MEMORY_PRESENT (1 << 27)
43
Pierre Ossman112c9db2007-07-06 13:35:01 +020044/*
Pierre Ossmanb2bcc792007-05-22 20:25:21 +020045 SDIO status in R5
46 Type
47 e : error bit
48 s : status bit
49 r : detected and set for the actual command response
50 x : detected and set during command execution. the host must poll
51 the card by sending status command in order to read these bits.
52 Clear condition
53 a : according to the card state
54 b : always related to the previous command. Reception of
55 a valid command will clear it (with a delay of one command)
56 c : clear by read
57 */
58
59#define R5_COM_CRC_ERROR (1 << 15) /* er, b */
60#define R5_ILLEGAL_COMMAND (1 << 14) /* er, b */
61#define R5_ERROR (1 << 11) /* erx, c */
62#define R5_FUNCTION_NUMBER (1 << 9) /* er, c */
63#define R5_OUT_OF_RANGE (1 << 8) /* er, c */
64#define R5_STATUS(x) (x & 0xCB00)
65#define R5_IO_CURRENT_STATE(x) ((x & 0x3000) >> 12) /* s, b */
Pierre Ossman5c4e6f12007-05-21 20:23:20 +020066
Pierre Ossmanfa64efa2007-05-27 14:22:37 +020067/*
68 * Card Common Control Registers (CCCR)
69 */
70
71#define SDIO_CCCR_CCCR 0x00
72
73#define SDIO_CCCR_REV_1_00 0 /* CCCR/FBR Version 1.00 */
74#define SDIO_CCCR_REV_1_10 1 /* CCCR/FBR Version 1.10 */
75#define SDIO_CCCR_REV_1_20 2 /* CCCR/FBR Version 1.20 */
Bing Zhaob4625da2011-10-20 19:16:32 -070076#define SDIO_CCCR_REV_3_00 3 /* CCCR/FBR Version 3.00 */
Pierre Ossmanfa64efa2007-05-27 14:22:37 +020077
78#define SDIO_SDIO_REV_1_00 0 /* SDIO Spec Version 1.00 */
79#define SDIO_SDIO_REV_1_10 1 /* SDIO Spec Version 1.10 */
80#define SDIO_SDIO_REV_1_20 2 /* SDIO Spec Version 1.20 */
81#define SDIO_SDIO_REV_2_00 3 /* SDIO Spec Version 2.00 */
Bing Zhaob4625da2011-10-20 19:16:32 -070082#define SDIO_SDIO_REV_3_00 4 /* SDIO Spec Version 3.00 */
Pierre Ossmanfa64efa2007-05-27 14:22:37 +020083
84#define SDIO_CCCR_SD 0x01
85
86#define SDIO_SD_REV_1_01 0 /* SD Physical Spec Version 1.01 */
87#define SDIO_SD_REV_1_10 1 /* SD Physical Spec Version 1.10 */
88#define SDIO_SD_REV_2_00 2 /* SD Physical Spec Version 2.00 */
Philip Rakitya303c532011-11-14 19:14:38 -080089#define SDIO_SD_REV_3_00 3 /* SD Physical Spev Version 3.00 */
Pierre Ossmanfa64efa2007-05-27 14:22:37 +020090
91#define SDIO_CCCR_IOEx 0x02
92#define SDIO_CCCR_IORx 0x03
93
94#define SDIO_CCCR_IENx 0x04 /* Function/Master Interrupt Enable */
95#define SDIO_CCCR_INTx 0x05 /* Function Interrupt Pending */
96
97#define SDIO_CCCR_ABORT 0x06 /* function abort/card reset */
98
99#define SDIO_CCCR_IF 0x07 /* bus interface controls */
100
101#define SDIO_BUS_WIDTH_1BIT 0x00
102#define SDIO_BUS_WIDTH_4BIT 0x02
Daniel Mack8a64c0f2010-04-06 10:52:44 +0200103#define SDIO_BUS_ECSI 0x20 /* Enable continuous SPI interrupt */
104#define SDIO_BUS_SCSI 0x40 /* Support continuous SPI interrupt */
Pierre Ossmanfa64efa2007-05-27 14:22:37 +0200105
Daniel Drake6b5eda32010-03-05 13:43:34 -0800106#define SDIO_BUS_ASYNC_INT 0x20
107
Pierre Ossmanfa64efa2007-05-27 14:22:37 +0200108#define SDIO_BUS_CD_DISABLE 0x80 /* disable pull-up on DAT3 (pin 1) */
109
110#define SDIO_CCCR_CAPS 0x08
111
112#define SDIO_CCCR_CAP_SDC 0x01 /* can do CMD52 while data transfer */
113#define SDIO_CCCR_CAP_SMB 0x02 /* can do multi-block xfers (CMD53) */
114#define SDIO_CCCR_CAP_SRW 0x04 /* supports read-wait protocol */
115#define SDIO_CCCR_CAP_SBS 0x08 /* supports suspend/resume */
116#define SDIO_CCCR_CAP_S4MI 0x10 /* interrupt during 4-bit CMD53 */
117#define SDIO_CCCR_CAP_E4MI 0x20 /* enable ints during 4-bit CMD53 */
118#define SDIO_CCCR_CAP_LSC 0x40 /* low speed card */
119#define SDIO_CCCR_CAP_4BLS 0x80 /* 4 bit low speed card */
120
121#define SDIO_CCCR_CIS 0x09 /* common CIS pointer (3 bytes) */
122
123/* Following 4 regs are valid only if SBS is set */
124#define SDIO_CCCR_SUSPEND 0x0c
125#define SDIO_CCCR_SELx 0x0d
126#define SDIO_CCCR_EXECx 0x0e
127#define SDIO_CCCR_READYx 0x0f
128
129#define SDIO_CCCR_BLKSIZE 0x10
130
131#define SDIO_CCCR_POWER 0x12
132
133#define SDIO_POWER_SMPC 0x01 /* Supports Master Power Control */
134#define SDIO_POWER_EMPC 0x02 /* Enable Master Power Control */
135
136#define SDIO_CCCR_SPEED 0x13
137
138#define SDIO_SPEED_SHS 0x01 /* Supports High-Speed mode */
Philip Rakitya303c532011-11-14 19:14:38 -0800139#define SDIO_SPEED_BSS_SHIFT 1
140#define SDIO_SPEED_BSS_MASK (7<<SDIO_SPEED_BSS_SHIFT)
141#define SDIO_SPEED_SDR12 (0<<SDIO_SPEED_BSS_SHIFT)
142#define SDIO_SPEED_SDR25 (1<<SDIO_SPEED_BSS_SHIFT)
143#define SDIO_SPEED_SDR50 (2<<SDIO_SPEED_BSS_SHIFT)
144#define SDIO_SPEED_SDR104 (3<<SDIO_SPEED_BSS_SHIFT)
145#define SDIO_SPEED_DDR50 (4<<SDIO_SPEED_BSS_SHIFT)
146#define SDIO_SPEED_EHS SDIO_SPEED_SDR25 /* Enable High-Speed */
Pierre Ossmanfa64efa2007-05-27 14:22:37 +0200147
Philip Rakitya303c532011-11-14 19:14:38 -0800148#define SDIO_CCCR_UHS 0x14
149#define SDIO_UHS_SDR50 0x01
150#define SDIO_UHS_SDR104 0x02
151#define SDIO_UHS_DDR50 0x04
152
153#define SDIO_CCCR_DRIVE_STRENGTH 0x15
154#define SDIO_SDTx_MASK 0x07
155#define SDIO_DRIVE_SDTA (1<<0)
156#define SDIO_DRIVE_SDTC (1<<1)
157#define SDIO_DRIVE_SDTD (1<<2)
158#define SDIO_DRIVE_DTSx_MASK 0x03
159#define SDIO_DRIVE_DTSx_SHIFT 4
160#define SDIO_DTSx_SET_TYPE_B (0 << SDIO_DRIVE_DTSx_SHIFT)
161#define SDIO_DTSx_SET_TYPE_A (1 << SDIO_DRIVE_DTSx_SHIFT)
162#define SDIO_DTSx_SET_TYPE_C (2 << SDIO_DRIVE_DTSx_SHIFT)
163#define SDIO_DTSx_SET_TYPE_D (3 << SDIO_DRIVE_DTSx_SHIFT)
Pierre Ossmanfa64efa2007-05-27 14:22:37 +0200164/*
165 * Function Basic Registers (FBR)
166 */
167
David Vrabel7616ee92007-08-08 14:23:05 +0100168#define SDIO_FBR_BASE(f) ((f) * 0x100) /* base of function f's FBRs */
169
Pierre Ossmanfa64efa2007-05-27 14:22:37 +0200170#define SDIO_FBR_STD_IF 0x00
171
172#define SDIO_FBR_SUPPORTS_CSA 0x40 /* supports Code Storage Area */
173#define SDIO_FBR_ENABLE_CSA 0x80 /* enable Code Storage Area */
174
175#define SDIO_FBR_STD_IF_EXT 0x01
176
177#define SDIO_FBR_POWER 0x02
178
179#define SDIO_FBR_POWER_SPS 0x01 /* Supports Power Selection */
180#define SDIO_FBR_POWER_EPS 0x02 /* Enable (low) Power Selection */
181
182#define SDIO_FBR_CIS 0x09 /* CIS pointer (3 bytes) */
183
184
185#define SDIO_FBR_CSA 0x0C /* CSA pointer (3 bytes) */
186
187#define SDIO_FBR_CSA_DATA 0x0F
188
189#define SDIO_FBR_BLKSIZE 0x10 /* block size (2 bytes) */
190
Robert P. J. Day100e9182011-05-27 16:04:03 -0400191#endif /* LINUX_MMC_SDIO_H */