blob: 0ae01f57b3df7fea9ba2f76cff67968a8f6f39a7 [file] [log] [blame]
Ajay Kumar Guptaeb830922010-10-19 10:08:12 +03001/*
2 * Texas Instruments AM35x "glue layer"
3 *
4 * Copyright (c) 2010, by Texas Instruments
5 *
6 * Based on the DA8xx "glue layer" code.
7 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This file is part of the Inventra Controller Driver for Linux.
10 *
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
14 * Foundation.
15 *
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
26 *
27 */
28
29#include <linux/init.h>
30#include <linux/clk.h>
31#include <linux/io.h>
Felipe Balbice40c572010-12-02 09:06:51 +020032#include <linux/platform_device.h>
33#include <linux/dma-mapping.h>
Ajay Kumar Guptaeb830922010-10-19 10:08:12 +030034
35#include <plat/control.h>
36#include <plat/usb.h>
37
38#include "musb_core.h"
39
40/*
41 * AM35x specific definitions
42 */
43/* USB 2.0 OTG module registers */
44#define USB_REVISION_REG 0x00
45#define USB_CTRL_REG 0x04
46#define USB_STAT_REG 0x08
47#define USB_EMULATION_REG 0x0c
48/* 0x10 Reserved */
49#define USB_AUTOREQ_REG 0x14
50#define USB_SRP_FIX_TIME_REG 0x18
51#define USB_TEARDOWN_REG 0x1c
52#define EP_INTR_SRC_REG 0x20
53#define EP_INTR_SRC_SET_REG 0x24
54#define EP_INTR_SRC_CLEAR_REG 0x28
55#define EP_INTR_MASK_REG 0x2c
56#define EP_INTR_MASK_SET_REG 0x30
57#define EP_INTR_MASK_CLEAR_REG 0x34
58#define EP_INTR_SRC_MASKED_REG 0x38
59#define CORE_INTR_SRC_REG 0x40
60#define CORE_INTR_SRC_SET_REG 0x44
61#define CORE_INTR_SRC_CLEAR_REG 0x48
62#define CORE_INTR_MASK_REG 0x4c
63#define CORE_INTR_MASK_SET_REG 0x50
64#define CORE_INTR_MASK_CLEAR_REG 0x54
65#define CORE_INTR_SRC_MASKED_REG 0x58
66/* 0x5c Reserved */
67#define USB_END_OF_INTR_REG 0x60
68
69/* Control register bits */
70#define AM35X_SOFT_RESET_MASK 1
71
72/* USB interrupt register bits */
73#define AM35X_INTR_USB_SHIFT 16
74#define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
75#define AM35X_INTR_DRVVBUS 0x100
76#define AM35X_INTR_RX_SHIFT 16
77#define AM35X_INTR_TX_SHIFT 0
78#define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
79#define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
80#define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
81#define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
82
83#define USB_MENTOR_CORE_OFFSET 0x400
84
85static inline void phy_on(void)
86{
87 unsigned long timeout = jiffies + msecs_to_jiffies(100);
88 u32 devconf2;
89
90 /*
91 * Start the on-chip PHY and its PLL.
92 */
93 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
94
95 devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
96 devconf2 |= CONF2_PHY_PLLON;
97
98 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
99
100 DBG(1, "Waiting for PHY clock good...\n");
101 while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
102 & CONF2_PHYCLKGD)) {
103 cpu_relax();
104
105 if (time_after(jiffies, timeout)) {
106 DBG(1, "musb PHY clock good timed out\n");
107 break;
108 }
109 }
110}
111
112static inline void phy_off(void)
113{
114 u32 devconf2;
115
116 /*
117 * Power down the on-chip PHY.
118 */
119 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
120
121 devconf2 &= ~CONF2_PHY_PLLON;
122 devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN;
123 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
124}
125
126/*
Felipe Balbi743411b2010-12-01 13:22:05 +0200127 * am35x_musb_enable - enable interrupts
Ajay Kumar Guptaeb830922010-10-19 10:08:12 +0300128 */
Felipe Balbi743411b2010-12-01 13:22:05 +0200129static void am35x_musb_enable(struct musb *musb)
Ajay Kumar Guptaeb830922010-10-19 10:08:12 +0300130{
131 void __iomem *reg_base = musb->ctrl_base;
132 u32 epmask;
133
134 /* Workaround: setup IRQs through both register sets. */
135 epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
136 ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
137
138 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
139 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
140
141 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
142 if (is_otg_enabled(musb))
143 musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
144 AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
145}
146
147/*
Felipe Balbi743411b2010-12-01 13:22:05 +0200148 * am35x_musb_disable - disable HDRC and flush interrupts
Ajay Kumar Guptaeb830922010-10-19 10:08:12 +0300149 */
Felipe Balbi743411b2010-12-01 13:22:05 +0200150static void am35x_musb_disable(struct musb *musb)
Ajay Kumar Guptaeb830922010-10-19 10:08:12 +0300151{
152 void __iomem *reg_base = musb->ctrl_base;
153
154 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
155 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
156 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
157 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
158 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
159}
160
161#ifdef CONFIG_USB_MUSB_HDRC_HCD
162#define portstate(stmt) stmt
163#else
164#define portstate(stmt)
165#endif
166
Felipe Balbi743411b2010-12-01 13:22:05 +0200167static void am35x_musb_set_vbus(struct musb *musb, int is_on)
Ajay Kumar Guptaeb830922010-10-19 10:08:12 +0300168{
169 WARN_ON(is_on && is_peripheral_active(musb));
170}
171
172#define POLL_SECONDS 2
173
174static struct timer_list otg_workaround;
175
176static void otg_timer(unsigned long _musb)
177{
178 struct musb *musb = (void *)_musb;
179 void __iomem *mregs = musb->mregs;
180 u8 devctl;
181 unsigned long flags;
182
183 /*
184 * We poll because AM35x's won't expose several OTG-critical
185 * status change events (from the transceiver) otherwise.
186 */
187 devctl = musb_readb(mregs, MUSB_DEVCTL);
188 DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
189
190 spin_lock_irqsave(&musb->lock, flags);
191 switch (musb->xceiv->state) {
192 case OTG_STATE_A_WAIT_BCON:
193 devctl &= ~MUSB_DEVCTL_SESSION;
194 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
195
196 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
197 if (devctl & MUSB_DEVCTL_BDEVICE) {
198 musb->xceiv->state = OTG_STATE_B_IDLE;
199 MUSB_DEV_MODE(musb);
200 } else {
201 musb->xceiv->state = OTG_STATE_A_IDLE;
202 MUSB_HST_MODE(musb);
203 }
204 break;
205 case OTG_STATE_A_WAIT_VFALL:
206 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
207 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
208 MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
209 break;
210 case OTG_STATE_B_IDLE:
211 if (!is_peripheral_enabled(musb))
212 break;
213
214 devctl = musb_readb(mregs, MUSB_DEVCTL);
215 if (devctl & MUSB_DEVCTL_BDEVICE)
216 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
217 else
218 musb->xceiv->state = OTG_STATE_A_IDLE;
219 break;
220 default:
221 break;
222 }
223 spin_unlock_irqrestore(&musb->lock, flags);
224}
225
Felipe Balbi743411b2010-12-01 13:22:05 +0200226static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
Ajay Kumar Guptaeb830922010-10-19 10:08:12 +0300227{
228 static unsigned long last_timer;
229
230 if (!is_otg_enabled(musb))
231 return;
232
233 if (timeout == 0)
234 timeout = jiffies + msecs_to_jiffies(3);
235
236 /* Never idle if active, or when VBUS timeout is not set as host */
237 if (musb->is_active || (musb->a_wait_bcon == 0 &&
238 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
239 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
240 del_timer(&otg_workaround);
241 last_timer = jiffies;
242 return;
243 }
244
245 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
246 DBG(4, "Longer idle timer already pending, ignoring...\n");
247 return;
248 }
249 last_timer = timeout;
250
251 DBG(4, "%s inactive, starting idle timer for %u ms\n",
252 otg_state_string(musb), jiffies_to_msecs(timeout - jiffies));
253 mod_timer(&otg_workaround, timeout);
254}
255
Felipe Balbi743411b2010-12-01 13:22:05 +0200256static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
Ajay Kumar Guptaeb830922010-10-19 10:08:12 +0300257{
258 struct musb *musb = hci;
259 void __iomem *reg_base = musb->ctrl_base;
260 unsigned long flags;
261 irqreturn_t ret = IRQ_NONE;
262 u32 epintr, usbintr, lvl_intr;
263
264 spin_lock_irqsave(&musb->lock, flags);
265
266 /* Get endpoint interrupts */
267 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
268
269 if (epintr) {
270 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
271
272 musb->int_rx =
273 (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
274 musb->int_tx =
275 (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
276 }
277
278 /* Get usb core interrupts */
279 usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
280 if (!usbintr && !epintr)
281 goto eoi;
282
283 if (usbintr) {
284 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
285
286 musb->int_usb =
287 (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
288 }
289 /*
290 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
291 * AM35x's missing ID change IRQ. We need an ID change IRQ to
292 * switch appropriately between halves of the OTG state machine.
293 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
294 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
295 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
296 */
297 if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
298 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
299 void __iomem *mregs = musb->mregs;
300 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
301 int err;
302
303 err = is_host_enabled(musb) && (musb->int_usb &
304 MUSB_INTR_VBUSERROR);
305 if (err) {
306 /*
307 * The Mentor core doesn't debounce VBUS as needed
308 * to cope with device connect current spikes. This
309 * means it's not uncommon for bus-powered devices
310 * to get VBUS errors during enumeration.
311 *
312 * This is a workaround, but newer RTL from Mentor
313 * seems to allow a better one: "re"-starting sessions
314 * without waiting for VBUS to stop registering in
315 * devctl.
316 */
317 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
318 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
319 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
320 WARNING("VBUS error workaround (delay coming)\n");
321 } else if (is_host_enabled(musb) && drvvbus) {
322 MUSB_HST_MODE(musb);
323 musb->xceiv->default_a = 1;
324 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
325 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
326 del_timer(&otg_workaround);
327 } else {
328 musb->is_active = 0;
329 MUSB_DEV_MODE(musb);
330 musb->xceiv->default_a = 0;
331 musb->xceiv->state = OTG_STATE_B_IDLE;
332 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
333 }
334
335 /* NOTE: this must complete power-on within 100 ms. */
336 DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
337 drvvbus ? "on" : "off",
338 otg_state_string(musb),
339 err ? " ERROR" : "",
340 devctl);
341 ret = IRQ_HANDLED;
342 }
343
344 if (musb->int_tx || musb->int_rx || musb->int_usb)
345 ret |= musb_interrupt(musb);
346
347eoi:
348 /* EOI needs to be written for the IRQ to be re-asserted. */
349 if (ret == IRQ_HANDLED || epintr || usbintr) {
350 /* clear level interrupt */
351 lvl_intr = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
352 lvl_intr |= AM35XX_USBOTGSS_INT_CLR;
353 omap_ctrl_writel(lvl_intr, AM35XX_CONTROL_LVL_INTR_CLEAR);
354 /* write EOI */
355 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
356 }
357
358 /* Poll for ID change */
359 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
360 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
361
362 spin_unlock_irqrestore(&musb->lock, flags);
363
364 return ret;
365}
366
Felipe Balbi743411b2010-12-01 13:22:05 +0200367static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
Ajay Kumar Guptaeb830922010-10-19 10:08:12 +0300368{
369 u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
370
371 devconf2 &= ~CONF2_OTGMODE;
372 switch (musb_mode) {
373#ifdef CONFIG_USB_MUSB_HDRC_HCD
374 case MUSB_HOST: /* Force VBUS valid, ID = 0 */
375 devconf2 |= CONF2_FORCE_HOST;
376 break;
377#endif
378#ifdef CONFIG_USB_GADGET_MUSB_HDRC
379 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
380 devconf2 |= CONF2_FORCE_DEVICE;
381 break;
382#endif
383#ifdef CONFIG_USB_MUSB_OTG
384 case MUSB_OTG: /* Don't override the VBUS/ID comparators */
385 devconf2 |= CONF2_NO_OVERRIDE;
386 break;
387#endif
388 default:
389 DBG(2, "Trying to set unsupported mode %u\n", musb_mode);
390 }
391
392 omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
393 return 0;
394}
395
Felipe Balbi743411b2010-12-01 13:22:05 +0200396static int am35x_musb_init(struct musb *musb)
Ajay Kumar Guptaeb830922010-10-19 10:08:12 +0300397{
398 void __iomem *reg_base = musb->ctrl_base;
399 u32 rev, lvl_intr, sw_reset;
400 int status;
401
402 musb->mregs += USB_MENTOR_CORE_OFFSET;
403
404 clk_enable(musb->clock);
405 DBG(2, "musb->clock=%lud\n", clk_get_rate(musb->clock));
406
407 musb->phy_clock = clk_get(musb->controller, "fck");
408 if (IS_ERR(musb->phy_clock)) {
409 status = PTR_ERR(musb->phy_clock);
410 goto exit0;
411 }
412 clk_enable(musb->phy_clock);
413 DBG(2, "musb->phy_clock=%lud\n", clk_get_rate(musb->phy_clock));
414
415 /* Returns zero if e.g. not clocked */
416 rev = musb_readl(reg_base, USB_REVISION_REG);
417 if (!rev) {
418 status = -ENODEV;
419 goto exit1;
420 }
421
422 usb_nop_xceiv_register();
423 musb->xceiv = otg_get_transceiver();
424 if (!musb->xceiv) {
425 status = -ENODEV;
426 goto exit1;
427 }
428
429 if (is_host_enabled(musb))
430 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
431
Felipe Balbi743411b2010-12-01 13:22:05 +0200432 musb->board_set_vbus = am35x_musb_set_vbus;
Ajay Kumar Guptaeb830922010-10-19 10:08:12 +0300433
434 /* Global reset */
435 sw_reset = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
436
437 sw_reset |= AM35XX_USBOTGSS_SW_RST;
438 omap_ctrl_writel(sw_reset, AM35XX_CONTROL_IP_SW_RESET);
439
440 sw_reset &= ~AM35XX_USBOTGSS_SW_RST;
441 omap_ctrl_writel(sw_reset, AM35XX_CONTROL_IP_SW_RESET);
442
443 /* Reset the controller */
444 musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
445
446 /* Start the on-chip PHY and its PLL. */
447 phy_on();
448
449 msleep(5);
450
Felipe Balbi743411b2010-12-01 13:22:05 +0200451 musb->isr = am35x_musb_interrupt;
Ajay Kumar Guptaeb830922010-10-19 10:08:12 +0300452
453 /* clear level interrupt */
454 lvl_intr = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
455 lvl_intr |= AM35XX_USBOTGSS_INT_CLR;
456 omap_ctrl_writel(lvl_intr, AM35XX_CONTROL_LVL_INTR_CLEAR);
457 return 0;
458exit1:
459 clk_disable(musb->phy_clock);
460 clk_put(musb->phy_clock);
461exit0:
462 clk_disable(musb->clock);
463 return status;
464}
465
Felipe Balbi743411b2010-12-01 13:22:05 +0200466static int am35x_musb_exit(struct musb *musb)
Ajay Kumar Guptaeb830922010-10-19 10:08:12 +0300467{
468 if (is_host_enabled(musb))
469 del_timer_sync(&otg_workaround);
470
471 phy_off();
472
473 otg_put_transceiver(musb->xceiv);
474 usb_nop_xceiv_unregister();
475
476 clk_disable(musb->clock);
477
478 clk_disable(musb->phy_clock);
479 clk_put(musb->phy_clock);
480
481 return 0;
482}
483
484#ifdef CONFIG_PM
485void musb_platform_save_context(struct musb *musb,
486 struct musb_context_registers *musb_context)
487{
488 phy_off();
489}
490
491void musb_platform_restore_context(struct musb *musb,
492 struct musb_context_registers *musb_context)
493{
494 phy_on();
495}
496#endif
Ajay Kumar Gupta843bb1d2010-10-19 10:08:13 +0300497
498/* AM35x supports only 32bit read operation */
499void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
500{
501 void __iomem *fifo = hw_ep->fifo;
502 u32 val;
503 int i;
504
505 /* Read for 32bit-aligned destination address */
506 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
507 readsl(fifo, dst, len >> 2);
508 dst += len & ~0x03;
509 len &= 0x03;
510 }
511 /*
512 * Now read the remaining 1 to 3 byte or complete length if
513 * unaligned address.
514 */
515 if (len > 4) {
516 for (i = 0; i < (len >> 2); i++) {
517 *(u32 *) dst = musb_readl(fifo, 0);
518 dst += 4;
519 }
520 len &= 0x03;
521 }
522 if (len > 0) {
523 val = musb_readl(fifo, 0);
524 memcpy(dst, &val, len);
525 }
526}
Felipe Balbi743411b2010-12-01 13:22:05 +0200527
528const struct musb_platform_ops musb_ops = {
529 .init = am35x_musb_init,
530 .exit = am35x_musb_exit,
531
532 .enable = am35x_musb_enable,
533 .disable = am35x_musb_disable,
534
535 .set_mode = am35x_musb_set_mode,
536 .try_idle = am35x_musb_try_idle,
537
538 .set_vbus = am35x_musb_set_vbus,
539};
Felipe Balbice40c572010-12-02 09:06:51 +0200540
541static u64 am35x_dmamask = DMA_BIT_MASK(32);
542
543static int __init am35x_probe(struct platform_device *pdev)
544{
545 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
546 struct platform_device *musb;
547
548 int ret = -ENOMEM;
549
550 musb = platform_device_alloc("musb-hdrc", -1);
551 if (!musb) {
552 dev_err(&pdev->dev, "failed to allocate musb device\n");
553 goto err0;
554 }
555
556 musb->dev.parent = &pdev->dev;
557 musb->dev.dma_mask = &am35x_dmamask;
558 musb->dev.coherent_dma_mask = am35x_dmamask;
559
560 platform_set_drvdata(pdev, musb);
561
562 ret = platform_device_add_resources(musb, pdev->resource,
563 pdev->num_resources);
564 if (ret) {
565 dev_err(&pdev->dev, "failed to add resources\n");
566 goto err1;
567 }
568
569 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
570 if (ret) {
571 dev_err(&pdev->dev, "failed to add platform_data\n");
572 goto err1;
573 }
574
575 ret = platform_device_add(musb);
576 if (ret) {
577 dev_err(&pdev->dev, "failed to register musb device\n");
578 goto err1;
579 }
580
581 return 0;
582
583err1:
584 platform_device_put(musb);
585
586err0:
587 return ret;
588}
589
590static int __exit am35x_remove(struct platform_device *pdev)
591{
592 struct platform_device *musb = platform_get_drvdata(pdev);
593
594 platform_device_del(musb);
595 platform_device_put(musb);
596
597 return 0;
598}
599
600static struct platform_driver am35x_driver = {
601 .remove = __exit_p(am35x_remove),
602 .driver = {
603 .name = "musb-am35x",
604 },
605};
606
607MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
608MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
609MODULE_LICENSE("GPL v2");
610
611static int __init am35x_init(void)
612{
613 return platform_driver_probe(&am35x_driver, am35x_probe);
614}
615subsys_initcall(am35x_init);
616
617static void __exit am35x_exit(void)
618{
619 platform_driver_unregister(&am35x_driver);
620}
621module_exit(am35x_exit);