blob: 1fa38979396853a274242e0771f9c9c939091df5 [file] [log] [blame]
Michael Hennerich59003142007-10-21 16:54:27 +08001/*
2 * File: arch/blackfin/mach-bf537/ints-priority.c
3 * Based on: arch/blackfin/mach-bf533/ints-priority.c
4 * Author: Michael Hennerich (michael.hennerich@analog.com)
5 *
6 * Created:
7 * Description: Set up the interrupt priorities
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/module.h>
31#include <linux/irq.h>
32#include <asm/blackfin.h>
33
34void program_IAR(void)
35{
36 /* Program the IAR0 Register with the configured priority */
37 bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
38 ((CONFIG_IRQ_DMA0_ERROR - 7) << IRQ_DMA0_ERROR_POS) |
39 ((CONFIG_IRQ_DMAR0_BLK - 7) << IRQ_DMAR0_BLK_POS) |
40 ((CONFIG_IRQ_DMAR1_BLK - 7) << IRQ_DMAR1_BLK_POS) |
41 ((CONFIG_IRQ_DMAR0_OVR - 7) << IRQ_DMAR0_OVR_POS) |
42 ((CONFIG_IRQ_DMAR1_OVR - 7) << IRQ_DMAR1_OVR_POS) |
43 ((CONFIG_IRQ_PPI_ERROR - 7) << IRQ_PPI_ERROR_POS) |
44 ((CONFIG_IRQ_MAC_ERROR - 7) << IRQ_MAC_ERROR_POS));
45
46
47 bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
48 ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS) |
49 ((CONFIG_IRQ_UART0_ERROR - 7) << IRQ_UART0_ERROR_POS) |
50 ((CONFIG_IRQ_UART1_ERROR - 7) << IRQ_UART1_ERROR_POS) |
51 ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
52 ((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS));
53
54 bfin_write_SIC_IAR2(((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
55 ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
56 ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
57 ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
58 ((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
59 ((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) |
60 ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
61 ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
62
63 bfin_write_SIC_IAR3(((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
64 ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
65 ((CONFIG_IRQ_OPTSEC - 7) << IRQ_OPTSEC_POS) |
66 ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
67 ((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
68 ((CONFIG_IRQ_PORTH_INTA - 7) << IRQ_PORTH_INTA_POS) |
69 ((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
70 ((CONFIG_IRQ_PORTH_INTB - 7) << IRQ_PORTH_INTB_POS));
71
72 bfin_write_SIC_IAR4(((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) |
73 ((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) |
74 ((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) |
75 ((CONFIG_IRQ_TMR3 - 7) << IRQ_TMR3_POS) |
76 ((CONFIG_IRQ_TMR4 - 7) << IRQ_TMR4_POS) |
77 ((CONFIG_IRQ_TMR5 - 7) << IRQ_TMR5_POS) |
78 ((CONFIG_IRQ_TMR6 - 7) << IRQ_TMR6_POS) |
79 ((CONFIG_IRQ_TMR7 - 7) << IRQ_TMR7_POS));
80
81 bfin_write_SIC_IAR5(((CONFIG_IRQ_PORTG_INTA - 7) << IRQ_PORTG_INTA_POS) |
82 ((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
83 ((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
84 ((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
85 ((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS) |
86 ((CONFIG_IRQ_PORTF_INTA - 7) << IRQ_PORTF_INTA_POS) |
87 ((CONFIG_IRQ_PORTF_INTB - 7) << IRQ_PORTF_INTB_POS) |
88 ((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS));
89
90 bfin_write_SIC_IAR6(((CONFIG_IRQ_NFC_ERROR - 7) << IRQ_NFC_ERROR_POS) |
91 ((CONFIG_IRQ_HDMA_ERROR - 7) << IRQ_HDMA_ERROR_POS) |
92 ((CONFIG_IRQ_HDMA - 7) << IRQ_HDMA_POS) |
93 ((CONFIG_IRQ_USB_EINT - 7) << IRQ_USB_EINT_POS) |
94 ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
95 ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
96 ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
97 ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS));
98
99 SSYNC();
100}