blob: 360f6600427b21919f93b9a39b4129ec01eb6b56 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33/* General customization:
34 */
35
36#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
37
38#define DRIVER_NAME "i915"
39#define DRIVER_DESC "Intel Graphics"
Dave Airliede227f52006-01-25 15:31:43 +110040#define DRIVER_DATE "20060119"
Linus Torvalds1da177e2005-04-16 15:20:36 -070041
42/* Interface history:
43 *
44 * 1.1: Original.
Dave Airlie0d6aa602006-01-02 20:14:23 +110045 * 1.2: Add Power Management
46 * 1.3: Add vblank support
Dave Airliede227f52006-01-25 15:31:43 +110047 * 1.4: Fix cmdbuffer path, add heap destroy
Dave Airlie702880f2006-06-24 17:07:34 +100048 * 1.5: Add vblank pipe configuration
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +100049 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
50 * - Support vertical blank on secondary display pipe
Linus Torvalds1da177e2005-04-16 15:20:36 -070051 */
52#define DRIVER_MAJOR 1
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +100053#define DRIVER_MINOR 6
Linus Torvalds1da177e2005-04-16 15:20:36 -070054#define DRIVER_PATCHLEVEL 0
55
Linus Torvalds1da177e2005-04-16 15:20:36 -070056typedef struct _drm_i915_ring_buffer {
57 int tail_mask;
58 unsigned long Start;
59 unsigned long End;
60 unsigned long Size;
61 u8 *virtual_start;
62 int head;
63 int tail;
64 int space;
65 drm_local_map_t map;
66} drm_i915_ring_buffer_t;
67
68struct mem_block {
69 struct mem_block *next;
70 struct mem_block *prev;
71 int start;
72 int size;
Eric Anholt6c340ea2007-08-25 20:23:09 +100073 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
Linus Torvalds1da177e2005-04-16 15:20:36 -070074};
75
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +100076typedef struct _drm_i915_vbl_swap {
77 struct list_head head;
78 drm_drawable_t drw_id;
79 unsigned int pipe;
80 unsigned int sequence;
81} drm_i915_vbl_swap_t;
82
Linus Torvalds1da177e2005-04-16 15:20:36 -070083typedef struct drm_i915_private {
84 drm_local_map_t *sarea;
85 drm_local_map_t *mmio_map;
86
87 drm_i915_sarea_t *sarea_priv;
88 drm_i915_ring_buffer_t ring;
89
Dave Airlie9c8da5e2005-07-10 15:38:56 +100090 drm_dma_handle_t *status_page_dmah;
Linus Torvalds1da177e2005-04-16 15:20:36 -070091 void *hw_status_page;
Linus Torvalds1da177e2005-04-16 15:20:36 -070092 dma_addr_t dma_status_page;
Dave Airlie9c8da5e2005-07-10 15:38:56 +100093 unsigned long counter;
Wang Zhenyudc7a9312007-06-10 15:58:19 +100094 unsigned int status_gfx_addr;
95 drm_local_map_t hws_map;
Linus Torvalds1da177e2005-04-16 15:20:36 -070096
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +100097 unsigned int cpp;
Linus Torvalds1da177e2005-04-16 15:20:36 -070098 int back_offset;
99 int front_offset;
100 int current_page;
101 int page_flipping;
102 int use_mi_batchbuffer_start;
103
104 wait_queue_head_t irq_queue;
105 atomic_t irq_received;
106 atomic_t irq_emitted;
107
108 int tex_lru_log_granularity;
109 int allow_batchbuffer;
110 struct mem_block *agp_heap;
Dave Airlie0d6aa602006-01-02 20:14:23 +1100111 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
Dave Airlie702880f2006-06-24 17:07:34 +1000112 int vblank_pipe;
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000113
114 spinlock_t swaps_lock;
115 drm_i915_vbl_swap_t vbl_swaps;
116 unsigned int swaps_pending;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000117
118 /* Register state */
119 u8 saveLBB;
120 u32 saveDSPACNTR;
121 u32 saveDSPBCNTR;
122 u32 savePIPEACONF;
123 u32 savePIPEBCONF;
124 u32 savePIPEASRC;
125 u32 savePIPEBSRC;
126 u32 saveFPA0;
127 u32 saveFPA1;
128 u32 saveDPLL_A;
129 u32 saveDPLL_A_MD;
130 u32 saveHTOTAL_A;
131 u32 saveHBLANK_A;
132 u32 saveHSYNC_A;
133 u32 saveVTOTAL_A;
134 u32 saveVBLANK_A;
135 u32 saveVSYNC_A;
136 u32 saveBCLRPAT_A;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000137 u32 savePIPEASTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000138 u32 saveDSPASTRIDE;
139 u32 saveDSPASIZE;
140 u32 saveDSPAPOS;
141 u32 saveDSPABASE;
142 u32 saveDSPASURF;
143 u32 saveDSPATILEOFF;
144 u32 savePFIT_PGM_RATIOS;
145 u32 saveBLC_PWM_CTL;
146 u32 saveBLC_PWM_CTL2;
147 u32 saveFPB0;
148 u32 saveFPB1;
149 u32 saveDPLL_B;
150 u32 saveDPLL_B_MD;
151 u32 saveHTOTAL_B;
152 u32 saveHBLANK_B;
153 u32 saveHSYNC_B;
154 u32 saveVTOTAL_B;
155 u32 saveVBLANK_B;
156 u32 saveVSYNC_B;
157 u32 saveBCLRPAT_B;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000158 u32 savePIPEBSTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000159 u32 saveDSPBSTRIDE;
160 u32 saveDSPBSIZE;
161 u32 saveDSPBPOS;
162 u32 saveDSPBBASE;
163 u32 saveDSPBSURF;
164 u32 saveDSPBTILEOFF;
165 u32 saveVCLK_DIVISOR_VGA0;
166 u32 saveVCLK_DIVISOR_VGA1;
167 u32 saveVCLK_POST_DIV;
168 u32 saveVGACNTRL;
169 u32 saveADPA;
170 u32 saveLVDS;
171 u32 saveLVDSPP_ON;
172 u32 saveLVDSPP_OFF;
173 u32 saveDVOA;
174 u32 saveDVOB;
175 u32 saveDVOC;
176 u32 savePP_ON;
177 u32 savePP_OFF;
178 u32 savePP_CONTROL;
179 u32 savePP_CYCLE;
180 u32 savePFIT_CONTROL;
181 u32 save_palette_a[256];
182 u32 save_palette_b[256];
183 u32 saveFBC_CFB_BASE;
184 u32 saveFBC_LL_BASE;
185 u32 saveFBC_CONTROL;
186 u32 saveFBC_CONTROL2;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000187 u32 saveIER;
188 u32 saveIIR;
189 u32 saveIMR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000190 u32 saveSWF0[16];
191 u32 saveSWF1[16];
192 u32 saveSWF2[3];
193 u8 saveMSR;
194 u8 saveSR[8];
Jesse Barnes123f7942008-02-07 11:15:20 -0800195 u8 saveGR[25];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000196 u8 saveAR_INDEX;
197 u8 saveAR[20];
198 u8 saveDACMASK;
199 u8 saveDACDATA[256*3]; /* 256 3-byte colors */
200 u8 saveCR[36];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201} drm_i915_private_t;
202
Eric Anholtc153f452007-09-03 12:06:45 +1000203extern struct drm_ioctl_desc i915_ioctls[];
Dave Airlieb3a83632005-09-30 18:37:36 +1000204extern int i915_max_ioctl;
205
Linus Torvalds1da177e2005-04-16 15:20:36 -0700206 /* i915_dma.c */
Dave Airlie84b1fd12007-07-11 15:53:27 +1000207extern void i915_kernel_lost_context(struct drm_device * dev);
Dave Airlie22eae942005-11-10 22:16:34 +1100208extern int i915_driver_load(struct drm_device *, unsigned long flags);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000209extern int i915_driver_unload(struct drm_device *);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000210extern void i915_driver_lastclose(struct drm_device * dev);
Eric Anholt6c340ea2007-08-25 20:23:09 +1000211extern void i915_driver_preclose(struct drm_device *dev,
212 struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000213extern int i915_driver_device_is_agp(struct drm_device * dev);
Dave Airlie0d6aa602006-01-02 20:14:23 +1100214extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
215 unsigned long arg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216
217/* i915_irq.c */
Eric Anholtc153f452007-09-03 12:06:45 +1000218extern int i915_irq_emit(struct drm_device *dev, void *data,
219 struct drm_file *file_priv);
220extern int i915_irq_wait(struct drm_device *dev, void *data,
221 struct drm_file *file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222
Dave Airlie84b1fd12007-07-11 15:53:27 +1000223extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
224extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000226extern void i915_driver_irq_preinstall(struct drm_device * dev);
227extern void i915_driver_irq_postinstall(struct drm_device * dev);
228extern void i915_driver_irq_uninstall(struct drm_device * dev);
Eric Anholtc153f452007-09-03 12:06:45 +1000229extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
230 struct drm_file *file_priv);
231extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
232 struct drm_file *file_priv);
233extern int i915_vblank_swap(struct drm_device *dev, void *data,
234 struct drm_file *file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235
236/* i915_mem.c */
Eric Anholtc153f452007-09-03 12:06:45 +1000237extern int i915_mem_alloc(struct drm_device *dev, void *data,
238 struct drm_file *file_priv);
239extern int i915_mem_free(struct drm_device *dev, void *data,
240 struct drm_file *file_priv);
241extern int i915_mem_init_heap(struct drm_device *dev, void *data,
242 struct drm_file *file_priv);
243extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
244 struct drm_file *file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245extern void i915_mem_takedown(struct mem_block **heap);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000246extern void i915_mem_release(struct drm_device * dev,
Eric Anholt6c340ea2007-08-25 20:23:09 +1000247 struct drm_file *file_priv, struct mem_block *heap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248
Dave Airlie0d6aa602006-01-02 20:14:23 +1100249#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
250#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
Dave Airliebc5f4522007-11-05 12:50:58 +1000251#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
Dave Airlie0d6aa602006-01-02 20:14:23 +1100252#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253
254#define I915_VERBOSE 0
255
256#define RING_LOCALS unsigned int outring, ringmask, outcount; \
257 volatile char *virt;
258
259#define BEGIN_LP_RING(n) do { \
260 if (I915_VERBOSE) \
Márton Németh3e684ea2008-01-24 15:58:57 +1000261 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
262 if (dev_priv->ring.space < (n)*4) \
Alan Hourihanec29b6692006-08-12 16:29:24 +1000263 i915_wait_ring(dev, (n)*4, __FUNCTION__); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264 outcount = 0; \
265 outring = dev_priv->ring.tail; \
266 ringmask = dev_priv->ring.tail_mask; \
267 virt = dev_priv->ring.virtual_start; \
268} while (0)
269
270#define OUT_RING(n) do { \
271 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
Alan Hourihanec29b6692006-08-12 16:29:24 +1000272 *(volatile unsigned int *)(virt + outring) = (n); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700273 outcount++; \
274 outring += 4; \
275 outring &= ringmask; \
276} while (0)
277
278#define ADVANCE_LP_RING() do { \
279 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
280 dev_priv->ring.tail = outring; \
281 dev_priv->ring.space -= outcount * 4; \
282 I915_WRITE(LP_RING + RING_TAIL, outring); \
283} while(0)
284
Dave Airlie84b1fd12007-07-11 15:53:27 +1000285extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700286
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000287/* Extended config space */
288#define LBB 0xf4
289
290/* VGA stuff */
291
292#define VGA_ST01_MDA 0x3ba
293#define VGA_ST01_CGA 0x3da
294
295#define VGA_MSR_WRITE 0x3c2
296#define VGA_MSR_READ 0x3cc
297#define VGA_MSR_MEM_EN (1<<1)
298#define VGA_MSR_CGA_MODE (1<<0)
299
300#define VGA_SR_INDEX 0x3c4
301#define VGA_SR_DATA 0x3c5
302
303#define VGA_AR_INDEX 0x3c0
304#define VGA_AR_VID_EN (1<<5)
305#define VGA_AR_DATA_WRITE 0x3c0
306#define VGA_AR_DATA_READ 0x3c1
307
308#define VGA_GR_INDEX 0x3ce
309#define VGA_GR_DATA 0x3cf
310/* GR05 */
311#define VGA_GR_MEM_READ_MODE_SHIFT 3
312#define VGA_GR_MEM_READ_MODE_PLANE 1
313/* GR06 */
314#define VGA_GR_MEM_MODE_MASK 0xc
315#define VGA_GR_MEM_MODE_SHIFT 2
316#define VGA_GR_MEM_A0000_AFFFF 0
317#define VGA_GR_MEM_A0000_BFFFF 1
318#define VGA_GR_MEM_B0000_B7FFF 2
319#define VGA_GR_MEM_B0000_BFFFF 3
320
321#define VGA_DACMASK 0x3c6
322#define VGA_DACRX 0x3c7
323#define VGA_DACWX 0x3c8
324#define VGA_DACDATA 0x3c9
325
326#define VGA_CR_INDEX_MDA 0x3b4
327#define VGA_CR_DATA_MDA 0x3b5
328#define VGA_CR_INDEX_CGA 0x3d4
329#define VGA_CR_DATA_CGA 0x3d5
330
Dave Airliebc5f4522007-11-05 12:50:58 +1000331#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700332#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
333#define CMD_REPORT_HEAD (7<<23)
334#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
335#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
336
337#define INST_PARSER_CLIENT 0x00000000
338#define INST_OP_FLUSH 0x02000000
339#define INST_FLUSH_MAP_CACHE 0x00000001
340
341#define BB1_START_ADDR_MASK (~0x7)
342#define BB1_PROTECTED (1<<0)
343#define BB1_UNPROTECTED (0<<0)
344#define BB2_END_ADDR_MASK (~0x7)
345
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000346/* Framebuffer compression */
347#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
348#define FBC_LL_BASE 0x03204 /* 4k page aligned */
349#define FBC_CONTROL 0x03208
350#define FBC_CTL_EN (1<<31)
351#define FBC_CTL_PERIODIC (1<<30)
352#define FBC_CTL_INTERVAL_SHIFT (16)
353#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
354#define FBC_CTL_STRIDE_SHIFT (5)
355#define FBC_CTL_FENCENO (1<<0)
356#define FBC_COMMAND 0x0320c
357#define FBC_CMD_COMPRESS (1<<0)
358#define FBC_STATUS 0x03210
359#define FBC_STAT_COMPRESSING (1<<31)
360#define FBC_STAT_COMPRESSED (1<<30)
361#define FBC_STAT_MODIFIED (1<<29)
362#define FBC_STAT_CURRENT_LINE (1<<0)
363#define FBC_CONTROL2 0x03214
364#define FBC_CTL_FENCE_DBL (0<<4)
365#define FBC_CTL_IDLE_IMM (0<<2)
366#define FBC_CTL_IDLE_FULL (1<<2)
367#define FBC_CTL_IDLE_LINE (2<<2)
368#define FBC_CTL_IDLE_DEBUG (3<<2)
369#define FBC_CTL_CPU_FENCE (1<<1)
370#define FBC_CTL_PLANEA (0<<0)
371#define FBC_CTL_PLANEB (1<<0)
372#define FBC_FENCE_OFF 0x0321b
373
374#define FBC_LL_SIZE (1536)
375#define FBC_LL_PAD (32)
376
377/* Interrupt bits:
378 */
379#define USER_INT_FLAG (1<<1)
380#define VSYNC_PIPEB_FLAG (1<<5)
381#define VSYNC_PIPEA_FLAG (1<<7)
382#define HWB_OOM_FLAG (1<<13) /* binner out of memory */
383
Linus Torvalds1da177e2005-04-16 15:20:36 -0700384#define I915REG_HWSTAM 0x02098
385#define I915REG_INT_IDENTITY_R 0x020a4
Dave Airliebc5f4522007-11-05 12:50:58 +1000386#define I915REG_INT_MASK_R 0x020a8
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387#define I915REG_INT_ENABLE_R 0x020a0
388
Dave Airliee4a7b1d2007-09-28 11:46:28 +1000389#define I915REG_PIPEASTAT 0x70024
390#define I915REG_PIPEBSTAT 0x71024
391
392#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
393#define I915_VBLANK_CLEAR (1UL<<1)
394
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395#define SRX_INDEX 0x3c4
396#define SRX_DATA 0x3c5
397#define SR01 1
Dave Airliebc5f4522007-11-05 12:50:58 +1000398#define SR01_SCREEN_OFF (1<<5)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399
400#define PPCR 0x61204
401#define PPCR_ON (1<<0)
402
Dave Airlie0d6aa602006-01-02 20:14:23 +1100403#define DVOB 0x61140
404#define DVOB_ON (1<<31)
405#define DVOC 0x61160
406#define DVOC_ON (1<<31)
407#define LVDS 0x61180
408#define LVDS_ON (1<<31)
409
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410#define ADPA 0x61100
411#define ADPA_DPMS_MASK (~(3<<10))
412#define ADPA_DPMS_ON (0<<10)
413#define ADPA_DPMS_SUSPEND (1<<10)
414#define ADPA_DPMS_STANDBY (2<<10)
415#define ADPA_DPMS_OFF (3<<10)
416
417#define NOPID 0x2094
Dave Airliebc5f4522007-11-05 12:50:58 +1000418#define LP_RING 0x2030
419#define HP_RING 0x2040
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000420/* The binner has its own ring buffer:
421 */
422#define HWB_RING 0x2400
423
Dave Airliebc5f4522007-11-05 12:50:58 +1000424#define RING_TAIL 0x00
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425#define TAIL_ADDR 0x001FFFF8
Dave Airliebc5f4522007-11-05 12:50:58 +1000426#define RING_HEAD 0x04
427#define HEAD_WRAP_COUNT 0xFFE00000
428#define HEAD_WRAP_ONE 0x00200000
429#define HEAD_ADDR 0x001FFFFC
430#define RING_START 0x08
431#define START_ADDR 0x0xFFFFF000
432#define RING_LEN 0x0C
433#define RING_NR_PAGES 0x001FF000
434#define RING_REPORT_MASK 0x00000006
435#define RING_REPORT_64K 0x00000002
436#define RING_REPORT_128K 0x00000004
437#define RING_NO_REPORT 0x00000000
438#define RING_VALID_MASK 0x00000001
439#define RING_VALID 0x00000001
440#define RING_INVALID 0x00000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000442/* Instruction parser error reg:
443 */
444#define IPEIR 0x2088
445
446/* Scratch pad debug 0 reg:
447 */
448#define SCPD0 0x209c
449
450/* Error status reg:
451 */
452#define ESR 0x20b8
453
454/* Secondary DMA fetch address debug reg:
455 */
456#define DMA_FADD_S 0x20d4
457
458/* Cache mode 0 reg.
459 * - Manipulating render cache behaviour is central
460 * to the concept of zone rendering, tuning this reg can help avoid
461 * unnecessary render cache reads and even writes (for z/stencil)
462 * at beginning and end of scene.
463 *
464 * - To change a bit, write to this reg with a mask bit set and the
465 * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set.
466 */
467#define Cache_Mode_0 0x2120
468#define CM0_MASK_SHIFT 16
469#define CM0_IZ_OPT_DISABLE (1<<6)
470#define CM0_ZR_OPT_DISABLE (1<<5)
471#define CM0_DEPTH_EVICT_DISABLE (1<<4)
472#define CM0_COLOR_EVICT_DISABLE (1<<3)
473#define CM0_DEPTH_WRITE_DISABLE (1<<1)
474#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
475
476
477/* Graphics flush control. A CPU write flushes the GWB of all writes.
478 * The data is discarded.
479 */
480#define GFX_FLSH_CNTL 0x2170
481
482/* Binner control. Defines the location of the bin pointer list:
483 */
484#define BINCTL 0x2420
485#define BC_MASK (1 << 9)
486
487/* Binned scene info.
488 */
489#define BINSCENE 0x2428
490#define BS_OP_LOAD (1 << 8)
491#define BS_MASK (1 << 22)
492
493/* Bin command parser debug reg:
494 */
495#define BCPD 0x2480
496
497/* Bin memory control debug reg:
498 */
499#define BMCD 0x2484
500
501/* Bin data cache debug reg:
502 */
503#define BDCD 0x2488
504
505/* Binner pointer cache debug reg:
506 */
507#define BPCD 0x248c
508
509/* Binner scratch pad debug reg:
510 */
511#define BINSKPD 0x24f0
512
513/* HWB scratch pad debug reg:
514 */
515#define HWBSKPD 0x24f4
516
517/* Binner memory pool reg:
518 */
519#define BMP_BUFFER 0x2430
520#define BMP_PAGE_SIZE_4K (0 << 10)
521#define BMP_BUFFER_SIZE_SHIFT 1
522#define BMP_ENABLE (1 << 0)
523
524/* Get/put memory from the binner memory pool:
525 */
526#define BMP_GET 0x2438
527#define BMP_PUT 0x2440
528#define BMP_OFFSET_SHIFT 5
529
530/* 3D state packets:
531 */
532#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
533
Linus Torvalds1da177e2005-04-16 15:20:36 -0700534#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
535#define SC_UPDATE_SCISSOR (0x1<<1)
536#define SC_ENABLE_MASK (0x1<<0)
537#define SC_ENABLE (0x1<<0)
538
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000539#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
540
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
542#define SCI_YMIN_MASK (0xffff<<16)
543#define SCI_XMIN_MASK (0xffff<<0)
544#define SCI_YMAX_MASK (0xffff<<16)
545#define SCI_XMAX_MASK (0xffff<<0)
546
547#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
548#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
549#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
550#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
551#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
552#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
553#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
554
Alan Hourihanec29b6692006-08-12 16:29:24 +1000555#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
556
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000557#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000558#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
559#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
560#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
561
Dave Airliebc5f4522007-11-05 12:50:58 +1000562#define MI_BATCH_BUFFER ((0x30<<23)|1)
563#define MI_BATCH_BUFFER_START (0x31<<23)
564#define MI_BATCH_BUFFER_END (0xA<<23)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565#define MI_BATCH_NON_SECURE (1)
Dave Airlie21f16282007-08-07 09:09:51 +1000566#define MI_BATCH_NON_SECURE_I965 (1<<8)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700567
568#define MI_WAIT_FOR_EVENT ((0x3<<23))
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000569#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700570#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
571#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
572
573#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
574
575#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
576#define ASYNC_FLIP (1<<22)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000577#define DISPLAY_PLANE_A (0<<20)
578#define DISPLAY_PLANE_B (1<<20)
579
580/* Display regs */
581#define DSPACNTR 0x70180
582#define DSPBCNTR 0x71180
583#define DISPPLANE_SEL_PIPE_MASK (1<<24)
584
585/* Define the region of interest for the binner:
586 */
587#define CMD_OP_BIN_CONTROL ((0x3<<29)|(0x1d<<24)|(0x84<<16)|4)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700588
589#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
590
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000591#define CMD_MI_FLUSH (0x04 << 23)
592#define MI_NO_WRITE_FLUSH (1 << 2)
593#define MI_READ_FLUSH (1 << 0)
594#define MI_EXE_FLUSH (1 << 1)
595#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
596#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
597
598#define BREADCRUMB_BITS 31
599#define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)
600
601#define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5])
602#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
603
604#define BLC_PWM_CTL 0x61254
605#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
606
607#define BLC_PWM_CTL2 0x61250
608/**
609 * This is the most significant 15 bits of the number of backlight cycles in a
610 * complete cycle of the modulated backlight control.
611 *
612 * The actual value is this field multiplied by two.
613 */
614#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
615#define BLM_LEGACY_MODE (1 << 16)
616/**
617 * This is the number of cycles out of the backlight modulation cycle for which
618 * the backlight is on.
619 *
620 * This field must be no greater than the number of cycles in the complete
621 * backlight modulation cycle.
622 */
623#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
624#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
625
626#define I915_GCFGC 0xf0
627#define I915_LOW_FREQUENCY_ENABLE (1 << 7)
628#define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
629#define I915_DISPLAY_CLOCK_333_MHZ (4 << 4)
630#define I915_DISPLAY_CLOCK_MASK (7 << 4)
631
632#define I855_HPLLCC 0xc0
633#define I855_CLOCK_CONTROL_MASK (3 << 0)
634#define I855_CLOCK_133_200 (0 << 0)
635#define I855_CLOCK_100_200 (1 << 0)
636#define I855_CLOCK_100_133 (2 << 0)
637#define I855_CLOCK_166_250 (3 << 0)
638
639/* p317, 319
640 */
641#define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */
642#define VCLK2_VCO_N 0x600a
643#define VCLK2_VCO_DIV_SEL 0x6012
644
645#define VCLK_DIVISOR_VGA0 0x6000
646#define VCLK_DIVISOR_VGA1 0x6004
647#define VCLK_POST_DIV 0x6010
648/** Selects a post divisor of 4 instead of 2. */
649# define VGA1_PD_P2_DIV_4 (1 << 15)
650/** Overrides the p2 post divisor field */
651# define VGA1_PD_P1_DIV_2 (1 << 13)
652# define VGA1_PD_P1_SHIFT 8
653/** P1 value is 2 greater than this field */
654# define VGA1_PD_P1_MASK (0x1f << 8)
655/** Selects a post divisor of 4 instead of 2. */
656# define VGA0_PD_P2_DIV_4 (1 << 7)
657/** Overrides the p2 post divisor field */
658# define VGA0_PD_P1_DIV_2 (1 << 5)
659# define VGA0_PD_P1_SHIFT 0
660/** P1 value is 2 greater than this field */
661# define VGA0_PD_P1_MASK (0x1f << 0)
662
663/* I830 CRTC registers */
664#define HTOTAL_A 0x60000
665#define HBLANK_A 0x60004
666#define HSYNC_A 0x60008
667#define VTOTAL_A 0x6000c
668#define VBLANK_A 0x60010
669#define VSYNC_A 0x60014
670#define PIPEASRC 0x6001c
671#define BCLRPAT_A 0x60020
672#define VSYNCSHIFT_A 0x60028
673
674#define HTOTAL_B 0x61000
675#define HBLANK_B 0x61004
676#define HSYNC_B 0x61008
677#define VTOTAL_B 0x6100c
678#define VBLANK_B 0x61010
679#define VSYNC_B 0x61014
680#define PIPEBSRC 0x6101c
681#define BCLRPAT_B 0x61020
682#define VSYNCSHIFT_B 0x61028
683
684#define PP_STATUS 0x61200
685# define PP_ON (1 << 31)
686/**
687 * Indicates that all dependencies of the panel are on:
688 *
689 * - PLL enabled
690 * - pipe enabled
691 * - LVDS/DVOB/DVOC on
692 */
693# define PP_READY (1 << 30)
694# define PP_SEQUENCE_NONE (0 << 28)
695# define PP_SEQUENCE_ON (1 << 28)
696# define PP_SEQUENCE_OFF (2 << 28)
697# define PP_SEQUENCE_MASK 0x30000000
698#define PP_CONTROL 0x61204
699# define POWER_TARGET_ON (1 << 0)
700
701#define LVDSPP_ON 0x61208
702#define LVDSPP_OFF 0x6120c
703#define PP_CYCLE 0x61210
704
705#define PFIT_CONTROL 0x61230
706# define PFIT_ENABLE (1 << 31)
707# define PFIT_PIPE_MASK (3 << 29)
708# define PFIT_PIPE_SHIFT 29
709# define VERT_INTERP_DISABLE (0 << 10)
710# define VERT_INTERP_BILINEAR (1 << 10)
711# define VERT_INTERP_MASK (3 << 10)
712# define VERT_AUTO_SCALE (1 << 9)
713# define HORIZ_INTERP_DISABLE (0 << 6)
714# define HORIZ_INTERP_BILINEAR (1 << 6)
715# define HORIZ_INTERP_MASK (3 << 6)
716# define HORIZ_AUTO_SCALE (1 << 5)
717# define PANEL_8TO6_DITHER_ENABLE (1 << 3)
718
719#define PFIT_PGM_RATIOS 0x61234
720# define PFIT_VERT_SCALE_MASK 0xfff00000
721# define PFIT_HORIZ_SCALE_MASK 0x0000fff0
722
723#define PFIT_AUTO_RATIOS 0x61238
724
725
726#define DPLL_A 0x06014
727#define DPLL_B 0x06018
728# define DPLL_VCO_ENABLE (1 << 31)
729# define DPLL_DVO_HIGH_SPEED (1 << 30)
730# define DPLL_SYNCLOCK_ENABLE (1 << 29)
731# define DPLL_VGA_MODE_DIS (1 << 28)
732# define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
733# define DPLLB_MODE_LVDS (2 << 26) /* i915 */
734# define DPLL_MODE_MASK (3 << 26)
735# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
736# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
737# define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
738# define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
739# define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
740# define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
741/**
742 * The i830 generation, in DAC/serial mode, defines p1 as two plus this
743 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
744 */
745# define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
746/**
747 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
748 * this field (only one bit may be set).
749 */
750# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
751# define DPLL_FPA01_P1_POST_DIV_SHIFT 16
752# define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */
753# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
754# define PLL_REF_INPUT_DREFCLK (0 << 13)
755# define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
756# define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
757# define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
758# define PLL_REF_INPUT_MASK (3 << 13)
759# define PLL_LOAD_PULSE_PHASE_SHIFT 9
760/*
761 * Parallel to Serial Load Pulse phase selection.
762 * Selects the phase for the 10X DPLL clock for the PCIe
763 * digital display port. The range is 4 to 13; 10 or more
764 * is just a flip delay. The default is 6
765 */
766# define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
767# define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
768
769/**
770 * SDVO multiplier for 945G/GM. Not used on 965.
771 *
772 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
773 */
774# define SDVO_MULTIPLIER_MASK 0x000000ff
775# define SDVO_MULTIPLIER_SHIFT_HIRES 4
776# define SDVO_MULTIPLIER_SHIFT_VGA 0
777
778/** @defgroup DPLL_MD
779 * @{
780 */
781/** Pipe A SDVO/UDI clock multiplier/divider register for G965. */
782#define DPLL_A_MD 0x0601c
783/** Pipe B SDVO/UDI clock multiplier/divider register for G965. */
784#define DPLL_B_MD 0x06020
785/**
786 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
787 *
788 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
789 */
790# define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
791# define DPLL_MD_UDI_DIVIDER_SHIFT 24
792/** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
793# define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
794# define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
795/**
796 * SDVO/UDI pixel multiplier.
797 *
798 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
799 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
800 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
801 * dummy bytes in the datastream at an increased clock rate, with both sides of
802 * the link knowing how many bytes are fill.
803 *
804 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
805 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
806 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
807 * through an SDVO command.
808 *
809 * This register field has values of multiplication factor minus 1, with
810 * a maximum multiplier of 5 for SDVO.
811 */
812# define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
813# define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
814/** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
815 * This best be set to the default value (3) or the CRT won't work. No,
816 * I don't entirely understand what this does...
817 */
818# define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
819# define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
820/** @} */
821
822#define DPLL_TEST 0x606c
823# define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
824# define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
825# define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
826# define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
827# define DPLLB_TEST_N_BYPASS (1 << 19)
828# define DPLLB_TEST_M_BYPASS (1 << 18)
829# define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
830# define DPLLA_TEST_N_BYPASS (1 << 3)
831# define DPLLA_TEST_M_BYPASS (1 << 2)
832# define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
833
834#define ADPA 0x61100
835#define ADPA_DAC_ENABLE (1<<31)
836#define ADPA_DAC_DISABLE 0
837#define ADPA_PIPE_SELECT_MASK (1<<30)
838#define ADPA_PIPE_A_SELECT 0
839#define ADPA_PIPE_B_SELECT (1<<30)
840#define ADPA_USE_VGA_HVPOLARITY (1<<15)
841#define ADPA_SETS_HVPOLARITY 0
842#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
843#define ADPA_VSYNC_CNTL_ENABLE 0
844#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
845#define ADPA_HSYNC_CNTL_ENABLE 0
846#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
847#define ADPA_VSYNC_ACTIVE_LOW 0
848#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
849#define ADPA_HSYNC_ACTIVE_LOW 0
850
851#define FPA0 0x06040
852#define FPA1 0x06044
853#define FPB0 0x06048
854#define FPB1 0x0604c
855# define FP_N_DIV_MASK 0x003f0000
856# define FP_N_DIV_SHIFT 16
857# define FP_M1_DIV_MASK 0x00003f00
858# define FP_M1_DIV_SHIFT 8
859# define FP_M2_DIV_MASK 0x0000003f
860# define FP_M2_DIV_SHIFT 0
861
862
863#define PORT_HOTPLUG_EN 0x61110
864# define SDVOB_HOTPLUG_INT_EN (1 << 26)
865# define SDVOC_HOTPLUG_INT_EN (1 << 25)
866# define TV_HOTPLUG_INT_EN (1 << 18)
867# define CRT_HOTPLUG_INT_EN (1 << 9)
868# define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
869
870#define PORT_HOTPLUG_STAT 0x61114
871# define CRT_HOTPLUG_INT_STATUS (1 << 11)
872# define TV_HOTPLUG_INT_STATUS (1 << 10)
873# define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
874# define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
875# define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
876# define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
877# define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
878# define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
879
880#define SDVOB 0x61140
881#define SDVOC 0x61160
882#define SDVO_ENABLE (1 << 31)
883#define SDVO_PIPE_B_SELECT (1 << 30)
884#define SDVO_STALL_SELECT (1 << 29)
885#define SDVO_INTERRUPT_ENABLE (1 << 26)
886/**
887 * 915G/GM SDVO pixel multiplier.
888 *
889 * Programmed value is multiplier - 1, up to 5x.
890 *
891 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
892 */
893#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
894#define SDVO_PORT_MULTIPLY_SHIFT 23
895#define SDVO_PHASE_SELECT_MASK (15 << 19)
896#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
897#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
898#define SDVOC_GANG_MODE (1 << 16)
899#define SDVO_BORDER_ENABLE (1 << 7)
900#define SDVOB_PCIE_CONCURRENCY (1 << 3)
901#define SDVO_DETECTED (1 << 2)
902/* Bits to be preserved when writing */
903#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14))
904#define SDVOC_PRESERVE_MASK (1 << 17)
905
906/** @defgroup LVDS
907 * @{
908 */
909/**
910 * This register controls the LVDS output enable, pipe selection, and data
911 * format selection.
912 *
913 * All of the clock/data pairs are force powered down by power sequencing.
914 */
915#define LVDS 0x61180
916/**
917 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
918 * the DPLL semantics change when the LVDS is assigned to that pipe.
919 */
920# define LVDS_PORT_EN (1 << 31)
921/** Selects pipe B for LVDS data. Must be set on pre-965. */
922# define LVDS_PIPEB_SELECT (1 << 30)
923
924/**
925 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
926 * pixel.
927 */
928# define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
929# define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
930# define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
931/**
932 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
933 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
934 * on.
935 */
936# define LVDS_A3_POWER_MASK (3 << 6)
937# define LVDS_A3_POWER_DOWN (0 << 6)
938# define LVDS_A3_POWER_UP (3 << 6)
939/**
940 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
941 * is set.
942 */
943# define LVDS_CLKB_POWER_MASK (3 << 4)
944# define LVDS_CLKB_POWER_DOWN (0 << 4)
945# define LVDS_CLKB_POWER_UP (3 << 4)
946
947/**
948 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
949 * setting for whether we are in dual-channel mode. The B3 pair will
950 * additionally only be powered up when LVDS_A3_POWER_UP is set.
951 */
952# define LVDS_B0B3_POWER_MASK (3 << 2)
953# define LVDS_B0B3_POWER_DOWN (0 << 2)
954# define LVDS_B0B3_POWER_UP (3 << 2)
955
956#define PIPEACONF 0x70008
957#define PIPEACONF_ENABLE (1<<31)
958#define PIPEACONF_DISABLE 0
959#define PIPEACONF_DOUBLE_WIDE (1<<30)
960#define I965_PIPECONF_ACTIVE (1<<30)
961#define PIPEACONF_SINGLE_WIDE 0
962#define PIPEACONF_PIPE_UNLOCKED 0
963#define PIPEACONF_PIPE_LOCKED (1<<25)
964#define PIPEACONF_PALETTE 0
965#define PIPEACONF_GAMMA (1<<24)
966#define PIPECONF_FORCE_BORDER (1<<25)
967#define PIPECONF_PROGRESSIVE (0 << 21)
968#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
969#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
970
971#define PIPEBCONF 0x71008
972#define PIPEBCONF_ENABLE (1<<31)
973#define PIPEBCONF_DISABLE 0
974#define PIPEBCONF_DOUBLE_WIDE (1<<30)
975#define PIPEBCONF_DISABLE 0
976#define PIPEBCONF_GAMMA (1<<24)
977#define PIPEBCONF_PALETTE 0
978
979#define PIPEBGCMAXRED 0x71010
980#define PIPEBGCMAXGREEN 0x71014
981#define PIPEBGCMAXBLUE 0x71018
982#define PIPEBSTAT 0x71024
983#define PIPEBFRAMEHIGH 0x71040
984#define PIPEBFRAMEPIXEL 0x71044
985
986#define DSPACNTR 0x70180
987#define DSPBCNTR 0x71180
988#define DISPLAY_PLANE_ENABLE (1<<31)
989#define DISPLAY_PLANE_DISABLE 0
990#define DISPPLANE_GAMMA_ENABLE (1<<30)
991#define DISPPLANE_GAMMA_DISABLE 0
992#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
993#define DISPPLANE_8BPP (0x2<<26)
994#define DISPPLANE_15_16BPP (0x4<<26)
995#define DISPPLANE_16BPP (0x5<<26)
996#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
997#define DISPPLANE_32BPP (0x7<<26)
998#define DISPPLANE_STEREO_ENABLE (1<<25)
999#define DISPPLANE_STEREO_DISABLE 0
1000#define DISPPLANE_SEL_PIPE_MASK (1<<24)
1001#define DISPPLANE_SEL_PIPE_A 0
1002#define DISPPLANE_SEL_PIPE_B (1<<24)
1003#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
1004#define DISPPLANE_SRC_KEY_DISABLE 0
1005#define DISPPLANE_LINE_DOUBLE (1<<20)
1006#define DISPPLANE_NO_LINE_DOUBLE 0
1007#define DISPPLANE_STEREO_POLARITY_FIRST 0
1008#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1009/* plane B only */
1010#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
1011#define DISPPLANE_ALPHA_TRANS_DISABLE 0
1012#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
1013#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
1014
1015#define DSPABASE 0x70184
1016#define DSPASTRIDE 0x70188
1017
1018#define DSPBBASE 0x71184
1019#define DSPBADDR DSPBBASE
1020#define DSPBSTRIDE 0x71188
1021
1022#define DSPAKEYVAL 0x70194
1023#define DSPAKEYMASK 0x70198
1024
1025#define DSPAPOS 0x7018C /* reserved */
1026#define DSPASIZE 0x70190
1027#define DSPBPOS 0x7118C
1028#define DSPBSIZE 0x71190
1029
1030#define DSPASURF 0x7019C
1031#define DSPATILEOFF 0x701A4
1032
1033#define DSPBSURF 0x7119C
1034#define DSPBTILEOFF 0x711A4
1035
1036#define VGACNTRL 0x71400
1037# define VGA_DISP_DISABLE (1 << 31)
1038# define VGA_2X_MODE (1 << 30)
1039# define VGA_PIPE_B_SELECT (1 << 29)
1040
1041/*
1042 * Some BIOS scratch area registers. The 845 (and 830?) store the amount
1043 * of video memory available to the BIOS in SWF1.
1044 */
1045
1046#define SWF0 0x71410
1047
1048/*
1049 * 855 scratch registers.
1050 */
1051#define SWF10 0x70410
1052
1053#define SWF30 0x72414
1054
1055/*
1056 * Overlay registers. These are overlay registers accessed via MMIO.
1057 * Those loaded via the overlay register page are defined in i830_video.c.
1058 */
1059#define OVADD 0x30000
1060
1061#define DOVSTA 0x30008
1062#define OC_BUF (0x3<<20)
1063
1064#define OGAMC5 0x30010
1065#define OGAMC4 0x30014
1066#define OGAMC3 0x30018
1067#define OGAMC2 0x3001c
1068#define OGAMC1 0x30020
1069#define OGAMC0 0x30024
1070/*
1071 * Palette registers
1072 */
1073#define PALETTE_A 0x0a000
1074#define PALETTE_B 0x0a800
1075
1076#define IS_I830(dev) ((dev)->pci_device == 0x3577)
1077#define IS_845G(dev) ((dev)->pci_device == 0x2562)
1078#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
1079#define IS_I855(dev) ((dev)->pci_device == 0x3582)
1080#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1081
Carlos Martín4d1f7882008-01-23 16:41:17 +10001082#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001083#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1084#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1085#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2)
1086
1087#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
1088 (dev)->pci_device == 0x2982 || \
1089 (dev)->pci_device == 0x2992 || \
1090 (dev)->pci_device == 0x29A2 || \
1091 (dev)->pci_device == 0x2A02 || \
Zhenyu Wang5f5f9d42008-01-24 16:46:36 +10001092 (dev)->pci_device == 0x2A12 || \
1093 (dev)->pci_device == 0x2A42)
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001094
1095#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
1096
Zhenyu Wang5f5f9d42008-01-24 16:46:36 +10001097#define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42)
1098
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001099#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
1100 (dev)->pci_device == 0x29B2 || \
1101 (dev)->pci_device == 0x29D2)
1102
1103#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
1104 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
1105
1106#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
Zhenyu Wang5f5f9d42008-01-24 16:46:36 +10001107 IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev))
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001108
Zhenyu Wangb39d50e2008-02-19 20:59:09 +10001109#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev))
1110
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001111#define PRIMARY_RINGBUFFER_SIZE (128*1024)
Dave Airlie0d6aa602006-01-02 20:14:23 +11001112
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113#endif