Blame - drivers/gpu/drm/radeon/rs600d.h - kernel/msm

Jerome Glisse

c010f80

2009-09-30 22:09:06 +0200

[diff] [blame]

/*

*

* Permission is hereby granted, free of charge, to any person obtaining a

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* copy of this software and associated documentation files (the "Software"),

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* to deal in the Software without restriction, including without limitation

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* the rights to use, copy, modify, merge, publish, distribute, sublicense,

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* and/or sell copies of the Software, and to permit persons to whom the

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* Software is furnished to do so, subject to the following conditions:

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*

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* The above copyright notice and this permission notice shall be included in

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* all copies or substantial portions of the Software.

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*

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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

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* OTHER DEALINGS IN THE SOFTWARE.

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*

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* Authors: Dave Airlie

* Alex Deucher

* Jerome Glisse

*/

#ifndef __RS600D_H__

#define __RS600D_H__

/* Registers */

#define R_000040_GEN_INT_CNTL 0x000040

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2009-12-03 13:08:53 -0500

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#define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18)

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#define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1)

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#define C_000040_SCRATCH_INT_MASK 0xFFFBFFFF

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#define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19)

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#define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1)

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#define C_000040_GUI_IDLE_MASK 0xFFF7FFFF

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#define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13)

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#define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1)

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#define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF

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#define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14)

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#define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1)

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#define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF

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#define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15)

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#define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1)

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#define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF

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#define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17)

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#define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1)

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#define C_000040_I2C_INT_EN 0xFFFDFFFF

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#define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19)

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#define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1)

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#define C_000040_GUI_IDLE 0xFFF7FFFF

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#define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24)

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#define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1)

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#define C_000040_VIPH_INT_EN 0xFEFFFFFF

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#define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25)

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#define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1)

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#define C_000040_SW_INT_EN 0xFDFFFFFF

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#define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27)

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#define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1)

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#define C_000040_GEYSERVILLE 0xF7FFFFFF

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#define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28)

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#define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1)

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#define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF

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#define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29)

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#define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1)

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#define C_000040_DVI_I2C_INT 0xDFFFFFFF

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#define S_000040_GUIDMA(x) (((x) & 0x1) << 30)

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#define G_000040_GUIDMA(x) (((x) >> 30) & 0x1)

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#define C_000040_GUIDMA 0xBFFFFFFF

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#define S_000040_VIDDMA(x) (((x) & 0x1) << 31)

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#define G_000040_VIDDMA(x) (((x) >> 31) & 0x1)

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#define C_000040_VIDDMA 0x7FFFFFFF

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#define R_000044_GEN_INT_STATUS 0x000044

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#define S_000044_DISPLAY_INT_STAT(x) (((x) & 0x1) << 0)

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#define G_000044_DISPLAY_INT_STAT(x) (((x) >> 0) & 0x1)

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#define C_000044_DISPLAY_INT_STAT 0xFFFFFFFE

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#define S_000044_VGA_INT_STAT(x) (((x) & 0x1) << 1)

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#define G_000044_VGA_INT_STAT(x) (((x) >> 1) & 0x1)

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#define C_000044_VGA_INT_STAT 0xFFFFFFFD

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#define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8)

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#define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1)

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#define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF

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#define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12)

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#define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1)

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#define C_000044_DMA_VIPH0_INT 0xFFFFEFFF

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#define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13)

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#define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1)

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#define C_000044_DMA_VIPH1_INT 0xFFFFDFFF

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#define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14)

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#define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1)

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#define C_000044_DMA_VIPH2_INT 0xFFFFBFFF

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#define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15)

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#define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1)

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#define C_000044_DMA_VIPH3_INT 0xFFFF7FFF

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#define S_000044_MC_PROBE_FAULT_STAT(x) (((x) & 0x1) << 16)

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#define G_000044_MC_PROBE_FAULT_STAT(x) (((x) >> 16) & 0x1)

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#define C_000044_MC_PROBE_FAULT_STAT 0xFFFEFFFF

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#define S_000044_I2C_INT(x) (((x) & 0x1) << 17)

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#define G_000044_I2C_INT(x) (((x) >> 17) & 0x1)

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#define C_000044_I2C_INT 0xFFFDFFFF

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#define S_000044_SCRATCH_INT_STAT(x) (((x) & 0x1) << 18)

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#define G_000044_SCRATCH_INT_STAT(x) (((x) >> 18) & 0x1)

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#define C_000044_SCRATCH_INT_STAT 0xFFFBFFFF

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#define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19)

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#define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1)

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#define C_000044_GUI_IDLE_STAT 0xFFF7FFFF

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#define S_000044_ATI_OVERDRIVE_INT_STAT(x) (((x) & 0x1) << 20)

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#define G_000044_ATI_OVERDRIVE_INT_STAT(x) (((x) >> 20) & 0x1)

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#define C_000044_ATI_OVERDRIVE_INT_STAT 0xFFEFFFFF

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#define S_000044_MC_PROTECTION_FAULT_STAT(x) (((x) & 0x1) << 21)

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#define G_000044_MC_PROTECTION_FAULT_STAT(x) (((x) >> 21) & 0x1)

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#define C_000044_MC_PROTECTION_FAULT_STAT 0xFFDFFFFF

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#define S_000044_RBBM_READ_INT_STAT(x) (((x) & 0x1) << 22)

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#define G_000044_RBBM_READ_INT_STAT(x) (((x) >> 22) & 0x1)

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#define C_000044_RBBM_READ_INT_STAT 0xFFBFFFFF

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#define S_000044_CB_CONTEXT_SWITCH_STAT(x) (((x) & 0x1) << 23)

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#define G_000044_CB_CONTEXT_SWITCH_STAT(x) (((x) >> 23) & 0x1)

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#define C_000044_CB_CONTEXT_SWITCH_STAT 0xFF7FFFFF

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#define S_000044_VIPH_INT(x) (((x) & 0x1) << 24)

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#define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1)

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#define C_000044_VIPH_INT 0xFEFFFFFF

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#define S_000044_SW_INT(x) (((x) & 0x1) << 25)

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#define G_000044_SW_INT(x) (((x) >> 25) & 0x1)

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#define C_000044_SW_INT 0xFDFFFFFF

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#define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26)

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#define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1)

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#define C_000044_SW_INT_SET 0xFBFFFFFF

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#define S_000044_IDCT_INT_STAT(x) (((x) & 0x1) << 27)

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#define G_000044_IDCT_INT_STAT(x) (((x) >> 27) & 0x1)

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#define C_000044_IDCT_INT_STAT 0xF7FFFFFF

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#define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30)

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#define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1)

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#define C_000044_GUIDMA_STAT 0xBFFFFFFF

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#define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31)

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#define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1)

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#define C_000044_VIDDMA_STAT 0x7FFFFFFF

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#define R_00004C_BUS_CNTL 0x00004C

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#define S_00004C_BUS_MASTER_DIS(x) (((x) & 0x1) << 14)

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#define G_00004C_BUS_MASTER_DIS(x) (((x) >> 14) & 0x1)

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#define C_00004C_BUS_MASTER_DIS 0xFFFFBFFF

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#define S_00004C_BUS_MSI_REARM(x) (((x) & 0x1) << 20)

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#define G_00004C_BUS_MSI_REARM(x) (((x) >> 20) & 0x1)

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#define C_00004C_BUS_MSI_REARM 0xFFEFFFFF

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#define R_000070_MC_IND_INDEX 0x000070

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#define S_000070_MC_IND_ADDR(x) (((x) & 0xFFFF) << 0)

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#define G_000070_MC_IND_ADDR(x) (((x) >> 0) & 0xFFFF)

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#define C_000070_MC_IND_ADDR 0xFFFF0000

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#define S_000070_MC_IND_SEQ_RBS_0(x) (((x) & 0x1) << 16)

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#define G_000070_MC_IND_SEQ_RBS_0(x) (((x) >> 16) & 0x1)

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#define C_000070_MC_IND_SEQ_RBS_0 0xFFFEFFFF

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#define S_000070_MC_IND_SEQ_RBS_1(x) (((x) & 0x1) << 17)

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#define G_000070_MC_IND_SEQ_RBS_1(x) (((x) >> 17) & 0x1)

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#define C_000070_MC_IND_SEQ_RBS_1 0xFFFDFFFF

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#define S_000070_MC_IND_SEQ_RBS_2(x) (((x) & 0x1) << 18)

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#define G_000070_MC_IND_SEQ_RBS_2(x) (((x) >> 18) & 0x1)

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#define C_000070_MC_IND_SEQ_RBS_2 0xFFFBFFFF

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#define S_000070_MC_IND_SEQ_RBS_3(x) (((x) & 0x1) << 19)

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#define G_000070_MC_IND_SEQ_RBS_3(x) (((x) >> 19) & 0x1)

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#define C_000070_MC_IND_SEQ_RBS_3 0xFFF7FFFF

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#define S_000070_MC_IND_AIC_RBS(x) (((x) & 0x1) << 20)

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#define G_000070_MC_IND_AIC_RBS(x) (((x) >> 20) & 0x1)

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#define C_000070_MC_IND_AIC_RBS 0xFFEFFFFF

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#define S_000070_MC_IND_CITF_ARB0(x) (((x) & 0x1) << 21)

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#define G_000070_MC_IND_CITF_ARB0(x) (((x) >> 21) & 0x1)

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#define C_000070_MC_IND_CITF_ARB0 0xFFDFFFFF

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#define S_000070_MC_IND_CITF_ARB1(x) (((x) & 0x1) << 22)

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#define G_000070_MC_IND_CITF_ARB1(x) (((x) >> 22) & 0x1)

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#define C_000070_MC_IND_CITF_ARB1 0xFFBFFFFF

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#define S_000070_MC_IND_WR_EN(x) (((x) & 0x1) << 23)

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#define G_000070_MC_IND_WR_EN(x) (((x) >> 23) & 0x1)

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#define C_000070_MC_IND_WR_EN 0xFF7FFFFF

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#define S_000070_MC_IND_RD_INV(x) (((x) & 0x1) << 24)

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#define G_000070_MC_IND_RD_INV(x) (((x) >> 24) & 0x1)

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#define C_000070_MC_IND_RD_INV 0xFEFFFFFF

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#define R_000074_MC_IND_DATA 0x000074

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#define S_000074_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0)

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#define G_000074_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF)

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#define C_000074_MC_IND_DATA 0x00000000

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#define R_0000F0_RBBM_SOFT_RESET 0x0000F0

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#define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0)

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#define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1)

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#define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE

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#define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1)

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#define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1)

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#define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD

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#define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2)

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#define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1)

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#define C_0000F0_SOFT_RESET_VAP 0xFFFFFFFB

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#define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3)

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#define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1)

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#define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7

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#define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4)

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#define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1)

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#define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF

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#define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5)

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#define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1)

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#define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF

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#define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6)

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#define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1)

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#define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF

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#define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7)

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#define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1)

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#define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F

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#define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8)

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#define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1)

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#define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF

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#define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9)

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#define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1)

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#define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF

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#define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10)

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#define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1)

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#define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF

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#define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11)

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#define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1)

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#define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF

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#define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12)

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#define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1)

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#define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF

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#define S_0000F0_SOFT_RESET_GA(x) (((x) & 0x1) << 13)

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#define G_0000F0_SOFT_RESET_GA(x) (((x) >> 13) & 0x1)

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#define C_0000F0_SOFT_RESET_GA 0xFFFFDFFF

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#define S_0000F0_SOFT_RESET_IDCT(x) (((x) & 0x1) << 14)

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#define G_0000F0_SOFT_RESET_IDCT(x) (((x) >> 14) & 0x1)

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#define C_0000F0_SOFT_RESET_IDCT 0xFFFFBFFF

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#define R_000134_HDP_FB_LOCATION 0x000134

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#define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0)

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#define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF)

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#define C_000134_HDP_FB_START 0xFFFF0000

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#define R_0007C0_CP_STAT 0x0007C0

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#define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)

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#define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)

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#define C_0007C0_MRU_BUSY 0xFFFFFFFE

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#define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)

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#define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)

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#define C_0007C0_MWU_BUSY 0xFFFFFFFD

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#define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)

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#define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)

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#define C_0007C0_RSIU_BUSY 0xFFFFFFFB

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#define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)

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#define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)

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#define C_0007C0_RCIU_BUSY 0xFFFFFFF7

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#define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)

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#define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)

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#define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF

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#define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10)

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#define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1)

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#define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF

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#define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11)

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#define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1)

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#define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF

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#define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12)

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#define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1)

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#define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF

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#define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13)

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#define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1)

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#define C_0007C0_CSI_BUSY 0xFFFFDFFF

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#define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14)

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#define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1)

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#define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF

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#define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15)

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#define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1)

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#define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF

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#define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28)

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#define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1)

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#define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF

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#define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29)

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#define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1)

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#define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF

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#define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30)

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#define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1)

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#define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF

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#define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31)

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#define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1)

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#define C_0007C0_CP_BUSY 0x7FFFFFFF

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#define R_000E40_RBBM_STATUS 0x000E40

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#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0)

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#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F)

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#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80

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#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8)

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#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1)

283

#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF

284

#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9)

285

#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1)

286

#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF

287

#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10)

288

#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1)

289

#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF

290

#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11)

291

#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1)

292

#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF

293

#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12)

294

#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1)

295

#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF

296

#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13)

297

#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1)

298

#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF

299

#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14)

300

#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1)

301

#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF

302

#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15)

303

#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1)

304

#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF

305

#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16)

306

#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1)

307

#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF

308

#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17)

309

#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1)

310

#define C_000E40_E2_BUSY 0xFFFDFFFF

311

#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18)

312

#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1)

313

#define C_000E40_RB2D_BUSY 0xFFFBFFFF

314

#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19)

315

#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1)

316

#define C_000E40_RB3D_BUSY 0xFFF7FFFF

317

#define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20)

318

#define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1)

319

#define C_000E40_VAP_BUSY 0xFFEFFFFF

320

#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21)

321

#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1)

322

#define C_000E40_RE_BUSY 0xFFDFFFFF

323

#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22)

324

#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1)

325

#define C_000E40_TAM_BUSY 0xFFBFFFFF

326

#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23)

327

#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1)

328

#define C_000E40_TDM_BUSY 0xFF7FFFFF

329

#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24)

330

#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1)

331

#define C_000E40_PB_BUSY 0xFEFFFFFF

332

#define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25)

333

#define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1)

334

#define C_000E40_TIM_BUSY 0xFDFFFFFF

335

#define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26)

336

#define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1)

337

#define C_000E40_GA_BUSY 0xFBFFFFFF

338

#define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27)

339

#define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1)

340

#define C_000E40_CBA2D_BUSY 0xF7FFFFFF

341

#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31)

342

#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1)

343

#define C_000E40_GUI_ACTIVE 0x7FFFFFFF

344

#define R_0060A4_D1CRTC_STATUS_FRAME_COUNT 0x0060A4

345

#define S_0060A4_D1CRTC_FRAME_COUNT(x) (((x) & 0xFFFFFF) << 0)

346

#define G_0060A4_D1CRTC_FRAME_COUNT(x) (((x) >> 0) & 0xFFFFFF)

347

#define C_0060A4_D1CRTC_FRAME_COUNT 0xFF000000

348

#define R_006534_D1MODE_VBLANK_STATUS 0x006534

349

#define S_006534_D1MODE_VBLANK_OCCURRED(x) (((x) & 0x1) << 0)

350

#define G_006534_D1MODE_VBLANK_OCCURRED(x) (((x) >> 0) & 0x1)

351

#define C_006534_D1MODE_VBLANK_OCCURRED 0xFFFFFFFE

352

#define S_006534_D1MODE_VBLANK_ACK(x) (((x) & 0x1) << 4)

353

#define G_006534_D1MODE_VBLANK_ACK(x) (((x) >> 4) & 0x1)

354

#define C_006534_D1MODE_VBLANK_ACK 0xFFFFFFEF

355

#define S_006534_D1MODE_VBLANK_STAT(x) (((x) & 0x1) << 12)

356

#define G_006534_D1MODE_VBLANK_STAT(x) (((x) >> 12) & 0x1)

357

#define C_006534_D1MODE_VBLANK_STAT 0xFFFFEFFF

358

#define S_006534_D1MODE_VBLANK_INTERRUPT(x) (((x) & 0x1) << 16)

359

#define G_006534_D1MODE_VBLANK_INTERRUPT(x) (((x) >> 16) & 0x1)

360

#define C_006534_D1MODE_VBLANK_INTERRUPT 0xFFFEFFFF

361

#define R_006540_DxMODE_INT_MASK 0x006540

362

#define S_006540_D1MODE_VBLANK_INT_MASK(x) (((x) & 0x1) << 0)

363

#define G_006540_D1MODE_VBLANK_INT_MASK(x) (((x) >> 0) & 0x1)

364

#define C_006540_D1MODE_VBLANK_INT_MASK 0xFFFFFFFE

365

#define S_006540_D1MODE_VLINE_INT_MASK(x) (((x) & 0x1) << 4)

366

#define G_006540_D1MODE_VLINE_INT_MASK(x) (((x) >> 4) & 0x1)

367

#define C_006540_D1MODE_VLINE_INT_MASK 0xFFFFFFEF

368

#define S_006540_D2MODE_VBLANK_INT_MASK(x) (((x) & 0x1) << 8)

369

#define G_006540_D2MODE_VBLANK_INT_MASK(x) (((x) >> 8) & 0x1)

370

#define C_006540_D2MODE_VBLANK_INT_MASK 0xFFFFFEFF

371

#define S_006540_D2MODE_VLINE_INT_MASK(x) (((x) & 0x1) << 12)

372

#define G_006540_D2MODE_VLINE_INT_MASK(x) (((x) >> 12) & 0x1)

373

#define C_006540_D2MODE_VLINE_INT_MASK 0xFFFFEFFF

374

#define S_006540_D1MODE_VBLANK_CP_SEL(x) (((x) & 0x1) << 30)

375

#define G_006540_D1MODE_VBLANK_CP_SEL(x) (((x) >> 30) & 0x1)

376

#define C_006540_D1MODE_VBLANK_CP_SEL 0xBFFFFFFF

377

#define S_006540_D2MODE_VBLANK_CP_SEL(x) (((x) & 0x1) << 31)

378

#define G_006540_D2MODE_VBLANK_CP_SEL(x) (((x) >> 31) & 0x1)

379

#define C_006540_D2MODE_VBLANK_CP_SEL 0x7FFFFFFF

380

#define R_0068A4_D2CRTC_STATUS_FRAME_COUNT 0x0068A4

381

#define S_0068A4_D2CRTC_FRAME_COUNT(x) (((x) & 0xFFFFFF) << 0)

382

#define G_0068A4_D2CRTC_FRAME_COUNT(x) (((x) >> 0) & 0xFFFFFF)

383

#define C_0068A4_D2CRTC_FRAME_COUNT 0xFF000000

384

#define R_006D34_D2MODE_VBLANK_STATUS 0x006D34

385

#define S_006D34_D2MODE_VBLANK_OCCURRED(x) (((x) & 0x1) << 0)

386

#define G_006D34_D2MODE_VBLANK_OCCURRED(x) (((x) >> 0) & 0x1)

387

#define C_006D34_D2MODE_VBLANK_OCCURRED 0xFFFFFFFE

388

#define S_006D34_D2MODE_VBLANK_ACK(x) (((x) & 0x1) << 4)

389

#define G_006D34_D2MODE_VBLANK_ACK(x) (((x) >> 4) & 0x1)

390

#define C_006D34_D2MODE_VBLANK_ACK 0xFFFFFFEF

391

#define S_006D34_D2MODE_VBLANK_STAT(x) (((x) & 0x1) << 12)

392

#define G_006D34_D2MODE_VBLANK_STAT(x) (((x) >> 12) & 0x1)

393

#define C_006D34_D2MODE_VBLANK_STAT 0xFFFFEFFF

394

#define S_006D34_D2MODE_VBLANK_INTERRUPT(x) (((x) & 0x1) << 16)

395

#define G_006D34_D2MODE_VBLANK_INTERRUPT(x) (((x) >> 16) & 0x1)

396

#define C_006D34_D2MODE_VBLANK_INTERRUPT 0xFFFEFFFF

397

#define R_007EDC_DISP_INTERRUPT_STATUS 0x007EDC

398

#define S_007EDC_LB_D1_VBLANK_INTERRUPT(x) (((x) & 0x1) << 4)

399

#define G_007EDC_LB_D1_VBLANK_INTERRUPT(x) (((x) >> 4) & 0x1)

400

#define C_007EDC_LB_D1_VBLANK_INTERRUPT 0xFFFFFFEF

401

#define S_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) & 0x1) << 5)

402

#define G_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) >> 5) & 0x1)

403

#define C_007EDC_LB_D2_VBLANK_INTERRUPT 0xFFFFFFDF

Alex Deucher

b500f68

2009-12-03 13:08:53 -0500

[diff] [blame]

404

#define S_007EDC_DACA_AUTODETECT_INTERRUPT(x) (((x) & 0x1) << 16)

405

#define G_007EDC_DACA_AUTODETECT_INTERRUPT(x) (((x) >> 16) & 0x1)

406

#define C_007EDC_DACA_AUTODETECT_INTERRUPT 0xFFFEFFFF

407

#define S_007EDC_DACB_AUTODETECT_INTERRUPT(x) (((x) & 0x1) << 17)

408

#define G_007EDC_DACB_AUTODETECT_INTERRUPT(x) (((x) >> 17) & 0x1)

409

#define C_007EDC_DACB_AUTODETECT_INTERRUPT 0xFFFDFFFF

410

#define S_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x) (((x) & 0x1) << 18)

411

#define G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x) (((x) >> 18) & 0x1)

412

#define C_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT 0xFFFBFFFF

413

#define S_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x) (((x) & 0x1) << 19)

414

#define G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x) (((x) >> 19) & 0x1)

415

#define C_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT 0xFFF7FFFF

416

#define R_007828_DACA_AUTODETECT_CONTROL 0x007828

417

#define S_007828_DACA_AUTODETECT_MODE(x) (((x) & 0x3) << 0)

418

#define G_007828_DACA_AUTODETECT_MODE(x) (((x) >> 0) & 0x3)

419

#define C_007828_DACA_AUTODETECT_MODE 0xFFFFFFFC

420

#define S_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8)

421

#define G_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff)

422

#define C_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER 0xFFFF00FF

423

#define S_007828_DACA_AUTODETECT_CHECK_MASK(x) (((x) & 0x3) << 16)

424

#define G_007828_DACA_AUTODETECT_CHECK_MASK(x) (((x) >> 16) & 0x3)

425

#define C_007828_DACA_AUTODETECT_CHECK_MASK 0xFFFCFFFF

426

#define R_007838_DACA_AUTODETECT_INT_CONTROL 0x007838

427

#define S_007838_DACA_AUTODETECT_ACK(x) (((x) & 0x1) << 0)

428

#define C_007838_DACA_DACA_AUTODETECT_ACK 0xFFFFFFFE

429

#define S_007838_DACA_AUTODETECT_INT_ENABLE(x) (((x) & 0x1) << 16)

430

#define G_007838_DACA_AUTODETECT_INT_ENABLE(x) (((x) >> 16) & 0x1)

431

#define C_007838_DACA_AUTODETECT_INT_ENABLE 0xFFFCFFFF

432

#define R_007A28_DACB_AUTODETECT_CONTROL 0x007A28

433

#define S_007A28_DACB_AUTODETECT_MODE(x) (((x) & 0x3) << 0)

434

#define G_007A28_DACB_AUTODETECT_MODE(x) (((x) >> 0) & 0x3)

435

#define C_007A28_DACB_AUTODETECT_MODE 0xFFFFFFFC

436

#define S_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8)

437

#define G_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff)

438

#define C_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER 0xFFFF00FF

439

#define S_007A28_DACB_AUTODETECT_CHECK_MASK(x) (((x) & 0x3) << 16)

440

#define G_007A28_DACB_AUTODETECT_CHECK_MASK(x) (((x) >> 16) & 0x3)

441

#define C_007A28_DACB_AUTODETECT_CHECK_MASK 0xFFFCFFFF

442

#define R_007A38_DACB_AUTODETECT_INT_CONTROL 0x007A38

443

#define S_007A38_DACB_AUTODETECT_ACK(x) (((x) & 0x1) << 0)

444

#define C_007A38_DACB_DACA_AUTODETECT_ACK 0xFFFFFFFE

445

#define S_007A38_DACB_AUTODETECT_INT_ENABLE(x) (((x) & 0x1) << 16)

446

#define G_007A38_DACB_AUTODETECT_INT_ENABLE(x) (((x) >> 16) & 0x1)

447

#define C_007A38_DACB_AUTODETECT_INT_ENABLE 0xFFFCFFFF

448

#define R_007D00_DC_HOT_PLUG_DETECT1_CONTROL 0x007D00

449

#define S_007D00_DC_HOT_PLUG_DETECT1_EN(x) (((x) & 0x1) << 0)

450

#define G_007D00_DC_HOT_PLUG_DETECT1_EN(x) (((x) >> 0) & 0x1)

451

#define C_007D00_DC_HOT_PLUG_DETECT1_EN 0xFFFFFFFE

452

#define R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS 0x007D04

453

#define S_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x) (((x) & 0x1) << 0)

454

#define G_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x) (((x) >> 0) & 0x1)

455

#define C_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS 0xFFFFFFFE

456

#define S_007D04_DC_HOT_PLUG_DETECT1_SENSE(x) (((x) & 0x1) << 1)

457

#define G_007D04_DC_HOT_PLUG_DETECT1_SENSE(x) (((x) >> 1) & 0x1)

458

#define C_007D04_DC_HOT_PLUG_DETECT1_SENSE 0xFFFFFFFD

459

#define R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL 0x007D08

460

#define S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(x) (((x) & 0x1) << 0)

461

#define C_007D08_DC_HOT_PLUG_DETECT1_INT_ACK 0xFFFFFFFE

462

#define S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) & 0x1) << 8)

463

#define G_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) >> 8) & 0x1)

464

#define C_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY 0xFFFFFEFF

465

#define S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x) (((x) & 0x1) << 16)

466

#define G_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x) (((x) >> 16) & 0x1)

467

#define C_007D08_DC_HOT_PLUG_DETECT1_INT_EN 0xFFFEFFFF

468

#define R_007D10_DC_HOT_PLUG_DETECT2_CONTROL 0x007D10

469

#define S_007D10_DC_HOT_PLUG_DETECT2_EN(x) (((x) & 0x1) << 0)

470

#define G_007D10_DC_HOT_PLUG_DETECT2_EN(x) (((x) >> 0) & 0x1)

471

#define C_007D10_DC_HOT_PLUG_DETECT2_EN 0xFFFFFFFE

472

#define R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS 0x007D14

473

#define S_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x) (((x) & 0x1) << 0)

474

#define G_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x) (((x) >> 0) & 0x1)

475

#define C_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS 0xFFFFFFFE

476

#define S_007D14_DC_HOT_PLUG_DETECT2_SENSE(x) (((x) & 0x1) << 1)

477

#define G_007D14_DC_HOT_PLUG_DETECT2_SENSE(x) (((x) >> 1) & 0x1)

478

#define C_007D14_DC_HOT_PLUG_DETECT2_SENSE 0xFFFFFFFD

479

#define R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL 0x007D18

480

#define S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(x) (((x) & 0x1) << 0)

481

#define C_007D18_DC_HOT_PLUG_DETECT2_INT_ACK 0xFFFFFFFE

482

#define S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) & 0x1) << 8)

483

#define G_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) >> 8) & 0x1)

484

#define C_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY 0xFFFFFEFF

485

#define S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x) (((x) & 0x1) << 16)

486

#define G_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x) (((x) >> 16) & 0x1)

487

#define C_007D18_DC_HOT_PLUG_DETECT2_INT_EN 0xFFFEFFFF

Jerome Glisse

c010f80

2009-09-30 22:09:06 +0200

[diff] [blame]

488

489

/* MC registers */

490

#define R_000000_MC_STATUS 0x000000

491

#define S_000000_MC_IDLE(x) (((x) & 0x1) << 0)

492

#define G_000000_MC_IDLE(x) (((x) >> 0) & 0x1)

493

#define C_000000_MC_IDLE 0xFFFFFFFE

494

#define R_000004_MC_FB_LOCATION 0x000004

495

#define S_000004_MC_FB_START(x) (((x) & 0xFFFF) << 0)

496

#define G_000004_MC_FB_START(x) (((x) >> 0) & 0xFFFF)

497

#define C_000004_MC_FB_START 0xFFFF0000

498

#define S_000004_MC_FB_TOP(x) (((x) & 0xFFFF) << 16)

499

#define G_000004_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF)

500

#define C_000004_MC_FB_TOP 0x0000FFFF

501

#define R_000005_MC_AGP_LOCATION 0x000005

502

#define S_000005_MC_AGP_START(x) (((x) & 0xFFFF) << 0)

503

#define G_000005_MC_AGP_START(x) (((x) >> 0) & 0xFFFF)

504

#define C_000005_MC_AGP_START 0xFFFF0000

505

#define S_000005_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16)

506

#define G_000005_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF)

507

#define C_000005_MC_AGP_TOP 0x0000FFFF

508

#define R_000006_AGP_BASE 0x000006

509

#define S_000006_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)

510

#define G_000006_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)

511

#define C_000006_AGP_BASE_ADDR 0x00000000

512

#define R_000007_AGP_BASE_2 0x000007

513

#define S_000007_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0)

514

#define G_000007_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF)

515

#define C_000007_AGP_BASE_ADDR_2 0xFFFFFFF0

516

#define R_000009_MC_CNTL1 0x000009

517

#define S_000009_ENABLE_PAGE_TABLES(x) (((x) & 0x1) << 26)

518

#define G_000009_ENABLE_PAGE_TABLES(x) (((x) >> 26) & 0x1)

519

#define C_000009_ENABLE_PAGE_TABLES 0xFBFFFFFF

520

/* FIXME don't know the various field size need feedback from AMD */

521

#define R_000100_MC_PT0_CNTL 0x000100

522

#define S_000100_ENABLE_PT(x) (((x) & 0x1) << 0)

523

#define G_000100_ENABLE_PT(x) (((x) >> 0) & 0x1)

524

#define C_000100_ENABLE_PT 0xFFFFFFFE

525

#define S_000100_EFFECTIVE_L2_CACHE_SIZE(x) (((x) & 0x7) << 15)

526

#define G_000100_EFFECTIVE_L2_CACHE_SIZE(x) (((x) >> 15) & 0x7)

527

#define C_000100_EFFECTIVE_L2_CACHE_SIZE 0xFFFC7FFF

528

#define S_000100_EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 0x7) << 21)

529

#define G_000100_EFFECTIVE_L2_QUEUE_SIZE(x) (((x) >> 21) & 0x7)

530

#define C_000100_EFFECTIVE_L2_QUEUE_SIZE 0xFF1FFFFF

531

#define S_000100_INVALIDATE_ALL_L1_TLBS(x) (((x) & 0x1) << 28)

532

#define G_000100_INVALIDATE_ALL_L1_TLBS(x) (((x) >> 28) & 0x1)

533

#define C_000100_INVALIDATE_ALL_L1_TLBS 0xEFFFFFFF

534

#define S_000100_INVALIDATE_L2_CACHE(x) (((x) & 0x1) << 29)

535

#define G_000100_INVALIDATE_L2_CACHE(x) (((x) >> 29) & 0x1)

536

#define C_000100_INVALIDATE_L2_CACHE 0xDFFFFFFF

537

#define R_000102_MC_PT0_CONTEXT0_CNTL 0x000102

538

#define S_000102_ENABLE_PAGE_TABLE(x) (((x) & 0x1) << 0)

539

#define G_000102_ENABLE_PAGE_TABLE(x) (((x) >> 0) & 0x1)

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#define C_000102_ENABLE_PAGE_TABLE 0xFFFFFFFE

541

#define S_000102_PAGE_TABLE_DEPTH(x) (((x) & 0x3) << 1)

542

#define G_000102_PAGE_TABLE_DEPTH(x) (((x) >> 1) & 0x3)

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#define C_000102_PAGE_TABLE_DEPTH 0xFFFFFFF9

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#define V_000102_PAGE_TABLE_FLAT 0

545

/* R600 documentation suggest that this should be a number of pages */

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#define R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x000112

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#define R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x000114

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#define R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x00011C

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#define R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x00012C

550

#define R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x00013C

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#define R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x00014C

552

#define R_00016C_MC_PT0_CLIENT0_CNTL 0x00016C

553

#define S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 0)

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#define G_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 0) & 0x1)

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#define C_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE 0xFFFFFFFE

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#define S_00016C_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 1)

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#define G_00016C_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 1) & 0x1)

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#define C_00016C_TRANSLATION_MODE_OVERRIDE 0xFFFFFFFD

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#define S_00016C_SYSTEM_ACCESS_MODE_MASK(x) (((x) & 0x3) << 8)

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#define G_00016C_SYSTEM_ACCESS_MODE_MASK(x) (((x) >> 8) & 0x3)

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#define C_00016C_SYSTEM_ACCESS_MODE_MASK 0xFFFFFCFF

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#define V_00016C_SYSTEM_ACCESS_MODE_PA_ONLY 0

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#define V_00016C_SYSTEM_ACCESS_MODE_USE_SYS_MAP 1

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#define V_00016C_SYSTEM_ACCESS_MODE_IN_SYS 2

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#define V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS 3

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#define S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x) (((x) & 0x1) << 10)

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#define G_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x) (((x) >> 10) & 0x1)

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#define C_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS 0xFFFFFBFF

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#define V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH 0

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#define V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE 1

571

#define S_00016C_EFFECTIVE_L1_CACHE_SIZE(x) (((x) & 0x7) << 11)

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#define G_00016C_EFFECTIVE_L1_CACHE_SIZE(x) (((x) >> 11) & 0x7)

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#define C_00016C_EFFECTIVE_L1_CACHE_SIZE 0xFFFFC7FF

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#define S_00016C_ENABLE_FRAGMENT_PROCESSING(x) (((x) & 0x1) << 14)

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#define G_00016C_ENABLE_FRAGMENT_PROCESSING(x) (((x) >> 14) & 0x1)

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#define C_00016C_ENABLE_FRAGMENT_PROCESSING 0xFFFFBFFF

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#define S_00016C_EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 0x7) << 15)

578

#define G_00016C_EFFECTIVE_L1_QUEUE_SIZE(x) (((x) >> 15) & 0x7)

579

#define C_00016C_EFFECTIVE_L1_QUEUE_SIZE 0xFFFC7FFF

580

#define S_00016C_INVALIDATE_L1_TLB(x) (((x) & 0x1) << 20)

581

#define G_00016C_INVALIDATE_L1_TLB(x) (((x) >> 20) & 0x1)

582

#define C_00016C_INVALIDATE_L1_TLB 0xFFEFFFFF

583

Alex Deucher

f46c012

2010-03-31 00:33:27 -0400

[diff] [blame]

584

#define R_006548_D1MODE_PRIORITY_A_CNT 0x006548

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#define S_006548_D1MODE_PRIORITY_MARK_A(x) (((x) & 0x7FFF) << 0)

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#define G_006548_D1MODE_PRIORITY_MARK_A(x) (((x) >> 0) & 0x7FFF)

587

#define C_006548_D1MODE_PRIORITY_MARK_A 0xFFFF8000

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#define S_006548_D1MODE_PRIORITY_A_OFF(x) (((x) & 0x1) << 16)

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#define G_006548_D1MODE_PRIORITY_A_OFF(x) (((x) >> 16) & 0x1)

590

#define C_006548_D1MODE_PRIORITY_A_OFF 0xFFFEFFFF

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#define S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x) (((x) & 0x1) << 20)

592

#define G_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x) (((x) >> 20) & 0x1)

593

#define C_006548_D1MODE_PRIORITY_A_ALWAYS_ON 0xFFEFFFFF

594

#define S_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) & 0x1) << 24)

595

#define G_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) >> 24) & 0x1)

596

#define C_006548_D1MODE_PRIORITY_A_FORCE_MASK 0xFEFFFFFF

597

#define R_00654C_D1MODE_PRIORITY_B_CNT 0x00654C

598

#define S_00654C_D1MODE_PRIORITY_MARK_B(x) (((x) & 0x7FFF) << 0)

599

#define G_00654C_D1MODE_PRIORITY_MARK_B(x) (((x) >> 0) & 0x7FFF)

600

#define C_00654C_D1MODE_PRIORITY_MARK_B 0xFFFF8000

601

#define S_00654C_D1MODE_PRIORITY_B_OFF(x) (((x) & 0x1) << 16)

602

#define G_00654C_D1MODE_PRIORITY_B_OFF(x) (((x) >> 16) & 0x1)

603

#define C_00654C_D1MODE_PRIORITY_B_OFF 0xFFFEFFFF

604

#define S_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x) (((x) & 0x1) << 20)

605

#define G_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x) (((x) >> 20) & 0x1)

606

#define C_00654C_D1MODE_PRIORITY_B_ALWAYS_ON 0xFFEFFFFF

607

#define S_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x) (((x) & 0x1) << 24)

608

#define G_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x) (((x) >> 24) & 0x1)

609

#define C_00654C_D1MODE_PRIORITY_B_FORCE_MASK 0xFEFFFFFF

610

#define R_006D48_D2MODE_PRIORITY_A_CNT 0x006D48

611

#define S_006D48_D2MODE_PRIORITY_MARK_A(x) (((x) & 0x7FFF) << 0)

612

#define G_006D48_D2MODE_PRIORITY_MARK_A(x) (((x) >> 0) & 0x7FFF)

613

#define C_006D48_D2MODE_PRIORITY_MARK_A 0xFFFF8000

614

#define S_006D48_D2MODE_PRIORITY_A_OFF(x) (((x) & 0x1) << 16)

615

#define G_006D48_D2MODE_PRIORITY_A_OFF(x) (((x) >> 16) & 0x1)

616

#define C_006D48_D2MODE_PRIORITY_A_OFF 0xFFFEFFFF

617

#define S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x) (((x) & 0x1) << 20)

618

#define G_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x) (((x) >> 20) & 0x1)

619

#define C_006D48_D2MODE_PRIORITY_A_ALWAYS_ON 0xFFEFFFFF

620

#define S_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x) (((x) & 0x1) << 24)

621

#define G_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x) (((x) >> 24) & 0x1)

622

#define C_006D48_D2MODE_PRIORITY_A_FORCE_MASK 0xFEFFFFFF

623

#define R_006D4C_D2MODE_PRIORITY_B_CNT 0x006D4C

624

#define S_006D4C_D2MODE_PRIORITY_MARK_B(x) (((x) & 0x7FFF) << 0)

625

#define G_006D4C_D2MODE_PRIORITY_MARK_B(x) (((x) >> 0) & 0x7FFF)

626

#define C_006D4C_D2MODE_PRIORITY_MARK_B 0xFFFF8000

627

#define S_006D4C_D2MODE_PRIORITY_B_OFF(x) (((x) & 0x1) << 16)

628

#define G_006D4C_D2MODE_PRIORITY_B_OFF(x) (((x) >> 16) & 0x1)

629

#define C_006D4C_D2MODE_PRIORITY_B_OFF 0xFFFEFFFF

630

#define S_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x) (((x) & 0x1) << 20)

631

#define G_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x) (((x) >> 20) & 0x1)

632

#define C_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON 0xFFEFFFFF

633

#define S_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x) (((x) & 0x1) << 24)

634

#define G_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x) (((x) >> 24) & 0x1)

635

#define C_006D4C_D2MODE_PRIORITY_B_FORCE_MASK 0xFEFFFFFF

636

Alex Deucher

49e02b7

2010-04-23 17:57:27 -0400

[diff] [blame]

637

/* PLL regs */

638

#define GENERAL_PWRMGT 0x8

639

#define GLOBAL_PWRMGT_EN (1 << 0)

640

#define MOBILE_SU (1 << 2)

641

#define DYN_PWRMGT_SCLK_LENGTH 0xc

642

#define NORMAL_POWER_SCLK_HILEN(x) ((x) << 0)

643

#define NORMAL_POWER_SCLK_LOLEN(x) ((x) << 4)

644

#define REDUCED_POWER_SCLK_HILEN(x) ((x) << 8)

645

#define REDUCED_POWER_SCLK_LOLEN(x) ((x) << 12)

646

#define POWER_D1_SCLK_HILEN(x) ((x) << 16)

647

#define POWER_D1_SCLK_LOLEN(x) ((x) << 20)

648

#define STATIC_SCREEN_HILEN(x) ((x) << 24)

649

#define STATIC_SCREEN_LOLEN(x) ((x) << 28)

650

#define DYN_SCLK_VOL_CNTL 0xe

651

#define IO_CG_VOLTAGE_DROP (1 << 0)

652

#define VOLTAGE_DROP_SYNC (1 << 2)

653

#define VOLTAGE_DELAY_SEL(x) ((x) << 3)

654

#define HDP_DYN_CNTL 0x10

655

#define HDP_FORCEON (1 << 0)

656

#define MC_HOST_DYN_CNTL 0x1e

657

#define MC_HOST_FORCEON (1 << 0)

Alex Deucher

536fcd5

2010-04-29 16:33:38 -0400

[diff] [blame]

658

#define DYN_BACKBIAS_CNTL 0x29

659

#define IO_CG_BACKBIAS_EN (1 << 0)

Alex Deucher

49e02b7

2010-04-23 17:57:27 -0400

[diff] [blame]

660

661

/* mmreg */

662

#define DOUT_POWER_MANAGEMENT_CNTL 0x7ee0

663

#define PWRDN_WAIT_BUSY_OFF (1 << 0)

664

#define PWRDN_WAIT_PWRSEQ_OFF (1 << 4)

665

#define PWRDN_WAIT_PPLL_OFF (1 << 8)

666

#define PWRUP_WAIT_PPLL_ON (1 << 12)

667

#define PWRUP_WAIT_MEM_INIT_DONE (1 << 16)

668

#define PM_ASSERT_RESET (1 << 20)

669

#define PM_PWRDN_PPLL (1 << 24)

670

Jerome Glisse

c010f80

2009-09-30 22:09:06 +0200

[diff] [blame]

671

#endif