Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap3/sram.S |
| 3 | * |
| 4 | * Omap3 specific functions that need to be run in internal SRAM |
| 5 | * |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 6 | * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc. |
| 7 | * Copyright (C) 2008 Nokia Corporation |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 8 | * |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 9 | * Rajendra Nayak <rnayak@ti.com> |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 10 | * Richard Woodruff <r-woodruff2@ti.com> |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 11 | * Paul Walmsley |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 12 | * |
| 13 | * This program is free software; you can redistribute it and/or |
| 14 | * modify it under the terms of the GNU General Public License as |
| 15 | * published by the Free Software Foundation; either version 2 of |
| 16 | * the License, or (at your option) any later version. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
| 21 | * GNU General Public License for more details. |
| 22 | * |
| 23 | * You should have received a copy of the GNU General Public License |
| 24 | * along with this program; if not, write to the Free Software |
| 25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 26 | * MA 02111-1307 USA |
| 27 | */ |
| 28 | #include <linux/linkage.h> |
| 29 | #include <asm/assembler.h> |
| 30 | #include <mach/hardware.h> |
| 31 | |
| 32 | #include <mach/io.h> |
| 33 | |
| 34 | #include "sdrc.h" |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 35 | #include "cm2xxx_3xxx.h" |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 36 | |
| 37 | .text |
| 38 | |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 39 | /* r1 parameters */ |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 40 | #define SDRC_NO_UNLOCK_DLL 0x0 |
| 41 | #define SDRC_UNLOCK_DLL 0x1 |
| 42 | |
| 43 | /* SDRC_DLLA_CTRL bit settings */ |
Paul Walmsley | 7b7bcef | 2009-06-19 19:08:29 -0600 | [diff] [blame] | 44 | #define FIXEDDELAY_SHIFT 24 |
| 45 | #define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT) |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 46 | #define DLLIDLE_MASK 0x4 |
| 47 | |
Paul Walmsley | 7b7bcef | 2009-06-19 19:08:29 -0600 | [diff] [blame] | 48 | /* |
| 49 | * SDRC_DLLA_CTRL default values: TI hardware team indicates that |
| 50 | * FIXEDDELAY should be initialized to 0xf. This apparently was |
| 51 | * empirically determined during process testing, so no derivation |
| 52 | * was provided. |
| 53 | */ |
| 54 | #define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT) |
| 55 | |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 56 | /* SDRC_DLLA_STATUS bit settings */ |
| 57 | #define LOCKSTATUS_MASK 0x4 |
| 58 | |
| 59 | /* SDRC_POWER bit settings */ |
| 60 | #define SRFRONIDLEREQ_MASK 0x40 |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 61 | |
| 62 | /* CM_IDLEST1_CORE bit settings */ |
| 63 | #define ST_SDRC_MASK 0x2 |
| 64 | |
| 65 | /* CM_ICLKEN1_CORE bit settings */ |
| 66 | #define EN_SDRC_MASK 0x2 |
| 67 | |
| 68 | /* CM_CLKSEL1_PLL bit settings */ |
| 69 | #define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b |
| 70 | |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 71 | /* |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 72 | * omap3_sram_configure_core_dpll - change DPLL3 M2 divider |
Paul Walmsley | c9812d0 | 2009-06-19 19:08:26 -0600 | [diff] [blame] | 73 | * |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 74 | * Params passed in registers: |
| 75 | * r0 = new M2 divider setting (only 1 and 2 supported right now) |
| 76 | * r1 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for |
| 77 | * SDRC rates < 83MHz |
| 78 | * r2 = number of MPU cycles to wait for SDRC to stabilize after |
| 79 | * reprogramming the SDRC when switching to a slower MPU speed |
| 80 | * r3 = increasing SDRC rate? (1 = yes, 0 = no) |
| 81 | * |
| 82 | * Params passed via the stack. The needed params will be copied in SRAM |
| 83 | * before use by the code in SRAM (SDRAM is not accessible during SDRC |
| 84 | * reconfiguration): |
| 85 | * new SDRC_RFR_CTRL_0 register contents |
| 86 | * new SDRC_ACTIM_CTRL_A_0 register contents |
| 87 | * new SDRC_ACTIM_CTRL_B_0 register contents |
| 88 | * new SDRC_MR_0 register value |
| 89 | * new SDRC_RFR_CTRL_1 register contents |
| 90 | * new SDRC_ACTIM_CTRL_A_1 register contents |
| 91 | * new SDRC_ACTIM_CTRL_B_1 register contents |
| 92 | * new SDRC_MR_1 register value |
| 93 | * |
Paul Walmsley | 18862cb | 2009-12-08 16:33:14 -0700 | [diff] [blame] | 94 | * If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into |
| 95 | * the SDRC CS1 registers |
| 96 | * |
| 97 | * NOTE: This code no longer attempts to program the SDRC AC timing and MR |
| 98 | * registers. This is because the code currently cannot ensure that all |
| 99 | * L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the |
| 100 | * SDRAM when the registers are written. If the registers are changed while |
| 101 | * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC |
| 102 | * may enter an unpredictable state. In the future, the intent is to |
| 103 | * re-enable this code in cases where we can ensure that no initiators are |
| 104 | * touching the SDRAM. Until that time, users who know that their use case |
| 105 | * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING |
| 106 | * option. |
Paul Walmsley | 1124d2f | 2010-12-21 21:08:14 -0700 | [diff] [blame^] | 107 | * |
| 108 | * Richard Woodruff notes that any changes to this code must be carefully |
| 109 | * audited and tested to ensure that they don't cause a TLB miss while |
| 110 | * the SDRAM is inaccessible. Such a situation will crash the system |
| 111 | * since it will cause the ARM MMU to attempt to walk the page tables. |
| 112 | * These crashes may be intermittent. |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 113 | */ |
| 114 | ENTRY(omap3_sram_configure_core_dpll) |
| 115 | stmfd sp!, {r1-r12, lr} @ store regs to stack |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 116 | |
| 117 | @ pull the extra args off the stack |
| 118 | @ and store them in SRAM |
| 119 | ldr r4, [sp, #52] |
| 120 | str r4, omap_sdrc_rfr_ctrl_0_val |
| 121 | ldr r4, [sp, #56] |
| 122 | str r4, omap_sdrc_actim_ctrl_a_0_val |
| 123 | ldr r4, [sp, #60] |
| 124 | str r4, omap_sdrc_actim_ctrl_b_0_val |
| 125 | ldr r4, [sp, #64] |
| 126 | str r4, omap_sdrc_mr_0_val |
| 127 | ldr r4, [sp, #68] |
| 128 | str r4, omap_sdrc_rfr_ctrl_1_val |
| 129 | cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0, |
| 130 | beq skip_cs1_params @ do not use cs1 params |
| 131 | ldr r4, [sp, #72] |
| 132 | str r4, omap_sdrc_actim_ctrl_a_1_val |
| 133 | ldr r4, [sp, #76] |
| 134 | str r4, omap_sdrc_actim_ctrl_b_1_val |
| 135 | ldr r4, [sp, #80] |
| 136 | str r4, omap_sdrc_mr_1_val |
| 137 | skip_cs1_params: |
Jon Hunter | a3fed9b | 2010-09-27 14:02:59 -0600 | [diff] [blame] | 138 | mrc p15, 0, r8, c1, c0, 0 @ read ctrl register |
| 139 | bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction |
| 140 | mcr p15, 0, r10, c1, c0, 0 @ write ctrl register |
Paul Walmsley | 69d4255 | 2009-05-12 17:27:09 -0600 | [diff] [blame] | 141 | dsb @ flush buffered writes to interconnect |
Jon Hunter | a3fed9b | 2010-09-27 14:02:59 -0600 | [diff] [blame] | 142 | isb @ prevent speculative exec past here |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 143 | cmp r3, #1 @ if increasing SDRC clk rate, |
Tero Kristo | 3afec63 | 2009-06-19 19:08:29 -0600 | [diff] [blame] | 144 | bleq configure_sdrc @ program the SDRC regs early (for RFR) |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 145 | cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state |
Paul Walmsley | 4519c2b | 2009-05-12 17:26:32 -0600 | [diff] [blame] | 146 | bleq unlock_dll |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 147 | blne lock_dll |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 148 | bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC |
| 149 | bl configure_core_dpll @ change the DPLL3 M2 divider |
Rajendra Nayak | df56556 | 2009-07-24 19:44:02 -0600 | [diff] [blame] | 150 | mov r12, r2 |
| 151 | bl wait_clk_stable @ wait for SDRC to stabilize |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 152 | bl enable_sdrc @ take SDRC out of idle |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 153 | cmp r1, #SDRC_UNLOCK_DLL @ wait for DLL status to change |
Paul Walmsley | 4519c2b | 2009-05-12 17:26:32 -0600 | [diff] [blame] | 154 | bleq wait_dll_unlock |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 155 | blne wait_dll_lock |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 156 | cmp r3, #1 @ if increasing SDRC clk rate, |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 157 | beq return_to_sdram @ return to SDRAM code, otherwise, |
| 158 | bl configure_sdrc @ reprogram SDRC regs now |
Paul Walmsley | c9812d0 | 2009-06-19 19:08:26 -0600 | [diff] [blame] | 159 | return_to_sdram: |
Jon Hunter | a3fed9b | 2010-09-27 14:02:59 -0600 | [diff] [blame] | 160 | mcr p15, 0, r8, c1, c0, 0 @ restore ctrl register |
Paul Walmsley | 69d4255 | 2009-05-12 17:27:09 -0600 | [diff] [blame] | 161 | isb @ prevent speculative exec past here |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 162 | mov r0, #0 @ return value |
| 163 | ldmfd sp!, {r1-r12, pc} @ restore regs and return |
| 164 | unlock_dll: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 165 | ldr r11, omap3_sdrc_dlla_ctrl |
| 166 | ldr r12, [r11] |
Rajendra Nayak | 8ff120e | 2009-07-24 19:44:01 -0600 | [diff] [blame] | 167 | bic r12, r12, #FIXEDDELAY_MASK |
Paul Walmsley | 7b7bcef | 2009-06-19 19:08:29 -0600 | [diff] [blame] | 168 | orr r12, r12, #FIXEDDELAY_DEFAULT |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 169 | orr r12, r12, #DLLIDLE_MASK |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 170 | str r12, [r11] @ (no OCP barrier needed) |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 171 | bx lr |
| 172 | lock_dll: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 173 | ldr r11, omap3_sdrc_dlla_ctrl |
| 174 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 175 | bic r12, r12, #DLLIDLE_MASK |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 176 | str r12, [r11] @ (no OCP barrier needed) |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 177 | bx lr |
| 178 | sdram_in_selfrefresh: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 179 | ldr r11, omap3_sdrc_power @ read the SDRC_POWER register |
| 180 | ldr r12, [r11] @ read the contents of SDRC_POWER |
| 181 | mov r9, r12 @ keep a copy of SDRC_POWER bits |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 182 | orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 183 | str r12, [r11] @ write back to SDRC_POWER register |
| 184 | ldr r12, [r11] @ posted-write barrier for SDRC |
Paul Walmsley | 4267b5d | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 185 | idle_sdrc: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 186 | ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg |
| 187 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 188 | bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 189 | str r12, [r11] |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 190 | wait_sdrc_idle: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 191 | ldr r11, omap3_cm_idlest1_core |
| 192 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 193 | and r12, r12, #ST_SDRC_MASK @ check for SDRC idle |
| 194 | cmp r12, #ST_SDRC_MASK |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 195 | bne wait_sdrc_idle |
| 196 | bx lr |
| 197 | configure_core_dpll: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 198 | ldr r11, omap3_cm_clksel1_pll |
| 199 | ldr r12, [r11] |
| 200 | ldr r10, core_m2_mask_val @ modify m2 for core dpll |
| 201 | and r12, r12, r10 |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 202 | orr r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 203 | str r12, [r11] |
| 204 | ldr r12, [r11] @ posted-write barrier for CM |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 205 | bx lr |
| 206 | wait_clk_stable: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 207 | subs r12, r12, #1 |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 208 | bne wait_clk_stable |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 209 | bx lr |
| 210 | enable_sdrc: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 211 | ldr r11, omap3_cm_iclken1_core |
| 212 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 213 | orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 214 | str r12, [r11] |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 215 | wait_sdrc_idle1: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 216 | ldr r11, omap3_cm_idlest1_core |
| 217 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 218 | and r12, r12, #ST_SDRC_MASK |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 219 | cmp r12, #0 |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 220 | bne wait_sdrc_idle1 |
Paul Walmsley | fa0406a | 2009-05-12 17:27:09 -0600 | [diff] [blame] | 221 | restore_sdrc_power_val: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 222 | ldr r11, omap3_sdrc_power |
| 223 | str r9, [r11] @ restore SDRC_POWER, no barrier needed |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 224 | bx lr |
| 225 | wait_dll_lock: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 226 | ldr r11, omap3_sdrc_dlla_status |
| 227 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 228 | and r12, r12, #LOCKSTATUS_MASK |
| 229 | cmp r12, #LOCKSTATUS_MASK |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 230 | bne wait_dll_lock |
| 231 | bx lr |
| 232 | wait_dll_unlock: |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 233 | ldr r11, omap3_sdrc_dlla_status |
| 234 | ldr r12, [r11] |
Paul Walmsley | df14e47 | 2009-06-19 19:08:28 -0600 | [diff] [blame] | 235 | and r12, r12, #LOCKSTATUS_MASK |
Paul Walmsley | b2abb27 | 2009-05-12 17:27:10 -0600 | [diff] [blame] | 236 | cmp r12, #0x0 |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 237 | bne wait_dll_unlock |
| 238 | bx lr |
| 239 | configure_sdrc: |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 240 | ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM |
| 241 | ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM |
| 242 | str r12, [r11] @ store |
Paul Walmsley | 18862cb | 2009-12-08 16:33:14 -0700 | [diff] [blame] | 243 | #ifdef CONFIG_OMAP3_SDRC_AC_TIMING |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 244 | ldr r12, omap_sdrc_actim_ctrl_a_0_val |
| 245 | ldr r11, omap3_sdrc_actim_ctrl_a_0 |
| 246 | str r12, [r11] |
| 247 | ldr r12, omap_sdrc_actim_ctrl_b_0_val |
| 248 | ldr r11, omap3_sdrc_actim_ctrl_b_0 |
| 249 | str r12, [r11] |
| 250 | ldr r12, omap_sdrc_mr_0_val |
Paul Walmsley | d0ba392 | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 251 | ldr r11, omap3_sdrc_mr_0 |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 252 | str r12, [r11] |
Paul Walmsley | 18862cb | 2009-12-08 16:33:14 -0700 | [diff] [blame] | 253 | #endif |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 254 | ldr r12, omap_sdrc_rfr_ctrl_1_val |
| 255 | cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0, |
| 256 | beq skip_cs1_prog @ do not program cs1 params |
| 257 | ldr r11, omap3_sdrc_rfr_ctrl_1 |
| 258 | str r12, [r11] |
Paul Walmsley | 18862cb | 2009-12-08 16:33:14 -0700 | [diff] [blame] | 259 | #ifdef CONFIG_OMAP3_SDRC_AC_TIMING |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 260 | ldr r12, omap_sdrc_actim_ctrl_a_1_val |
| 261 | ldr r11, omap3_sdrc_actim_ctrl_a_1 |
| 262 | str r12, [r11] |
| 263 | ldr r12, omap_sdrc_actim_ctrl_b_1_val |
| 264 | ldr r11, omap3_sdrc_actim_ctrl_b_1 |
| 265 | str r12, [r11] |
| 266 | ldr r12, omap_sdrc_mr_1_val |
| 267 | ldr r11, omap3_sdrc_mr_1 |
| 268 | str r12, [r11] |
Paul Walmsley | 18862cb | 2009-12-08 16:33:14 -0700 | [diff] [blame] | 269 | #endif |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 270 | skip_cs1_prog: |
| 271 | ldr r12, [r11] @ posted-write barrier for SDRC |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 272 | bx lr |
| 273 | |
| 274 | omap3_sdrc_power: |
| 275 | .word OMAP34XX_SDRC_REGADDR(SDRC_POWER) |
| 276 | omap3_cm_clksel1_pll: |
| 277 | .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1) |
| 278 | omap3_cm_idlest1_core: |
| 279 | .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST) |
| 280 | omap3_cm_iclken1_core: |
| 281 | .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1) |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 282 | |
| 283 | omap3_sdrc_rfr_ctrl_0: |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 284 | .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0) |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 285 | omap3_sdrc_rfr_ctrl_1: |
| 286 | .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1) |
| 287 | omap3_sdrc_actim_ctrl_a_0: |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 288 | .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0) |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 289 | omap3_sdrc_actim_ctrl_a_1: |
| 290 | .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1) |
| 291 | omap3_sdrc_actim_ctrl_b_0: |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 292 | .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0) |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 293 | omap3_sdrc_actim_ctrl_b_1: |
| 294 | .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1) |
Paul Walmsley | d0ba392 | 2009-06-19 19:08:27 -0600 | [diff] [blame] | 295 | omap3_sdrc_mr_0: |
| 296 | .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0) |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 297 | omap3_sdrc_mr_1: |
| 298 | .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1) |
| 299 | omap_sdrc_rfr_ctrl_0_val: |
| 300 | .word 0xDEADBEEF |
| 301 | omap_sdrc_rfr_ctrl_1_val: |
| 302 | .word 0xDEADBEEF |
| 303 | omap_sdrc_actim_ctrl_a_0_val: |
| 304 | .word 0xDEADBEEF |
| 305 | omap_sdrc_actim_ctrl_a_1_val: |
| 306 | .word 0xDEADBEEF |
| 307 | omap_sdrc_actim_ctrl_b_0_val: |
| 308 | .word 0xDEADBEEF |
| 309 | omap_sdrc_actim_ctrl_b_1_val: |
| 310 | .word 0xDEADBEEF |
| 311 | omap_sdrc_mr_0_val: |
| 312 | .word 0xDEADBEEF |
| 313 | omap_sdrc_mr_1_val: |
| 314 | .word 0xDEADBEEF |
| 315 | |
Syed Mohammed, Khasim | cc26b3b | 2008-10-09 17:51:41 +0300 | [diff] [blame] | 316 | omap3_sdrc_dlla_status: |
| 317 | .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) |
| 318 | omap3_sdrc_dlla_ctrl: |
| 319 | .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) |
| 320 | core_m2_mask_val: |
| 321 | .word 0x07FFFFFF |
| 322 | |
| 323 | ENTRY(omap3_sram_configure_core_dpll_sz) |
| 324 | .word . - omap3_sram_configure_core_dpll |
Jean Pihet | 58cda88 | 2009-07-24 19:43:25 -0600 | [diff] [blame] | 325 | |