blob: 07aea8d0beeb11e7a9b376bf07fdff38db8a9be9 [file] [log] [blame]
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -07001/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#ifndef _MLX4_EN_H_
35#define _MLX4_EN_H_
36
37#include <linux/compiler.h>
38#include <linux/list.h>
39#include <linux/mutex.h>
40#include <linux/netdevice.h>
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -070041
42#include <linux/mlx4/device.h>
43#include <linux/mlx4/qp.h>
44#include <linux/mlx4/cq.h>
45#include <linux/mlx4/srq.h>
46#include <linux/mlx4/doorbell.h>
Yevgeny Petriline7c1c2c42010-08-24 03:46:18 +000047#include <linux/mlx4/cmd.h>
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -070048
49#include "en_port.h"
50
51#define DRV_NAME "mlx4_en"
Yevgeny Petrilin04714a12010-08-24 03:46:49 +000052#define DRV_VERSION "1.5.1.6"
53#define DRV_RELDATE "August 2010"
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -070054
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -070055#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
56
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -070057/*
58 * Device constants
59 */
60
61
62#define MLX4_EN_PAGE_SHIFT 12
63#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -070064#define MAX_RX_RINGS 16
Yevgeny Petrilin1fb98762011-03-22 22:37:52 +000065#define MIN_RX_RINGS 4
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -070066#define TXBB_SIZE 64
67#define HEADROOM (2048 / TXBB_SIZE + 1)
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -070068#define STAMP_STRIDE 64
69#define STAMP_DWORDS (STAMP_STRIDE / 4)
70#define STAMP_SHIFT 31
71#define STAMP_VAL 0x7fffffff
72#define STATS_DELAY (HZ / 4)
73
74/* Typical TSO descriptor with 16 gather entries is 352 bytes... */
75#define MAX_DESC_SIZE 512
76#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
77
78/*
79 * OS related constants and tunables
80 */
81
82#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
83
84#define MLX4_EN_ALLOC_ORDER 2
85#define MLX4_EN_ALLOC_SIZE (PAGE_SIZE << MLX4_EN_ALLOC_ORDER)
86
87#define MLX4_EN_MAX_LRO_DESCRIPTORS 32
88
89/* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
90 * and 4K allocations) */
91enum {
92 FRAG_SZ0 = 512 - NET_IP_ALIGN,
93 FRAG_SZ1 = 1024,
94 FRAG_SZ2 = 4096,
95 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
96};
97#define MLX4_EN_MAX_RX_FRAGS 4
98
Yevgeny Petrilinbd531e32009-01-08 10:57:37 -080099/* Maximum ring sizes */
100#define MLX4_EN_MAX_TX_SIZE 8192
101#define MLX4_EN_MAX_RX_SIZE 8192
102
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700103/* Minimum ring size for our page-allocation sceme to work */
104#define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
105#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
106
Yevgeny Petrilinf813cad2009-06-01 23:24:07 +0000107#define MLX4_EN_SMALL_PKT_SIZE 64
108#define MLX4_EN_NUM_TX_RINGS 8
109#define MLX4_EN_NUM_PPP_RINGS 8
Yevgeny Petrilina0b4e6e2010-08-24 03:45:54 +0000110#define MAX_TX_RINGS (MLX4_EN_NUM_TX_RINGS + MLX4_EN_NUM_PPP_RINGS)
Yevgeny Petrilinf813cad2009-06-01 23:24:07 +0000111#define MLX4_EN_DEF_TX_RING_SIZE 512
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700112#define MLX4_EN_DEF_RX_RING_SIZE 1024
113
Yevgeny Petrilin3db36fb2009-06-01 23:23:13 +0000114/* Target number of packets to coalesce with interrupt moderation */
115#define MLX4_EN_RX_COAL_TARGET 44
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700116#define MLX4_EN_RX_COAL_TIME 0x10
117
118#define MLX4_EN_TX_COAL_PKTS 5
119#define MLX4_EN_TX_COAL_TIME 0x80
120
121#define MLX4_EN_RX_RATE_LOW 400000
122#define MLX4_EN_RX_COAL_TIME_LOW 0
123#define MLX4_EN_RX_RATE_HIGH 450000
124#define MLX4_EN_RX_COAL_TIME_HIGH 128
125#define MLX4_EN_RX_SIZE_THRESH 1024
126#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
127#define MLX4_EN_SAMPLE_INTERVAL 0
Yevgeny Petrilin46afd0f2011-03-22 22:37:36 +0000128#define MLX4_EN_AVG_PKT_SMALL 256
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700129
130#define MLX4_EN_AUTO_CONF 0xffff
131
132#define MLX4_EN_DEF_RX_PAUSE 1
133#define MLX4_EN_DEF_TX_PAUSE 1
134
André Goddard Rosaaf901ca2009-11-14 13:09:05 -0200135/* Interval between successive polls in the Tx routine when polling is used
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700136 instead of interrupts (in per-core Tx rings) - should be power of 2 */
137#define MLX4_EN_TX_POLL_MODER 16
138#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
139
140#define ETH_LLC_SNAP_SIZE 8
141
142#define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
143#define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
Yevgeny Petriline7c1c2c42010-08-24 03:46:18 +0000144#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700145
146#define MLX4_EN_MIN_MTU 46
147#define ETH_BCAST 0xffffffffffffULL
148
Yevgeny Petriline7c1c2c42010-08-24 03:46:18 +0000149#define MLX4_EN_LOOPBACK_RETRIES 5
150#define MLX4_EN_LOOPBACK_TIMEOUT 100
151
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700152#ifdef MLX4_EN_PERF_STAT
153/* Number of samples to 'average' */
154#define AVG_SIZE 128
155#define AVG_FACTOR 1024
156#define NUM_PERF_STATS NUM_PERF_COUNTERS
157
158#define INC_PERF_COUNTER(cnt) (++(cnt))
159#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
160#define AVG_PERF_COUNTER(cnt, sample) \
161 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
162#define GET_PERF_COUNTER(cnt) (cnt)
163#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
164
165#else
166
167#define NUM_PERF_STATS 0
168#define INC_PERF_COUNTER(cnt) do {} while (0)
169#define ADD_PERF_COUNTER(cnt, add) do {} while (0)
170#define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
171#define GET_PERF_COUNTER(cnt) (0)
172#define GET_AVG_PERF_COUNTER(cnt) (0)
173#endif /* MLX4_EN_PERF_STAT */
174
175/*
176 * Configurables
177 */
178
179enum cq_type {
180 RX = 0,
181 TX = 1,
182};
183
184
185/*
186 * Useful macros
187 */
188#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
189#define XNOR(x, y) (!(x) == !(y))
190#define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0)
191
192
193struct mlx4_en_tx_info {
194 struct sk_buff *skb;
195 u32 nr_txbb;
196 u8 linear;
197 u8 data_offset;
Yevgeny Petrilin41efea52009-01-08 10:57:15 -0800198 u8 inl;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700199};
200
201
202#define MLX4_EN_BIT_DESC_OWN 0x80000000
203#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
204#define MLX4_EN_MEMTYPE_PAD 0x100
205#define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
206
207
208struct mlx4_en_tx_desc {
209 struct mlx4_wqe_ctrl_seg ctrl;
210 union {
211 struct mlx4_wqe_data_seg data; /* at least one data segment */
212 struct mlx4_wqe_lso_seg lso;
213 struct mlx4_wqe_inline_seg inl;
214 };
215};
216
217#define MLX4_EN_USE_SRQ 0x01000000
218
219struct mlx4_en_rx_alloc {
220 struct page *page;
221 u16 offset;
222};
223
224struct mlx4_en_tx_ring {
225 struct mlx4_hwq_resources wqres;
226 u32 size ; /* number of TXBBs */
227 u32 size_mask;
228 u16 stride;
229 u16 cqn; /* index of port CQ associated with this ring */
230 u32 prod;
231 u32 cons;
232 u32 buf_size;
233 u32 doorbell_qpn;
234 void *buf;
235 u16 poll_cnt;
236 int blocked;
237 struct mlx4_en_tx_info *tx_info;
238 u8 *bounce_buf;
239 u32 last_nr_txbb;
240 struct mlx4_qp qp;
241 struct mlx4_qp_context context;
242 int qpn;
243 enum mlx4_qp_state qp_state;
244 struct mlx4_srq dummy;
245 unsigned long bytes;
246 unsigned long packets;
247 spinlock_t comp_lock;
248};
249
250struct mlx4_en_rx_desc {
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700251 /* actual number of entries depends on rx ring stride */
252 struct mlx4_wqe_data_seg data[0];
253};
254
255struct mlx4_en_rx_ring {
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700256 struct mlx4_hwq_resources wqres;
257 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700258 u32 size ; /* number of Rx descs*/
259 u32 actual_size;
260 u32 size_mask;
261 u16 stride;
262 u16 log_stride;
263 u16 cqn; /* index of port CQ associated with this ring */
264 u32 prod;
265 u32 cons;
266 u32 buf_size;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700267 void *buf;
268 void *rx_info;
269 unsigned long bytes;
270 unsigned long packets;
271};
272
273
274static inline int mlx4_en_can_lro(__be16 status)
275{
276 return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
277 MLX4_CQE_STATUS_IPV4F |
278 MLX4_CQE_STATUS_IPV6 |
279 MLX4_CQE_STATUS_IPV4OPT |
280 MLX4_CQE_STATUS_TCP |
281 MLX4_CQE_STATUS_UDP |
282 MLX4_CQE_STATUS_IPOK)) ==
283 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
284 MLX4_CQE_STATUS_IPOK |
285 MLX4_CQE_STATUS_TCP);
286}
287
288struct mlx4_en_cq {
289 struct mlx4_cq mcq;
290 struct mlx4_hwq_resources wqres;
291 int ring;
292 spinlock_t lock;
293 struct net_device *dev;
294 struct napi_struct napi;
295 /* Per-core Tx cq processing support */
296 struct timer_list timer;
297 int size;
298 int buf_size;
299 unsigned vector;
300 enum cq_type is_tx;
301 u16 moder_time;
302 u16 moder_cnt;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700303 struct mlx4_cqe *buf;
304#define MLX4_EN_OPCODE_ERROR 0x1e
305};
306
307struct mlx4_en_port_profile {
308 u32 flags;
309 u32 tx_ring_num;
310 u32 rx_ring_num;
311 u32 tx_ring_size;
312 u32 rx_ring_size;
Yevgeny Petrilind53b93f2008-11-05 04:48:36 +0000313 u8 rx_pause;
314 u8 rx_ppp;
315 u8 tx_pause;
316 u8 tx_ppp;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700317};
318
319struct mlx4_en_profile {
320 int rss_xor;
Yevgeny Petrilin05339432010-08-24 03:46:42 +0000321 int tcp_rss;
322 int udp_rss;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700323 u8 rss_mask;
324 u32 active_ports;
325 u32 small_pkt_int;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700326 u8 no_reset;
327 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
328};
329
330struct mlx4_en_dev {
331 struct mlx4_dev *dev;
332 struct pci_dev *pdev;
333 struct mutex state_lock;
334 struct net_device *pndev[MLX4_MAX_PORTS + 1];
335 u32 port_cnt;
336 bool device_up;
337 struct mlx4_en_profile profile;
338 u32 LSO_support;
339 struct workqueue_struct *workqueue;
340 struct device *dma_device;
341 void __iomem *uar_map;
342 struct mlx4_uar priv_uar;
343 struct mlx4_mr mr;
344 u32 priv_pdn;
345 spinlock_t uar_lock;
Yevgeny Petrilind7e1a482010-08-24 03:46:38 +0000346 u8 mac_removed[MLX4_MAX_PORTS + 1];
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700347};
348
349
350struct mlx4_en_rss_map {
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700351 int base_qpn;
Yevgeny Petrilinb6b912e2009-08-06 19:27:51 -0700352 struct mlx4_qp qps[MAX_RX_RINGS];
353 enum mlx4_qp_state state[MAX_RX_RINGS];
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700354 struct mlx4_qp indir_qp;
355 enum mlx4_qp_state indir_state;
356};
357
358struct mlx4_en_rss_context {
359 __be32 base_qpn;
360 __be32 default_qpn;
361 u16 reserved;
362 u8 hash_fn;
363 u8 flags;
364 __be32 rss_key[10];
Yevgeny Petrilin05339432010-08-24 03:46:42 +0000365 __be32 base_qpn_udp;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700366};
367
Yevgeny Petriline7c1c2c42010-08-24 03:46:18 +0000368struct mlx4_en_port_state {
369 int link_state;
370 int link_speed;
371 int transciver;
372};
373
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700374struct mlx4_en_pkt_stats {
375 unsigned long broadcast;
376 unsigned long rx_prio[8];
377 unsigned long tx_prio[8];
378#define NUM_PKT_STATS 17
379};
380
381struct mlx4_en_port_stats {
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700382 unsigned long tso_packets;
383 unsigned long queue_stopped;
384 unsigned long wake_queue;
385 unsigned long tx_timeout;
386 unsigned long rx_alloc_failed;
387 unsigned long rx_chksum_good;
388 unsigned long rx_chksum_none;
389 unsigned long tx_chksum_offload;
Yevgeny Petrilind61702f2010-09-05 22:20:24 +0000390#define NUM_PORT_STATS 8
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700391};
392
393struct mlx4_en_perf_stats {
394 u32 tx_poll;
395 u64 tx_pktsz_avg;
396 u32 inflight_avg;
397 u16 tx_coal_avg;
398 u16 rx_coal_avg;
399 u32 napi_quota;
400#define NUM_PERF_COUNTERS 6
401};
402
403struct mlx4_en_frag_info {
404 u16 frag_size;
405 u16 frag_prefix_size;
406 u16 frag_stride;
407 u16 frag_align;
408 u16 last_offset;
409
410};
411
412struct mlx4_en_priv {
413 struct mlx4_en_dev *mdev;
414 struct mlx4_en_port_profile *prof;
415 struct net_device *dev;
416 struct vlan_group *vlgrp;
417 struct net_device_stats stats;
418 struct net_device_stats ret_stats;
Yevgeny Petriline7c1c2c42010-08-24 03:46:18 +0000419 struct mlx4_en_port_state port_state;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700420 spinlock_t stats_lock;
421
422 unsigned long last_moder_packets;
423 unsigned long last_moder_tx_packets;
424 unsigned long last_moder_bytes;
425 unsigned long last_moder_jiffies;
426 int last_moder_time;
427 u16 rx_usecs;
428 u16 rx_frames;
429 u16 tx_usecs;
430 u16 tx_frames;
431 u32 pkt_rate_low;
432 u16 rx_usecs_low;
433 u32 pkt_rate_high;
434 u16 rx_usecs_high;
435 u16 sample_interval;
436 u16 adaptive_rx_coal;
437 u32 msg_enable;
Yevgeny Petriline7c1c2c42010-08-24 03:46:18 +0000438 u32 loopback_ok;
439 u32 validate_loopback;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700440
441 struct mlx4_hwq_resources res;
442 int link_state;
443 int last_link_state;
444 bool port_up;
445 int port;
446 int registered;
447 int allocated;
448 int stride;
449 int rx_csum;
450 u64 mac;
451 int mac_index;
452 unsigned max_mtu;
453 int base_qpn;
454
455 struct mlx4_en_rss_map rss_map;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700456 u32 flags;
457#define MLX4_EN_FLAG_PROMISC 0x1
458 u32 tx_ring_num;
459 u32 rx_ring_num;
460 u32 rx_skb_size;
461 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
462 u16 num_frags;
463 u16 log_rx_info;
464
465 struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
Yevgeny Petrilin1fb98762011-03-22 22:37:52 +0000466 int tx_vector;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700467 struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
468 struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
469 struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
470 struct work_struct mcast_task;
471 struct work_struct mac_task;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700472 struct work_struct watchdog_task;
473 struct work_struct linkstate_task;
474 struct delayed_work stats_task;
475 struct mlx4_en_perf_stats pstats;
476 struct mlx4_en_pkt_stats pkstats;
477 struct mlx4_en_port_stats port_stats;
Jiri Pirkoff6e2162010-03-01 05:09:14 +0000478 char *mc_addrs;
479 int mc_addrs_cnt;
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700480 struct mlx4_en_stat_out_mbox hw_stats;
Eli Cohen4c3eb3c2010-08-26 17:19:22 +0300481 int vids[128];
Yevgeny Petrilin14c07b12011-03-22 22:37:59 +0000482 bool wol;
483};
484
485enum mlx4_en_wol {
486 MLX4_EN_WOL_MAGIC = (1ULL << 61),
487 MLX4_EN_WOL_ENABLED = (1ULL << 62),
488 MLX4_EN_WOL_DO_MODIFY = (1ULL << 63),
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700489};
490
491
492void mlx4_en_destroy_netdev(struct net_device *dev);
493int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
494 struct mlx4_en_port_profile *prof);
495
Yevgeny Petrilin18cc42a2008-12-29 18:39:20 -0800496int mlx4_en_start_port(struct net_device *dev);
497void mlx4_en_stop_port(struct net_device *dev);
498
Yevgeny Petrilin1fb98762011-03-22 22:37:52 +0000499void mlx4_en_free_resources(struct mlx4_en_priv *priv, bool reserve_vectors);
Yevgeny Petrilin18cc42a2008-12-29 18:39:20 -0800500int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
501
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700502int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
503 int entries, int ring, enum cq_type mode);
Yevgeny Petrilin1fb98762011-03-22 22:37:52 +0000504void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
505 bool reserve_vectors);
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700506int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
507void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
508int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
509int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
510
511void mlx4_en_poll_tx_cq(unsigned long data);
512void mlx4_en_tx_irq(struct mlx4_cq *mcq);
Yevgeny Petrilinf813cad2009-06-01 23:24:07 +0000513u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
Stephen Hemminger613573252009-08-31 19:50:58 +0000514netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700515
516int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
517 u32 size, u16 stride);
518void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
519int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
520 struct mlx4_en_tx_ring *ring,
Yevgeny Petrilin9f519f62009-08-06 19:28:18 -0700521 int cq);
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700522void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
523 struct mlx4_en_tx_ring *ring);
524
525int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
526 struct mlx4_en_rx_ring *ring,
527 u32 size, u16 stride);
528void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
529 struct mlx4_en_rx_ring *ring);
530int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
531void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
532 struct mlx4_en_rx_ring *ring);
533int mlx4_en_process_rx_cq(struct net_device *dev,
534 struct mlx4_en_cq *cq,
535 int budget);
536int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
537void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
Yevgeny Petrilin9f519f62009-08-06 19:28:18 -0700538 int is_tx, int rss, int qpn, int cqn,
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700539 struct mlx4_qp_context *context);
Yevgeny Petrilin966508f2009-04-20 04:30:03 +0000540void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700541int mlx4_en_map_buffer(struct mlx4_buf *buf);
542void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
543
544void mlx4_en_calc_rx_buf(struct net_device *dev);
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700545int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
546void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
547int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700548void mlx4_en_rx_irq(struct mlx4_cq *mcq);
549
550int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
551int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, struct vlan_group *grp);
552int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
553 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
554int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
555 u8 promisc);
556
557int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
Yevgeny Petriline7c1c2c42010-08-24 03:46:18 +0000558int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
559
560#define MLX4_EN_NUM_SELF_TEST 5
561void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
562u64 mlx4_en_mac_to_u64(u8 *addr);
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700563
564/*
565 * Globals
566 */
567extern const struct ethtool_ops mlx4_en_ethtool_ops;
Joe Perches0a645e82010-07-10 07:22:46 +0000568
569
570
571/*
572 * printk / logging functions
573 */
574
575int en_print(const char *level, const struct mlx4_en_priv *priv,
576 const char *format, ...) __attribute__ ((format (printf, 3, 4)));
577
578#define en_dbg(mlevel, priv, format, arg...) \
579do { \
580 if (NETIF_MSG_##mlevel & priv->msg_enable) \
581 en_print(KERN_DEBUG, priv, format, ##arg); \
582} while (0)
583#define en_warn(priv, format, arg...) \
584 en_print(KERN_WARNING, priv, format, ##arg)
585#define en_err(priv, format, arg...) \
586 en_print(KERN_ERR, priv, format, ##arg)
Yevgeny Petriline5cc44b2010-08-24 03:46:01 +0000587#define en_info(priv, format, arg...) \
588 en_print(KERN_INFO, priv, format, ## arg)
Joe Perches0a645e82010-07-10 07:22:46 +0000589
590#define mlx4_err(mdev, format, arg...) \
591 pr_err("%s %s: " format, DRV_NAME, \
592 dev_name(&mdev->pdev->dev), ##arg)
593#define mlx4_info(mdev, format, arg...) \
594 pr_info("%s %s: " format, DRV_NAME, \
595 dev_name(&mdev->pdev->dev), ##arg)
596#define mlx4_warn(mdev, format, arg...) \
597 pr_warning("%s %s: " format, DRV_NAME, \
598 dev_name(&mdev->pdev->dev), ##arg)
599
Yevgeny Petrilinc27a02c2008-10-22 15:47:49 -0700600#endif