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gerrit-public.fairphone.software / kernel / msm / 150e6c67f4bf6ab51e62defc41bd19a2eefe5709 / . / arch / blackfin / mach-bf527 / dma.c
blob: 231877578243484ce446bbe308086d4594f2fa71 [file] [log] [blame]
Michael Hennerich59003142007-10-21 16:54:27 +0800[diff] [blame]1/*
2 * File: arch/blackfin/mach-bf527/dma.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: This file contains the simple DMA Implementation for Blackfin
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
Bernd Schmidtac86a972008-04-24 05:23:31 +0800[diff] [blame]29#include <linux/module.h>
30
Michael Hennerich59003142007-10-21 16:54:27 +0800[diff] [blame]31#include <asm/blackfin.h>
32#include <asm/dma.h>
33
Mike Frysinger211daf92009-01-07 23:14:39 +0800[diff] [blame]34struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
Michael Hennerich59003142007-10-21 16:54:27 +0800[diff] [blame]35 (struct dma_register *) DMA0_NEXT_DESC_PTR,
36 (struct dma_register *) DMA1_NEXT_DESC_PTR,
37 (struct dma_register *) DMA2_NEXT_DESC_PTR,
38 (struct dma_register *) DMA3_NEXT_DESC_PTR,
39 (struct dma_register *) DMA4_NEXT_DESC_PTR,
40 (struct dma_register *) DMA5_NEXT_DESC_PTR,
41 (struct dma_register *) DMA6_NEXT_DESC_PTR,
42 (struct dma_register *) DMA7_NEXT_DESC_PTR,
43 (struct dma_register *) DMA8_NEXT_DESC_PTR,
44 (struct dma_register *) DMA9_NEXT_DESC_PTR,
45 (struct dma_register *) DMA10_NEXT_DESC_PTR,
46 (struct dma_register *) DMA11_NEXT_DESC_PTR,
47 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
48 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
49 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
50 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
51};
Bernd Schmidt77955662008-04-24 05:31:18 +0800[diff] [blame]52EXPORT_SYMBOL(dma_io_base_addr);
Michael Hennerich59003142007-10-21 16:54:27 +0800[diff] [blame]53
54int channel2irq(unsigned int channel)
55{
56 int ret_irq = -1;
57
58 switch (channel) {
59 case CH_PPI:
60 ret_irq = IRQ_PPI;
61 break;
62
63 case CH_EMAC_RX:
64 ret_irq = IRQ_MAC_RX;
65 break;
66
67 case CH_EMAC_TX:
68 ret_irq = IRQ_MAC_TX;
69 break;
70
71 case CH_UART1_RX:
72 ret_irq = IRQ_UART1_RX;
73 break;
74
75 case CH_UART1_TX:
76 ret_irq = IRQ_UART1_TX;
77 break;
78
79 case CH_SPORT0_RX:
80 ret_irq = IRQ_SPORT0_RX;
81 break;
82
83 case CH_SPORT0_TX:
84 ret_irq = IRQ_SPORT0_TX;
85 break;
86
87 case CH_SPORT1_RX:
88 ret_irq = IRQ_SPORT1_RX;
89 break;
90
91 case CH_SPORT1_TX:
92 ret_irq = IRQ_SPORT1_TX;
93 break;
94
95 case CH_SPI:
96 ret_irq = IRQ_SPI;
97 break;
98
99 case CH_UART0_RX:
100 ret_irq = IRQ_UART0_RX;
101 break;
102
103 case CH_UART0_TX:
104 ret_irq = IRQ_UART0_TX;
105 break;
106
107 case CH_MEM_STREAM0_SRC:
108 case CH_MEM_STREAM0_DEST:
109 ret_irq = IRQ_MEM_DMA0;
110 break;
111
112 case CH_MEM_STREAM1_SRC:
113 case CH_MEM_STREAM1_DEST:
114 ret_irq = IRQ_MEM_DMA1;
115 break;
116 }
117 return ret_irq;
118}