blob: 0770671fa8af32caa35fcf762f000698c5a28af0 [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Jesse Barnes23b2f8b2011-06-28 13:04:16 -070027#include <linux/cpufreq.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080035#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
Dave Airlieab2c0672009-12-04 10:55:24 +100040#include "drm_dp_helper.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080041#include "drm_crtc_helper.h"
Keith Packardc0f372b32011-11-16 22:24:52 -080042#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080043
Zhenyu Wang32f9d652009-07-24 01:00:32 +080044#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
Akshay Joshi0206e352011-08-16 15:34:10 -040046bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
Shaohua Li7662c8b2009-06-26 11:23:55 +080047static void intel_update_watermarks(struct drm_device *dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +020048static void intel_increase_pllclock(struct drm_crtc *crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +010049static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080050
51typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040052 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
Jesse Barnes79e53942008-11-07 14:24:08 -080061} intel_clock_t;
62
63typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040064 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -080065} intel_range_t;
66
67typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040068 int dot_limit;
69 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -080070} intel_p2_t;
71
72#define INTEL_P2_NUM 2
Ma Lingd4906092009-03-18 20:13:27 +080073typedef struct intel_limit intel_limit_t;
74struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -040075 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
Sean Paulcec2f352012-01-10 15:09:36 -080078 int, int, intel_clock_t *, intel_clock_t *);
Ma Lingd4906092009-03-18 20:13:27 +080079};
Jesse Barnes79e53942008-11-07 14:24:08 -080080
Jesse Barnes2377b742010-07-07 14:06:43 -070081/* FDI */
82#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
Ma Lingd4906092009-03-18 20:13:27 +080084static bool
85intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -080086 int target, int refclk, intel_clock_t *match_clock,
87 intel_clock_t *best_clock);
Ma Lingd4906092009-03-18 20:13:27 +080088static bool
89intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -080090 int target, int refclk, intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
Jesse Barnes79e53942008-11-07 14:24:08 -080092
Keith Packarda4fc5ed2009-04-07 16:16:42 -070093static bool
94intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -080095 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080097static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -050098intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -080099 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700101
Chris Wilson021357a2010-09-07 20:54:59 +0100102static inline u32 /* units of 100MHz */
103intel_fdi_link_freq(struct drm_device *dev)
104{
Chris Wilson8b99e682010-10-13 09:59:17 +0100105 if (IS_GEN5(dev)) {
106 struct drm_i915_private *dev_priv = dev->dev_private;
107 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
108 } else
109 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100110}
111
Keith Packarde4b36692009-06-05 19:22:17 -0700112static const intel_limit_t intel_limits_i8xx_dvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400113 .dot = { .min = 25000, .max = 350000 },
114 .vco = { .min = 930000, .max = 1400000 },
115 .n = { .min = 3, .max = 16 },
116 .m = { .min = 96, .max = 140 },
117 .m1 = { .min = 18, .max = 26 },
118 .m2 = { .min = 6, .max = 16 },
119 .p = { .min = 4, .max = 128 },
120 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700121 .p2 = { .dot_limit = 165000,
122 .p2_slow = 4, .p2_fast = 2 },
Ma Lingd4906092009-03-18 20:13:27 +0800123 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700124};
125
126static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 14, .p2_fast = 7 },
Ma Lingd4906092009-03-18 20:13:27 +0800137 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700138};
Eric Anholt273e27c2011-03-30 13:01:10 -0700139
Keith Packarde4b36692009-06-05 19:22:17 -0700140static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400141 .dot = { .min = 20000, .max = 400000 },
142 .vco = { .min = 1400000, .max = 2800000 },
143 .n = { .min = 1, .max = 6 },
144 .m = { .min = 70, .max = 120 },
145 .m1 = { .min = 10, .max = 22 },
146 .m2 = { .min = 5, .max = 9 },
147 .p = { .min = 5, .max = 80 },
148 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700149 .p2 = { .dot_limit = 200000,
150 .p2_slow = 10, .p2_fast = 5 },
Ma Lingd4906092009-03-18 20:13:27 +0800151 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700152};
153
154static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 7, .max = 98 },
162 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700163 .p2 = { .dot_limit = 112000,
164 .p2_slow = 14, .p2_fast = 7 },
Ma Lingd4906092009-03-18 20:13:27 +0800165 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700166};
167
Eric Anholt273e27c2011-03-30 13:01:10 -0700168
Keith Packarde4b36692009-06-05 19:22:17 -0700169static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700170 .dot = { .min = 25000, .max = 270000 },
171 .vco = { .min = 1750000, .max = 3500000},
172 .n = { .min = 1, .max = 4 },
173 .m = { .min = 104, .max = 138 },
174 .m1 = { .min = 17, .max = 23 },
175 .m2 = { .min = 5, .max = 11 },
176 .p = { .min = 10, .max = 30 },
177 .p1 = { .min = 1, .max = 3},
178 .p2 = { .dot_limit = 270000,
179 .p2_slow = 10,
180 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800181 },
Ma Lingd4906092009-03-18 20:13:27 +0800182 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700183};
184
185static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700186 .dot = { .min = 22000, .max = 400000 },
187 .vco = { .min = 1750000, .max = 3500000},
188 .n = { .min = 1, .max = 4 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 16, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 5, .max = 80 },
193 .p1 = { .min = 1, .max = 8},
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 10, .p2_fast = 5 },
Ma Lingd4906092009-03-18 20:13:27 +0800196 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700197};
198
199static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700200 .dot = { .min = 20000, .max = 115000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 28, .max = 112 },
207 .p1 = { .min = 2, .max = 8 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800210 },
Ma Lingd4906092009-03-18 20:13:27 +0800211 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700212};
213
214static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800225 },
Ma Lingd4906092009-03-18 20:13:27 +0800226 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700227};
228
229static const intel_limit_t intel_limits_g4x_display_port = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400230 .dot = { .min = 161670, .max = 227000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 2 },
233 .m = { .min = 97, .max = 108 },
234 .m1 = { .min = 0x10, .max = 0x12 },
235 .m2 = { .min = 0x05, .max = 0x06 },
236 .p = { .min = 10, .max = 20 },
237 .p1 = { .min = 1, .max = 2},
238 .p2 = { .dot_limit = 0,
Eric Anholt273e27c2011-03-30 13:01:10 -0700239 .p2_slow = 10, .p2_fast = 10 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400240 .find_pll = intel_find_pll_g4x_dp,
Keith Packarde4b36692009-06-05 19:22:17 -0700241};
242
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500243static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400244 .dot = { .min = 20000, .max = 400000},
245 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700246 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400247 .n = { .min = 3, .max = 6 },
248 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700249 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400250 .m1 = { .min = 0, .max = 0 },
251 .m2 = { .min = 0, .max = 254 },
252 .p = { .min = 5, .max = 80 },
253 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700254 .p2 = { .dot_limit = 200000,
255 .p2_slow = 10, .p2_fast = 5 },
Shaohua Li61157072009-04-03 15:24:43 +0800256 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700257};
258
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500259static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400260 .dot = { .min = 20000, .max = 400000 },
261 .vco = { .min = 1700000, .max = 3500000 },
262 .n = { .min = 3, .max = 6 },
263 .m = { .min = 2, .max = 256 },
264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 7, .max = 112 },
267 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700268 .p2 = { .dot_limit = 112000,
269 .p2_slow = 14, .p2_fast = 14 },
Shaohua Li61157072009-04-03 15:24:43 +0800270 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700271};
272
Eric Anholt273e27c2011-03-30 13:01:10 -0700273/* Ironlake / Sandybridge
274 *
275 * We calculate clock using (register_value + 2) for N/M1/M2, so here
276 * the range value for them is (actual_value - 2).
277 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800278static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700279 .dot = { .min = 25000, .max = 350000 },
280 .vco = { .min = 1760000, .max = 3510000 },
281 .n = { .min = 1, .max = 5 },
282 .m = { .min = 79, .max = 127 },
283 .m1 = { .min = 12, .max = 22 },
284 .m2 = { .min = 5, .max = 9 },
285 .p = { .min = 5, .max = 80 },
286 .p1 = { .min = 1, .max = 8 },
287 .p2 = { .dot_limit = 225000,
288 .p2_slow = 10, .p2_fast = 5 },
Zhao Yakui45476682009-12-31 16:06:04 +0800289 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700290};
291
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800292static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 3 },
296 .m = { .min = 79, .max = 118 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 28, .max = 112 },
300 .p1 = { .min = 2, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800303 .find_pll = intel_g4x_find_best_PLL,
304};
305
306static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 14, .max = 56 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800317 .find_pll = intel_g4x_find_best_PLL,
318};
319
Eric Anholt273e27c2011-03-30 13:01:10 -0700320/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800321static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700322 .dot = { .min = 25000, .max = 350000 },
323 .vco = { .min = 1760000, .max = 3510000 },
324 .n = { .min = 1, .max = 2 },
325 .m = { .min = 79, .max = 126 },
326 .m1 = { .min = 12, .max = 22 },
327 .m2 = { .min = 5, .max = 9 },
328 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400329 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700330 .p2 = { .dot_limit = 225000,
331 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800332 .find_pll = intel_g4x_find_best_PLL,
333};
334
335static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 3 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400343 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_display_port = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000},
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 81, .max = 90 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 10, .max = 20 },
357 .p1 = { .min = 1, .max = 2},
358 .p2 = { .dot_limit = 0,
Eric Anholt273e27c2011-03-30 13:01:10 -0700359 .p2_slow = 10, .p2_fast = 10 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400360 .find_pll = intel_find_pll_ironlake_dp,
Jesse Barnes79e53942008-11-07 14:24:08 -0800361};
362
Chris Wilson1b894b52010-12-14 20:04:54 +0000363static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
364 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800365{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800366 struct drm_device *dev = crtc->dev;
367 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800368 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800369
370 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800371 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
372 LVDS_CLKB_POWER_UP) {
373 /* LVDS dual channel */
Chris Wilson1b894b52010-12-14 20:04:54 +0000374 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800375 limit = &intel_limits_ironlake_dual_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_dual_lvds;
378 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000379 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800380 limit = &intel_limits_ironlake_single_lvds_100m;
381 else
382 limit = &intel_limits_ironlake_single_lvds;
383 }
384 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
Zhao Yakui45476682009-12-31 16:06:04 +0800385 HAS_eDP)
386 limit = &intel_limits_ironlake_display_port;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800387 else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800388 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800389
390 return limit;
391}
392
Ma Ling044c7c42009-03-18 20:13:23 +0800393static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
394{
395 struct drm_device *dev = crtc->dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 const intel_limit_t *limit;
398
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
400 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
401 LVDS_CLKB_POWER_UP)
402 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700403 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800404 else
405 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700406 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800407 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
408 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700409 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800410 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700411 limit = &intel_limits_g4x_sdvo;
Akshay Joshi0206e352011-08-16 15:34:10 -0400412 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700413 limit = &intel_limits_g4x_display_port;
Ma Ling044c7c42009-03-18 20:13:23 +0800414 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700415 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800416
417 return limit;
418}
419
Chris Wilson1b894b52010-12-14 20:04:54 +0000420static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800421{
422 struct drm_device *dev = crtc->dev;
423 const intel_limit_t *limit;
424
Eric Anholtbad720f2009-10-22 16:11:14 -0700425 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000426 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800427 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800428 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500429 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500431 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800432 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500433 limit = &intel_limits_pineview_sdvo;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100434 } else if (!IS_GEN2(dev)) {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436 limit = &intel_limits_i9xx_lvds;
437 else
438 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800439 } else {
440 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700441 limit = &intel_limits_i8xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800442 else
Keith Packarde4b36692009-06-05 19:22:17 -0700443 limit = &intel_limits_i8xx_dvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800444 }
445 return limit;
446}
447
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500448/* m1 is reserved as 0 in Pineview, n is a ring counter */
449static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800450{
Shaohua Li21778322009-02-23 15:19:16 +0800451 clock->m = clock->m2 + 2;
452 clock->p = clock->p1 * clock->p2;
453 clock->vco = refclk * clock->m / clock->n;
454 clock->dot = clock->vco / clock->p;
455}
456
457static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
458{
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500459 if (IS_PINEVIEW(dev)) {
460 pineview_clock(refclk, clock);
Shaohua Li21778322009-02-23 15:19:16 +0800461 return;
462 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800463 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
464 clock->p = clock->p1 * clock->p2;
465 clock->vco = refclk * clock->m / (clock->n + 2);
466 clock->dot = clock->vco / clock->p;
467}
468
Jesse Barnes79e53942008-11-07 14:24:08 -0800469/**
470 * Returns whether any output on the specified pipe is of the specified type
471 */
Chris Wilson4ef69c72010-09-09 15:14:28 +0100472bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
Jesse Barnes79e53942008-11-07 14:24:08 -0800473{
Chris Wilson4ef69c72010-09-09 15:14:28 +0100474 struct drm_device *dev = crtc->dev;
475 struct drm_mode_config *mode_config = &dev->mode_config;
476 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -0800477
Chris Wilson4ef69c72010-09-09 15:14:28 +0100478 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
479 if (encoder->base.crtc == crtc && encoder->type == type)
480 return true;
481
482 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -0800483}
484
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800485#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800486/**
487 * Returns whether the given set of divisors are valid for a given refclk with
488 * the given connectors.
489 */
490
Chris Wilson1b894b52010-12-14 20:04:54 +0000491static bool intel_PLL_is_valid(struct drm_device *dev,
492 const intel_limit_t *limit,
493 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800494{
Jesse Barnes79e53942008-11-07 14:24:08 -0800495 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400496 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800497 if (clock->p < limit->p.min || limit->p.max < clock->p)
Akshay Joshi0206e352011-08-16 15:34:10 -0400498 INTELPllInvalid("p out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800499 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400500 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800501 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400502 INTELPllInvalid("m1 out of range\n");
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500503 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
Akshay Joshi0206e352011-08-16 15:34:10 -0400504 INTELPllInvalid("m1 <= m2\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800505 if (clock->m < limit->m.min || limit->m.max < clock->m)
Akshay Joshi0206e352011-08-16 15:34:10 -0400506 INTELPllInvalid("m out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800507 if (clock->n < limit->n.min || limit->n.max < clock->n)
Akshay Joshi0206e352011-08-16 15:34:10 -0400508 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800509 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400510 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800511 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
512 * connector, etc., rather than just a single range.
513 */
514 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400515 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800516
517 return true;
518}
519
Ma Lingd4906092009-03-18 20:13:27 +0800520static bool
521intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800522 int target, int refclk, intel_clock_t *match_clock,
523 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800524
Jesse Barnes79e53942008-11-07 14:24:08 -0800525{
526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800529 int err = target;
530
Bruno Prémontbc5e5712009-08-08 13:01:17 +0200531 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Florian Mickler832cc282009-07-13 18:40:32 +0800532 (I915_READ(LVDS)) != 0) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800533 /*
534 * For LVDS, if the panel is on, just rely on its current
535 * settings for dual-channel. We haven't figured out how to
536 * reliably set up different single/dual channel state, if we
537 * even can.
538 */
539 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
540 LVDS_CLKB_POWER_UP)
541 clock.p2 = limit->p2.p2_fast;
542 else
543 clock.p2 = limit->p2.p2_slow;
544 } else {
545 if (target < limit->p2.dot_limit)
546 clock.p2 = limit->p2.p2_slow;
547 else
548 clock.p2 = limit->p2.p2_fast;
549 }
550
Akshay Joshi0206e352011-08-16 15:34:10 -0400551 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800552
Zhao Yakui42158662009-11-20 11:24:18 +0800553 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
554 clock.m1++) {
555 for (clock.m2 = limit->m2.min;
556 clock.m2 <= limit->m2.max; clock.m2++) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500557 /* m1 is always 0 in Pineview */
558 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
Zhao Yakui42158662009-11-20 11:24:18 +0800559 break;
560 for (clock.n = limit->n.min;
561 clock.n <= limit->n.max; clock.n++) {
562 for (clock.p1 = limit->p1.min;
563 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800564 int this_err;
565
Shaohua Li21778322009-02-23 15:19:16 +0800566 intel_clock(dev, refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000567 if (!intel_PLL_is_valid(dev, limit,
568 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800569 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800570 if (match_clock &&
571 clock.p != match_clock->p)
572 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800573
574 this_err = abs(clock.dot - target);
575 if (this_err < err) {
576 *best_clock = clock;
577 err = this_err;
578 }
579 }
580 }
581 }
582 }
583
584 return (err != target);
585}
586
Ma Lingd4906092009-03-18 20:13:27 +0800587static bool
588intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800589 int target, int refclk, intel_clock_t *match_clock,
590 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800591{
592 struct drm_device *dev = crtc->dev;
593 struct drm_i915_private *dev_priv = dev->dev_private;
594 intel_clock_t clock;
595 int max_n;
596 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400597 /* approximately equals target * 0.00585 */
598 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800599 found = false;
600
601 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Zhao Yakui45476682009-12-31 16:06:04 +0800602 int lvds_reg;
603
Eric Anholtc619eed2010-01-28 16:45:52 -0800604 if (HAS_PCH_SPLIT(dev))
Zhao Yakui45476682009-12-31 16:06:04 +0800605 lvds_reg = PCH_LVDS;
606 else
607 lvds_reg = LVDS;
608 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
Ma Lingd4906092009-03-18 20:13:27 +0800609 LVDS_CLKB_POWER_UP)
610 clock.p2 = limit->p2.p2_fast;
611 else
612 clock.p2 = limit->p2.p2_slow;
613 } else {
614 if (target < limit->p2.dot_limit)
615 clock.p2 = limit->p2.p2_slow;
616 else
617 clock.p2 = limit->p2.p2_fast;
618 }
619
620 memset(best_clock, 0, sizeof(*best_clock));
621 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200622 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800623 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200624 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800625 for (clock.m1 = limit->m1.max;
626 clock.m1 >= limit->m1.min; clock.m1--) {
627 for (clock.m2 = limit->m2.max;
628 clock.m2 >= limit->m2.min; clock.m2--) {
629 for (clock.p1 = limit->p1.max;
630 clock.p1 >= limit->p1.min; clock.p1--) {
631 int this_err;
632
Shaohua Li21778322009-02-23 15:19:16 +0800633 intel_clock(dev, refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000634 if (!intel_PLL_is_valid(dev, limit,
635 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800636 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800637 if (match_clock &&
638 clock.p != match_clock->p)
639 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000640
641 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800642 if (this_err < err_most) {
643 *best_clock = clock;
644 err_most = this_err;
645 max_n = clock.n;
646 found = true;
647 }
648 }
649 }
650 }
651 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800652 return found;
653}
Ma Lingd4906092009-03-18 20:13:27 +0800654
Zhenyu Wang2c072452009-06-05 15:38:42 +0800655static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500656intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800657 int target, int refclk, intel_clock_t *match_clock,
658 intel_clock_t *best_clock)
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800659{
660 struct drm_device *dev = crtc->dev;
661 intel_clock_t clock;
Zhao Yakui45476682009-12-31 16:06:04 +0800662
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800663 if (target < 200000) {
664 clock.n = 1;
665 clock.p1 = 2;
666 clock.p2 = 10;
667 clock.m1 = 12;
668 clock.m2 = 9;
669 } else {
670 clock.n = 2;
671 clock.p1 = 1;
672 clock.p2 = 10;
673 clock.m1 = 14;
674 clock.m2 = 8;
675 }
676 intel_clock(dev, refclk, &clock);
677 memcpy(best_clock, &clock, sizeof(intel_clock_t));
678 return true;
679}
680
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700681/* DisplayPort has only two frequencies, 162MHz and 270MHz */
682static bool
683intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700686{
Chris Wilson5eddb702010-09-11 13:48:45 +0100687 intel_clock_t clock;
688 if (target < 200000) {
689 clock.p1 = 2;
690 clock.p2 = 10;
691 clock.n = 2;
692 clock.m1 = 23;
693 clock.m2 = 8;
694 } else {
695 clock.p1 = 1;
696 clock.p2 = 10;
697 clock.n = 1;
698 clock.m1 = 14;
699 clock.m2 = 2;
700 }
701 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
702 clock.p = (clock.p1 * clock.p2);
703 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
704 clock.vco = 0;
705 memcpy(best_clock, &clock, sizeof(intel_clock_t));
706 return true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700707}
708
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700709/**
710 * intel_wait_for_vblank - wait for vblank on a given pipe
711 * @dev: drm device
712 * @pipe: pipe to wait for
713 *
714 * Wait for vblank to occur on a given pipe. Needed for various bits of
715 * mode setting code.
716 */
717void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800718{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700719 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800720 int pipestat_reg = PIPESTAT(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700721
Chris Wilson300387c2010-09-05 20:25:43 +0100722 /* Clear existing vblank status. Note this will clear any other
723 * sticky status fields as well.
724 *
725 * This races with i915_driver_irq_handler() with the result
726 * that either function could miss a vblank event. Here it is not
727 * fatal, as we will either wait upon the next vblank interrupt or
728 * timeout. Generally speaking intel_wait_for_vblank() is only
729 * called during modeset at which time the GPU should be idle and
730 * should *not* be performing page flips and thus not waiting on
731 * vblanks...
732 * Currently, the result of us stealing a vblank from the irq
733 * handler is that a single frame will be skipped during swapbuffers.
734 */
735 I915_WRITE(pipestat_reg,
736 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
737
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700738 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +0100739 if (wait_for(I915_READ(pipestat_reg) &
740 PIPE_VBLANK_INTERRUPT_STATUS,
741 50))
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700742 DRM_DEBUG_KMS("vblank wait timed out\n");
743}
744
Keith Packardab7ad7f2010-10-03 00:33:06 -0700745/*
746 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700747 * @dev: drm device
748 * @pipe: pipe to wait for
749 *
750 * After disabling a pipe, we can't wait for vblank in the usual way,
751 * spinning on the vblank interrupt status bit, since we won't actually
752 * see an interrupt when the pipe is disabled.
753 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700754 * On Gen4 and above:
755 * wait for the pipe register state bit to turn off
756 *
757 * Otherwise:
758 * wait for the display line value to settle (it usually
759 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100760 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700761 */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100762void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700765
Keith Packardab7ad7f2010-10-03 00:33:06 -0700766 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson58e10eb2010-10-03 10:56:11 +0100767 int reg = PIPECONF(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700768
Keith Packardab7ad7f2010-10-03 00:33:06 -0700769 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100770 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
771 100))
Keith Packardab7ad7f2010-10-03 00:33:06 -0700772 DRM_DEBUG_KMS("pipe_off wait timed out\n");
773 } else {
774 u32 last_line;
Chris Wilson58e10eb2010-10-03 10:56:11 +0100775 int reg = PIPEDSL(pipe);
Keith Packardab7ad7f2010-10-03 00:33:06 -0700776 unsigned long timeout = jiffies + msecs_to_jiffies(100);
777
778 /* Wait for the display line to settle */
779 do {
Chris Wilson58e10eb2010-10-03 10:56:11 +0100780 last_line = I915_READ(reg) & DSL_LINEMASK;
Keith Packardab7ad7f2010-10-03 00:33:06 -0700781 mdelay(5);
Chris Wilson58e10eb2010-10-03 10:56:11 +0100782 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
Keith Packardab7ad7f2010-10-03 00:33:06 -0700783 time_after(timeout, jiffies));
784 if (time_after(jiffies, timeout))
785 DRM_DEBUG_KMS("pipe_off wait timed out\n");
786 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800787}
788
Jesse Barnesb24e7172011-01-04 15:09:30 -0800789static const char *state_string(bool enabled)
790{
791 return enabled ? "on" : "off";
792}
793
794/* Only for pre-ILK configs */
795static void assert_pll(struct drm_i915_private *dev_priv,
796 enum pipe pipe, bool state)
797{
798 int reg;
799 u32 val;
800 bool cur_state;
801
802 reg = DPLL(pipe);
803 val = I915_READ(reg);
804 cur_state = !!(val & DPLL_VCO_ENABLE);
805 WARN(cur_state != state,
806 "PLL state assertion failure (expected %s, current %s)\n",
807 state_string(state), state_string(cur_state));
808}
809#define assert_pll_enabled(d, p) assert_pll(d, p, true)
810#define assert_pll_disabled(d, p) assert_pll(d, p, false)
811
Jesse Barnes040484a2011-01-03 12:14:26 -0800812/* For ILK+ */
813static void assert_pch_pll(struct drm_i915_private *dev_priv,
814 enum pipe pipe, bool state)
815{
816 int reg;
817 u32 val;
818 bool cur_state;
819
Jesse Barnesd3ccbe82011-10-12 09:27:42 -0700820 if (HAS_PCH_CPT(dev_priv->dev)) {
821 u32 pch_dpll;
822
823 pch_dpll = I915_READ(PCH_DPLL_SEL);
824
825 /* Make sure the selected PLL is enabled to the transcoder */
826 WARN(!((pch_dpll >> (4 * pipe)) & 8),
827 "transcoder %d PLL not enabled\n", pipe);
828
829 /* Convert the transcoder pipe number to a pll pipe number */
830 pipe = (pch_dpll >> (4 * pipe)) & 1;
831 }
832
Jesse Barnes040484a2011-01-03 12:14:26 -0800833 reg = PCH_DPLL(pipe);
834 val = I915_READ(reg);
835 cur_state = !!(val & DPLL_VCO_ENABLE);
836 WARN(cur_state != state,
837 "PCH PLL state assertion failure (expected %s, current %s)\n",
838 state_string(state), state_string(cur_state));
839}
840#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
841#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
842
843static void assert_fdi_tx(struct drm_i915_private *dev_priv,
844 enum pipe pipe, bool state)
845{
846 int reg;
847 u32 val;
848 bool cur_state;
849
850 reg = FDI_TX_CTL(pipe);
851 val = I915_READ(reg);
852 cur_state = !!(val & FDI_TX_ENABLE);
853 WARN(cur_state != state,
854 "FDI TX state assertion failure (expected %s, current %s)\n",
855 state_string(state), state_string(cur_state));
856}
857#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
858#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
859
860static void assert_fdi_rx(struct drm_i915_private *dev_priv,
861 enum pipe pipe, bool state)
862{
863 int reg;
864 u32 val;
865 bool cur_state;
866
867 reg = FDI_RX_CTL(pipe);
868 val = I915_READ(reg);
869 cur_state = !!(val & FDI_RX_ENABLE);
870 WARN(cur_state != state,
871 "FDI RX state assertion failure (expected %s, current %s)\n",
872 state_string(state), state_string(cur_state));
873}
874#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
875#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
876
877static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879{
880 int reg;
881 u32 val;
882
883 /* ILK FDI PLL is always enabled */
884 if (dev_priv->info->gen == 5)
885 return;
886
887 reg = FDI_TX_CTL(pipe);
888 val = I915_READ(reg);
889 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
890}
891
892static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
893 enum pipe pipe)
894{
895 int reg;
896 u32 val;
897
898 reg = FDI_RX_CTL(pipe);
899 val = I915_READ(reg);
900 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
901}
902
Jesse Barnesea0760c2011-01-04 15:09:32 -0800903static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
904 enum pipe pipe)
905{
906 int pp_reg, lvds_reg;
907 u32 val;
908 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +0200909 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -0800910
911 if (HAS_PCH_SPLIT(dev_priv->dev)) {
912 pp_reg = PCH_PP_CONTROL;
913 lvds_reg = PCH_LVDS;
914 } else {
915 pp_reg = PP_CONTROL;
916 lvds_reg = LVDS;
917 }
918
919 val = I915_READ(pp_reg);
920 if (!(val & PANEL_POWER_ON) ||
921 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
922 locked = false;
923
924 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
925 panel_pipe = PIPE_B;
926
927 WARN(panel_pipe == pipe && locked,
928 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800929 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -0800930}
931
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800932void assert_pipe(struct drm_i915_private *dev_priv,
933 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -0800934{
935 int reg;
936 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -0800937 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -0800938
Daniel Vetter8e636782012-01-22 01:36:48 +0100939 /* if we need the pipe A quirk it must be always on */
940 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
941 state = true;
942
Jesse Barnesb24e7172011-01-04 15:09:30 -0800943 reg = PIPECONF(pipe);
944 val = I915_READ(reg);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -0800945 cur_state = !!(val & PIPECONF_ENABLE);
946 WARN(cur_state != state,
947 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800948 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -0800949}
950
Chris Wilson931872f2012-01-16 23:01:13 +0000951static void assert_plane(struct drm_i915_private *dev_priv,
952 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -0800953{
954 int reg;
955 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +0000956 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -0800957
958 reg = DSPCNTR(plane);
959 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +0000960 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
961 WARN(cur_state != state,
962 "plane %c assertion failure (expected %s, current %s)\n",
963 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -0800964}
965
Chris Wilson931872f2012-01-16 23:01:13 +0000966#define assert_plane_enabled(d, p) assert_plane(d, p, true)
967#define assert_plane_disabled(d, p) assert_plane(d, p, false)
968
Jesse Barnesb24e7172011-01-04 15:09:30 -0800969static void assert_planes_disabled(struct drm_i915_private *dev_priv,
970 enum pipe pipe)
971{
972 int reg, i;
973 u32 val;
974 int cur_pipe;
975
Jesse Barnes19ec1352011-02-02 12:28:02 -0800976 /* Planes are fixed to pipes on ILK+ */
Adam Jackson28c057942011-10-07 14:38:42 -0400977 if (HAS_PCH_SPLIT(dev_priv->dev)) {
978 reg = DSPCNTR(pipe);
979 val = I915_READ(reg);
980 WARN((val & DISPLAY_PLANE_ENABLE),
981 "plane %c assertion failure, should be disabled but not\n",
982 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -0800983 return;
Adam Jackson28c057942011-10-07 14:38:42 -0400984 }
Jesse Barnes19ec1352011-02-02 12:28:02 -0800985
Jesse Barnesb24e7172011-01-04 15:09:30 -0800986 /* Need to check both planes against the pipe */
987 for (i = 0; i < 2; i++) {
988 reg = DSPCNTR(i);
989 val = I915_READ(reg);
990 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
991 DISPPLANE_SEL_PIPE_SHIFT;
992 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800993 "plane %c assertion failure, should be off on pipe %c but is still active\n",
994 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -0800995 }
996}
997
Jesse Barnes92f25842011-01-04 15:09:34 -0800998static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
999{
1000 u32 val;
1001 bool enabled;
1002
1003 val = I915_READ(PCH_DREF_CONTROL);
1004 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1005 DREF_SUPERSPREAD_SOURCE_MASK));
1006 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1007}
1008
1009static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe)
1011{
1012 int reg;
1013 u32 val;
1014 bool enabled;
1015
1016 reg = TRANSCONF(pipe);
1017 val = I915_READ(reg);
1018 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001019 WARN(enabled,
1020 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1021 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001022}
1023
Keith Packard4e634382011-08-06 10:39:45 -07001024static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001026{
1027 if ((val & DP_PORT_EN) == 0)
1028 return false;
1029
1030 if (HAS_PCH_CPT(dev_priv->dev)) {
1031 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1032 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1033 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1034 return false;
1035 } else {
1036 if ((val & DP_PIPE_MASK) != (pipe << 30))
1037 return false;
1038 }
1039 return true;
1040}
1041
Keith Packard1519b992011-08-06 10:35:34 -07001042static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1043 enum pipe pipe, u32 val)
1044{
1045 if ((val & PORT_ENABLE) == 0)
1046 return false;
1047
1048 if (HAS_PCH_CPT(dev_priv->dev)) {
1049 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1050 return false;
1051 } else {
1052 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1053 return false;
1054 }
1055 return true;
1056}
1057
1058static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, u32 val)
1060{
1061 if ((val & LVDS_PORT_EN) == 0)
1062 return false;
1063
1064 if (HAS_PCH_CPT(dev_priv->dev)) {
1065 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1066 return false;
1067 } else {
1068 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1069 return false;
1070 }
1071 return true;
1072}
1073
1074static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1075 enum pipe pipe, u32 val)
1076{
1077 if ((val & ADPA_DAC_ENABLE) == 0)
1078 return false;
1079 if (HAS_PCH_CPT(dev_priv->dev)) {
1080 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1081 return false;
1082 } else {
1083 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1084 return false;
1085 }
1086 return true;
1087}
1088
Jesse Barnes291906f2011-02-02 12:28:03 -08001089static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001090 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001091{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001092 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001093 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001094 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001095 reg, pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001096}
1097
1098static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1099 enum pipe pipe, int reg)
1100{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001101 u32 val = I915_READ(reg);
Keith Packard1519b992011-08-06 10:35:34 -07001102 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
Adam Jackson23c99e72011-10-07 14:38:43 -04001103 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001104 reg, pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001105}
1106
1107static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1108 enum pipe pipe)
1109{
1110 int reg;
1111 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001112
Keith Packardf0575e92011-07-25 22:12:43 -07001113 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1114 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1115 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001116
1117 reg = PCH_ADPA;
1118 val = I915_READ(reg);
Keith Packard1519b992011-08-06 10:35:34 -07001119 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
Jesse Barnes291906f2011-02-02 12:28:03 -08001120 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001121 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001122
1123 reg = PCH_LVDS;
1124 val = I915_READ(reg);
Keith Packard1519b992011-08-06 10:35:34 -07001125 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
Jesse Barnes291906f2011-02-02 12:28:03 -08001126 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001127 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001128
1129 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1130 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1131 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1132}
1133
Jesse Barnesb24e7172011-01-04 15:09:30 -08001134/**
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001135 * intel_enable_pll - enable a PLL
1136 * @dev_priv: i915 private structure
1137 * @pipe: pipe PLL to enable
1138 *
1139 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1140 * make sure the PLL reg is writable first though, since the panel write
1141 * protect mechanism may be enabled.
1142 *
1143 * Note! This is for pre-ILK only.
1144 */
1145static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1146{
1147 int reg;
1148 u32 val;
1149
1150 /* No really, not for ILK+ */
1151 BUG_ON(dev_priv->info->gen >= 5);
1152
1153 /* PLL is protected by panel, make sure we can write it */
1154 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1155 assert_panel_unlocked(dev_priv, pipe);
1156
1157 reg = DPLL(pipe);
1158 val = I915_READ(reg);
1159 val |= DPLL_VCO_ENABLE;
1160
1161 /* We do this three times for luck */
1162 I915_WRITE(reg, val);
1163 POSTING_READ(reg);
1164 udelay(150); /* wait for warmup */
1165 I915_WRITE(reg, val);
1166 POSTING_READ(reg);
1167 udelay(150); /* wait for warmup */
1168 I915_WRITE(reg, val);
1169 POSTING_READ(reg);
1170 udelay(150); /* wait for warmup */
1171}
1172
1173/**
1174 * intel_disable_pll - disable a PLL
1175 * @dev_priv: i915 private structure
1176 * @pipe: pipe PLL to disable
1177 *
1178 * Disable the PLL for @pipe, making sure the pipe is off first.
1179 *
1180 * Note! This is for pre-ILK only.
1181 */
1182static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1183{
1184 int reg;
1185 u32 val;
1186
1187 /* Don't disable pipe A or pipe A PLLs if needed */
1188 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1189 return;
1190
1191 /* Make sure the pipe isn't still relying on us */
1192 assert_pipe_disabled(dev_priv, pipe);
1193
1194 reg = DPLL(pipe);
1195 val = I915_READ(reg);
1196 val &= ~DPLL_VCO_ENABLE;
1197 I915_WRITE(reg, val);
1198 POSTING_READ(reg);
1199}
1200
1201/**
Jesse Barnes92f25842011-01-04 15:09:34 -08001202 * intel_enable_pch_pll - enable PCH PLL
1203 * @dev_priv: i915 private structure
1204 * @pipe: pipe PLL to enable
1205 *
1206 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1207 * drives the transcoder clock.
1208 */
1209static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
1211{
1212 int reg;
1213 u32 val;
1214
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001215 if (pipe > 1)
1216 return;
1217
Jesse Barnes92f25842011-01-04 15:09:34 -08001218 /* PCH only available on ILK+ */
1219 BUG_ON(dev_priv->info->gen < 5);
1220
1221 /* PCH refclock must be enabled first */
1222 assert_pch_refclk_enabled(dev_priv);
1223
1224 reg = PCH_DPLL(pipe);
1225 val = I915_READ(reg);
1226 val |= DPLL_VCO_ENABLE;
1227 I915_WRITE(reg, val);
1228 POSTING_READ(reg);
1229 udelay(200);
1230}
1231
1232static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
1234{
1235 int reg;
Jesse Barnes7a419862011-11-15 10:28:53 -08001236 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1237 pll_sel = TRANSC_DPLL_ENABLE;
Jesse Barnes92f25842011-01-04 15:09:34 -08001238
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001239 if (pipe > 1)
1240 return;
1241
Jesse Barnes92f25842011-01-04 15:09:34 -08001242 /* PCH only available on ILK+ */
1243 BUG_ON(dev_priv->info->gen < 5);
1244
1245 /* Make sure transcoder isn't still depending on us */
1246 assert_transcoder_disabled(dev_priv, pipe);
1247
Jesse Barnes7a419862011-11-15 10:28:53 -08001248 if (pipe == 0)
1249 pll_sel |= TRANSC_DPLLA_SEL;
1250 else if (pipe == 1)
1251 pll_sel |= TRANSC_DPLLB_SEL;
1252
1253
1254 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1255 return;
1256
Jesse Barnes92f25842011-01-04 15:09:34 -08001257 reg = PCH_DPLL(pipe);
1258 val = I915_READ(reg);
1259 val &= ~DPLL_VCO_ENABLE;
1260 I915_WRITE(reg, val);
1261 POSTING_READ(reg);
1262 udelay(200);
1263}
1264
Jesse Barnes040484a2011-01-03 12:14:26 -08001265static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1266 enum pipe pipe)
1267{
1268 int reg;
1269 u32 val;
1270
1271 /* PCH only available on ILK+ */
1272 BUG_ON(dev_priv->info->gen < 5);
1273
1274 /* Make sure PCH DPLL is enabled */
1275 assert_pch_pll_enabled(dev_priv, pipe);
1276
1277 /* FDI must be feeding us bits for PCH ports */
1278 assert_fdi_tx_enabled(dev_priv, pipe);
1279 assert_fdi_rx_enabled(dev_priv, pipe);
1280
1281 reg = TRANSCONF(pipe);
1282 val = I915_READ(reg);
Jesse Barnese9bcff52011-06-24 12:19:20 -07001283
1284 if (HAS_PCH_IBX(dev_priv->dev)) {
1285 /*
1286 * make the BPC in transcoder be consistent with
1287 * that in pipeconf reg.
1288 */
1289 val &= ~PIPE_BPC_MASK;
1290 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1291 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001292 I915_WRITE(reg, val | TRANS_ENABLE);
1293 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1294 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1295}
1296
1297static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1298 enum pipe pipe)
1299{
1300 int reg;
1301 u32 val;
1302
1303 /* FDI relies on the transcoder */
1304 assert_fdi_tx_disabled(dev_priv, pipe);
1305 assert_fdi_rx_disabled(dev_priv, pipe);
1306
Jesse Barnes291906f2011-02-02 12:28:03 -08001307 /* Ports must be off as well */
1308 assert_pch_ports_disabled(dev_priv, pipe);
1309
Jesse Barnes040484a2011-01-03 12:14:26 -08001310 reg = TRANSCONF(pipe);
1311 val = I915_READ(reg);
1312 val &= ~TRANS_ENABLE;
1313 I915_WRITE(reg, val);
1314 /* wait for PCH transcoder off, transcoder state */
1315 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Jesse Barnes4c9c18c2011-10-13 09:46:32 -07001316 DRM_ERROR("failed to disable transcoder %d\n", pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001317}
1318
Jesse Barnes92f25842011-01-04 15:09:34 -08001319/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001320 * intel_enable_pipe - enable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001321 * @dev_priv: i915 private structure
1322 * @pipe: pipe to enable
Jesse Barnes040484a2011-01-03 12:14:26 -08001323 * @pch_port: on ILK+, is this pipe driving a PCH port or not
Jesse Barnesb24e7172011-01-04 15:09:30 -08001324 *
1325 * Enable @pipe, making sure that various hardware specific requirements
1326 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1327 *
1328 * @pipe should be %PIPE_A or %PIPE_B.
1329 *
1330 * Will wait until the pipe is actually running (i.e. first vblank) before
1331 * returning.
1332 */
Jesse Barnes040484a2011-01-03 12:14:26 -08001333static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1334 bool pch_port)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001335{
1336 int reg;
1337 u32 val;
1338
1339 /*
1340 * A pipe without a PLL won't actually be able to drive bits from
1341 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1342 * need the check.
1343 */
1344 if (!HAS_PCH_SPLIT(dev_priv->dev))
1345 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001346 else {
1347 if (pch_port) {
1348 /* if driving the PCH, we need FDI enabled */
1349 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1350 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1351 }
1352 /* FIXME: assert CPU port conditions for SNB+ */
1353 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08001354
1355 reg = PIPECONF(pipe);
1356 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001357 if (val & PIPECONF_ENABLE)
1358 return;
1359
1360 I915_WRITE(reg, val | PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001361 intel_wait_for_vblank(dev_priv->dev, pipe);
1362}
1363
1364/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001365 * intel_disable_pipe - disable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001366 * @dev_priv: i915 private structure
1367 * @pipe: pipe to disable
1368 *
1369 * Disable @pipe, making sure that various hardware specific requirements
1370 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1371 *
1372 * @pipe should be %PIPE_A or %PIPE_B.
1373 *
1374 * Will wait until the pipe has shut down before returning.
1375 */
1376static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1377 enum pipe pipe)
1378{
1379 int reg;
1380 u32 val;
1381
1382 /*
1383 * Make sure planes won't keep trying to pump pixels to us,
1384 * or we might hang the display.
1385 */
1386 assert_planes_disabled(dev_priv, pipe);
1387
1388 /* Don't disable pipe A or pipe A PLLs if needed */
1389 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1390 return;
1391
1392 reg = PIPECONF(pipe);
1393 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001394 if ((val & PIPECONF_ENABLE) == 0)
1395 return;
1396
1397 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001398 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1399}
1400
Keith Packardd74362c2011-07-28 14:47:14 -07001401/*
1402 * Plane regs are double buffered, going from enabled->disabled needs a
1403 * trigger in order to latch. The display address reg provides this.
1404 */
1405static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1406 enum plane plane)
1407{
1408 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1409 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1410}
1411
Jesse Barnesb24e7172011-01-04 15:09:30 -08001412/**
1413 * intel_enable_plane - enable a display plane on a given pipe
1414 * @dev_priv: i915 private structure
1415 * @plane: plane to enable
1416 * @pipe: pipe being fed
1417 *
1418 * Enable @plane on @pipe, making sure that @pipe is running first.
1419 */
1420static void intel_enable_plane(struct drm_i915_private *dev_priv,
1421 enum plane plane, enum pipe pipe)
1422{
1423 int reg;
1424 u32 val;
1425
1426 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1427 assert_pipe_enabled(dev_priv, pipe);
1428
1429 reg = DSPCNTR(plane);
1430 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001431 if (val & DISPLAY_PLANE_ENABLE)
1432 return;
1433
1434 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
Keith Packardd74362c2011-07-28 14:47:14 -07001435 intel_flush_display_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001436 intel_wait_for_vblank(dev_priv->dev, pipe);
1437}
1438
Jesse Barnesb24e7172011-01-04 15:09:30 -08001439/**
1440 * intel_disable_plane - disable a display plane
1441 * @dev_priv: i915 private structure
1442 * @plane: plane to disable
1443 * @pipe: pipe consuming the data
1444 *
1445 * Disable @plane; should be an independent operation.
1446 */
1447static void intel_disable_plane(struct drm_i915_private *dev_priv,
1448 enum plane plane, enum pipe pipe)
1449{
1450 int reg;
1451 u32 val;
1452
1453 reg = DSPCNTR(plane);
1454 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001455 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1456 return;
1457
1458 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001459 intel_flush_display_plane(dev_priv, plane);
1460 intel_wait_for_vblank(dev_priv->dev, pipe);
1461}
1462
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001463static void disable_pch_dp(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001464 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001465{
1466 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001467 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
Keith Packardf0575e92011-07-25 22:12:43 -07001468 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001469 I915_WRITE(reg, val & ~DP_PORT_EN);
Keith Packardf0575e92011-07-25 22:12:43 -07001470 }
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001471}
1472
1473static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1474 enum pipe pipe, int reg)
1475{
1476 u32 val = I915_READ(reg);
Keith Packard1519b992011-08-06 10:35:34 -07001477 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
Keith Packardf0575e92011-07-25 22:12:43 -07001478 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1479 reg, pipe);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001480 I915_WRITE(reg, val & ~PORT_ENABLE);
Keith Packardf0575e92011-07-25 22:12:43 -07001481 }
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001482}
1483
1484/* Disable any ports connected to this transcoder */
1485static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1486 enum pipe pipe)
1487{
1488 u32 reg, val;
1489
1490 val = I915_READ(PCH_PP_CONTROL);
1491 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1492
Keith Packardf0575e92011-07-25 22:12:43 -07001493 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1494 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1495 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001496
1497 reg = PCH_ADPA;
1498 val = I915_READ(reg);
Keith Packard1519b992011-08-06 10:35:34 -07001499 if (adpa_pipe_enabled(dev_priv, val, pipe))
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001500 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1501
1502 reg = PCH_LVDS;
1503 val = I915_READ(reg);
Keith Packard1519b992011-08-06 10:35:34 -07001504 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1505 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001506 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1507 POSTING_READ(reg);
1508 udelay(100);
1509 }
1510
1511 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1512 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1513 disable_pch_hdmi(dev_priv, pipe, HDMID);
1514}
1515
Chris Wilson43a95392011-07-08 12:22:36 +01001516static void i8xx_disable_fbc(struct drm_device *dev)
1517{
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1519 u32 fbc_ctl;
1520
1521 /* Disable compression */
1522 fbc_ctl = I915_READ(FBC_CONTROL);
1523 if ((fbc_ctl & FBC_CTL_EN) == 0)
1524 return;
1525
1526 fbc_ctl &= ~FBC_CTL_EN;
1527 I915_WRITE(FBC_CONTROL, fbc_ctl);
1528
1529 /* Wait for compressing bit to clear */
1530 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1531 DRM_DEBUG_KMS("FBC idle timed out\n");
1532 return;
1533 }
1534
1535 DRM_DEBUG_KMS("disabled FBC\n");
1536}
1537
Jesse Barnes80824002009-09-10 15:28:06 -07001538static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1539{
1540 struct drm_device *dev = crtc->dev;
1541 struct drm_i915_private *dev_priv = dev->dev_private;
1542 struct drm_framebuffer *fb = crtc->fb;
1543 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00001544 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes80824002009-09-10 15:28:06 -07001545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson016b9b62011-07-08 12:22:43 +01001546 int cfb_pitch;
Jesse Barnes80824002009-09-10 15:28:06 -07001547 int plane, i;
1548 u32 fbc_ctl, fbc_ctl2;
1549
Chris Wilson016b9b62011-07-08 12:22:43 +01001550 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02001551 if (fb->pitches[0] < cfb_pitch)
1552 cfb_pitch = fb->pitches[0];
Jesse Barnes80824002009-09-10 15:28:06 -07001553
1554 /* FBC_CTL wants 64B units */
Chris Wilson016b9b62011-07-08 12:22:43 +01001555 cfb_pitch = (cfb_pitch / 64) - 1;
1556 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
Jesse Barnes80824002009-09-10 15:28:06 -07001557
1558 /* Clear old tags */
1559 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1560 I915_WRITE(FBC_TAG + (i * 4), 0);
1561
1562 /* Set it up... */
Chris Wilsonde568512011-07-08 12:22:39 +01001563 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1564 fbc_ctl2 |= plane;
Jesse Barnes80824002009-09-10 15:28:06 -07001565 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1566 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1567
1568 /* enable it... */
1569 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
Jesse Barnesee25df22010-02-06 10:41:53 -08001570 if (IS_I945GM(dev))
Priit Laes49677902010-03-02 11:37:00 +02001571 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
Chris Wilson016b9b62011-07-08 12:22:43 +01001572 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
Jesse Barnes80824002009-09-10 15:28:06 -07001573 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
Chris Wilson016b9b62011-07-08 12:22:43 +01001574 fbc_ctl |= obj->fence_reg;
Jesse Barnes80824002009-09-10 15:28:06 -07001575 I915_WRITE(FBC_CONTROL, fbc_ctl);
1576
Chris Wilson016b9b62011-07-08 12:22:43 +01001577 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1578 cfb_pitch, crtc->y, intel_crtc->plane);
Jesse Barnes80824002009-09-10 15:28:06 -07001579}
1580
Adam Jacksonee5382a2010-04-23 11:17:39 -04001581static bool i8xx_fbc_enabled(struct drm_device *dev)
Jesse Barnes80824002009-09-10 15:28:06 -07001582{
Jesse Barnes80824002009-09-10 15:28:06 -07001583 struct drm_i915_private *dev_priv = dev->dev_private;
1584
1585 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1586}
1587
Jesse Barnes74dff282009-09-14 15:39:40 -07001588static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1589{
1590 struct drm_device *dev = crtc->dev;
1591 struct drm_i915_private *dev_priv = dev->dev_private;
1592 struct drm_framebuffer *fb = crtc->fb;
1593 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00001594 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes74dff282009-09-14 15:39:40 -07001595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5eddb702010-09-11 13:48:45 +01001596 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
Jesse Barnes74dff282009-09-14 15:39:40 -07001597 unsigned long stall_watermark = 200;
1598 u32 dpfc_ctl;
1599
Jesse Barnes74dff282009-09-14 15:39:40 -07001600 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
Chris Wilson016b9b62011-07-08 12:22:43 +01001601 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
Chris Wilsonde568512011-07-08 12:22:39 +01001602 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
Jesse Barnes74dff282009-09-14 15:39:40 -07001603
Jesse Barnes74dff282009-09-14 15:39:40 -07001604 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1605 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1606 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1607 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1608
1609 /* enable it... */
1610 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1611
Zhao Yakui28c97732009-10-09 11:39:41 +08001612 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
Jesse Barnes74dff282009-09-14 15:39:40 -07001613}
1614
Chris Wilson43a95392011-07-08 12:22:36 +01001615static void g4x_disable_fbc(struct drm_device *dev)
Jesse Barnes74dff282009-09-14 15:39:40 -07001616{
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 u32 dpfc_ctl;
1619
1620 /* Disable compression */
1621 dpfc_ctl = I915_READ(DPFC_CONTROL);
Chris Wilsonbed4a672010-09-11 10:47:47 +01001622 if (dpfc_ctl & DPFC_CTL_EN) {
1623 dpfc_ctl &= ~DPFC_CTL_EN;
1624 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
Jesse Barnes74dff282009-09-14 15:39:40 -07001625
Chris Wilsonbed4a672010-09-11 10:47:47 +01001626 DRM_DEBUG_KMS("disabled FBC\n");
1627 }
Jesse Barnes74dff282009-09-14 15:39:40 -07001628}
1629
Adam Jacksonee5382a2010-04-23 11:17:39 -04001630static bool g4x_fbc_enabled(struct drm_device *dev)
Jesse Barnes74dff282009-09-14 15:39:40 -07001631{
Jesse Barnes74dff282009-09-14 15:39:40 -07001632 struct drm_i915_private *dev_priv = dev->dev_private;
1633
1634 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1635}
1636
Jesse Barnes4efe0702011-01-18 11:25:41 -08001637static void sandybridge_blit_fbc_update(struct drm_device *dev)
1638{
1639 struct drm_i915_private *dev_priv = dev->dev_private;
1640 u32 blt_ecoskpd;
1641
1642 /* Make sure blitter notifies FBC of writes */
Ben Widawskyfcca7922011-04-25 11:23:07 -07001643 gen6_gt_force_wake_get(dev_priv);
Jesse Barnes4efe0702011-01-18 11:25:41 -08001644 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1645 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1646 GEN6_BLITTER_LOCK_SHIFT;
1647 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1648 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1649 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1650 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1651 GEN6_BLITTER_LOCK_SHIFT);
1652 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1653 POSTING_READ(GEN6_BLITTER_ECOSKPD);
Ben Widawskyfcca7922011-04-25 11:23:07 -07001654 gen6_gt_force_wake_put(dev_priv);
Jesse Barnes4efe0702011-01-18 11:25:41 -08001655}
1656
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001657static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1658{
1659 struct drm_device *dev = crtc->dev;
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 struct drm_framebuffer *fb = crtc->fb;
1662 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00001663 struct drm_i915_gem_object *obj = intel_fb->obj;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5eddb702010-09-11 13:48:45 +01001665 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001666 unsigned long stall_watermark = 200;
1667 u32 dpfc_ctl;
1668
Chris Wilsonbed4a672010-09-11 10:47:47 +01001669 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001670 dpfc_ctl &= DPFC_RESERVED;
1671 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
Chris Wilson9ce9d062011-07-08 12:22:40 +01001672 /* Set persistent mode for front-buffer rendering, ala X. */
1673 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
Chris Wilson016b9b62011-07-08 12:22:43 +01001674 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
Chris Wilsonde568512011-07-08 12:22:39 +01001675 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001676
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001677 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1678 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1679 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1680 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
Chris Wilson05394f32010-11-08 19:18:58 +00001681 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001682 /* enable it... */
Chris Wilsonbed4a672010-09-11 10:47:47 +01001683 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001684
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001685 if (IS_GEN6(dev)) {
1686 I915_WRITE(SNB_DPFC_CTL_SA,
Chris Wilson016b9b62011-07-08 12:22:43 +01001687 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001688 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
Jesse Barnes4efe0702011-01-18 11:25:41 -08001689 sandybridge_blit_fbc_update(dev);
Yuanhan Liu9c04f012010-12-15 15:42:32 +08001690 }
1691
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001692 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1693}
1694
Chris Wilson43a95392011-07-08 12:22:36 +01001695static void ironlake_disable_fbc(struct drm_device *dev)
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001696{
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698 u32 dpfc_ctl;
1699
1700 /* Disable compression */
1701 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
Chris Wilsonbed4a672010-09-11 10:47:47 +01001702 if (dpfc_ctl & DPFC_CTL_EN) {
1703 dpfc_ctl &= ~DPFC_CTL_EN;
1704 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001705
Chris Wilsonbed4a672010-09-11 10:47:47 +01001706 DRM_DEBUG_KMS("disabled FBC\n");
1707 }
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08001708}
1709
1710static bool ironlake_fbc_enabled(struct drm_device *dev)
1711{
1712 struct drm_i915_private *dev_priv = dev->dev_private;
1713
1714 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1715}
1716
Adam Jacksonee5382a2010-04-23 11:17:39 -04001717bool intel_fbc_enabled(struct drm_device *dev)
1718{
1719 struct drm_i915_private *dev_priv = dev->dev_private;
1720
1721 if (!dev_priv->display.fbc_enabled)
1722 return false;
1723
1724 return dev_priv->display.fbc_enabled(dev);
1725}
1726
Chris Wilson1630fe72011-07-08 12:22:42 +01001727static void intel_fbc_work_fn(struct work_struct *__work)
1728{
1729 struct intel_fbc_work *work =
1730 container_of(to_delayed_work(__work),
1731 struct intel_fbc_work, work);
1732 struct drm_device *dev = work->crtc->dev;
1733 struct drm_i915_private *dev_priv = dev->dev_private;
1734
1735 mutex_lock(&dev->struct_mutex);
1736 if (work == dev_priv->fbc_work) {
1737 /* Double check that we haven't switched fb without cancelling
1738 * the prior work.
1739 */
Chris Wilson016b9b62011-07-08 12:22:43 +01001740 if (work->crtc->fb == work->fb) {
Chris Wilson1630fe72011-07-08 12:22:42 +01001741 dev_priv->display.enable_fbc(work->crtc,
1742 work->interval);
1743
Chris Wilson016b9b62011-07-08 12:22:43 +01001744 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1745 dev_priv->cfb_fb = work->crtc->fb->base.id;
1746 dev_priv->cfb_y = work->crtc->y;
1747 }
1748
Chris Wilson1630fe72011-07-08 12:22:42 +01001749 dev_priv->fbc_work = NULL;
1750 }
1751 mutex_unlock(&dev->struct_mutex);
1752
1753 kfree(work);
1754}
1755
1756static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1757{
1758 if (dev_priv->fbc_work == NULL)
1759 return;
1760
1761 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1762
1763 /* Synchronisation is provided by struct_mutex and checking of
1764 * dev_priv->fbc_work, so we can perform the cancellation
1765 * entirely asynchronously.
1766 */
1767 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1768 /* tasklet was killed before being run, clean up */
1769 kfree(dev_priv->fbc_work);
1770
1771 /* Mark the work as no longer wanted so that if it does
1772 * wake-up (because the work was already running and waiting
1773 * for our mutex), it will discover that is no longer
1774 * necessary to run.
1775 */
1776 dev_priv->fbc_work = NULL;
1777}
1778
Chris Wilson43a95392011-07-08 12:22:36 +01001779static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
Adam Jacksonee5382a2010-04-23 11:17:39 -04001780{
Chris Wilson1630fe72011-07-08 12:22:42 +01001781 struct intel_fbc_work *work;
1782 struct drm_device *dev = crtc->dev;
1783 struct drm_i915_private *dev_priv = dev->dev_private;
Adam Jacksonee5382a2010-04-23 11:17:39 -04001784
1785 if (!dev_priv->display.enable_fbc)
1786 return;
1787
Chris Wilson1630fe72011-07-08 12:22:42 +01001788 intel_cancel_fbc_work(dev_priv);
1789
1790 work = kzalloc(sizeof *work, GFP_KERNEL);
1791 if (work == NULL) {
1792 dev_priv->display.enable_fbc(crtc, interval);
1793 return;
1794 }
1795
1796 work->crtc = crtc;
1797 work->fb = crtc->fb;
1798 work->interval = interval;
1799 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1800
1801 dev_priv->fbc_work = work;
1802
1803 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1804
1805 /* Delay the actual enabling to let pageflipping cease and the
Chris Wilson016b9b62011-07-08 12:22:43 +01001806 * display to settle before starting the compression. Note that
1807 * this delay also serves a second purpose: it allows for a
1808 * vblank to pass after disabling the FBC before we attempt
1809 * to modify the control registers.
Chris Wilson1630fe72011-07-08 12:22:42 +01001810 *
1811 * A more complicated solution would involve tracking vblanks
1812 * following the termination of the page-flipping sequence
1813 * and indeed performing the enable as a co-routine and not
1814 * waiting synchronously upon the vblank.
1815 */
1816 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
Adam Jacksonee5382a2010-04-23 11:17:39 -04001817}
1818
1819void intel_disable_fbc(struct drm_device *dev)
1820{
1821 struct drm_i915_private *dev_priv = dev->dev_private;
1822
Chris Wilson1630fe72011-07-08 12:22:42 +01001823 intel_cancel_fbc_work(dev_priv);
1824
Adam Jacksonee5382a2010-04-23 11:17:39 -04001825 if (!dev_priv->display.disable_fbc)
1826 return;
1827
1828 dev_priv->display.disable_fbc(dev);
Chris Wilson016b9b62011-07-08 12:22:43 +01001829 dev_priv->cfb_plane = -1;
Adam Jacksonee5382a2010-04-23 11:17:39 -04001830}
1831
Jesse Barnes80824002009-09-10 15:28:06 -07001832/**
1833 * intel_update_fbc - enable/disable FBC as needed
Chris Wilsonbed4a672010-09-11 10:47:47 +01001834 * @dev: the drm_device
Jesse Barnes80824002009-09-10 15:28:06 -07001835 *
1836 * Set up the framebuffer compression hardware at mode set time. We
1837 * enable it if possible:
1838 * - plane A only (on pre-965)
1839 * - no pixel mulitply/line duplication
1840 * - no alpha buffer discard
1841 * - no dual wide
1842 * - framebuffer <= 2048 in width, 1536 in height
1843 *
1844 * We can't assume that any compression will take place (worst case),
1845 * so the compressed buffer has to be the same size as the uncompressed
1846 * one. It also must reside (along with the line length buffer) in
1847 * stolen memory.
1848 *
1849 * We need to enable/disable FBC on a global basis.
1850 */
Chris Wilsonbed4a672010-09-11 10:47:47 +01001851static void intel_update_fbc(struct drm_device *dev)
Jesse Barnes80824002009-09-10 15:28:06 -07001852{
Jesse Barnes80824002009-09-10 15:28:06 -07001853 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonbed4a672010-09-11 10:47:47 +01001854 struct drm_crtc *crtc = NULL, *tmp_crtc;
1855 struct intel_crtc *intel_crtc;
1856 struct drm_framebuffer *fb;
Jesse Barnes80824002009-09-10 15:28:06 -07001857 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00001858 struct drm_i915_gem_object *obj;
Keith Packardcd0de032011-09-19 21:34:19 -07001859 int enable_fbc;
Jesse Barnes9c928d12010-07-23 15:20:00 -07001860
1861 DRM_DEBUG_KMS("\n");
Jesse Barnes80824002009-09-10 15:28:06 -07001862
1863 if (!i915_powersave)
1864 return;
1865
Adam Jacksonee5382a2010-04-23 11:17:39 -04001866 if (!I915_HAS_FBC(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07001867 return;
1868
Jesse Barnes80824002009-09-10 15:28:06 -07001869 /*
1870 * If FBC is already on, we just have to verify that we can
1871 * keep it that way...
1872 * Need to disable if:
Jesse Barnes9c928d12010-07-23 15:20:00 -07001873 * - more than one pipe is active
Jesse Barnes80824002009-09-10 15:28:06 -07001874 * - changing FBC params (stride, fence, mode)
1875 * - new fb is too large to fit in compressed buffer
1876 * - going to an unsupported config (interlace, pixel multiply, etc.)
1877 */
Jesse Barnes9c928d12010-07-23 15:20:00 -07001878 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
Chris Wilsond2102462011-01-24 17:43:27 +00001879 if (tmp_crtc->enabled && tmp_crtc->fb) {
Chris Wilsonbed4a672010-09-11 10:47:47 +01001880 if (crtc) {
1881 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1882 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1883 goto out_disable;
1884 }
1885 crtc = tmp_crtc;
1886 }
Jesse Barnes9c928d12010-07-23 15:20:00 -07001887 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01001888
1889 if (!crtc || crtc->fb == NULL) {
1890 DRM_DEBUG_KMS("no output, disabling\n");
1891 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
Jesse Barnes9c928d12010-07-23 15:20:00 -07001892 goto out_disable;
1893 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01001894
1895 intel_crtc = to_intel_crtc(crtc);
1896 fb = crtc->fb;
1897 intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00001898 obj = intel_fb->obj;
Chris Wilsonbed4a672010-09-11 10:47:47 +01001899
Keith Packardcd0de032011-09-19 21:34:19 -07001900 enable_fbc = i915_enable_fbc;
1901 if (enable_fbc < 0) {
1902 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1903 enable_fbc = 1;
1904 if (INTEL_INFO(dev)->gen <= 5)
1905 enable_fbc = 0;
1906 }
1907 if (!enable_fbc) {
1908 DRM_DEBUG_KMS("fbc disabled per module param\n");
Jesse Barnesc1a9f042011-05-05 15:24:21 -07001909 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1910 goto out_disable;
1911 }
Chris Wilson05394f32010-11-08 19:18:58 +00001912 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001913 DRM_DEBUG_KMS("framebuffer too large, disabling "
Chris Wilson5eddb702010-09-11 13:48:45 +01001914 "compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001915 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
Jesse Barnes80824002009-09-10 15:28:06 -07001916 goto out_disable;
1917 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01001918 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1919 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001920 DRM_DEBUG_KMS("mode incompatible with compression, "
Chris Wilson5eddb702010-09-11 13:48:45 +01001921 "disabling\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001922 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
Jesse Barnes80824002009-09-10 15:28:06 -07001923 goto out_disable;
1924 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01001925 if ((crtc->mode.hdisplay > 2048) ||
1926 (crtc->mode.vdisplay > 1536)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001927 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001928 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
Jesse Barnes80824002009-09-10 15:28:06 -07001929 goto out_disable;
1930 }
Chris Wilsonbed4a672010-09-11 10:47:47 +01001931 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
Zhao Yakui28c97732009-10-09 11:39:41 +08001932 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001933 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
Jesse Barnes80824002009-09-10 15:28:06 -07001934 goto out_disable;
1935 }
Chris Wilsonde568512011-07-08 12:22:39 +01001936
1937 /* The use of a CPU fence is mandatory in order to detect writes
1938 * by the CPU to the scanout and trigger updates to the FBC.
1939 */
1940 if (obj->tiling_mode != I915_TILING_X ||
1941 obj->fence_reg == I915_FENCE_REG_NONE) {
1942 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001943 dev_priv->no_fbc_reason = FBC_NOT_TILED;
Jesse Barnes80824002009-09-10 15:28:06 -07001944 goto out_disable;
1945 }
1946
Jason Wesselc924b932010-08-05 09:22:32 -05001947 /* If the kernel debugger is active, always disable compression */
1948 if (in_dbg_master())
1949 goto out_disable;
1950
Chris Wilson016b9b62011-07-08 12:22:43 +01001951 /* If the scanout has not changed, don't modify the FBC settings.
1952 * Note that we make the fundamental assumption that the fb->obj
1953 * cannot be unpinned (and have its GTT offset and fence revoked)
1954 * without first being decoupled from the scanout and FBC disabled.
1955 */
1956 if (dev_priv->cfb_plane == intel_crtc->plane &&
1957 dev_priv->cfb_fb == fb->base.id &&
1958 dev_priv->cfb_y == crtc->y)
1959 return;
1960
1961 if (intel_fbc_enabled(dev)) {
1962 /* We update FBC along two paths, after changing fb/crtc
1963 * configuration (modeswitching) and after page-flipping
1964 * finishes. For the latter, we know that not only did
1965 * we disable the FBC at the start of the page-flip
1966 * sequence, but also more than one vblank has passed.
1967 *
1968 * For the former case of modeswitching, it is possible
1969 * to switch between two FBC valid configurations
1970 * instantaneously so we do need to disable the FBC
1971 * before we can modify its control registers. We also
1972 * have to wait for the next vblank for that to take
1973 * effect. However, since we delay enabling FBC we can
1974 * assume that a vblank has passed since disabling and
1975 * that we can safely alter the registers in the deferred
1976 * callback.
1977 *
1978 * In the scenario that we go from a valid to invalid
1979 * and then back to valid FBC configuration we have
1980 * no strict enforcement that a vblank occurred since
1981 * disabling the FBC. However, along all current pipe
1982 * disabling paths we do need to wait for a vblank at
1983 * some point. And we wait before enabling FBC anyway.
1984 */
1985 DRM_DEBUG_KMS("disabling active FBC for update\n");
1986 intel_disable_fbc(dev);
1987 }
1988
Chris Wilsonbed4a672010-09-11 10:47:47 +01001989 intel_enable_fbc(crtc, 500);
Jesse Barnes80824002009-09-10 15:28:06 -07001990 return;
1991
1992out_disable:
Jesse Barnes80824002009-09-10 15:28:06 -07001993 /* Multiple disables should be harmless */
Chris Wilsona9394062010-05-27 13:18:16 +01001994 if (intel_fbc_enabled(dev)) {
1995 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
Adam Jacksonee5382a2010-04-23 11:17:39 -04001996 intel_disable_fbc(dev);
Chris Wilsona9394062010-05-27 13:18:16 +01001997 }
Jesse Barnes80824002009-09-10 15:28:06 -07001998}
1999
Chris Wilson127bd2a2010-07-23 23:32:05 +01002000int
Chris Wilson48b956c2010-09-14 12:50:34 +01002001intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00002002 struct drm_i915_gem_object *obj,
Chris Wilson919926a2010-11-12 13:42:53 +00002003 struct intel_ring_buffer *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002004{
Chris Wilsonce453d82011-02-21 14:43:56 +00002005 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002006 u32 alignment;
2007 int ret;
2008
Chris Wilson05394f32010-11-08 19:18:58 +00002009 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002010 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01002011 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2012 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002013 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01002014 alignment = 4 * 1024;
2015 else
2016 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002017 break;
2018 case I915_TILING_X:
2019 /* pin() will align the object as required by fence */
2020 alignment = 0;
2021 break;
2022 case I915_TILING_Y:
2023 /* FIXME: Is this true? */
2024 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2025 return -EINVAL;
2026 default:
2027 BUG();
2028 }
2029
Chris Wilsonce453d82011-02-21 14:43:56 +00002030 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01002031 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01002032 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00002033 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002034
2035 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2036 * fence, whereas 965+ only requires a fence if using
2037 * framebuffer compression. For simplicity, we always install
2038 * a fence as the cost is not that onerous.
2039 */
Chris Wilson05394f32010-11-08 19:18:58 +00002040 if (obj->tiling_mode != I915_TILING_NONE) {
Chris Wilsonce453d82011-02-21 14:43:56 +00002041 ret = i915_gem_object_get_fence(obj, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01002042 if (ret)
2043 goto err_unpin;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002044 }
2045
Chris Wilsonce453d82011-02-21 14:43:56 +00002046 dev_priv->mm.interruptible = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002047 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01002048
2049err_unpin:
2050 i915_gem_object_unpin(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00002051err_interruptible:
2052 dev_priv->mm.interruptible = true;
Chris Wilson48b956c2010-09-14 12:50:34 +01002053 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002054}
2055
Jesse Barnes17638cd2011-06-24 12:19:23 -07002056static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2057 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07002058{
2059 struct drm_device *dev = crtc->dev;
2060 struct drm_i915_private *dev_priv = dev->dev_private;
2061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2062 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00002063 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002064 int plane = intel_crtc->plane;
2065 unsigned long Start, Offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002066 u32 dspcntr;
Chris Wilson5eddb702010-09-11 13:48:45 +01002067 u32 reg;
Jesse Barnes81255562010-08-02 12:07:50 -07002068
2069 switch (plane) {
2070 case 0:
2071 case 1:
2072 break;
2073 default:
2074 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2075 return -EINVAL;
2076 }
2077
2078 intel_fb = to_intel_framebuffer(fb);
2079 obj = intel_fb->obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002080
Chris Wilson5eddb702010-09-11 13:48:45 +01002081 reg = DSPCNTR(plane);
2082 dspcntr = I915_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002083 /* Mask out pixel format bits in case we change it */
2084 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2085 switch (fb->bits_per_pixel) {
2086 case 8:
2087 dspcntr |= DISPPLANE_8BPP;
2088 break;
2089 case 16:
2090 if (fb->depth == 15)
2091 dspcntr |= DISPPLANE_15_16BPP;
2092 else
2093 dspcntr |= DISPPLANE_16BPP;
2094 break;
2095 case 24:
2096 case 32:
2097 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2098 break;
2099 default:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002100 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
Jesse Barnes81255562010-08-02 12:07:50 -07002101 return -EINVAL;
2102 }
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002103 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson05394f32010-11-08 19:18:58 +00002104 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes81255562010-08-02 12:07:50 -07002105 dspcntr |= DISPPLANE_TILED;
2106 else
2107 dspcntr &= ~DISPPLANE_TILED;
2108 }
2109
Chris Wilson5eddb702010-09-11 13:48:45 +01002110 I915_WRITE(reg, dspcntr);
Jesse Barnes81255562010-08-02 12:07:50 -07002111
Chris Wilson05394f32010-11-08 19:18:58 +00002112 Start = obj->gtt_offset;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002113 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Jesse Barnes81255562010-08-02 12:07:50 -07002114
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002115 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002116 Start, Offset, x, y, fb->pitches[0]);
2117 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002118 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002119 I915_WRITE(DSPSURF(plane), Start);
2120 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2121 I915_WRITE(DSPADDR(plane), Offset);
2122 } else
2123 I915_WRITE(DSPADDR(plane), Start + Offset);
2124 POSTING_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002125
Jesse Barnes17638cd2011-06-24 12:19:23 -07002126 return 0;
2127}
2128
2129static int ironlake_update_plane(struct drm_crtc *crtc,
2130 struct drm_framebuffer *fb, int x, int y)
2131{
2132 struct drm_device *dev = crtc->dev;
2133 struct drm_i915_private *dev_priv = dev->dev_private;
2134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2135 struct intel_framebuffer *intel_fb;
2136 struct drm_i915_gem_object *obj;
2137 int plane = intel_crtc->plane;
2138 unsigned long Start, Offset;
2139 u32 dspcntr;
2140 u32 reg;
2141
2142 switch (plane) {
2143 case 0:
2144 case 1:
Jesse Barnes27f82272011-09-02 12:54:37 -07002145 case 2:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002146 break;
2147 default:
2148 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2149 return -EINVAL;
2150 }
2151
2152 intel_fb = to_intel_framebuffer(fb);
2153 obj = intel_fb->obj;
2154
2155 reg = DSPCNTR(plane);
2156 dspcntr = I915_READ(reg);
2157 /* Mask out pixel format bits in case we change it */
2158 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2159 switch (fb->bits_per_pixel) {
2160 case 8:
2161 dspcntr |= DISPPLANE_8BPP;
2162 break;
2163 case 16:
2164 if (fb->depth != 16)
2165 return -EINVAL;
2166
2167 dspcntr |= DISPPLANE_16BPP;
2168 break;
2169 case 24:
2170 case 32:
2171 if (fb->depth == 24)
2172 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2173 else if (fb->depth == 30)
2174 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2175 else
2176 return -EINVAL;
2177 break;
2178 default:
2179 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2180 return -EINVAL;
2181 }
2182
2183 if (obj->tiling_mode != I915_TILING_NONE)
2184 dspcntr |= DISPPLANE_TILED;
2185 else
2186 dspcntr &= ~DISPPLANE_TILED;
2187
2188 /* must disable */
2189 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2190
2191 I915_WRITE(reg, dspcntr);
2192
2193 Start = obj->gtt_offset;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002194 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002195
2196 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002197 Start, Offset, x, y, fb->pitches[0]);
2198 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002199 I915_WRITE(DSPSURF(plane), Start);
2200 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2201 I915_WRITE(DSPADDR(plane), Offset);
2202 POSTING_READ(reg);
2203
2204 return 0;
2205}
2206
2207/* Assume fb object is pinned & idle & fenced and just update base pointers */
2208static int
2209intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2210 int x, int y, enum mode_set_atomic state)
2211{
2212 struct drm_device *dev = crtc->dev;
2213 struct drm_i915_private *dev_priv = dev->dev_private;
2214 int ret;
2215
2216 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2217 if (ret)
2218 return ret;
2219
Chris Wilsonbed4a672010-09-11 10:47:47 +01002220 intel_update_fbc(dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +02002221 intel_increase_pllclock(crtc);
Jesse Barnes81255562010-08-02 12:07:50 -07002222
2223 return 0;
2224}
2225
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002226static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002227intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2228 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002229{
2230 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08002231 struct drm_i915_master_private *master_priv;
2232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002233 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002234
2235 /* no fb bound */
2236 if (!crtc->fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002237 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002238 return 0;
2239 }
2240
Chris Wilson265db952010-09-20 15:41:01 +01002241 switch (intel_crtc->plane) {
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002242 case 0:
2243 case 1:
2244 break;
Jesse Barnes27f82272011-09-02 12:54:37 -07002245 case 2:
2246 if (IS_IVYBRIDGE(dev))
2247 break;
2248 /* fall through otherwise */
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002249 default:
Jesse Barnesa5071c22011-07-19 15:38:56 -07002250 DRM_ERROR("no plane for crtc\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002251 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002252 }
2253
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002254 mutex_lock(&dev->struct_mutex);
Chris Wilson265db952010-09-20 15:41:01 +01002255 ret = intel_pin_and_fence_fb_obj(dev,
2256 to_intel_framebuffer(crtc->fb)->obj,
Chris Wilson919926a2010-11-12 13:42:53 +00002257 NULL);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002258 if (ret != 0) {
2259 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002260 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002261 return ret;
2262 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002263
Chris Wilson265db952010-09-20 15:41:01 +01002264 if (old_fb) {
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002265 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson05394f32010-11-08 19:18:58 +00002266 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
Chris Wilson265db952010-09-20 15:41:01 +01002267
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002268 wait_event(dev_priv->pending_flip_queue,
Chris Wilson01eec722011-02-11 20:47:45 +00002269 atomic_read(&dev_priv->mm.wedged) ||
Chris Wilson05394f32010-11-08 19:18:58 +00002270 atomic_read(&obj->pending_flip) == 0);
Chris Wilson85345512010-11-13 09:49:11 +00002271
2272 /* Big Hammer, we also need to ensure that any pending
2273 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2274 * current scanout is retired before unpinning the old
2275 * framebuffer.
Chris Wilson01eec722011-02-11 20:47:45 +00002276 *
2277 * This should only fail upon a hung GPU, in which case we
2278 * can safely continue.
Chris Wilson85345512010-11-13 09:49:11 +00002279 */
Chris Wilsona8198ee2011-04-13 22:04:09 +01002280 ret = i915_gem_object_finish_gpu(obj);
Chris Wilson01eec722011-02-11 20:47:45 +00002281 (void) ret;
Chris Wilson265db952010-09-20 15:41:01 +01002282 }
2283
Jason Wessel21c74a82010-10-13 14:09:44 -05002284 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2285 LEAVE_ATOMIC_MODE_SET);
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002286 if (ret) {
Chris Wilson265db952010-09-20 15:41:01 +01002287 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002288 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002289 DRM_ERROR("failed to update base address\n");
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002290 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002291 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002292
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002293 if (old_fb) {
2294 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson265db952010-09-20 15:41:01 +01002295 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002296 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002297
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002298 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002299
2300 if (!dev->primary->master)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002301 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002302
2303 master_priv = dev->primary->master->driver_priv;
2304 if (!master_priv->sarea_priv)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002305 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002306
Chris Wilson265db952010-09-20 15:41:01 +01002307 if (intel_crtc->pipe) {
Jesse Barnes79e53942008-11-07 14:24:08 -08002308 master_priv->sarea_priv->pipeB_x = x;
2309 master_priv->sarea_priv->pipeB_y = y;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002310 } else {
2311 master_priv->sarea_priv->pipeA_x = x;
2312 master_priv->sarea_priv->pipeA_y = y;
Jesse Barnes79e53942008-11-07 14:24:08 -08002313 }
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002314
2315 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002316}
2317
Chris Wilson5eddb702010-09-11 13:48:45 +01002318static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002319{
2320 struct drm_device *dev = crtc->dev;
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322 u32 dpa_ctl;
2323
Zhao Yakui28c97732009-10-09 11:39:41 +08002324 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002325 dpa_ctl = I915_READ(DP_A);
2326 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2327
2328 if (clock < 200000) {
2329 u32 temp;
2330 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2331 /* workaround for 160Mhz:
2332 1) program 0x4600c bits 15:0 = 0x8124
2333 2) program 0x46010 bit 0 = 1
2334 3) program 0x46034 bit 24 = 1
2335 4) program 0x64000 bit 14 = 1
2336 */
2337 temp = I915_READ(0x4600c);
2338 temp &= 0xffff0000;
2339 I915_WRITE(0x4600c, temp | 0x8124);
2340
2341 temp = I915_READ(0x46010);
2342 I915_WRITE(0x46010, temp | 1);
2343
2344 temp = I915_READ(0x46034);
2345 I915_WRITE(0x46034, temp | (1 << 24));
2346 } else {
2347 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2348 }
2349 I915_WRITE(DP_A, dpa_ctl);
2350
Chris Wilson5eddb702010-09-11 13:48:45 +01002351 POSTING_READ(DP_A);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002352 udelay(500);
2353}
2354
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002355static void intel_fdi_normal_train(struct drm_crtc *crtc)
2356{
2357 struct drm_device *dev = crtc->dev;
2358 struct drm_i915_private *dev_priv = dev->dev_private;
2359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2360 int pipe = intel_crtc->pipe;
2361 u32 reg, temp;
2362
2363 /* enable normal train */
2364 reg = FDI_TX_CTL(pipe);
2365 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002366 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002367 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2368 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002369 } else {
2370 temp &= ~FDI_LINK_TRAIN_NONE;
2371 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002372 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002373 I915_WRITE(reg, temp);
2374
2375 reg = FDI_RX_CTL(pipe);
2376 temp = I915_READ(reg);
2377 if (HAS_PCH_CPT(dev)) {
2378 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2379 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2380 } else {
2381 temp &= ~FDI_LINK_TRAIN_NONE;
2382 temp |= FDI_LINK_TRAIN_NONE;
2383 }
2384 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2385
2386 /* wait one idle pattern time */
2387 POSTING_READ(reg);
2388 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002389
2390 /* IVB wants error correction enabled */
2391 if (IS_IVYBRIDGE(dev))
2392 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2393 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002394}
2395
Jesse Barnes291427f2011-07-29 12:42:37 -07002396static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2397{
2398 struct drm_i915_private *dev_priv = dev->dev_private;
2399 u32 flags = I915_READ(SOUTH_CHICKEN1);
2400
2401 flags |= FDI_PHASE_SYNC_OVR(pipe);
2402 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2403 flags |= FDI_PHASE_SYNC_EN(pipe);
2404 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2405 POSTING_READ(SOUTH_CHICKEN1);
2406}
2407
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002408/* The FDI link training functions for ILK/Ibexpeak. */
2409static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2410{
2411 struct drm_device *dev = crtc->dev;
2412 struct drm_i915_private *dev_priv = dev->dev_private;
2413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2414 int pipe = intel_crtc->pipe;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002415 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01002416 u32 reg, temp, tries;
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002417
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002418 /* FDI needs bits from pipe & plane first */
2419 assert_pipe_enabled(dev_priv, pipe);
2420 assert_plane_enabled(dev_priv, plane);
2421
Adam Jacksone1a44742010-06-25 15:32:14 -04002422 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2423 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002424 reg = FDI_RX_IMR(pipe);
2425 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002426 temp &= ~FDI_RX_SYMBOL_LOCK;
2427 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002428 I915_WRITE(reg, temp);
2429 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002430 udelay(150);
2431
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002432 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002433 reg = FDI_TX_CTL(pipe);
2434 temp = I915_READ(reg);
Adam Jackson77ffb592010-04-12 11:38:44 -04002435 temp &= ~(7 << 19);
2436 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002437 temp &= ~FDI_LINK_TRAIN_NONE;
2438 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002439 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002440
Chris Wilson5eddb702010-09-11 13:48:45 +01002441 reg = FDI_RX_CTL(pipe);
2442 temp = I915_READ(reg);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002443 temp &= ~FDI_LINK_TRAIN_NONE;
2444 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002445 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2446
2447 POSTING_READ(reg);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002448 udelay(150);
2449
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002450 /* Ironlake workaround, enable clock pointer after FDI enable*/
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002451 if (HAS_PCH_IBX(dev)) {
2452 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2453 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2454 FDI_RX_PHASE_SYNC_POINTER_EN);
2455 }
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002456
Chris Wilson5eddb702010-09-11 13:48:45 +01002457 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002458 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002459 temp = I915_READ(reg);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002460 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2461
2462 if ((temp & FDI_RX_BIT_LOCK)) {
2463 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002464 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002465 break;
2466 }
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002467 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002468 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002469 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002470
2471 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002472 reg = FDI_TX_CTL(pipe);
2473 temp = I915_READ(reg);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002474 temp &= ~FDI_LINK_TRAIN_NONE;
2475 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002476 I915_WRITE(reg, temp);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002477
Chris Wilson5eddb702010-09-11 13:48:45 +01002478 reg = FDI_RX_CTL(pipe);
2479 temp = I915_READ(reg);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002480 temp &= ~FDI_LINK_TRAIN_NONE;
2481 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002482 I915_WRITE(reg, temp);
2483
2484 POSTING_READ(reg);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002485 udelay(150);
2486
Chris Wilson5eddb702010-09-11 13:48:45 +01002487 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002488 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002489 temp = I915_READ(reg);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002490 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2491
2492 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002493 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002494 DRM_DEBUG_KMS("FDI train 2 done.\n");
2495 break;
2496 }
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002497 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002498 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002499 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002500
2501 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002502
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002503}
2504
Akshay Joshi0206e352011-08-16 15:34:10 -04002505static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002506 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2507 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2508 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2509 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2510};
2511
2512/* The FDI link training functions for SNB/Cougarpoint. */
2513static void gen6_fdi_link_train(struct drm_crtc *crtc)
2514{
2515 struct drm_device *dev = crtc->dev;
2516 struct drm_i915_private *dev_priv = dev->dev_private;
2517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2518 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002519 u32 reg, temp, i;
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002520
Adam Jacksone1a44742010-06-25 15:32:14 -04002521 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2522 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002523 reg = FDI_RX_IMR(pipe);
2524 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002525 temp &= ~FDI_RX_SYMBOL_LOCK;
2526 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002527 I915_WRITE(reg, temp);
2528
2529 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002530 udelay(150);
2531
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002532 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002533 reg = FDI_TX_CTL(pipe);
2534 temp = I915_READ(reg);
Adam Jackson77ffb592010-04-12 11:38:44 -04002535 temp &= ~(7 << 19);
2536 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002537 temp &= ~FDI_LINK_TRAIN_NONE;
2538 temp |= FDI_LINK_TRAIN_PATTERN_1;
2539 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2540 /* SNB-B */
2541 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01002542 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002543
Chris Wilson5eddb702010-09-11 13:48:45 +01002544 reg = FDI_RX_CTL(pipe);
2545 temp = I915_READ(reg);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002546 if (HAS_PCH_CPT(dev)) {
2547 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2548 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2549 } else {
2550 temp &= ~FDI_LINK_TRAIN_NONE;
2551 temp |= FDI_LINK_TRAIN_PATTERN_1;
2552 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002553 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2554
2555 POSTING_READ(reg);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002556 udelay(150);
2557
Jesse Barnes291427f2011-07-29 12:42:37 -07002558 if (HAS_PCH_CPT(dev))
2559 cpt_phase_pointer_enable(dev, pipe);
2560
Akshay Joshi0206e352011-08-16 15:34:10 -04002561 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002562 reg = FDI_TX_CTL(pipe);
2563 temp = I915_READ(reg);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002564 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2565 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002566 I915_WRITE(reg, temp);
2567
2568 POSTING_READ(reg);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002569 udelay(500);
2570
Chris Wilson5eddb702010-09-11 13:48:45 +01002571 reg = FDI_RX_IIR(pipe);
2572 temp = I915_READ(reg);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002573 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2574
2575 if (temp & FDI_RX_BIT_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002576 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002577 DRM_DEBUG_KMS("FDI train 1 done.\n");
2578 break;
2579 }
2580 }
2581 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002582 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002583
2584 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002585 reg = FDI_TX_CTL(pipe);
2586 temp = I915_READ(reg);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002587 temp &= ~FDI_LINK_TRAIN_NONE;
2588 temp |= FDI_LINK_TRAIN_PATTERN_2;
2589 if (IS_GEN6(dev)) {
2590 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2591 /* SNB-B */
2592 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2593 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002594 I915_WRITE(reg, temp);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002595
Chris Wilson5eddb702010-09-11 13:48:45 +01002596 reg = FDI_RX_CTL(pipe);
2597 temp = I915_READ(reg);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002598 if (HAS_PCH_CPT(dev)) {
2599 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2600 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2601 } else {
2602 temp &= ~FDI_LINK_TRAIN_NONE;
2603 temp |= FDI_LINK_TRAIN_PATTERN_2;
2604 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002605 I915_WRITE(reg, temp);
2606
2607 POSTING_READ(reg);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002608 udelay(150);
2609
Akshay Joshi0206e352011-08-16 15:34:10 -04002610 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002613 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2614 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002615 I915_WRITE(reg, temp);
2616
2617 POSTING_READ(reg);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002618 udelay(500);
2619
Chris Wilson5eddb702010-09-11 13:48:45 +01002620 reg = FDI_RX_IIR(pipe);
2621 temp = I915_READ(reg);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002622 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2623
2624 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002625 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002626 DRM_DEBUG_KMS("FDI train 2 done.\n");
2627 break;
2628 }
2629 }
2630 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002631 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08002632
2633 DRM_DEBUG_KMS("FDI train done.\n");
2634}
2635
Jesse Barnes357555c2011-04-28 15:09:55 -07002636/* Manual link training for Ivy Bridge A0 parts */
2637static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2638{
2639 struct drm_device *dev = crtc->dev;
2640 struct drm_i915_private *dev_priv = dev->dev_private;
2641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2642 int pipe = intel_crtc->pipe;
2643 u32 reg, temp, i;
2644
2645 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2646 for train result */
2647 reg = FDI_RX_IMR(pipe);
2648 temp = I915_READ(reg);
2649 temp &= ~FDI_RX_SYMBOL_LOCK;
2650 temp &= ~FDI_RX_BIT_LOCK;
2651 I915_WRITE(reg, temp);
2652
2653 POSTING_READ(reg);
2654 udelay(150);
2655
2656 /* enable CPU FDI TX and PCH FDI RX */
2657 reg = FDI_TX_CTL(pipe);
2658 temp = I915_READ(reg);
2659 temp &= ~(7 << 19);
2660 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2661 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2662 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2663 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2664 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07002665 temp |= FDI_COMPOSITE_SYNC;
Jesse Barnes357555c2011-04-28 15:09:55 -07002666 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2667
2668 reg = FDI_RX_CTL(pipe);
2669 temp = I915_READ(reg);
2670 temp &= ~FDI_LINK_TRAIN_AUTO;
2671 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2672 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07002673 temp |= FDI_COMPOSITE_SYNC;
Jesse Barnes357555c2011-04-28 15:09:55 -07002674 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2675
2676 POSTING_READ(reg);
2677 udelay(150);
2678
Jesse Barnes291427f2011-07-29 12:42:37 -07002679 if (HAS_PCH_CPT(dev))
2680 cpt_phase_pointer_enable(dev, pipe);
2681
Akshay Joshi0206e352011-08-16 15:34:10 -04002682 for (i = 0; i < 4; i++) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002683 reg = FDI_TX_CTL(pipe);
2684 temp = I915_READ(reg);
2685 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2686 temp |= snb_b_fdi_train_param[i];
2687 I915_WRITE(reg, temp);
2688
2689 POSTING_READ(reg);
2690 udelay(500);
2691
2692 reg = FDI_RX_IIR(pipe);
2693 temp = I915_READ(reg);
2694 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2695
2696 if (temp & FDI_RX_BIT_LOCK ||
2697 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2698 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2699 DRM_DEBUG_KMS("FDI train 1 done.\n");
2700 break;
2701 }
2702 }
2703 if (i == 4)
2704 DRM_ERROR("FDI train 1 fail!\n");
2705
2706 /* Train 2 */
2707 reg = FDI_TX_CTL(pipe);
2708 temp = I915_READ(reg);
2709 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2710 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2711 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2712 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2713 I915_WRITE(reg, temp);
2714
2715 reg = FDI_RX_CTL(pipe);
2716 temp = I915_READ(reg);
2717 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2718 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2719 I915_WRITE(reg, temp);
2720
2721 POSTING_READ(reg);
2722 udelay(150);
2723
Akshay Joshi0206e352011-08-16 15:34:10 -04002724 for (i = 0; i < 4; i++) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002725 reg = FDI_TX_CTL(pipe);
2726 temp = I915_READ(reg);
2727 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2728 temp |= snb_b_fdi_train_param[i];
2729 I915_WRITE(reg, temp);
2730
2731 POSTING_READ(reg);
2732 udelay(500);
2733
2734 reg = FDI_RX_IIR(pipe);
2735 temp = I915_READ(reg);
2736 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2737
2738 if (temp & FDI_RX_SYMBOL_LOCK) {
2739 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2740 DRM_DEBUG_KMS("FDI train 2 done.\n");
2741 break;
2742 }
2743 }
2744 if (i == 4)
2745 DRM_ERROR("FDI train 2 fail!\n");
2746
2747 DRM_DEBUG_KMS("FDI train done.\n");
2748}
2749
2750static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07002751{
2752 struct drm_device *dev = crtc->dev;
2753 struct drm_i915_private *dev_priv = dev->dev_private;
2754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2755 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002756 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002757
Jesse Barnesc64e3112010-09-10 11:27:03 -07002758 /* Write the TU size bits so error detection works */
Chris Wilson5eddb702010-09-11 13:48:45 +01002759 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2760 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
Jesse Barnesc64e3112010-09-10 11:27:03 -07002761
Jesse Barnes0e23b992010-09-10 11:10:00 -07002762 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01002763 reg = FDI_RX_CTL(pipe);
2764 temp = I915_READ(reg);
2765 temp &= ~((0x7 << 19) | (0x7 << 16));
Jesse Barnes0e23b992010-09-10 11:10:00 -07002766 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Chris Wilson5eddb702010-09-11 13:48:45 +01002767 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2768 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2769
2770 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002771 udelay(200);
2772
2773 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01002774 temp = I915_READ(reg);
2775 I915_WRITE(reg, temp | FDI_PCDCLK);
2776
2777 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002778 udelay(200);
2779
2780 /* Enable CPU FDI TX PLL, always on for Ironlake */
Chris Wilson5eddb702010-09-11 13:48:45 +01002781 reg = FDI_TX_CTL(pipe);
2782 temp = I915_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002783 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002784 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2785
2786 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002787 udelay(100);
2788 }
2789}
2790
Jesse Barnes291427f2011-07-29 12:42:37 -07002791static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2792{
2793 struct drm_i915_private *dev_priv = dev->dev_private;
2794 u32 flags = I915_READ(SOUTH_CHICKEN1);
2795
2796 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2797 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2798 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2799 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2800 POSTING_READ(SOUTH_CHICKEN1);
2801}
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002802static void ironlake_fdi_disable(struct drm_crtc *crtc)
2803{
2804 struct drm_device *dev = crtc->dev;
2805 struct drm_i915_private *dev_priv = dev->dev_private;
2806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2807 int pipe = intel_crtc->pipe;
2808 u32 reg, temp;
2809
2810 /* disable CPU FDI tx and PCH FDI rx */
2811 reg = FDI_TX_CTL(pipe);
2812 temp = I915_READ(reg);
2813 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2814 POSTING_READ(reg);
2815
2816 reg = FDI_RX_CTL(pipe);
2817 temp = I915_READ(reg);
2818 temp &= ~(0x7 << 16);
2819 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2820 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2821
2822 POSTING_READ(reg);
2823 udelay(100);
2824
2825 /* Ironlake workaround, disable clock pointer after downing FDI */
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002826 if (HAS_PCH_IBX(dev)) {
2827 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002828 I915_WRITE(FDI_RX_CHICKEN(pipe),
2829 I915_READ(FDI_RX_CHICKEN(pipe) &
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002830 ~FDI_RX_PHASE_SYNC_POINTER_EN));
Jesse Barnes291427f2011-07-29 12:42:37 -07002831 } else if (HAS_PCH_CPT(dev)) {
2832 cpt_phase_pointer_disable(dev, pipe);
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002833 }
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002834
2835 /* still set train pattern 1 */
2836 reg = FDI_TX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 temp &= ~FDI_LINK_TRAIN_NONE;
2839 temp |= FDI_LINK_TRAIN_PATTERN_1;
2840 I915_WRITE(reg, temp);
2841
2842 reg = FDI_RX_CTL(pipe);
2843 temp = I915_READ(reg);
2844 if (HAS_PCH_CPT(dev)) {
2845 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2846 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2847 } else {
2848 temp &= ~FDI_LINK_TRAIN_NONE;
2849 temp |= FDI_LINK_TRAIN_PATTERN_1;
2850 }
2851 /* BPC in FDI rx is consistent with that in PIPECONF */
2852 temp &= ~(0x07 << 16);
2853 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2854 I915_WRITE(reg, temp);
2855
2856 POSTING_READ(reg);
2857 udelay(100);
2858}
2859
Chris Wilson6b383a72010-09-13 13:54:26 +01002860/*
2861 * When we disable a pipe, we need to clear any pending scanline wait events
2862 * to avoid hanging the ring, which we assume we are waiting on.
2863 */
2864static void intel_clear_scanline_wait(struct drm_device *dev)
2865{
2866 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson8168bd42010-11-11 17:54:52 +00002867 struct intel_ring_buffer *ring;
Chris Wilson6b383a72010-09-13 13:54:26 +01002868 u32 tmp;
2869
2870 if (IS_GEN2(dev))
2871 /* Can't break the hang on i8xx */
2872 return;
2873
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002874 ring = LP_RING(dev_priv);
Chris Wilson8168bd42010-11-11 17:54:52 +00002875 tmp = I915_READ_CTL(ring);
2876 if (tmp & RING_WAIT)
2877 I915_WRITE_CTL(ring, tmp);
Chris Wilson6b383a72010-09-13 13:54:26 +01002878}
2879
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002880static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2881{
Chris Wilson05394f32010-11-08 19:18:58 +00002882 struct drm_i915_gem_object *obj;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002883 struct drm_i915_private *dev_priv;
2884
2885 if (crtc->fb == NULL)
2886 return;
2887
Chris Wilson05394f32010-11-08 19:18:58 +00002888 obj = to_intel_framebuffer(crtc->fb)->obj;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002889 dev_priv = crtc->dev->dev_private;
2890 wait_event(dev_priv->pending_flip_queue,
Chris Wilson05394f32010-11-08 19:18:58 +00002891 atomic_read(&obj->pending_flip) == 0);
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002892}
2893
Jesse Barnes040484a2011-01-03 12:14:26 -08002894static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2895{
2896 struct drm_device *dev = crtc->dev;
2897 struct drm_mode_config *mode_config = &dev->mode_config;
2898 struct intel_encoder *encoder;
2899
2900 /*
2901 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2902 * must be driven by its own crtc; no sharing is possible.
2903 */
2904 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2905 if (encoder->base.crtc != crtc)
2906 continue;
2907
2908 switch (encoder->type) {
2909 case INTEL_OUTPUT_EDP:
2910 if (!intel_encoder_is_pch_edp(&encoder->base))
2911 return false;
2912 continue;
2913 }
2914 }
2915
2916 return true;
2917}
2918
Jesse Barnesf67a5592011-01-05 10:31:48 -08002919/*
2920 * Enable PCH resources required for PCH ports:
2921 * - PCH PLLs
2922 * - FDI training & RX/TX
2923 * - update transcoder timings
2924 * - DP transcoding bits
2925 * - transcoder
2926 */
2927static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08002928{
2929 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002930 struct drm_i915_private *dev_priv = dev->dev_private;
2931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2932 int pipe = intel_crtc->pipe;
Jesse Barnes4b645f12011-10-12 09:51:31 -07002933 u32 reg, temp, transc_sel;
Jesse Barnes6be4a602010-09-10 10:26:01 -07002934
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002935 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07002936 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002937
Jesse Barnes92f25842011-01-04 15:09:34 -08002938 intel_enable_pch_pll(dev_priv, pipe);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002939
2940 if (HAS_PCH_CPT(dev)) {
Jesse Barnes4b645f12011-10-12 09:51:31 -07002941 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2942 TRANSC_DPLLB_SEL;
2943
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002944 /* Be sure PCH DPLL SEL is set */
2945 temp = I915_READ(PCH_DPLL_SEL);
Jesse Barnesd64311a2011-10-12 15:01:33 -07002946 if (pipe == 0) {
2947 temp &= ~(TRANSA_DPLLB_SEL);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002948 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
Jesse Barnesd64311a2011-10-12 15:01:33 -07002949 } else if (pipe == 1) {
2950 temp &= ~(TRANSB_DPLLB_SEL);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002951 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
Jesse Barnesd64311a2011-10-12 15:01:33 -07002952 } else if (pipe == 2) {
2953 temp &= ~(TRANSC_DPLLB_SEL);
Jesse Barnes4b645f12011-10-12 09:51:31 -07002954 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
Jesse Barnesd64311a2011-10-12 15:01:33 -07002955 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002956 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002957 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002958
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08002959 /* set transcoder timing, panel must allow it */
2960 assert_panel_unlocked(dev_priv, pipe);
Chris Wilson5eddb702010-09-11 13:48:45 +01002961 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2962 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2963 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2964
2965 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2966 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2967 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002968
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002969 intel_fdi_normal_train(crtc);
2970
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002971 /* For PCH DP, enable TRANS_DP_CTL */
2972 if (HAS_PCH_CPT(dev) &&
Keith Packard417e8222011-11-01 19:54:11 -07002973 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2974 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Jesse Barnes9325c9f2011-06-24 12:19:21 -07002975 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01002976 reg = TRANS_DP_CTL(pipe);
2977 temp = I915_READ(reg);
2978 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08002979 TRANS_DP_SYNC_MASK |
2980 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01002981 temp |= (TRANS_DP_OUTPUT_ENABLE |
2982 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07002983 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002984
2985 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01002986 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002987 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01002988 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002989
2990 switch (intel_trans_dp_port_sel(crtc)) {
2991 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01002992 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002993 break;
2994 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01002995 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002996 break;
2997 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01002998 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002999 break;
3000 default:
3001 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01003002 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003003 break;
3004 }
3005
Chris Wilson5eddb702010-09-11 13:48:45 +01003006 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003007 }
3008
Jesse Barnes040484a2011-01-03 12:14:26 -08003009 intel_enable_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003010}
3011
Jesse Barnesd4270e52011-10-11 10:43:02 -07003012void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3013{
3014 struct drm_i915_private *dev_priv = dev->dev_private;
3015 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3016 u32 temp;
3017
3018 temp = I915_READ(dslreg);
3019 udelay(500);
3020 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3021 /* Without this, mode sets may fail silently on FDI */
3022 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3023 udelay(250);
3024 I915_WRITE(tc2reg, 0);
3025 if (wait_for(I915_READ(dslreg) != temp, 5))
3026 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3027 }
3028}
3029
Jesse Barnesf67a5592011-01-05 10:31:48 -08003030static void ironlake_crtc_enable(struct drm_crtc *crtc)
3031{
3032 struct drm_device *dev = crtc->dev;
3033 struct drm_i915_private *dev_priv = dev->dev_private;
3034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3035 int pipe = intel_crtc->pipe;
3036 int plane = intel_crtc->plane;
3037 u32 temp;
3038 bool is_pch_port;
3039
3040 if (intel_crtc->active)
3041 return;
3042
3043 intel_crtc->active = true;
3044 intel_update_watermarks(dev);
3045
3046 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3047 temp = I915_READ(PCH_LVDS);
3048 if ((temp & LVDS_PORT_EN) == 0)
3049 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3050 }
3051
3052 is_pch_port = intel_crtc_driving_pch(crtc);
3053
3054 if (is_pch_port)
Jesse Barnes357555c2011-04-28 15:09:55 -07003055 ironlake_fdi_pll_enable(crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003056 else
3057 ironlake_fdi_disable(crtc);
3058
3059 /* Enable panel fitting for LVDS */
3060 if (dev_priv->pch_pf_size &&
3061 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3062 /* Force use of hard-coded filter coefficients
3063 * as some pre-programmed values are broken,
3064 * e.g. x201.
3065 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003066 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3067 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3068 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003069 }
3070
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02003071 /*
3072 * On ILK+ LUT must be loaded before the pipe is running but with
3073 * clocks enabled
3074 */
3075 intel_crtc_load_lut(crtc);
3076
Jesse Barnesf67a5592011-01-05 10:31:48 -08003077 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3078 intel_enable_plane(dev_priv, plane, pipe);
3079
3080 if (is_pch_port)
3081 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003082
Ben Widawskyd1ebd812011-04-25 20:11:50 +01003083 mutex_lock(&dev->struct_mutex);
Chris Wilsonbed4a672010-09-11 10:47:47 +01003084 intel_update_fbc(dev);
Ben Widawskyd1ebd812011-04-25 20:11:50 +01003085 mutex_unlock(&dev->struct_mutex);
3086
Chris Wilson6b383a72010-09-13 13:54:26 +01003087 intel_crtc_update_cursor(crtc, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003088}
3089
3090static void ironlake_crtc_disable(struct drm_crtc *crtc)
3091{
3092 struct drm_device *dev = crtc->dev;
3093 struct drm_i915_private *dev_priv = dev->dev_private;
3094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3095 int pipe = intel_crtc->pipe;
3096 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01003097 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003098
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003099 if (!intel_crtc->active)
3100 return;
3101
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003102 intel_crtc_wait_for_pending_flips(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003103 drm_vblank_off(dev, pipe);
Chris Wilson6b383a72010-09-13 13:54:26 +01003104 intel_crtc_update_cursor(crtc, false);
Chris Wilson5eddb702010-09-11 13:48:45 +01003105
Jesse Barnesb24e7172011-01-04 15:09:30 -08003106 intel_disable_plane(dev_priv, plane, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003107
Chris Wilson973d04f2011-07-08 12:22:37 +01003108 if (dev_priv->cfb_plane == plane)
3109 intel_disable_fbc(dev);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003110
Jesse Barnesb24e7172011-01-04 15:09:30 -08003111 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003112
Jesse Barnes6be4a602010-09-10 10:26:01 -07003113 /* Disable PF */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003114 I915_WRITE(PF_CTL(pipe), 0);
3115 I915_WRITE(PF_WIN_SZ(pipe), 0);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003116
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003117 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003118
Jesse Barnes47a05ec2011-02-07 13:46:40 -08003119 /* This is a horrible layering violation; we should be doing this in
3120 * the connector/encoder ->prepare instead, but we don't always have
3121 * enough information there about the config to know whether it will
3122 * actually be necessary or just cause undesired flicker.
3123 */
3124 intel_disable_pch_ports(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003125
Jesse Barnes040484a2011-01-03 12:14:26 -08003126 intel_disable_transcoder(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003127
Jesse Barnes6be4a602010-09-10 10:26:01 -07003128 if (HAS_PCH_CPT(dev)) {
3129 /* disable TRANS_DP_CTL */
Chris Wilson5eddb702010-09-11 13:48:45 +01003130 reg = TRANS_DP_CTL(pipe);
3131 temp = I915_READ(reg);
3132 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
Eric Anholtcb3543c2011-02-02 12:08:07 -08003133 temp |= TRANS_DP_PORT_SEL_NONE;
Chris Wilson5eddb702010-09-11 13:48:45 +01003134 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003135
3136 /* disable DPLL_SEL */
3137 temp = I915_READ(PCH_DPLL_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003138 switch (pipe) {
3139 case 0:
Jesse Barnesd64311a2011-10-12 15:01:33 -07003140 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003141 break;
3142 case 1:
Jesse Barnes6be4a602010-09-10 10:26:01 -07003143 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003144 break;
3145 case 2:
Jesse Barnes4b645f12011-10-12 09:51:31 -07003146 /* C shares PLL A or B */
Jesse Barnesd64311a2011-10-12 15:01:33 -07003147 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003148 break;
3149 default:
3150 BUG(); /* wtf */
3151 }
Jesse Barnes6be4a602010-09-10 10:26:01 -07003152 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003153 }
3154
3155 /* disable PCH DPLL */
Jesse Barnes4b645f12011-10-12 09:51:31 -07003156 if (!intel_crtc->no_pll)
3157 intel_disable_pch_pll(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003158
3159 /* Switch from PCDclk to Rawclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01003160 reg = FDI_RX_CTL(pipe);
3161 temp = I915_READ(reg);
3162 I915_WRITE(reg, temp & ~FDI_PCDCLK);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003163
3164 /* Disable CPU FDI TX PLL */
Chris Wilson5eddb702010-09-11 13:48:45 +01003165 reg = FDI_TX_CTL(pipe);
3166 temp = I915_READ(reg);
3167 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3168
3169 POSTING_READ(reg);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003170 udelay(100);
3171
Chris Wilson5eddb702010-09-11 13:48:45 +01003172 reg = FDI_RX_CTL(pipe);
3173 temp = I915_READ(reg);
3174 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003175
3176 /* Wait for the clocks to turn off. */
Chris Wilson5eddb702010-09-11 13:48:45 +01003177 POSTING_READ(reg);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003178 udelay(100);
Chris Wilson6b383a72010-09-13 13:54:26 +01003179
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003180 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01003181 intel_update_watermarks(dev);
Ben Widawskyd1ebd812011-04-25 20:11:50 +01003182
3183 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01003184 intel_update_fbc(dev);
3185 intel_clear_scanline_wait(dev);
Ben Widawskyd1ebd812011-04-25 20:11:50 +01003186 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003187}
3188
3189static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3190{
3191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3192 int pipe = intel_crtc->pipe;
3193 int plane = intel_crtc->plane;
3194
Zhenyu Wang2c072452009-06-05 15:38:42 +08003195 /* XXX: When our outputs are all unaware of DPMS modes other than off
3196 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3197 */
3198 switch (mode) {
3199 case DRM_MODE_DPMS_ON:
3200 case DRM_MODE_DPMS_STANDBY:
3201 case DRM_MODE_DPMS_SUSPEND:
Chris Wilson868dc582010-08-07 11:01:31 +01003202 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003203 ironlake_crtc_enable(crtc);
Chris Wilson868dc582010-08-07 11:01:31 +01003204 break;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08003205
Zhenyu Wang2c072452009-06-05 15:38:42 +08003206 case DRM_MODE_DPMS_OFF:
Chris Wilson868dc582010-08-07 11:01:31 +01003207 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003208 ironlake_crtc_disable(crtc);
Zhenyu Wang2c072452009-06-05 15:38:42 +08003209 break;
3210 }
3211}
3212
Daniel Vetter02e792f2009-09-15 22:57:34 +02003213static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3214{
Daniel Vetter02e792f2009-09-15 22:57:34 +02003215 if (!enable && intel_crtc->overlay) {
Chris Wilson23f09ce2010-08-12 13:53:37 +01003216 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonce453d82011-02-21 14:43:56 +00003217 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter03f77ea2009-09-15 22:57:37 +02003218
Chris Wilson23f09ce2010-08-12 13:53:37 +01003219 mutex_lock(&dev->struct_mutex);
Chris Wilsonce453d82011-02-21 14:43:56 +00003220 dev_priv->mm.interruptible = false;
3221 (void) intel_overlay_switch_off(intel_crtc->overlay);
3222 dev_priv->mm.interruptible = true;
Chris Wilson23f09ce2010-08-12 13:53:37 +01003223 mutex_unlock(&dev->struct_mutex);
Daniel Vetter02e792f2009-09-15 22:57:34 +02003224 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02003225
Chris Wilson5dcdbcb2010-08-12 13:50:28 +01003226 /* Let userspace switch the overlay on again. In most cases userspace
3227 * has to recompute where to put it anyway.
3228 */
Daniel Vetter02e792f2009-09-15 22:57:34 +02003229}
3230
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003231static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003232{
3233 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08003234 struct drm_i915_private *dev_priv = dev->dev_private;
3235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3236 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07003237 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08003238
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003239 if (intel_crtc->active)
3240 return;
3241
3242 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01003243 intel_update_watermarks(dev);
3244
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08003245 intel_enable_pll(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08003246 intel_enable_pipe(dev_priv, pipe, false);
Jesse Barnesb24e7172011-01-04 15:09:30 -08003247 intel_enable_plane(dev_priv, plane, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003248
3249 intel_crtc_load_lut(crtc);
Chris Wilsonbed4a672010-09-11 10:47:47 +01003250 intel_update_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003251
3252 /* Give the overlay scaler a chance to enable if it's on this pipe */
3253 intel_crtc_dpms_overlay(intel_crtc, true);
Chris Wilson6b383a72010-09-13 13:54:26 +01003254 intel_crtc_update_cursor(crtc, true);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003255}
3256
3257static void i9xx_crtc_disable(struct drm_crtc *crtc)
3258{
3259 struct drm_device *dev = crtc->dev;
3260 struct drm_i915_private *dev_priv = dev->dev_private;
3261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3262 int pipe = intel_crtc->pipe;
3263 int plane = intel_crtc->plane;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003264
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003265 if (!intel_crtc->active)
3266 return;
3267
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003268 /* Give the overlay scaler a chance to disable if it's on this pipe */
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003269 intel_crtc_wait_for_pending_flips(crtc);
3270 drm_vblank_off(dev, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003271 intel_crtc_dpms_overlay(intel_crtc, false);
Chris Wilson6b383a72010-09-13 13:54:26 +01003272 intel_crtc_update_cursor(crtc, false);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003273
Chris Wilson973d04f2011-07-08 12:22:37 +01003274 if (dev_priv->cfb_plane == plane)
3275 intel_disable_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003276
Jesse Barnesb24e7172011-01-04 15:09:30 -08003277 intel_disable_plane(dev_priv, plane, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08003278 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08003279 intel_disable_pll(dev_priv, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003280
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003281 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01003282 intel_update_fbc(dev);
3283 intel_update_watermarks(dev);
3284 intel_clear_scanline_wait(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003285}
3286
3287static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3288{
Jesse Barnes79e53942008-11-07 14:24:08 -08003289 /* XXX: When our outputs are all unaware of DPMS modes other than off
3290 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3291 */
3292 switch (mode) {
3293 case DRM_MODE_DPMS_ON:
3294 case DRM_MODE_DPMS_STANDBY:
3295 case DRM_MODE_DPMS_SUSPEND:
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003296 i9xx_crtc_enable(crtc);
3297 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08003298 case DRM_MODE_DPMS_OFF:
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003299 i9xx_crtc_disable(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08003300 break;
3301 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08003302}
3303
3304/**
3305 * Sets the power management mode of the pipe and plane.
Zhenyu Wang2c072452009-06-05 15:38:42 +08003306 */
3307static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3308{
3309 struct drm_device *dev = crtc->dev;
Jesse Barnese70236a2009-09-21 10:42:27 -07003310 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003311 struct drm_i915_master_private *master_priv;
3312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3313 int pipe = intel_crtc->pipe;
3314 bool enabled;
3315
Chris Wilson032d2a02010-09-06 16:17:22 +01003316 if (intel_crtc->dpms_mode == mode)
3317 return;
3318
Chris Wilsondebcadd2010-08-07 11:01:33 +01003319 intel_crtc->dpms_mode = mode;
Chris Wilsondebcadd2010-08-07 11:01:33 +01003320
Jesse Barnese70236a2009-09-21 10:42:27 -07003321 dev_priv->display.dpms(crtc, mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08003322
3323 if (!dev->primary->master)
3324 return;
3325
3326 master_priv = dev->primary->master->driver_priv;
3327 if (!master_priv->sarea_priv)
3328 return;
3329
3330 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3331
3332 switch (pipe) {
3333 case 0:
3334 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3335 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3336 break;
3337 case 1:
3338 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3339 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3340 break;
3341 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003342 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08003343 break;
3344 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003345}
3346
Chris Wilsoncdd59982010-09-08 16:30:16 +01003347static void intel_crtc_disable(struct drm_crtc *crtc)
3348{
3349 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3350 struct drm_device *dev = crtc->dev;
3351
3352 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
Chris Wilson931872f2012-01-16 23:01:13 +00003353 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3354 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
Chris Wilsoncdd59982010-09-08 16:30:16 +01003355
3356 if (crtc->fb) {
3357 mutex_lock(&dev->struct_mutex);
3358 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3359 mutex_unlock(&dev->struct_mutex);
3360 }
3361}
3362
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003363/* Prepare for a mode set.
3364 *
3365 * Note we could be a lot smarter here. We need to figure out which outputs
3366 * will be enabled, which disabled (in short, how the config will changes)
3367 * and perform the minimum necessary steps to accomplish that, e.g. updating
3368 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3369 * panel fitting is in the proper state, etc.
3370 */
3371static void i9xx_crtc_prepare(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003372{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003373 i9xx_crtc_disable(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08003374}
3375
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003376static void i9xx_crtc_commit(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003377{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003378 i9xx_crtc_enable(crtc);
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003379}
3380
3381static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3382{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003383 ironlake_crtc_disable(crtc);
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003384}
3385
3386static void ironlake_crtc_commit(struct drm_crtc *crtc)
3387{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003388 ironlake_crtc_enable(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08003389}
3390
Akshay Joshi0206e352011-08-16 15:34:10 -04003391void intel_encoder_prepare(struct drm_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08003392{
3393 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3394 /* lvds has its own version of prepare see intel_lvds_prepare */
3395 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3396}
3397
Akshay Joshi0206e352011-08-16 15:34:10 -04003398void intel_encoder_commit(struct drm_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08003399{
3400 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
Jesse Barnesd4270e52011-10-11 10:43:02 -07003401 struct drm_device *dev = encoder->dev;
3402 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3403 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3404
Jesse Barnes79e53942008-11-07 14:24:08 -08003405 /* lvds has its own version of commit see intel_lvds_commit */
3406 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
Jesse Barnesd4270e52011-10-11 10:43:02 -07003407
3408 if (HAS_PCH_CPT(dev))
3409 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08003410}
3411
Chris Wilsonea5b2132010-08-04 13:50:23 +01003412void intel_encoder_destroy(struct drm_encoder *encoder)
3413{
Chris Wilson4ef69c72010-09-09 15:14:28 +01003414 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01003415
Chris Wilsonea5b2132010-08-04 13:50:23 +01003416 drm_encoder_cleanup(encoder);
3417 kfree(intel_encoder);
3418}
3419
Jesse Barnes79e53942008-11-07 14:24:08 -08003420static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3421 struct drm_display_mode *mode,
3422 struct drm_display_mode *adjusted_mode)
3423{
Zhenyu Wang2c072452009-06-05 15:38:42 +08003424 struct drm_device *dev = crtc->dev;
Chris Wilson89749352010-09-12 18:25:19 +01003425
Eric Anholtbad720f2009-10-22 16:11:14 -07003426 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08003427 /* FDI link clock is fixed at 2.7G */
Jesse Barnes2377b742010-07-07 14:06:43 -07003428 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3429 return false;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003430 }
Chris Wilson89749352010-09-12 18:25:19 +01003431
3432 /* XXX some encoders set the crtcinfo, others don't.
3433 * Obviously we need some form of conflict resolution here...
3434 */
3435 if (adjusted_mode->crtc_htotal == 0)
3436 drm_mode_set_crtcinfo(adjusted_mode, 0);
3437
Jesse Barnes79e53942008-11-07 14:24:08 -08003438 return true;
3439}
3440
Jesse Barnese70236a2009-09-21 10:42:27 -07003441static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08003442{
Jesse Barnese70236a2009-09-21 10:42:27 -07003443 return 400000;
3444}
Jesse Barnes79e53942008-11-07 14:24:08 -08003445
Jesse Barnese70236a2009-09-21 10:42:27 -07003446static int i915_get_display_clock_speed(struct drm_device *dev)
3447{
3448 return 333000;
3449}
Jesse Barnes79e53942008-11-07 14:24:08 -08003450
Jesse Barnese70236a2009-09-21 10:42:27 -07003451static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3452{
3453 return 200000;
3454}
Jesse Barnes79e53942008-11-07 14:24:08 -08003455
Jesse Barnese70236a2009-09-21 10:42:27 -07003456static int i915gm_get_display_clock_speed(struct drm_device *dev)
3457{
3458 u16 gcfgc = 0;
3459
3460 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3461
3462 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08003463 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07003464 else {
3465 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3466 case GC_DISPLAY_CLOCK_333_MHZ:
3467 return 333000;
3468 default:
3469 case GC_DISPLAY_CLOCK_190_200_MHZ:
3470 return 190000;
3471 }
3472 }
3473}
Jesse Barnes79e53942008-11-07 14:24:08 -08003474
Jesse Barnese70236a2009-09-21 10:42:27 -07003475static int i865_get_display_clock_speed(struct drm_device *dev)
3476{
3477 return 266000;
3478}
3479
3480static int i855_get_display_clock_speed(struct drm_device *dev)
3481{
3482 u16 hpllcc = 0;
3483 /* Assume that the hardware is in the high speed state. This
3484 * should be the default.
3485 */
3486 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3487 case GC_CLOCK_133_200:
3488 case GC_CLOCK_100_200:
3489 return 200000;
3490 case GC_CLOCK_166_250:
3491 return 250000;
3492 case GC_CLOCK_100_133:
3493 return 133000;
3494 }
3495
3496 /* Shouldn't happen */
3497 return 0;
3498}
3499
3500static int i830_get_display_clock_speed(struct drm_device *dev)
3501{
3502 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08003503}
3504
Zhenyu Wang2c072452009-06-05 15:38:42 +08003505struct fdi_m_n {
3506 u32 tu;
3507 u32 gmch_m;
3508 u32 gmch_n;
3509 u32 link_m;
3510 u32 link_n;
3511};
3512
3513static void
3514fdi_reduce_ratio(u32 *num, u32 *den)
3515{
3516 while (*num > 0xffffff || *den > 0xffffff) {
3517 *num >>= 1;
3518 *den >>= 1;
3519 }
3520}
3521
Zhenyu Wang2c072452009-06-05 15:38:42 +08003522static void
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003523ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3524 int link_clock, struct fdi_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003525{
Zhenyu Wang2c072452009-06-05 15:38:42 +08003526 m_n->tu = 64; /* default size */
3527
Chris Wilson22ed1112010-12-04 01:01:29 +00003528 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3529 m_n->gmch_m = bits_per_pixel * pixel_clock;
3530 m_n->gmch_n = link_clock * nlanes * 8;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003531 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3532
Chris Wilson22ed1112010-12-04 01:01:29 +00003533 m_n->link_m = pixel_clock;
3534 m_n->link_n = link_clock;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003535 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3536}
3537
3538
Shaohua Li7662c8b2009-06-26 11:23:55 +08003539struct intel_watermark_params {
3540 unsigned long fifo_size;
3541 unsigned long max_wm;
3542 unsigned long default_wm;
3543 unsigned long guard_size;
3544 unsigned long cacheline_size;
3545};
3546
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003547/* Pineview has different values for various configs */
Chris Wilsond2102462011-01-24 17:43:27 +00003548static const struct intel_watermark_params pineview_display_wm = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003549 PINEVIEW_DISPLAY_FIFO,
3550 PINEVIEW_MAX_WM,
3551 PINEVIEW_DFT_WM,
3552 PINEVIEW_GUARD_WM,
3553 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08003554};
Chris Wilsond2102462011-01-24 17:43:27 +00003555static const struct intel_watermark_params pineview_display_hplloff_wm = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003556 PINEVIEW_DISPLAY_FIFO,
3557 PINEVIEW_MAX_WM,
3558 PINEVIEW_DFT_HPLLOFF_WM,
3559 PINEVIEW_GUARD_WM,
3560 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08003561};
Chris Wilsond2102462011-01-24 17:43:27 +00003562static const struct intel_watermark_params pineview_cursor_wm = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003563 PINEVIEW_CURSOR_FIFO,
3564 PINEVIEW_CURSOR_MAX_WM,
3565 PINEVIEW_CURSOR_DFT_WM,
3566 PINEVIEW_CURSOR_GUARD_WM,
3567 PINEVIEW_FIFO_LINE_SIZE,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003568};
Chris Wilsond2102462011-01-24 17:43:27 +00003569static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003570 PINEVIEW_CURSOR_FIFO,
3571 PINEVIEW_CURSOR_MAX_WM,
3572 PINEVIEW_CURSOR_DFT_WM,
3573 PINEVIEW_CURSOR_GUARD_WM,
3574 PINEVIEW_FIFO_LINE_SIZE
Shaohua Li7662c8b2009-06-26 11:23:55 +08003575};
Chris Wilsond2102462011-01-24 17:43:27 +00003576static const struct intel_watermark_params g4x_wm_info = {
Jesse Barnes0e442c62009-10-19 10:09:33 +09003577 G4X_FIFO_SIZE,
3578 G4X_MAX_WM,
3579 G4X_MAX_WM,
3580 2,
3581 G4X_FIFO_LINE_SIZE,
3582};
Chris Wilsond2102462011-01-24 17:43:27 +00003583static const struct intel_watermark_params g4x_cursor_wm_info = {
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003584 I965_CURSOR_FIFO,
3585 I965_CURSOR_MAX_WM,
3586 I965_CURSOR_DFT_WM,
3587 2,
3588 G4X_FIFO_LINE_SIZE,
3589};
Chris Wilsond2102462011-01-24 17:43:27 +00003590static const struct intel_watermark_params i965_cursor_wm_info = {
Zhao Yakui4fe5e612010-06-12 14:32:25 +08003591 I965_CURSOR_FIFO,
3592 I965_CURSOR_MAX_WM,
3593 I965_CURSOR_DFT_WM,
3594 2,
3595 I915_FIFO_LINE_SIZE,
3596};
Chris Wilsond2102462011-01-24 17:43:27 +00003597static const struct intel_watermark_params i945_wm_info = {
Shaohua Li7662c8b2009-06-26 11:23:55 +08003598 I945_FIFO_SIZE,
3599 I915_MAX_WM,
3600 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003601 2,
3602 I915_FIFO_LINE_SIZE
3603};
Chris Wilsond2102462011-01-24 17:43:27 +00003604static const struct intel_watermark_params i915_wm_info = {
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003605 I915_FIFO_SIZE,
3606 I915_MAX_WM,
3607 1,
3608 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003609 I915_FIFO_LINE_SIZE
3610};
Chris Wilsond2102462011-01-24 17:43:27 +00003611static const struct intel_watermark_params i855_wm_info = {
Shaohua Li7662c8b2009-06-26 11:23:55 +08003612 I855GM_FIFO_SIZE,
3613 I915_MAX_WM,
3614 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003615 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003616 I830_FIFO_LINE_SIZE
3617};
Chris Wilsond2102462011-01-24 17:43:27 +00003618static const struct intel_watermark_params i830_wm_info = {
Shaohua Li7662c8b2009-06-26 11:23:55 +08003619 I830_FIFO_SIZE,
3620 I915_MAX_WM,
3621 1,
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003622 2,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003623 I830_FIFO_LINE_SIZE
3624};
3625
Chris Wilsond2102462011-01-24 17:43:27 +00003626static const struct intel_watermark_params ironlake_display_wm_info = {
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003627 ILK_DISPLAY_FIFO,
3628 ILK_DISPLAY_MAXWM,
3629 ILK_DISPLAY_DFTWM,
3630 2,
3631 ILK_FIFO_LINE_SIZE
3632};
Chris Wilsond2102462011-01-24 17:43:27 +00003633static const struct intel_watermark_params ironlake_cursor_wm_info = {
Zhao Yakuic936f442010-06-12 14:32:26 +08003634 ILK_CURSOR_FIFO,
3635 ILK_CURSOR_MAXWM,
3636 ILK_CURSOR_DFTWM,
3637 2,
3638 ILK_FIFO_LINE_SIZE
3639};
Chris Wilsond2102462011-01-24 17:43:27 +00003640static const struct intel_watermark_params ironlake_display_srwm_info = {
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003641 ILK_DISPLAY_SR_FIFO,
3642 ILK_DISPLAY_MAX_SRWM,
3643 ILK_DISPLAY_DFT_SRWM,
3644 2,
3645 ILK_FIFO_LINE_SIZE
3646};
Chris Wilsond2102462011-01-24 17:43:27 +00003647static const struct intel_watermark_params ironlake_cursor_srwm_info = {
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08003648 ILK_CURSOR_SR_FIFO,
3649 ILK_CURSOR_MAX_SRWM,
3650 ILK_CURSOR_DFT_SRWM,
3651 2,
3652 ILK_FIFO_LINE_SIZE
3653};
3654
Chris Wilsond2102462011-01-24 17:43:27 +00003655static const struct intel_watermark_params sandybridge_display_wm_info = {
Yuanhan Liu13982612010-12-15 15:42:31 +08003656 SNB_DISPLAY_FIFO,
3657 SNB_DISPLAY_MAXWM,
3658 SNB_DISPLAY_DFTWM,
3659 2,
3660 SNB_FIFO_LINE_SIZE
3661};
Chris Wilsond2102462011-01-24 17:43:27 +00003662static const struct intel_watermark_params sandybridge_cursor_wm_info = {
Yuanhan Liu13982612010-12-15 15:42:31 +08003663 SNB_CURSOR_FIFO,
3664 SNB_CURSOR_MAXWM,
3665 SNB_CURSOR_DFTWM,
3666 2,
3667 SNB_FIFO_LINE_SIZE
3668};
Chris Wilsond2102462011-01-24 17:43:27 +00003669static const struct intel_watermark_params sandybridge_display_srwm_info = {
Yuanhan Liu13982612010-12-15 15:42:31 +08003670 SNB_DISPLAY_SR_FIFO,
3671 SNB_DISPLAY_MAX_SRWM,
3672 SNB_DISPLAY_DFT_SRWM,
3673 2,
3674 SNB_FIFO_LINE_SIZE
3675};
Chris Wilsond2102462011-01-24 17:43:27 +00003676static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
Yuanhan Liu13982612010-12-15 15:42:31 +08003677 SNB_CURSOR_SR_FIFO,
3678 SNB_CURSOR_MAX_SRWM,
3679 SNB_CURSOR_DFT_SRWM,
3680 2,
3681 SNB_FIFO_LINE_SIZE
3682};
3683
3684
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003685/**
3686 * intel_calculate_wm - calculate watermark level
3687 * @clock_in_khz: pixel clock
3688 * @wm: chip FIFO params
3689 * @pixel_size: display pixel size
3690 * @latency_ns: memory latency for the platform
3691 *
3692 * Calculate the watermark level (the level at which the display plane will
3693 * start fetching from memory again). Each chip has a different display
3694 * FIFO size and allocation, so the caller needs to figure that out and pass
3695 * in the correct intel_watermark_params structure.
3696 *
3697 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3698 * on the pixel size. When it reaches the watermark level, it'll start
3699 * fetching FIFO line sized based chunks from memory until the FIFO fills
3700 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3701 * will occur, and a display engine hang could result.
3702 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003703static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
Chris Wilsond2102462011-01-24 17:43:27 +00003704 const struct intel_watermark_params *wm,
3705 int fifo_size,
Shaohua Li7662c8b2009-06-26 11:23:55 +08003706 int pixel_size,
3707 unsigned long latency_ns)
3708{
Jesse Barnes390c4dd2009-07-16 13:01:01 -07003709 long entries_required, wm_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003710
Jesse Barnesd6604672009-09-11 12:25:56 -07003711 /*
3712 * Note: we need to make sure we don't overflow for various clock &
3713 * latency values.
3714 * clocks go from a few thousand to several hundred thousand.
3715 * latency is usually a few thousand
3716 */
3717 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3718 1000;
Chris Wilson8de9b312010-07-19 19:59:52 +01003719 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003720
Joe Perchesbbb0aef2011-04-17 20:35:52 -07003721 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003722
Chris Wilsond2102462011-01-24 17:43:27 +00003723 wm_size = fifo_size - (entries_required + wm->guard_size);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003724
Joe Perchesbbb0aef2011-04-17 20:35:52 -07003725 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003726
Jesse Barnes390c4dd2009-07-16 13:01:01 -07003727 /* Don't promote wm_size to unsigned... */
3728 if (wm_size > (long)wm->max_wm)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003729 wm_size = wm->max_wm;
Chris Wilsonc3add4b2010-09-08 09:14:08 +01003730 if (wm_size <= 0)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003731 wm_size = wm->default_wm;
3732 return wm_size;
3733}
3734
3735struct cxsr_latency {
3736 int is_desktop;
Li Peng95534262010-05-18 18:58:44 +08003737 int is_ddr3;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003738 unsigned long fsb_freq;
3739 unsigned long mem_freq;
3740 unsigned long display_sr;
3741 unsigned long display_hpll_disable;
3742 unsigned long cursor_sr;
3743 unsigned long cursor_hpll_disable;
3744};
3745
Chris Wilson403c89f2010-08-04 15:25:31 +01003746static const struct cxsr_latency cxsr_latency_table[] = {
Li Peng95534262010-05-18 18:58:44 +08003747 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3748 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3749 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3750 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3751 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003752
Li Peng95534262010-05-18 18:58:44 +08003753 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3754 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3755 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3756 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3757 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003758
Li Peng95534262010-05-18 18:58:44 +08003759 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3760 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3761 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3762 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3763 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003764
Li Peng95534262010-05-18 18:58:44 +08003765 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3766 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3767 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3768 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3769 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003770
Li Peng95534262010-05-18 18:58:44 +08003771 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3772 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3773 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3774 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3775 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003776
Li Peng95534262010-05-18 18:58:44 +08003777 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3778 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3779 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3780 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3781 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
Shaohua Li7662c8b2009-06-26 11:23:55 +08003782};
3783
Chris Wilson403c89f2010-08-04 15:25:31 +01003784static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3785 int is_ddr3,
3786 int fsb,
3787 int mem)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003788{
Chris Wilson403c89f2010-08-04 15:25:31 +01003789 const struct cxsr_latency *latency;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003790 int i;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003791
3792 if (fsb == 0 || mem == 0)
3793 return NULL;
3794
3795 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3796 latency = &cxsr_latency_table[i];
3797 if (is_desktop == latency->is_desktop &&
Li Peng95534262010-05-18 18:58:44 +08003798 is_ddr3 == latency->is_ddr3 &&
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05303799 fsb == latency->fsb_freq && mem == latency->mem_freq)
3800 return latency;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003801 }
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05303802
Zhao Yakui28c97732009-10-09 11:39:41 +08003803 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
Jaswinder Singh Rajputdecbbcd2009-09-12 23:15:07 +05303804
3805 return NULL;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003806}
3807
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003808static void pineview_disable_cxsr(struct drm_device *dev)
Shaohua Li7662c8b2009-06-26 11:23:55 +08003809{
3810 struct drm_i915_private *dev_priv = dev->dev_private;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003811
3812 /* deactivate cxsr */
Chris Wilson3e33d942010-08-04 11:17:25 +01003813 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
Shaohua Li7662c8b2009-06-26 11:23:55 +08003814}
3815
Jesse Barnesbcc24fb2009-08-31 10:24:31 -07003816/*
3817 * Latency for FIFO fetches is dependent on several factors:
3818 * - memory configuration (speed, channels)
3819 * - chipset
3820 * - current MCH state
3821 * It can be fairly high in some situations, so here we assume a fairly
3822 * pessimal value. It's a tradeoff between extra memory fetches (if we
3823 * set this value too high, the FIFO will fetch frequently to stay full)
3824 * and power consumption (set it too low to save power and we might see
3825 * FIFO underruns and display "flicker").
3826 *
3827 * A value of 5us seems to be a good balance; safe for very low end
3828 * platforms but not overly aggressive on lower latency configs.
3829 */
Tobias Klauser69e302a2009-12-23 14:14:34 +01003830static const int latency_ns = 5000;
Shaohua Li7662c8b2009-06-26 11:23:55 +08003831
Jesse Barnese70236a2009-09-21 10:42:27 -07003832static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003833{
3834 struct drm_i915_private *dev_priv = dev->dev_private;
3835 uint32_t dsparb = I915_READ(DSPARB);
3836 int size;
3837
Chris Wilson8de9b312010-07-19 19:59:52 +01003838 size = dsparb & 0x7f;
3839 if (plane)
3840 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003841
Zhao Yakui28c97732009-10-09 11:39:41 +08003842 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
Chris Wilson5eddb702010-09-11 13:48:45 +01003843 plane ? "B" : "A", size);
Jesse Barnesdff33cf2009-07-14 10:15:56 -07003844
3845 return size;
3846}
Shaohua Li7662c8b2009-06-26 11:23:55 +08003847
Jesse Barnese70236a2009-09-21 10:42:27 -07003848static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3849{
3850 struct drm_i915_private *dev_priv = dev->dev_private;
3851 uint32_t dsparb = I915_READ(DSPARB);
3852 int size;
3853
Chris Wilson8de9b312010-07-19 19:59:52 +01003854 size = dsparb & 0x1ff;
3855 if (plane)
3856 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
Jesse Barnese70236a2009-09-21 10:42:27 -07003857 size >>= 1; /* Convert to cachelines */
3858
Zhao Yakui28c97732009-10-09 11:39:41 +08003859 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
Chris Wilson5eddb702010-09-11 13:48:45 +01003860 plane ? "B" : "A", size);
Jesse Barnese70236a2009-09-21 10:42:27 -07003861
3862 return size;
3863}
3864
3865static int i845_get_fifo_size(struct drm_device *dev, int plane)
3866{
3867 struct drm_i915_private *dev_priv = dev->dev_private;
3868 uint32_t dsparb = I915_READ(DSPARB);
3869 int size;
3870
3871 size = dsparb & 0x7f;
3872 size >>= 2; /* Convert to cachelines */
3873
Zhao Yakui28c97732009-10-09 11:39:41 +08003874 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
Chris Wilson5eddb702010-09-11 13:48:45 +01003875 plane ? "B" : "A",
3876 size);
Jesse Barnese70236a2009-09-21 10:42:27 -07003877
3878 return size;
3879}
3880
3881static int i830_get_fifo_size(struct drm_device *dev, int plane)
3882{
3883 struct drm_i915_private *dev_priv = dev->dev_private;
3884 uint32_t dsparb = I915_READ(DSPARB);
3885 int size;
3886
3887 size = dsparb & 0x7f;
3888 size >>= 1; /* Convert to cachelines */
3889
Zhao Yakui28c97732009-10-09 11:39:41 +08003890 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
Chris Wilson5eddb702010-09-11 13:48:45 +01003891 plane ? "B" : "A", size);
Jesse Barnese70236a2009-09-21 10:42:27 -07003892
3893 return size;
3894}
3895
Chris Wilsond2102462011-01-24 17:43:27 +00003896static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3897{
3898 struct drm_crtc *crtc, *enabled = NULL;
3899
3900 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3901 if (crtc->enabled && crtc->fb) {
3902 if (enabled)
3903 return NULL;
3904 enabled = crtc;
3905 }
3906 }
3907
3908 return enabled;
3909}
3910
3911static void pineview_update_wm(struct drm_device *dev)
Zhao Yakuid4294342010-03-22 22:45:36 +08003912{
3913 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond2102462011-01-24 17:43:27 +00003914 struct drm_crtc *crtc;
Chris Wilson403c89f2010-08-04 15:25:31 +01003915 const struct cxsr_latency *latency;
Zhao Yakuid4294342010-03-22 22:45:36 +08003916 u32 reg;
3917 unsigned long wm;
Zhao Yakuid4294342010-03-22 22:45:36 +08003918
Chris Wilson403c89f2010-08-04 15:25:31 +01003919 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
Li Peng95534262010-05-18 18:58:44 +08003920 dev_priv->fsb_freq, dev_priv->mem_freq);
Zhao Yakuid4294342010-03-22 22:45:36 +08003921 if (!latency) {
3922 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3923 pineview_disable_cxsr(dev);
3924 return;
3925 }
3926
Chris Wilsond2102462011-01-24 17:43:27 +00003927 crtc = single_enabled_crtc(dev);
3928 if (crtc) {
3929 int clock = crtc->mode.clock;
3930 int pixel_size = crtc->fb->bits_per_pixel / 8;
Zhao Yakuid4294342010-03-22 22:45:36 +08003931
3932 /* Display SR */
Chris Wilsond2102462011-01-24 17:43:27 +00003933 wm = intel_calculate_wm(clock, &pineview_display_wm,
3934 pineview_display_wm.fifo_size,
Zhao Yakuid4294342010-03-22 22:45:36 +08003935 pixel_size, latency->display_sr);
3936 reg = I915_READ(DSPFW1);
3937 reg &= ~DSPFW_SR_MASK;
3938 reg |= wm << DSPFW_SR_SHIFT;
3939 I915_WRITE(DSPFW1, reg);
3940 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3941
3942 /* cursor SR */
Chris Wilsond2102462011-01-24 17:43:27 +00003943 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3944 pineview_display_wm.fifo_size,
Zhao Yakuid4294342010-03-22 22:45:36 +08003945 pixel_size, latency->cursor_sr);
3946 reg = I915_READ(DSPFW3);
3947 reg &= ~DSPFW_CURSOR_SR_MASK;
3948 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3949 I915_WRITE(DSPFW3, reg);
3950
3951 /* Display HPLL off SR */
Chris Wilsond2102462011-01-24 17:43:27 +00003952 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3953 pineview_display_hplloff_wm.fifo_size,
Zhao Yakuid4294342010-03-22 22:45:36 +08003954 pixel_size, latency->display_hpll_disable);
3955 reg = I915_READ(DSPFW3);
3956 reg &= ~DSPFW_HPLL_SR_MASK;
3957 reg |= wm & DSPFW_HPLL_SR_MASK;
3958 I915_WRITE(DSPFW3, reg);
3959
3960 /* cursor HPLL off SR */
Chris Wilsond2102462011-01-24 17:43:27 +00003961 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3962 pineview_display_hplloff_wm.fifo_size,
Zhao Yakuid4294342010-03-22 22:45:36 +08003963 pixel_size, latency->cursor_hpll_disable);
3964 reg = I915_READ(DSPFW3);
3965 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3966 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3967 I915_WRITE(DSPFW3, reg);
3968 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3969
3970 /* activate cxsr */
Chris Wilson3e33d942010-08-04 11:17:25 +01003971 I915_WRITE(DSPFW3,
3972 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
Zhao Yakuid4294342010-03-22 22:45:36 +08003973 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3974 } else {
3975 pineview_disable_cxsr(dev);
3976 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3977 }
3978}
3979
Chris Wilson417ae142011-01-19 15:04:42 +00003980static bool g4x_compute_wm0(struct drm_device *dev,
3981 int plane,
3982 const struct intel_watermark_params *display,
3983 int display_latency_ns,
3984 const struct intel_watermark_params *cursor,
3985 int cursor_latency_ns,
3986 int *plane_wm,
3987 int *cursor_wm)
Jesse Barnes652c3932009-08-17 13:31:43 -07003988{
Chris Wilson417ae142011-01-19 15:04:42 +00003989 struct drm_crtc *crtc;
3990 int htotal, hdisplay, clock, pixel_size;
3991 int line_time_us, line_count;
3992 int entries, tlb_miss;
Jesse Barnes652c3932009-08-17 13:31:43 -07003993
Chris Wilson417ae142011-01-19 15:04:42 +00003994 crtc = intel_get_crtc_for_plane(dev, plane);
Chris Wilson5c72d062011-04-13 09:28:23 +01003995 if (crtc->fb == NULL || !crtc->enabled) {
3996 *cursor_wm = cursor->guard_size;
3997 *plane_wm = display->guard_size;
Chris Wilson417ae142011-01-19 15:04:42 +00003998 return false;
Chris Wilson5c72d062011-04-13 09:28:23 +01003999 }
Jesse Barnes0e442c62009-10-19 10:09:33 +09004000
Chris Wilson417ae142011-01-19 15:04:42 +00004001 htotal = crtc->mode.htotal;
4002 hdisplay = crtc->mode.hdisplay;
4003 clock = crtc->mode.clock;
4004 pixel_size = crtc->fb->bits_per_pixel / 8;
Jesse Barnes0e442c62009-10-19 10:09:33 +09004005
Chris Wilson417ae142011-01-19 15:04:42 +00004006 /* Use the small buffer method to calculate plane watermark */
4007 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4008 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4009 if (tlb_miss > 0)
4010 entries += tlb_miss;
4011 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4012 *plane_wm = entries + display->guard_size;
4013 if (*plane_wm > (int)display->max_wm)
4014 *plane_wm = display->max_wm;
Jesse Barnes0e442c62009-10-19 10:09:33 +09004015
Chris Wilson417ae142011-01-19 15:04:42 +00004016 /* Use the large buffer method to calculate cursor watermark */
4017 line_time_us = ((htotal * 1000) / clock);
4018 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4019 entries = line_count * 64 * pixel_size;
4020 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4021 if (tlb_miss > 0)
4022 entries += tlb_miss;
4023 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4024 *cursor_wm = entries + cursor->guard_size;
4025 if (*cursor_wm > (int)cursor->max_wm)
4026 *cursor_wm = (int)cursor->max_wm;
Jesse Barnes0e442c62009-10-19 10:09:33 +09004027
Chris Wilson417ae142011-01-19 15:04:42 +00004028 return true;
4029}
Jesse Barnes0e442c62009-10-19 10:09:33 +09004030
Chris Wilson417ae142011-01-19 15:04:42 +00004031/*
4032 * Check the wm result.
4033 *
4034 * If any calculated watermark values is larger than the maximum value that
4035 * can be programmed into the associated watermark register, that watermark
4036 * must be disabled.
4037 */
4038static bool g4x_check_srwm(struct drm_device *dev,
4039 int display_wm, int cursor_wm,
4040 const struct intel_watermark_params *display,
4041 const struct intel_watermark_params *cursor)
4042{
4043 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4044 display_wm, cursor_wm);
Jesse Barnes0e442c62009-10-19 10:09:33 +09004045
Chris Wilson417ae142011-01-19 15:04:42 +00004046 if (display_wm > display->max_wm) {
Joe Perchesbbb0aef2011-04-17 20:35:52 -07004047 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
Chris Wilson417ae142011-01-19 15:04:42 +00004048 display_wm, display->max_wm);
4049 return false;
Jesse Barnes0e442c62009-10-19 10:09:33 +09004050 }
4051
Chris Wilson417ae142011-01-19 15:04:42 +00004052 if (cursor_wm > cursor->max_wm) {
Joe Perchesbbb0aef2011-04-17 20:35:52 -07004053 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
Chris Wilson417ae142011-01-19 15:04:42 +00004054 cursor_wm, cursor->max_wm);
4055 return false;
4056 }
Jesse Barnes0e442c62009-10-19 10:09:33 +09004057
Chris Wilson417ae142011-01-19 15:04:42 +00004058 if (!(display_wm || cursor_wm)) {
4059 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4060 return false;
4061 }
Jesse Barnes0e442c62009-10-19 10:09:33 +09004062
Chris Wilson417ae142011-01-19 15:04:42 +00004063 return true;
4064}
4065
4066static bool g4x_compute_srwm(struct drm_device *dev,
Chris Wilsond2102462011-01-24 17:43:27 +00004067 int plane,
4068 int latency_ns,
Chris Wilson417ae142011-01-19 15:04:42 +00004069 const struct intel_watermark_params *display,
4070 const struct intel_watermark_params *cursor,
4071 int *display_wm, int *cursor_wm)
4072{
Chris Wilsond2102462011-01-24 17:43:27 +00004073 struct drm_crtc *crtc;
4074 int hdisplay, htotal, pixel_size, clock;
Chris Wilson417ae142011-01-19 15:04:42 +00004075 unsigned long line_time_us;
4076 int line_count, line_size;
4077 int small, large;
4078 int entries;
4079
4080 if (!latency_ns) {
4081 *display_wm = *cursor_wm = 0;
4082 return false;
4083 }
4084
Chris Wilsond2102462011-01-24 17:43:27 +00004085 crtc = intel_get_crtc_for_plane(dev, plane);
4086 hdisplay = crtc->mode.hdisplay;
4087 htotal = crtc->mode.htotal;
4088 clock = crtc->mode.clock;
4089 pixel_size = crtc->fb->bits_per_pixel / 8;
4090
Chris Wilson417ae142011-01-19 15:04:42 +00004091 line_time_us = (htotal * 1000) / clock;
4092 line_count = (latency_ns / line_time_us + 1000) / 1000;
4093 line_size = hdisplay * pixel_size;
4094
4095 /* Use the minimum of the small and large buffer method for primary */
4096 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4097 large = line_count * line_size;
4098
4099 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4100 *display_wm = entries + display->guard_size;
4101
4102 /* calculate the self-refresh watermark for display cursor */
4103 entries = line_count * pixel_size * 64;
4104 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4105 *cursor_wm = entries + cursor->guard_size;
4106
4107 return g4x_check_srwm(dev,
4108 *display_wm, *cursor_wm,
4109 display, cursor);
4110}
4111
Yuanhan Liu7ccb4a52011-03-18 07:37:35 +00004112#define single_plane_enabled(mask) is_power_of_2(mask)
Chris Wilsond2102462011-01-24 17:43:27 +00004113
4114static void g4x_update_wm(struct drm_device *dev)
Chris Wilson417ae142011-01-19 15:04:42 +00004115{
4116 static const int sr_latency_ns = 12000;
4117 struct drm_i915_private *dev_priv = dev->dev_private;
4118 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
Chris Wilsond2102462011-01-24 17:43:27 +00004119 int plane_sr, cursor_sr;
4120 unsigned int enabled = 0;
Chris Wilson417ae142011-01-19 15:04:42 +00004121
4122 if (g4x_compute_wm0(dev, 0,
4123 &g4x_wm_info, latency_ns,
4124 &g4x_cursor_wm_info, latency_ns,
4125 &planea_wm, &cursora_wm))
Chris Wilsond2102462011-01-24 17:43:27 +00004126 enabled |= 1;
Chris Wilson417ae142011-01-19 15:04:42 +00004127
4128 if (g4x_compute_wm0(dev, 1,
4129 &g4x_wm_info, latency_ns,
4130 &g4x_cursor_wm_info, latency_ns,
4131 &planeb_wm, &cursorb_wm))
Chris Wilsond2102462011-01-24 17:43:27 +00004132 enabled |= 2;
Chris Wilson417ae142011-01-19 15:04:42 +00004133
4134 plane_sr = cursor_sr = 0;
Chris Wilsond2102462011-01-24 17:43:27 +00004135 if (single_plane_enabled(enabled) &&
4136 g4x_compute_srwm(dev, ffs(enabled) - 1,
4137 sr_latency_ns,
Chris Wilson417ae142011-01-19 15:04:42 +00004138 &g4x_wm_info,
4139 &g4x_cursor_wm_info,
4140 &plane_sr, &cursor_sr))
4141 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4142 else
4143 I915_WRITE(FW_BLC_SELF,
4144 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4145
Chris Wilson308977a2011-02-02 10:41:20 +00004146 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4147 planea_wm, cursora_wm,
4148 planeb_wm, cursorb_wm,
4149 plane_sr, cursor_sr);
Chris Wilson417ae142011-01-19 15:04:42 +00004150
4151 I915_WRITE(DSPFW1,
4152 (plane_sr << DSPFW_SR_SHIFT) |
Jesse Barnes0e442c62009-10-19 10:09:33 +09004153 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
Chris Wilson417ae142011-01-19 15:04:42 +00004154 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4155 planea_wm);
4156 I915_WRITE(DSPFW2,
4157 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
Jesse Barnes0e442c62009-10-19 10:09:33 +09004158 (cursora_wm << DSPFW_CURSORA_SHIFT));
4159 /* HPLL off in SR has some issues on G4x... disable it */
Chris Wilson417ae142011-01-19 15:04:42 +00004160 I915_WRITE(DSPFW3,
4161 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
Jesse Barnes0e442c62009-10-19 10:09:33 +09004162 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
Jesse Barnes652c3932009-08-17 13:31:43 -07004163}
4164
Chris Wilsond2102462011-01-24 17:43:27 +00004165static void i965_update_wm(struct drm_device *dev)
Shaohua Li7662c8b2009-06-26 11:23:55 +08004166{
4167 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond2102462011-01-24 17:43:27 +00004168 struct drm_crtc *crtc;
4169 int srwm = 1;
Zhao Yakui4fe5e612010-06-12 14:32:25 +08004170 int cursor_sr = 16;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004171
Jesse Barnes1dc75462009-10-19 10:08:17 +09004172 /* Calc sr entries for one plane configs */
Chris Wilsond2102462011-01-24 17:43:27 +00004173 crtc = single_enabled_crtc(dev);
4174 if (crtc) {
Jesse Barnes1dc75462009-10-19 10:08:17 +09004175 /* self-refresh has much higher latency */
Tobias Klauser69e302a2009-12-23 14:14:34 +01004176 static const int sr_latency_ns = 12000;
Chris Wilsond2102462011-01-24 17:43:27 +00004177 int clock = crtc->mode.clock;
4178 int htotal = crtc->mode.htotal;
4179 int hdisplay = crtc->mode.hdisplay;
4180 int pixel_size = crtc->fb->bits_per_pixel / 8;
4181 unsigned long line_time_us;
4182 int entries;
Jesse Barnes1dc75462009-10-19 10:08:17 +09004183
Chris Wilsond2102462011-01-24 17:43:27 +00004184 line_time_us = ((htotal * 1000) / clock);
Jesse Barnes1dc75462009-10-19 10:08:17 +09004185
4186 /* Use ns/us then divide to preserve precision */
Chris Wilsond2102462011-01-24 17:43:27 +00004187 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4188 pixel_size * hdisplay;
4189 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
Chris Wilsond2102462011-01-24 17:43:27 +00004190 srwm = I965_FIFO_SIZE - entries;
Jesse Barnes1dc75462009-10-19 10:08:17 +09004191 if (srwm < 0)
4192 srwm = 1;
Zhao Yakui1b07e042010-06-12 14:32:24 +08004193 srwm &= 0x1ff;
Chris Wilson308977a2011-02-02 10:41:20 +00004194 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4195 entries, srwm);
Zhao Yakui4fe5e612010-06-12 14:32:25 +08004196
Chris Wilsond2102462011-01-24 17:43:27 +00004197 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
Chris Wilson5eddb702010-09-11 13:48:45 +01004198 pixel_size * 64;
Chris Wilsond2102462011-01-24 17:43:27 +00004199 entries = DIV_ROUND_UP(entries,
Chris Wilson8de9b312010-07-19 19:59:52 +01004200 i965_cursor_wm_info.cacheline_size);
Zhao Yakui4fe5e612010-06-12 14:32:25 +08004201 cursor_sr = i965_cursor_wm_info.fifo_size -
Chris Wilsond2102462011-01-24 17:43:27 +00004202 (entries + i965_cursor_wm_info.guard_size);
Zhao Yakui4fe5e612010-06-12 14:32:25 +08004203
4204 if (cursor_sr > i965_cursor_wm_info.max_wm)
4205 cursor_sr = i965_cursor_wm_info.max_wm;
4206
4207 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4208 "cursor %d\n", srwm, cursor_sr);
4209
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004210 if (IS_CRESTLINE(dev))
Jesse Barnesadcdbc62010-06-30 13:49:37 -07004211 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
David John33c5fd12010-01-27 15:19:08 +05304212 } else {
4213 /* Turn off self refresh if both pipes are enabled */
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004214 if (IS_CRESTLINE(dev))
Jesse Barnesadcdbc62010-06-30 13:49:37 -07004215 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4216 & ~FW_BLC_SELF_EN);
Jesse Barnes1dc75462009-10-19 10:08:17 +09004217 }
4218
4219 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4220 srwm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004221
4222 /* 965 has limitations... */
Chris Wilson417ae142011-01-19 15:04:42 +00004223 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4224 (8 << 16) | (8 << 8) | (8 << 0));
Shaohua Li7662c8b2009-06-26 11:23:55 +08004225 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
Zhao Yakui4fe5e612010-06-12 14:32:25 +08004226 /* update cursor SR watermark */
4227 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
Shaohua Li7662c8b2009-06-26 11:23:55 +08004228}
4229
Chris Wilsond2102462011-01-24 17:43:27 +00004230static void i9xx_update_wm(struct drm_device *dev)
Shaohua Li7662c8b2009-06-26 11:23:55 +08004231{
4232 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond2102462011-01-24 17:43:27 +00004233 const struct intel_watermark_params *wm_info;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004234 uint32_t fwater_lo;
4235 uint32_t fwater_hi;
Chris Wilsond2102462011-01-24 17:43:27 +00004236 int cwm, srwm = 1;
4237 int fifo_size;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004238 int planea_wm, planeb_wm;
Chris Wilsond2102462011-01-24 17:43:27 +00004239 struct drm_crtc *crtc, *enabled = NULL;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004240
Chris Wilson72557b42011-01-31 10:29:55 +00004241 if (IS_I945GM(dev))
Chris Wilsond2102462011-01-24 17:43:27 +00004242 wm_info = &i945_wm_info;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01004243 else if (!IS_GEN2(dev))
Chris Wilsond2102462011-01-24 17:43:27 +00004244 wm_info = &i915_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004245 else
Chris Wilsond2102462011-01-24 17:43:27 +00004246 wm_info = &i855_wm_info;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004247
Chris Wilsond2102462011-01-24 17:43:27 +00004248 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4249 crtc = intel_get_crtc_for_plane(dev, 0);
4250 if (crtc->enabled && crtc->fb) {
4251 planea_wm = intel_calculate_wm(crtc->mode.clock,
4252 wm_info, fifo_size,
4253 crtc->fb->bits_per_pixel / 8,
4254 latency_ns);
4255 enabled = crtc;
4256 } else
4257 planea_wm = fifo_size - wm_info->guard_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004258
Chris Wilsond2102462011-01-24 17:43:27 +00004259 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4260 crtc = intel_get_crtc_for_plane(dev, 1);
4261 if (crtc->enabled && crtc->fb) {
4262 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4263 wm_info, fifo_size,
4264 crtc->fb->bits_per_pixel / 8,
4265 latency_ns);
4266 if (enabled == NULL)
4267 enabled = crtc;
4268 else
4269 enabled = NULL;
4270 } else
4271 planeb_wm = fifo_size - wm_info->guard_size;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004272
Zhao Yakui28c97732009-10-09 11:39:41 +08004273 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004274
4275 /*
4276 * Overlay gets an aggressive default since video jitter is bad.
4277 */
4278 cwm = 2;
4279
Alexander Lam18b21902011-01-03 13:28:56 -05004280 /* Play safe and disable self-refresh before adjusting watermarks. */
4281 if (IS_I945G(dev) || IS_I945GM(dev))
4282 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4283 else if (IS_I915GM(dev))
4284 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4285
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004286 /* Calc sr entries for one plane configs */
Chris Wilsond2102462011-01-24 17:43:27 +00004287 if (HAS_FW_BLC(dev) && enabled) {
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004288 /* self-refresh has much higher latency */
Tobias Klauser69e302a2009-12-23 14:14:34 +01004289 static const int sr_latency_ns = 6000;
Chris Wilsond2102462011-01-24 17:43:27 +00004290 int clock = enabled->mode.clock;
4291 int htotal = enabled->mode.htotal;
4292 int hdisplay = enabled->mode.hdisplay;
4293 int pixel_size = enabled->fb->bits_per_pixel / 8;
4294 unsigned long line_time_us;
4295 int entries;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004296
Chris Wilsond2102462011-01-24 17:43:27 +00004297 line_time_us = (htotal * 1000) / clock;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004298
4299 /* Use ns/us then divide to preserve precision */
Chris Wilsond2102462011-01-24 17:43:27 +00004300 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4301 pixel_size * hdisplay;
4302 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4303 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4304 srwm = wm_info->fifo_size - entries;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004305 if (srwm < 0)
4306 srwm = 1;
Li Pengee980b82010-01-27 19:01:11 +08004307
4308 if (IS_I945G(dev) || IS_I945GM(dev))
Alexander Lam18b21902011-01-03 13:28:56 -05004309 I915_WRITE(FW_BLC_SELF,
4310 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4311 else if (IS_I915GM(dev))
Li Pengee980b82010-01-27 19:01:11 +08004312 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004313 }
4314
Zhao Yakui28c97732009-10-09 11:39:41 +08004315 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
Chris Wilson5eddb702010-09-11 13:48:45 +01004316 planea_wm, planeb_wm, cwm, srwm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004317
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004318 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4319 fwater_hi = (cwm & 0x1f);
4320
4321 /* Set request length to 8 cachelines per fetch */
4322 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4323 fwater_hi = fwater_hi | (1 << 8);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004324
4325 I915_WRITE(FW_BLC, fwater_lo);
4326 I915_WRITE(FW_BLC2, fwater_hi);
Alexander Lam18b21902011-01-03 13:28:56 -05004327
Chris Wilsond2102462011-01-24 17:43:27 +00004328 if (HAS_FW_BLC(dev)) {
4329 if (enabled) {
4330 if (IS_I945G(dev) || IS_I945GM(dev))
4331 I915_WRITE(FW_BLC_SELF,
4332 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4333 else if (IS_I915GM(dev))
4334 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4335 DRM_DEBUG_KMS("memory self refresh enabled\n");
4336 } else
4337 DRM_DEBUG_KMS("memory self refresh disabled\n");
4338 }
Shaohua Li7662c8b2009-06-26 11:23:55 +08004339}
4340
Chris Wilsond2102462011-01-24 17:43:27 +00004341static void i830_update_wm(struct drm_device *dev)
Shaohua Li7662c8b2009-06-26 11:23:55 +08004342{
4343 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond2102462011-01-24 17:43:27 +00004344 struct drm_crtc *crtc;
4345 uint32_t fwater_lo;
Jesse Barnesdff33cf2009-07-14 10:15:56 -07004346 int planea_wm;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004347
Chris Wilsond2102462011-01-24 17:43:27 +00004348 crtc = single_enabled_crtc(dev);
4349 if (crtc == NULL)
4350 return;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004351
Chris Wilsond2102462011-01-24 17:43:27 +00004352 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4353 dev_priv->display.get_fifo_size(dev, 0),
4354 crtc->fb->bits_per_pixel / 8,
4355 latency_ns);
4356 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
Jesse Barnesf3601322009-07-22 12:54:59 -07004357 fwater_lo |= (3<<8) | planea_wm;
4358
Zhao Yakui28c97732009-10-09 11:39:41 +08004359 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004360
4361 I915_WRITE(FW_BLC, fwater_lo);
4362}
4363
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004364#define ILK_LP0_PLANE_LATENCY 700
Zhao Yakuic936f442010-06-12 14:32:26 +08004365#define ILK_LP0_CURSOR_LATENCY 1300
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004366
Jesse Barnesb79d4992010-12-21 13:10:23 -08004367/*
4368 * Check the wm result.
4369 *
4370 * If any calculated watermark values is larger than the maximum value that
4371 * can be programmed into the associated watermark register, that watermark
4372 * must be disabled.
4373 */
4374static bool ironlake_check_srwm(struct drm_device *dev, int level,
4375 int fbc_wm, int display_wm, int cursor_wm,
4376 const struct intel_watermark_params *display,
4377 const struct intel_watermark_params *cursor)
4378{
4379 struct drm_i915_private *dev_priv = dev->dev_private;
4380
4381 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4382 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4383
4384 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4385 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4386 fbc_wm, SNB_FBC_MAX_SRWM, level);
4387
4388 /* fbc has it's own way to disable FBC WM */
4389 I915_WRITE(DISP_ARB_CTL,
4390 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4391 return false;
4392 }
4393
4394 if (display_wm > display->max_wm) {
4395 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4396 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4397 return false;
4398 }
4399
4400 if (cursor_wm > cursor->max_wm) {
4401 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4402 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4403 return false;
4404 }
4405
4406 if (!(fbc_wm || display_wm || cursor_wm)) {
4407 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4408 return false;
4409 }
4410
4411 return true;
4412}
4413
4414/*
4415 * Compute watermark values of WM[1-3],
4416 */
Chris Wilsond2102462011-01-24 17:43:27 +00004417static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4418 int latency_ns,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004419 const struct intel_watermark_params *display,
4420 const struct intel_watermark_params *cursor,
4421 int *fbc_wm, int *display_wm, int *cursor_wm)
4422{
Chris Wilsond2102462011-01-24 17:43:27 +00004423 struct drm_crtc *crtc;
Jesse Barnesb79d4992010-12-21 13:10:23 -08004424 unsigned long line_time_us;
Chris Wilsond2102462011-01-24 17:43:27 +00004425 int hdisplay, htotal, pixel_size, clock;
Jesse Barnesb79d4992010-12-21 13:10:23 -08004426 int line_count, line_size;
4427 int small, large;
4428 int entries;
4429
4430 if (!latency_ns) {
4431 *fbc_wm = *display_wm = *cursor_wm = 0;
4432 return false;
4433 }
4434
Chris Wilsond2102462011-01-24 17:43:27 +00004435 crtc = intel_get_crtc_for_plane(dev, plane);
4436 hdisplay = crtc->mode.hdisplay;
4437 htotal = crtc->mode.htotal;
4438 clock = crtc->mode.clock;
4439 pixel_size = crtc->fb->bits_per_pixel / 8;
4440
Jesse Barnesb79d4992010-12-21 13:10:23 -08004441 line_time_us = (htotal * 1000) / clock;
4442 line_count = (latency_ns / line_time_us + 1000) / 1000;
4443 line_size = hdisplay * pixel_size;
4444
4445 /* Use the minimum of the small and large buffer method for primary */
4446 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4447 large = line_count * line_size;
4448
4449 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4450 *display_wm = entries + display->guard_size;
4451
4452 /*
4453 * Spec says:
4454 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4455 */
4456 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4457
4458 /* calculate the self-refresh watermark for display cursor */
4459 entries = line_count * pixel_size * 64;
4460 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4461 *cursor_wm = entries + cursor->guard_size;
4462
4463 return ironlake_check_srwm(dev, level,
4464 *fbc_wm, *display_wm, *cursor_wm,
4465 display, cursor);
4466}
4467
Chris Wilsond2102462011-01-24 17:43:27 +00004468static void ironlake_update_wm(struct drm_device *dev)
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004469{
4470 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsond2102462011-01-24 17:43:27 +00004471 int fbc_wm, plane_wm, cursor_wm;
4472 unsigned int enabled;
Zhao Yakuic936f442010-06-12 14:32:26 +08004473
Chris Wilson4ed765f2010-09-11 10:46:47 +01004474 enabled = 0;
Chris Wilson9f405102011-05-12 22:17:14 +01004475 if (g4x_compute_wm0(dev, 0,
4476 &ironlake_display_wm_info,
4477 ILK_LP0_PLANE_LATENCY,
4478 &ironlake_cursor_wm_info,
4479 ILK_LP0_CURSOR_LATENCY,
4480 &plane_wm, &cursor_wm)) {
Chris Wilson4ed765f2010-09-11 10:46:47 +01004481 I915_WRITE(WM0_PIPEA_ILK,
4482 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4483 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4484 " plane %d, " "cursor: %d\n",
4485 plane_wm, cursor_wm);
Chris Wilsond2102462011-01-24 17:43:27 +00004486 enabled |= 1;
Zhao Yakuic936f442010-06-12 14:32:26 +08004487 }
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004488
Chris Wilson9f405102011-05-12 22:17:14 +01004489 if (g4x_compute_wm0(dev, 1,
4490 &ironlake_display_wm_info,
4491 ILK_LP0_PLANE_LATENCY,
4492 &ironlake_cursor_wm_info,
4493 ILK_LP0_CURSOR_LATENCY,
4494 &plane_wm, &cursor_wm)) {
Chris Wilson4ed765f2010-09-11 10:46:47 +01004495 I915_WRITE(WM0_PIPEB_ILK,
4496 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4497 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4498 " plane %d, cursor: %d\n",
4499 plane_wm, cursor_wm);
Chris Wilsond2102462011-01-24 17:43:27 +00004500 enabled |= 2;
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004501 }
4502
4503 /*
4504 * Calculate and update the self-refresh watermark only when one
4505 * display plane is used.
4506 */
Jesse Barnesb79d4992010-12-21 13:10:23 -08004507 I915_WRITE(WM3_LP_ILK, 0);
4508 I915_WRITE(WM2_LP_ILK, 0);
4509 I915_WRITE(WM1_LP_ILK, 0);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004510
Chris Wilsond2102462011-01-24 17:43:27 +00004511 if (!single_plane_enabled(enabled))
Jesse Barnesb79d4992010-12-21 13:10:23 -08004512 return;
Chris Wilsond2102462011-01-24 17:43:27 +00004513 enabled = ffs(enabled) - 1;
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08004514
Jesse Barnesb79d4992010-12-21 13:10:23 -08004515 /* WM1 */
Chris Wilsond2102462011-01-24 17:43:27 +00004516 if (!ironlake_compute_srwm(dev, 1, enabled,
4517 ILK_READ_WM1_LATENCY() * 500,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004518 &ironlake_display_srwm_info,
4519 &ironlake_cursor_srwm_info,
4520 &fbc_wm, &plane_wm, &cursor_wm))
4521 return;
Chris Wilson4ed765f2010-09-11 10:46:47 +01004522
Jesse Barnesb79d4992010-12-21 13:10:23 -08004523 I915_WRITE(WM1_LP_ILK,
4524 WM1_LP_SR_EN |
4525 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4526 (fbc_wm << WM1_LP_FBC_SHIFT) |
4527 (plane_wm << WM1_LP_SR_SHIFT) |
4528 cursor_wm);
Chris Wilson4ed765f2010-09-11 10:46:47 +01004529
Jesse Barnesb79d4992010-12-21 13:10:23 -08004530 /* WM2 */
Chris Wilsond2102462011-01-24 17:43:27 +00004531 if (!ironlake_compute_srwm(dev, 2, enabled,
4532 ILK_READ_WM2_LATENCY() * 500,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004533 &ironlake_display_srwm_info,
4534 &ironlake_cursor_srwm_info,
4535 &fbc_wm, &plane_wm, &cursor_wm))
4536 return;
Chris Wilson4ed765f2010-09-11 10:46:47 +01004537
Jesse Barnesb79d4992010-12-21 13:10:23 -08004538 I915_WRITE(WM2_LP_ILK,
4539 WM2_LP_EN |
4540 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4541 (fbc_wm << WM1_LP_FBC_SHIFT) |
4542 (plane_wm << WM1_LP_SR_SHIFT) |
4543 cursor_wm);
Yuanhan Liu13982612010-12-15 15:42:31 +08004544
4545 /*
Jesse Barnesb79d4992010-12-21 13:10:23 -08004546 * WM3 is unsupported on ILK, probably because we don't have latency
4547 * data for that power state
Yuanhan Liu13982612010-12-15 15:42:31 +08004548 */
Yuanhan Liu13982612010-12-15 15:42:31 +08004549}
4550
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004551void sandybridge_update_wm(struct drm_device *dev)
Yuanhan Liu13982612010-12-15 15:42:31 +08004552{
4553 struct drm_i915_private *dev_priv = dev->dev_private;
Yuanhan Liua0fa62d2010-12-23 16:35:40 +08004554 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
Jesse Barnes47842642012-01-16 11:57:54 -08004555 u32 val;
Chris Wilsond2102462011-01-24 17:43:27 +00004556 int fbc_wm, plane_wm, cursor_wm;
4557 unsigned int enabled;
Yuanhan Liu13982612010-12-15 15:42:31 +08004558
4559 enabled = 0;
Chris Wilson9f405102011-05-12 22:17:14 +01004560 if (g4x_compute_wm0(dev, 0,
4561 &sandybridge_display_wm_info, latency,
4562 &sandybridge_cursor_wm_info, latency,
4563 &plane_wm, &cursor_wm)) {
Jesse Barnes47842642012-01-16 11:57:54 -08004564 val = I915_READ(WM0_PIPEA_ILK);
4565 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4566 I915_WRITE(WM0_PIPEA_ILK, val |
4567 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
Yuanhan Liu13982612010-12-15 15:42:31 +08004568 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4569 " plane %d, " "cursor: %d\n",
4570 plane_wm, cursor_wm);
Chris Wilsond2102462011-01-24 17:43:27 +00004571 enabled |= 1;
Yuanhan Liu13982612010-12-15 15:42:31 +08004572 }
4573
Chris Wilson9f405102011-05-12 22:17:14 +01004574 if (g4x_compute_wm0(dev, 1,
4575 &sandybridge_display_wm_info, latency,
4576 &sandybridge_cursor_wm_info, latency,
4577 &plane_wm, &cursor_wm)) {
Jesse Barnes47842642012-01-16 11:57:54 -08004578 val = I915_READ(WM0_PIPEB_ILK);
4579 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4580 I915_WRITE(WM0_PIPEB_ILK, val |
4581 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
Yuanhan Liu13982612010-12-15 15:42:31 +08004582 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4583 " plane %d, cursor: %d\n",
4584 plane_wm, cursor_wm);
Chris Wilsond2102462011-01-24 17:43:27 +00004585 enabled |= 2;
Yuanhan Liu13982612010-12-15 15:42:31 +08004586 }
4587
Jesse Barnesd6c892d2011-10-12 15:36:42 -07004588 /* IVB has 3 pipes */
4589 if (IS_IVYBRIDGE(dev) &&
4590 g4x_compute_wm0(dev, 2,
4591 &sandybridge_display_wm_info, latency,
4592 &sandybridge_cursor_wm_info, latency,
4593 &plane_wm, &cursor_wm)) {
Jesse Barnes47842642012-01-16 11:57:54 -08004594 val = I915_READ(WM0_PIPEC_IVB);
4595 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4596 I915_WRITE(WM0_PIPEC_IVB, val |
4597 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
Jesse Barnesd6c892d2011-10-12 15:36:42 -07004598 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4599 " plane %d, cursor: %d\n",
4600 plane_wm, cursor_wm);
4601 enabled |= 3;
4602 }
4603
Yuanhan Liu13982612010-12-15 15:42:31 +08004604 /*
4605 * Calculate and update the self-refresh watermark only when one
4606 * display plane is used.
4607 *
4608 * SNB support 3 levels of watermark.
4609 *
4610 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4611 * and disabled in the descending order
4612 *
4613 */
4614 I915_WRITE(WM3_LP_ILK, 0);
4615 I915_WRITE(WM2_LP_ILK, 0);
4616 I915_WRITE(WM1_LP_ILK, 0);
4617
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004618 if (!single_plane_enabled(enabled) ||
4619 dev_priv->sprite_scaling_enabled)
Yuanhan Liu13982612010-12-15 15:42:31 +08004620 return;
Chris Wilsond2102462011-01-24 17:43:27 +00004621 enabled = ffs(enabled) - 1;
Yuanhan Liu13982612010-12-15 15:42:31 +08004622
4623 /* WM1 */
Chris Wilsond2102462011-01-24 17:43:27 +00004624 if (!ironlake_compute_srwm(dev, 1, enabled,
4625 SNB_READ_WM1_LATENCY() * 500,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004626 &sandybridge_display_srwm_info,
4627 &sandybridge_cursor_srwm_info,
4628 &fbc_wm, &plane_wm, &cursor_wm))
Yuanhan Liu13982612010-12-15 15:42:31 +08004629 return;
4630
4631 I915_WRITE(WM1_LP_ILK,
4632 WM1_LP_SR_EN |
4633 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4634 (fbc_wm << WM1_LP_FBC_SHIFT) |
4635 (plane_wm << WM1_LP_SR_SHIFT) |
4636 cursor_wm);
4637
4638 /* WM2 */
Chris Wilsond2102462011-01-24 17:43:27 +00004639 if (!ironlake_compute_srwm(dev, 2, enabled,
4640 SNB_READ_WM2_LATENCY() * 500,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004641 &sandybridge_display_srwm_info,
4642 &sandybridge_cursor_srwm_info,
4643 &fbc_wm, &plane_wm, &cursor_wm))
Yuanhan Liu13982612010-12-15 15:42:31 +08004644 return;
4645
4646 I915_WRITE(WM2_LP_ILK,
4647 WM2_LP_EN |
4648 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4649 (fbc_wm << WM1_LP_FBC_SHIFT) |
4650 (plane_wm << WM1_LP_SR_SHIFT) |
4651 cursor_wm);
4652
4653 /* WM3 */
Chris Wilsond2102462011-01-24 17:43:27 +00004654 if (!ironlake_compute_srwm(dev, 3, enabled,
4655 SNB_READ_WM3_LATENCY() * 500,
Jesse Barnesb79d4992010-12-21 13:10:23 -08004656 &sandybridge_display_srwm_info,
4657 &sandybridge_cursor_srwm_info,
4658 &fbc_wm, &plane_wm, &cursor_wm))
Yuanhan Liu13982612010-12-15 15:42:31 +08004659 return;
4660
4661 I915_WRITE(WM3_LP_ILK,
4662 WM3_LP_EN |
4663 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4664 (fbc_wm << WM1_LP_FBC_SHIFT) |
4665 (plane_wm << WM1_LP_SR_SHIFT) |
4666 cursor_wm);
4667}
4668
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004669static bool
4670sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4671 uint32_t sprite_width, int pixel_size,
4672 const struct intel_watermark_params *display,
4673 int display_latency_ns, int *sprite_wm)
4674{
4675 struct drm_crtc *crtc;
4676 int clock;
4677 int entries, tlb_miss;
4678
4679 crtc = intel_get_crtc_for_plane(dev, plane);
4680 if (crtc->fb == NULL || !crtc->enabled) {
4681 *sprite_wm = display->guard_size;
4682 return false;
4683 }
4684
4685 clock = crtc->mode.clock;
4686
4687 /* Use the small buffer method to calculate the sprite watermark */
4688 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4689 tlb_miss = display->fifo_size*display->cacheline_size -
4690 sprite_width * 8;
4691 if (tlb_miss > 0)
4692 entries += tlb_miss;
4693 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4694 *sprite_wm = entries + display->guard_size;
4695 if (*sprite_wm > (int)display->max_wm)
4696 *sprite_wm = display->max_wm;
4697
4698 return true;
4699}
4700
4701static bool
4702sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4703 uint32_t sprite_width, int pixel_size,
4704 const struct intel_watermark_params *display,
4705 int latency_ns, int *sprite_wm)
4706{
4707 struct drm_crtc *crtc;
4708 unsigned long line_time_us;
4709 int clock;
4710 int line_count, line_size;
4711 int small, large;
4712 int entries;
4713
4714 if (!latency_ns) {
4715 *sprite_wm = 0;
4716 return false;
4717 }
4718
4719 crtc = intel_get_crtc_for_plane(dev, plane);
4720 clock = crtc->mode.clock;
4721
4722 line_time_us = (sprite_width * 1000) / clock;
4723 line_count = (latency_ns / line_time_us + 1000) / 1000;
4724 line_size = sprite_width * pixel_size;
4725
4726 /* Use the minimum of the small and large buffer method for primary */
4727 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4728 large = line_count * line_size;
4729
4730 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4731 *sprite_wm = entries + display->guard_size;
4732
4733 return *sprite_wm > 0x3ff ? false : true;
4734}
4735
4736static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4737 uint32_t sprite_width, int pixel_size)
4738{
4739 struct drm_i915_private *dev_priv = dev->dev_private;
4740 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
Jesse Barnes47842642012-01-16 11:57:54 -08004741 u32 val;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004742 int sprite_wm, reg;
4743 int ret;
4744
4745 switch (pipe) {
4746 case 0:
4747 reg = WM0_PIPEA_ILK;
4748 break;
4749 case 1:
4750 reg = WM0_PIPEB_ILK;
4751 break;
4752 case 2:
4753 reg = WM0_PIPEC_IVB;
4754 break;
4755 default:
4756 return; /* bad pipe */
4757 }
4758
4759 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4760 &sandybridge_display_wm_info,
4761 latency, &sprite_wm);
4762 if (!ret) {
4763 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4764 pipe);
4765 return;
4766 }
4767
Jesse Barnes47842642012-01-16 11:57:54 -08004768 val = I915_READ(reg);
4769 val &= ~WM0_PIPE_SPRITE_MASK;
4770 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004771 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4772
4773
4774 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4775 pixel_size,
4776 &sandybridge_display_srwm_info,
4777 SNB_READ_WM1_LATENCY() * 500,
4778 &sprite_wm);
4779 if (!ret) {
4780 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4781 pipe);
4782 return;
4783 }
4784 I915_WRITE(WM1S_LP_ILK, sprite_wm);
4785
4786 /* Only IVB has two more LP watermarks for sprite */
4787 if (!IS_IVYBRIDGE(dev))
4788 return;
4789
4790 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4791 pixel_size,
4792 &sandybridge_display_srwm_info,
4793 SNB_READ_WM2_LATENCY() * 500,
4794 &sprite_wm);
4795 if (!ret) {
4796 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4797 pipe);
4798 return;
4799 }
4800 I915_WRITE(WM2S_LP_IVB, sprite_wm);
4801
4802 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4803 pixel_size,
4804 &sandybridge_display_srwm_info,
4805 SNB_READ_WM3_LATENCY() * 500,
4806 &sprite_wm);
4807 if (!ret) {
4808 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4809 pipe);
4810 return;
4811 }
4812 I915_WRITE(WM3S_LP_IVB, sprite_wm);
4813}
4814
Shaohua Li7662c8b2009-06-26 11:23:55 +08004815/**
4816 * intel_update_watermarks - update FIFO watermark values based on current modes
4817 *
4818 * Calculate watermark values for the various WM regs based on current mode
4819 * and plane configuration.
4820 *
4821 * There are several cases to deal with here:
4822 * - normal (i.e. non-self-refresh)
4823 * - self-refresh (SR) mode
4824 * - lines are large relative to FIFO size (buffer can hold up to 2)
4825 * - lines are small relative to FIFO size (buffer can hold more than 2
4826 * lines), so need to account for TLB latency
4827 *
4828 * The normal calculation is:
4829 * watermark = dotclock * bytes per pixel * latency
4830 * where latency is platform & configuration dependent (we assume pessimal
4831 * values here).
4832 *
4833 * The SR calculation is:
4834 * watermark = (trunc(latency/line time)+1) * surface width *
4835 * bytes per pixel
4836 * where
4837 * line time = htotal / dotclock
Zhao Yakuifa143212010-06-12 14:32:23 +08004838 * surface width = hdisplay for normal plane and 64 for cursor
Shaohua Li7662c8b2009-06-26 11:23:55 +08004839 * and latency is assumed to be high, as above.
4840 *
4841 * The final value programmed to the register should always be rounded up,
4842 * and include an extra 2 entries to account for clock crossings.
4843 *
4844 * We don't use the sprite, so we can ignore that. And on Crestline we have
4845 * to set the non-SR watermarks to 8.
Chris Wilson5eddb702010-09-11 13:48:45 +01004846 */
Shaohua Li7662c8b2009-06-26 11:23:55 +08004847static void intel_update_watermarks(struct drm_device *dev)
4848{
Jesse Barnese70236a2009-09-21 10:42:27 -07004849 struct drm_i915_private *dev_priv = dev->dev_private;
Shaohua Li7662c8b2009-06-26 11:23:55 +08004850
Chris Wilsond2102462011-01-24 17:43:27 +00004851 if (dev_priv->display.update_wm)
4852 dev_priv->display.update_wm(dev);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004853}
4854
Jesse Barnesb840d907f2011-12-13 13:19:38 -08004855void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4856 uint32_t sprite_width, int pixel_size)
4857{
4858 struct drm_i915_private *dev_priv = dev->dev_private;
4859
4860 if (dev_priv->display.update_sprite_wm)
4861 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4862 pixel_size);
4863}
4864
Chris Wilsona7615032011-01-12 17:04:08 +00004865static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4866{
Keith Packard72bbe582011-09-26 16:09:45 -07004867 if (i915_panel_use_ssc >= 0)
4868 return i915_panel_use_ssc != 0;
4869 return dev_priv->lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07004870 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00004871}
4872
Jesse Barnes5a354202011-06-24 12:19:22 -07004873/**
4874 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4875 * @crtc: CRTC structure
Adam Jackson3b5c78a2011-12-13 15:41:00 -08004876 * @mode: requested mode
Jesse Barnes5a354202011-06-24 12:19:22 -07004877 *
4878 * A pipe may be connected to one or more outputs. Based on the depth of the
4879 * attached framebuffer, choose a good color depth to use on the pipe.
4880 *
4881 * If possible, match the pipe depth to the fb depth. In some cases, this
4882 * isn't ideal, because the connected output supports a lesser or restricted
4883 * set of depths. Resolve that here:
4884 * LVDS typically supports only 6bpc, so clamp down in that case
4885 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4886 * Displays may support a restricted set as well, check EDID and clamp as
4887 * appropriate.
Adam Jackson3b5c78a2011-12-13 15:41:00 -08004888 * DP may want to dither down to 6bpc to fit larger modes
Jesse Barnes5a354202011-06-24 12:19:22 -07004889 *
4890 * RETURNS:
4891 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4892 * true if they don't match).
4893 */
4894static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
Adam Jackson3b5c78a2011-12-13 15:41:00 -08004895 unsigned int *pipe_bpp,
4896 struct drm_display_mode *mode)
Jesse Barnes5a354202011-06-24 12:19:22 -07004897{
4898 struct drm_device *dev = crtc->dev;
4899 struct drm_i915_private *dev_priv = dev->dev_private;
4900 struct drm_encoder *encoder;
4901 struct drm_connector *connector;
4902 unsigned int display_bpc = UINT_MAX, bpc;
4903
4904 /* Walk the encoders & connectors on this crtc, get min bpc */
4905 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4906 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4907
4908 if (encoder->crtc != crtc)
4909 continue;
4910
4911 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4912 unsigned int lvds_bpc;
4913
4914 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4915 LVDS_A3_POWER_UP)
4916 lvds_bpc = 8;
4917 else
4918 lvds_bpc = 6;
4919
4920 if (lvds_bpc < display_bpc) {
Adam Jackson82820492011-10-10 16:33:34 -04004921 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
Jesse Barnes5a354202011-06-24 12:19:22 -07004922 display_bpc = lvds_bpc;
4923 }
4924 continue;
4925 }
4926
4927 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4928 /* Use VBT settings if we have an eDP panel */
4929 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4930
4931 if (edp_bpc < display_bpc) {
Adam Jackson82820492011-10-10 16:33:34 -04004932 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
Jesse Barnes5a354202011-06-24 12:19:22 -07004933 display_bpc = edp_bpc;
4934 }
4935 continue;
4936 }
4937
4938 /* Not one of the known troublemakers, check the EDID */
4939 list_for_each_entry(connector, &dev->mode_config.connector_list,
4940 head) {
4941 if (connector->encoder != encoder)
4942 continue;
4943
Jesse Barnes62ac41a2011-07-28 12:55:14 -07004944 /* Don't use an invalid EDID bpc value */
4945 if (connector->display_info.bpc &&
4946 connector->display_info.bpc < display_bpc) {
Adam Jackson82820492011-10-10 16:33:34 -04004947 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
Jesse Barnes5a354202011-06-24 12:19:22 -07004948 display_bpc = connector->display_info.bpc;
4949 }
4950 }
4951
4952 /*
4953 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4954 * through, clamp it down. (Note: >12bpc will be caught below.)
4955 */
4956 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4957 if (display_bpc > 8 && display_bpc < 12) {
Adam Jackson82820492011-10-10 16:33:34 -04004958 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
Jesse Barnes5a354202011-06-24 12:19:22 -07004959 display_bpc = 12;
4960 } else {
Adam Jackson82820492011-10-10 16:33:34 -04004961 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
Jesse Barnes5a354202011-06-24 12:19:22 -07004962 display_bpc = 8;
4963 }
4964 }
4965 }
4966
Adam Jackson3b5c78a2011-12-13 15:41:00 -08004967 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4968 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4969 display_bpc = 6;
4970 }
4971
Jesse Barnes5a354202011-06-24 12:19:22 -07004972 /*
4973 * We could just drive the pipe at the highest bpc all the time and
4974 * enable dithering as needed, but that costs bandwidth. So choose
4975 * the minimum value that expresses the full color range of the fb but
4976 * also stays within the max display bpc discovered above.
4977 */
4978
4979 switch (crtc->fb->depth) {
4980 case 8:
4981 bpc = 8; /* since we go through a colormap */
4982 break;
4983 case 15:
4984 case 16:
4985 bpc = 6; /* min is 18bpp */
4986 break;
4987 case 24:
Keith Packard578393c2011-09-05 11:53:21 -07004988 bpc = 8;
Jesse Barnes5a354202011-06-24 12:19:22 -07004989 break;
4990 case 30:
Keith Packard578393c2011-09-05 11:53:21 -07004991 bpc = 10;
Jesse Barnes5a354202011-06-24 12:19:22 -07004992 break;
4993 case 48:
Keith Packard578393c2011-09-05 11:53:21 -07004994 bpc = 12;
Jesse Barnes5a354202011-06-24 12:19:22 -07004995 break;
4996 default:
4997 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4998 bpc = min((unsigned int)8, display_bpc);
4999 break;
5000 }
5001
Keith Packard578393c2011-09-05 11:53:21 -07005002 display_bpc = min(display_bpc, bpc);
5003
Adam Jackson82820492011-10-10 16:33:34 -04005004 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5005 bpc, display_bpc);
Jesse Barnes5a354202011-06-24 12:19:22 -07005006
Keith Packard578393c2011-09-05 11:53:21 -07005007 *pipe_bpp = display_bpc * 3;
Jesse Barnes5a354202011-06-24 12:19:22 -07005008
5009 return display_bpc != bpc;
5010}
5011
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005012static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5013{
5014 struct drm_device *dev = crtc->dev;
5015 struct drm_i915_private *dev_priv = dev->dev_private;
5016 int refclk;
5017
5018 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5019 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5020 refclk = dev_priv->lvds_ssc_freq * 1000;
5021 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5022 refclk / 1000);
5023 } else if (!IS_GEN2(dev)) {
5024 refclk = 96000;
5025 } else {
5026 refclk = 48000;
5027 }
5028
5029 return refclk;
5030}
5031
5032static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5033 intel_clock_t *clock)
5034{
5035 /* SDVO TV has fixed PLL values depend on its clock range,
5036 this mirrors vbios setting. */
5037 if (adjusted_mode->clock >= 100000
5038 && adjusted_mode->clock < 140500) {
5039 clock->p1 = 2;
5040 clock->p2 = 10;
5041 clock->n = 3;
5042 clock->m1 = 16;
5043 clock->m2 = 8;
5044 } else if (adjusted_mode->clock >= 140500
5045 && adjusted_mode->clock <= 200000) {
5046 clock->p1 = 1;
5047 clock->p2 = 10;
5048 clock->n = 6;
5049 clock->m1 = 12;
5050 clock->m2 = 8;
5051 }
5052}
5053
Jesse Barnesa7516a02011-12-15 12:30:37 -08005054static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5055 intel_clock_t *clock,
5056 intel_clock_t *reduced_clock)
5057{
5058 struct drm_device *dev = crtc->dev;
5059 struct drm_i915_private *dev_priv = dev->dev_private;
5060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5061 int pipe = intel_crtc->pipe;
5062 u32 fp, fp2 = 0;
5063
5064 if (IS_PINEVIEW(dev)) {
5065 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5066 if (reduced_clock)
5067 fp2 = (1 << reduced_clock->n) << 16 |
5068 reduced_clock->m1 << 8 | reduced_clock->m2;
5069 } else {
5070 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5071 if (reduced_clock)
5072 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5073 reduced_clock->m2;
5074 }
5075
5076 I915_WRITE(FP0(pipe), fp);
5077
5078 intel_crtc->lowfreq_avail = false;
5079 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5080 reduced_clock && i915_powersave) {
5081 I915_WRITE(FP1(pipe), fp2);
5082 intel_crtc->lowfreq_avail = true;
5083 } else {
5084 I915_WRITE(FP1(pipe), fp);
5085 }
5086}
5087
Eric Anholtf5640482011-03-30 13:01:02 -07005088static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5089 struct drm_display_mode *mode,
5090 struct drm_display_mode *adjusted_mode,
5091 int x, int y,
5092 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08005093{
5094 struct drm_device *dev = crtc->dev;
5095 struct drm_i915_private *dev_priv = dev->dev_private;
5096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5097 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07005098 int plane = intel_crtc->plane;
Eric Anholtc751ce42010-03-25 11:48:48 -07005099 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07005100 intel_clock_t clock, reduced_clock;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005101 u32 dpll, dspcntr, pipeconf;
Jesse Barnes652c3932009-08-17 13:31:43 -07005102 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07005103 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08005104 struct drm_mode_config *mode_config = &dev->mode_config;
Chris Wilson5eddb702010-09-11 13:48:45 +01005105 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08005106 const intel_limit_t *limit;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00005107 int ret;
Eric Anholtfae14982011-03-30 13:01:09 -07005108 u32 temp;
Bryan Freedaa9b5002011-01-12 13:43:19 -08005109 u32 lvds_sync = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08005110
Chris Wilson5eddb702010-09-11 13:48:45 +01005111 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5112 if (encoder->base.crtc != crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08005113 continue;
5114
Chris Wilson5eddb702010-09-11 13:48:45 +01005115 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005116 case INTEL_OUTPUT_LVDS:
5117 is_lvds = true;
5118 break;
5119 case INTEL_OUTPUT_SDVO:
Eric Anholt7d573822009-01-02 13:33:00 -08005120 case INTEL_OUTPUT_HDMI:
Jesse Barnes79e53942008-11-07 14:24:08 -08005121 is_sdvo = true;
Chris Wilson5eddb702010-09-11 13:48:45 +01005122 if (encoder->needs_tv_clock)
Jesse Barnese2f0ba92009-02-02 15:11:52 -08005123 is_tv = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08005124 break;
5125 case INTEL_OUTPUT_DVO:
5126 is_dvo = true;
5127 break;
5128 case INTEL_OUTPUT_TVOUT:
5129 is_tv = true;
5130 break;
5131 case INTEL_OUTPUT_ANALOG:
5132 is_crt = true;
5133 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07005134 case INTEL_OUTPUT_DISPLAYPORT:
5135 is_dp = true;
5136 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08005137 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05005138
Eric Anholtc751ce42010-03-25 11:48:48 -07005139 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08005140 }
5141
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005142 refclk = i9xx_get_refclk(crtc, num_connectors);
Jesse Barnes79e53942008-11-07 14:24:08 -08005143
Ma Lingd4906092009-03-18 20:13:27 +08005144 /*
5145 * Returns a set of divisors for the desired target clock with the given
5146 * refclk, or FALSE. The returned values represent the clock equation:
5147 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5148 */
Chris Wilson1b894b52010-12-14 20:04:54 +00005149 limit = intel_limit(crtc, refclk);
Sean Paulcec2f352012-01-10 15:09:36 -08005150 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5151 &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005152 if (!ok) {
5153 DRM_ERROR("Couldn't find PLL settings for mode!\n");
Eric Anholtf5640482011-03-30 13:01:02 -07005154 return -EINVAL;
5155 }
5156
5157 /* Ensure that the cursor is valid for the new mode before changing... */
5158 intel_crtc_update_cursor(crtc, true);
5159
5160 if (is_lvds && dev_priv->lvds_downclock_avail) {
Sean Paulcec2f352012-01-10 15:09:36 -08005161 /*
5162 * Ensure we match the reduced clock's P to the target clock.
5163 * If the clocks don't match, we can't switch the display clock
5164 * by using the FP0/FP1. In such case we will disable the LVDS
5165 * downclock feature.
5166 */
Eric Anholtf5640482011-03-30 13:01:02 -07005167 has_reduced_clock = limit->find_pll(limit, crtc,
5168 dev_priv->lvds_downclock,
5169 refclk,
Sean Paulcec2f352012-01-10 15:09:36 -08005170 &clock,
Eric Anholtf5640482011-03-30 13:01:02 -07005171 &reduced_clock);
Eric Anholtf5640482011-03-30 13:01:02 -07005172 }
Jesse Barnesc65d77d2011-12-15 12:30:36 -08005173
5174 if (is_sdvo && is_tv)
5175 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
Eric Anholtf5640482011-03-30 13:01:02 -07005176
Jesse Barnesa7516a02011-12-15 12:30:37 -08005177 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5178 &reduced_clock : NULL);
Eric Anholtf5640482011-03-30 13:01:02 -07005179
Eric Anholt929c77f2011-03-30 13:01:04 -07005180 dpll = DPLL_VGA_MODE_DIS;
Eric Anholtf5640482011-03-30 13:01:02 -07005181
5182 if (!IS_GEN2(dev)) {
5183 if (is_lvds)
5184 dpll |= DPLLB_MODE_LVDS;
5185 else
5186 dpll |= DPLLB_MODE_DAC_SERIAL;
5187 if (is_sdvo) {
5188 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5189 if (pixel_multiplier > 1) {
5190 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5191 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
Eric Anholtf5640482011-03-30 13:01:02 -07005192 }
5193 dpll |= DPLL_DVO_HIGH_SPEED;
5194 }
Eric Anholt929c77f2011-03-30 13:01:04 -07005195 if (is_dp)
Eric Anholtf5640482011-03-30 13:01:02 -07005196 dpll |= DPLL_DVO_HIGH_SPEED;
5197
5198 /* compute bitmask from p1 value */
5199 if (IS_PINEVIEW(dev))
5200 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5201 else {
5202 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
Eric Anholtf5640482011-03-30 13:01:02 -07005203 if (IS_G4X(dev) && has_reduced_clock)
5204 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5205 }
5206 switch (clock.p2) {
5207 case 5:
5208 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5209 break;
5210 case 7:
5211 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5212 break;
5213 case 10:
5214 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5215 break;
5216 case 14:
5217 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5218 break;
5219 }
Eric Anholt929c77f2011-03-30 13:01:04 -07005220 if (INTEL_INFO(dev)->gen >= 4)
Eric Anholtf5640482011-03-30 13:01:02 -07005221 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5222 } else {
5223 if (is_lvds) {
5224 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5225 } else {
5226 if (clock.p1 == 2)
5227 dpll |= PLL_P1_DIVIDE_BY_TWO;
5228 else
5229 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5230 if (clock.p2 == 4)
5231 dpll |= PLL_P2_DIVIDE_BY_4;
5232 }
5233 }
5234
5235 if (is_sdvo && is_tv)
5236 dpll |= PLL_REF_INPUT_TVCLKINBC;
5237 else if (is_tv)
5238 /* XXX: just matching BIOS for now */
5239 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5240 dpll |= 3;
5241 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5242 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5243 else
5244 dpll |= PLL_REF_INPUT_DREFCLK;
5245
5246 /* setup pipeconf */
5247 pipeconf = I915_READ(PIPECONF(pipe));
5248
5249 /* Set up the display plane register */
5250 dspcntr = DISPPLANE_GAMMA_ENABLE;
5251
Eric Anholt929c77f2011-03-30 13:01:04 -07005252 if (pipe == 0)
5253 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5254 else
5255 dspcntr |= DISPPLANE_SEL_PIPE_B;
Eric Anholtf5640482011-03-30 13:01:02 -07005256
5257 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5258 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5259 * core speed.
5260 *
5261 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5262 * pipe == 0 check?
5263 */
5264 if (mode->clock >
5265 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5266 pipeconf |= PIPECONF_DOUBLE_WIDE;
5267 else
5268 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5269 }
5270
Adam Jackson3b5c78a2011-12-13 15:41:00 -08005271 /* default to 8bpc */
5272 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5273 if (is_dp) {
5274 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5275 pipeconf |= PIPECONF_BPP_6 |
5276 PIPECONF_DITHER_EN |
5277 PIPECONF_DITHER_TYPE_SP;
5278 }
5279 }
5280
Eric Anholt929c77f2011-03-30 13:01:04 -07005281 dpll |= DPLL_VCO_ENABLE;
Eric Anholtf5640482011-03-30 13:01:02 -07005282
5283 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5284 drm_mode_debug_printmodeline(mode);
5285
Eric Anholtfae14982011-03-30 13:01:09 -07005286 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
Eric Anholtf5640482011-03-30 13:01:02 -07005287
Eric Anholtfae14982011-03-30 13:01:09 -07005288 POSTING_READ(DPLL(pipe));
Eric Anholtc713bb02011-03-30 13:01:05 -07005289 udelay(150);
Eric Anholtf5640482011-03-30 13:01:02 -07005290
Eric Anholtf5640482011-03-30 13:01:02 -07005291 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5292 * This is an exception to the general rule that mode_set doesn't turn
5293 * things on.
5294 */
5295 if (is_lvds) {
Eric Anholtfae14982011-03-30 13:01:09 -07005296 temp = I915_READ(LVDS);
Eric Anholtf5640482011-03-30 13:01:02 -07005297 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5298 if (pipe == 1) {
Eric Anholt929c77f2011-03-30 13:01:04 -07005299 temp |= LVDS_PIPEB_SELECT;
Eric Anholtf5640482011-03-30 13:01:02 -07005300 } else {
Eric Anholt929c77f2011-03-30 13:01:04 -07005301 temp &= ~LVDS_PIPEB_SELECT;
Eric Anholtf5640482011-03-30 13:01:02 -07005302 }
5303 /* set the corresponsding LVDS_BORDER bit */
5304 temp |= dev_priv->lvds_border_bits;
5305 /* Set the B0-B3 data pairs corresponding to whether we're going to
5306 * set the DPLLs for dual-channel mode or not.
5307 */
5308 if (clock.p2 == 7)
5309 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5310 else
5311 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5312
5313 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5314 * appropriately here, but we need to look more thoroughly into how
5315 * panels behave in the two modes.
5316 */
Eric Anholt929c77f2011-03-30 13:01:04 -07005317 /* set the dithering flag on LVDS as needed */
5318 if (INTEL_INFO(dev)->gen >= 4) {
Eric Anholtf5640482011-03-30 13:01:02 -07005319 if (dev_priv->lvds_dither)
5320 temp |= LVDS_ENABLE_DITHER;
5321 else
5322 temp &= ~LVDS_ENABLE_DITHER;
5323 }
5324 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5325 lvds_sync |= LVDS_HSYNC_POLARITY;
5326 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5327 lvds_sync |= LVDS_VSYNC_POLARITY;
5328 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5329 != lvds_sync) {
5330 char flags[2] = "-+";
5331 DRM_INFO("Changing LVDS panel from "
5332 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5333 flags[!(temp & LVDS_HSYNC_POLARITY)],
5334 flags[!(temp & LVDS_VSYNC_POLARITY)],
5335 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5336 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5337 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5338 temp |= lvds_sync;
5339 }
Eric Anholtfae14982011-03-30 13:01:09 -07005340 I915_WRITE(LVDS, temp);
Eric Anholtf5640482011-03-30 13:01:02 -07005341 }
5342
Eric Anholt929c77f2011-03-30 13:01:04 -07005343 if (is_dp) {
Eric Anholtf5640482011-03-30 13:01:02 -07005344 intel_dp_set_m_n(crtc, mode, adjusted_mode);
Eric Anholtf5640482011-03-30 13:01:02 -07005345 }
5346
Eric Anholtfae14982011-03-30 13:01:09 -07005347 I915_WRITE(DPLL(pipe), dpll);
Eric Anholtf5640482011-03-30 13:01:02 -07005348
Eric Anholtc713bb02011-03-30 13:01:05 -07005349 /* Wait for the clocks to stabilize. */
Eric Anholtfae14982011-03-30 13:01:09 -07005350 POSTING_READ(DPLL(pipe));
Eric Anholtc713bb02011-03-30 13:01:05 -07005351 udelay(150);
Eric Anholtf5640482011-03-30 13:01:02 -07005352
Eric Anholtc713bb02011-03-30 13:01:05 -07005353 if (INTEL_INFO(dev)->gen >= 4) {
5354 temp = 0;
5355 if (is_sdvo) {
5356 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5357 if (temp > 1)
5358 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5359 else
5360 temp = 0;
Eric Anholtf5640482011-03-30 13:01:02 -07005361 }
Eric Anholtc713bb02011-03-30 13:01:05 -07005362 I915_WRITE(DPLL_MD(pipe), temp);
5363 } else {
5364 /* The pixel multiplier can only be updated once the
5365 * DPLL is enabled and the clocks are stable.
5366 *
5367 * So write it again.
5368 */
Eric Anholtfae14982011-03-30 13:01:09 -07005369 I915_WRITE(DPLL(pipe), dpll);
Eric Anholtf5640482011-03-30 13:01:02 -07005370 }
5371
Jesse Barnesa7516a02011-12-15 12:30:37 -08005372 if (HAS_PIPE_CXSR(dev)) {
5373 if (intel_crtc->lowfreq_avail) {
Eric Anholtf5640482011-03-30 13:01:02 -07005374 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5375 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
Jesse Barnesa7516a02011-12-15 12:30:37 -08005376 } else {
Eric Anholtf5640482011-03-30 13:01:02 -07005377 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5378 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5379 }
5380 }
5381
5382 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5383 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5384 /* the chip adds 2 halflines automatically */
5385 adjusted_mode->crtc_vdisplay -= 1;
5386 adjusted_mode->crtc_vtotal -= 1;
5387 adjusted_mode->crtc_vblank_start -= 1;
5388 adjusted_mode->crtc_vblank_end -= 1;
5389 adjusted_mode->crtc_vsync_end -= 1;
5390 adjusted_mode->crtc_vsync_start -= 1;
5391 } else
Christian Schmidt59df7b12011-12-19 20:03:33 +01005392 pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */
Eric Anholtf5640482011-03-30 13:01:02 -07005393
5394 I915_WRITE(HTOTAL(pipe),
5395 (adjusted_mode->crtc_hdisplay - 1) |
5396 ((adjusted_mode->crtc_htotal - 1) << 16));
5397 I915_WRITE(HBLANK(pipe),
5398 (adjusted_mode->crtc_hblank_start - 1) |
5399 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5400 I915_WRITE(HSYNC(pipe),
5401 (adjusted_mode->crtc_hsync_start - 1) |
5402 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5403
5404 I915_WRITE(VTOTAL(pipe),
5405 (adjusted_mode->crtc_vdisplay - 1) |
5406 ((adjusted_mode->crtc_vtotal - 1) << 16));
5407 I915_WRITE(VBLANK(pipe),
5408 (adjusted_mode->crtc_vblank_start - 1) |
5409 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5410 I915_WRITE(VSYNC(pipe),
5411 (adjusted_mode->crtc_vsync_start - 1) |
5412 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5413
5414 /* pipesrc and dspsize control the size that is scaled from,
5415 * which should always be the user's requested size.
5416 */
Eric Anholt929c77f2011-03-30 13:01:04 -07005417 I915_WRITE(DSPSIZE(plane),
5418 ((mode->vdisplay - 1) << 16) |
5419 (mode->hdisplay - 1));
5420 I915_WRITE(DSPPOS(plane), 0);
Eric Anholtf5640482011-03-30 13:01:02 -07005421 I915_WRITE(PIPESRC(pipe),
5422 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5423
Eric Anholtf5640482011-03-30 13:01:02 -07005424 I915_WRITE(PIPECONF(pipe), pipeconf);
5425 POSTING_READ(PIPECONF(pipe));
Eric Anholt929c77f2011-03-30 13:01:04 -07005426 intel_enable_pipe(dev_priv, pipe, false);
Eric Anholtf5640482011-03-30 13:01:02 -07005427
5428 intel_wait_for_vblank(dev, pipe);
5429
Eric Anholtf5640482011-03-30 13:01:02 -07005430 I915_WRITE(DSPCNTR(plane), dspcntr);
5431 POSTING_READ(DSPCNTR(plane));
Keith Packard284d9522011-06-06 17:12:49 -07005432 intel_enable_plane(dev_priv, plane, pipe);
Eric Anholtf5640482011-03-30 13:01:02 -07005433
5434 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5435
5436 intel_update_watermarks(dev);
5437
Eric Anholtf5640482011-03-30 13:01:02 -07005438 return ret;
5439}
5440
Keith Packard9fb526d2011-09-26 22:24:57 -07005441/*
5442 * Initialize reference clocks when the driver loads
5443 */
5444void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07005445{
5446 struct drm_i915_private *dev_priv = dev->dev_private;
5447 struct drm_mode_config *mode_config = &dev->mode_config;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005448 struct intel_encoder *encoder;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005449 u32 temp;
5450 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07005451 bool has_cpu_edp = false;
5452 bool has_pch_edp = false;
5453 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07005454 bool has_ck505 = false;
5455 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005456
5457 /* We need to take the global config into account */
Keith Packard199e5d72011-09-22 12:01:57 -07005458 list_for_each_entry(encoder, &mode_config->encoder_list,
5459 base.head) {
5460 switch (encoder->type) {
5461 case INTEL_OUTPUT_LVDS:
5462 has_panel = true;
5463 has_lvds = true;
5464 break;
5465 case INTEL_OUTPUT_EDP:
5466 has_panel = true;
5467 if (intel_encoder_is_pch_edp(&encoder->base))
5468 has_pch_edp = true;
5469 else
5470 has_cpu_edp = true;
5471 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005472 }
5473 }
5474
Keith Packard99eb6a02011-09-26 14:29:12 -07005475 if (HAS_PCH_IBX(dev)) {
5476 has_ck505 = dev_priv->display_clock_mode;
5477 can_ssc = has_ck505;
5478 } else {
5479 has_ck505 = false;
5480 can_ssc = true;
5481 }
5482
5483 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5484 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5485 has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07005486
5487 /* Ironlake: try to setup display ref clock before DPLL
5488 * enabling. This is only under driver's control after
5489 * PCH B stepping, previous chipset stepping should be
5490 * ignoring this setting.
5491 */
5492 temp = I915_READ(PCH_DREF_CONTROL);
5493 /* Always enable nonspread source */
5494 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005495
Keith Packard99eb6a02011-09-26 14:29:12 -07005496 if (has_ck505)
5497 temp |= DREF_NONSPREAD_CK505_ENABLE;
5498 else
5499 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005500
Keith Packard199e5d72011-09-22 12:01:57 -07005501 if (has_panel) {
5502 temp &= ~DREF_SSC_SOURCE_MASK;
5503 temp |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005504
Keith Packard199e5d72011-09-22 12:01:57 -07005505 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07005506 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07005507 DRM_DEBUG_KMS("Using SSC on panel\n");
Jesse Barnes13d83a62011-08-03 12:59:20 -07005508 temp |= DREF_SSC1_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07005509 }
Keith Packard199e5d72011-09-22 12:01:57 -07005510
5511 /* Get SSC going before enabling the outputs */
5512 I915_WRITE(PCH_DREF_CONTROL, temp);
5513 POSTING_READ(PCH_DREF_CONTROL);
5514 udelay(200);
5515
Jesse Barnes13d83a62011-08-03 12:59:20 -07005516 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5517
5518 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07005519 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07005520 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07005521 DRM_DEBUG_KMS("Using SSC on eDP\n");
Jesse Barnes13d83a62011-08-03 12:59:20 -07005522 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07005523 }
Jesse Barnes13d83a62011-08-03 12:59:20 -07005524 else
5525 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07005526 } else
5527 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5528
5529 I915_WRITE(PCH_DREF_CONTROL, temp);
5530 POSTING_READ(PCH_DREF_CONTROL);
5531 udelay(200);
5532 } else {
5533 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5534
5535 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5536
5537 /* Turn off CPU output */
5538 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5539
5540 I915_WRITE(PCH_DREF_CONTROL, temp);
5541 POSTING_READ(PCH_DREF_CONTROL);
5542 udelay(200);
5543
5544 /* Turn off the SSC source */
5545 temp &= ~DREF_SSC_SOURCE_MASK;
5546 temp |= DREF_SSC_SOURCE_DISABLE;
5547
5548 /* Turn off SSC1 */
5549 temp &= ~ DREF_SSC1_ENABLE;
5550
Jesse Barnes13d83a62011-08-03 12:59:20 -07005551 I915_WRITE(PCH_DREF_CONTROL, temp);
5552 POSTING_READ(PCH_DREF_CONTROL);
5553 udelay(200);
5554 }
5555}
5556
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005557static int ironlake_get_refclk(struct drm_crtc *crtc)
5558{
5559 struct drm_device *dev = crtc->dev;
5560 struct drm_i915_private *dev_priv = dev->dev_private;
5561 struct intel_encoder *encoder;
5562 struct drm_mode_config *mode_config = &dev->mode_config;
5563 struct intel_encoder *edp_encoder = NULL;
5564 int num_connectors = 0;
5565 bool is_lvds = false;
5566
5567 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5568 if (encoder->base.crtc != crtc)
5569 continue;
5570
5571 switch (encoder->type) {
5572 case INTEL_OUTPUT_LVDS:
5573 is_lvds = true;
5574 break;
5575 case INTEL_OUTPUT_EDP:
5576 edp_encoder = encoder;
5577 break;
5578 }
5579 num_connectors++;
5580 }
5581
5582 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5583 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5584 dev_priv->lvds_ssc_freq);
5585 return dev_priv->lvds_ssc_freq * 1000;
5586 }
5587
5588 return 120000;
5589}
5590
Eric Anholtf5640482011-03-30 13:01:02 -07005591static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5592 struct drm_display_mode *mode,
5593 struct drm_display_mode *adjusted_mode,
5594 int x, int y,
5595 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08005596{
5597 struct drm_device *dev = crtc->dev;
5598 struct drm_i915_private *dev_priv = dev->dev_private;
5599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5600 int pipe = intel_crtc->pipe;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00005601 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08005602 int refclk, num_connectors = 0;
5603 intel_clock_t clock, reduced_clock;
5604 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
Eric Anholta07d6782011-03-30 13:01:08 -07005605 bool ok, has_reduced_clock = false, is_sdvo = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08005606 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5607 struct intel_encoder *has_edp_encoder = NULL;
5608 struct drm_mode_config *mode_config = &dev->mode_config;
5609 struct intel_encoder *encoder;
5610 const intel_limit_t *limit;
5611 int ret;
5612 struct fdi_m_n m_n = {0};
Eric Anholtfae14982011-03-30 13:01:09 -07005613 u32 temp;
Jesse Barnes79e53942008-11-07 14:24:08 -08005614 u32 lvds_sync = 0;
Jesse Barnes5a354202011-06-24 12:19:22 -07005615 int target_clock, pixel_multiplier, lane, link_bw, factor;
5616 unsigned int pipe_bpp;
5617 bool dither;
Jesse Barnes79e53942008-11-07 14:24:08 -08005618
Jesse Barnes79e53942008-11-07 14:24:08 -08005619 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5620 if (encoder->base.crtc != crtc)
5621 continue;
5622
5623 switch (encoder->type) {
5624 case INTEL_OUTPUT_LVDS:
5625 is_lvds = true;
5626 break;
5627 case INTEL_OUTPUT_SDVO:
5628 case INTEL_OUTPUT_HDMI:
5629 is_sdvo = true;
5630 if (encoder->needs_tv_clock)
5631 is_tv = true;
5632 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08005633 case INTEL_OUTPUT_TVOUT:
5634 is_tv = true;
5635 break;
5636 case INTEL_OUTPUT_ANALOG:
5637 is_crt = true;
5638 break;
5639 case INTEL_OUTPUT_DISPLAYPORT:
5640 is_dp = true;
5641 break;
5642 case INTEL_OUTPUT_EDP:
5643 has_edp_encoder = encoder;
5644 break;
5645 }
5646
Kristian Høgsberg43565a02009-02-13 20:56:52 -05005647 num_connectors++;
5648 }
5649
Jesse Barnesd9d444c2011-09-02 13:03:05 -07005650 refclk = ironlake_get_refclk(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005651
5652 /*
5653 * Returns a set of divisors for the desired target clock with the given
5654 * refclk, or FALSE. The returned values represent the clock equation:
5655 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5656 */
5657 limit = intel_limit(crtc, refclk);
Sean Paulcec2f352012-01-10 15:09:36 -08005658 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5659 &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005660 if (!ok) {
5661 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5662 return -EINVAL;
5663 }
5664
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005665 /* Ensure that the cursor is valid for the new mode before changing... */
Chris Wilson6b383a72010-09-13 13:54:26 +01005666 intel_crtc_update_cursor(crtc, true);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005667
Zhao Yakuiddc90032010-01-06 22:05:56 +08005668 if (is_lvds && dev_priv->lvds_downclock_avail) {
Sean Paulcec2f352012-01-10 15:09:36 -08005669 /*
5670 * Ensure we match the reduced clock's P to the target clock.
5671 * If the clocks don't match, we can't switch the display clock
5672 * by using the FP0/FP1. In such case we will disable the LVDS
5673 * downclock feature.
5674 */
Zhao Yakuiddc90032010-01-06 22:05:56 +08005675 has_reduced_clock = limit->find_pll(limit, crtc,
Chris Wilson5eddb702010-09-11 13:48:45 +01005676 dev_priv->lvds_downclock,
5677 refclk,
Sean Paulcec2f352012-01-10 15:09:36 -08005678 &clock,
Chris Wilson5eddb702010-09-11 13:48:45 +01005679 &reduced_clock);
Jesse Barnes652c3932009-08-17 13:31:43 -07005680 }
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08005681 /* SDVO TV has fixed PLL values depend on its clock range,
5682 this mirrors vbios setting. */
5683 if (is_sdvo && is_tv) {
5684 if (adjusted_mode->clock >= 100000
Chris Wilson5eddb702010-09-11 13:48:45 +01005685 && adjusted_mode->clock < 140500) {
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08005686 clock.p1 = 2;
5687 clock.p2 = 10;
5688 clock.n = 3;
5689 clock.m1 = 16;
5690 clock.m2 = 8;
5691 } else if (adjusted_mode->clock >= 140500
Chris Wilson5eddb702010-09-11 13:48:45 +01005692 && adjusted_mode->clock <= 200000) {
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08005693 clock.p1 = 1;
5694 clock.p2 = 10;
5695 clock.n = 6;
5696 clock.m1 = 12;
5697 clock.m2 = 8;
5698 }
5699 }
5700
Zhenyu Wang2c072452009-06-05 15:38:42 +08005701 /* FDI link */
Eric Anholt8febb292011-03-30 13:01:07 -07005702 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5703 lane = 0;
5704 /* CPU eDP doesn't require FDI link, so just set DP M/N
5705 according to current link config */
5706 if (has_edp_encoder &&
5707 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5708 target_clock = mode->clock;
5709 intel_edp_link_config(has_edp_encoder,
5710 &lane, &link_bw);
5711 } else {
5712 /* [e]DP over FDI requires target mode clock
5713 instead of link clock */
5714 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08005715 target_clock = mode->clock;
Eric Anholt8febb292011-03-30 13:01:07 -07005716 else
5717 target_clock = adjusted_mode->clock;
Chris Wilson021357a2010-09-07 20:54:59 +01005718
Eric Anholt8febb292011-03-30 13:01:07 -07005719 /* FDI is a binary signal running at ~2.7GHz, encoding
5720 * each output octet as 10 bits. The actual frequency
5721 * is stored as a divider into a 100MHz clock, and the
5722 * mode pixel clock is stored in units of 1KHz.
5723 * Hence the bw of each lane in terms of the mode signal
5724 * is:
5725 */
5726 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08005727 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08005728
Eric Anholt8febb292011-03-30 13:01:07 -07005729 /* determine panel color depth */
5730 temp = I915_READ(PIPECONF(pipe));
5731 temp &= ~PIPE_BPC_MASK;
Adam Jackson3b5c78a2011-12-13 15:41:00 -08005732 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
Jesse Barnes5a354202011-06-24 12:19:22 -07005733 switch (pipe_bpp) {
5734 case 18:
5735 temp |= PIPE_6BPC;
5736 break;
5737 case 24:
Eric Anholt8febb292011-03-30 13:01:07 -07005738 temp |= PIPE_8BPC;
Eric Anholt8febb292011-03-30 13:01:07 -07005739 break;
Jesse Barnes5a354202011-06-24 12:19:22 -07005740 case 30:
5741 temp |= PIPE_10BPC;
Eric Anholt8febb292011-03-30 13:01:07 -07005742 break;
Jesse Barnes5a354202011-06-24 12:19:22 -07005743 case 36:
5744 temp |= PIPE_12BPC;
Eric Anholt8febb292011-03-30 13:01:07 -07005745 break;
5746 default:
Jesse Barnes62ac41a2011-07-28 12:55:14 -07005747 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5748 pipe_bpp);
Jesse Barnes5a354202011-06-24 12:19:22 -07005749 temp |= PIPE_8BPC;
5750 pipe_bpp = 24;
5751 break;
Eric Anholt8febb292011-03-30 13:01:07 -07005752 }
5753
Jesse Barnes5a354202011-06-24 12:19:22 -07005754 intel_crtc->bpp = pipe_bpp;
5755 I915_WRITE(PIPECONF(pipe), temp);
5756
Eric Anholt8febb292011-03-30 13:01:07 -07005757 if (!lane) {
5758 /*
5759 * Account for spread spectrum to avoid
5760 * oversubscribing the link. Max center spread
5761 * is 2.5%; use 5% for safety's sake.
5762 */
Jesse Barnes5a354202011-06-24 12:19:22 -07005763 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
Eric Anholt8febb292011-03-30 13:01:07 -07005764 lane = bps / (link_bw * 8) + 1;
5765 }
5766
5767 intel_crtc->fdi_lanes = lane;
5768
5769 if (pixel_multiplier > 1)
5770 link_bw *= pixel_multiplier;
Jesse Barnes5a354202011-06-24 12:19:22 -07005771 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5772 &m_n);
Eric Anholt8febb292011-03-30 13:01:07 -07005773
Eric Anholta07d6782011-03-30 13:01:08 -07005774 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5775 if (has_reduced_clock)
5776 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5777 reduced_clock.m2;
Jesse Barnes79e53942008-11-07 14:24:08 -08005778
Chris Wilsonc1858122010-12-03 21:35:48 +00005779 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07005780 factor = 21;
5781 if (is_lvds) {
5782 if ((intel_panel_use_ssc(dev_priv) &&
5783 dev_priv->lvds_ssc_freq == 100) ||
5784 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5785 factor = 25;
5786 } else if (is_sdvo && is_tv)
5787 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00005788
Jesse Barnescb0e0932011-07-28 14:50:30 -07005789 if (clock.m < factor * clock.n)
Eric Anholt8febb292011-03-30 13:01:07 -07005790 fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00005791
Chris Wilson5eddb702010-09-11 13:48:45 +01005792 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08005793
Eric Anholta07d6782011-03-30 13:01:08 -07005794 if (is_lvds)
5795 dpll |= DPLLB_MODE_LVDS;
5796 else
5797 dpll |= DPLLB_MODE_DAC_SERIAL;
5798 if (is_sdvo) {
5799 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5800 if (pixel_multiplier > 1) {
5801 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08005802 }
Eric Anholta07d6782011-03-30 13:01:08 -07005803 dpll |= DPLL_DVO_HIGH_SPEED;
5804 }
5805 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5806 dpll |= DPLL_DVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08005807
Eric Anholta07d6782011-03-30 13:01:08 -07005808 /* compute bitmask from p1 value */
5809 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5810 /* also FPA1 */
5811 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5812
5813 switch (clock.p2) {
5814 case 5:
5815 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5816 break;
5817 case 7:
5818 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5819 break;
5820 case 10:
5821 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5822 break;
5823 case 14:
5824 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5825 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08005826 }
5827
5828 if (is_sdvo && is_tv)
5829 dpll |= PLL_REF_INPUT_TVCLKINBC;
5830 else if (is_tv)
5831 /* XXX: just matching BIOS for now */
5832 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5833 dpll |= 3;
Chris Wilsona7615032011-01-12 17:04:08 +00005834 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Jesse Barnes79e53942008-11-07 14:24:08 -08005835 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5836 else
5837 dpll |= PLL_REF_INPUT_DREFCLK;
5838
5839 /* setup pipeconf */
Chris Wilson5eddb702010-09-11 13:48:45 +01005840 pipeconf = I915_READ(PIPECONF(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005841
5842 /* Set up the display plane register */
5843 dspcntr = DISPPLANE_GAMMA_ENABLE;
5844
Jesse Barnesf7cb34d2011-10-12 10:49:14 -07005845 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005846 drm_mode_debug_printmodeline(mode);
5847
Jesse Barnes5c5313c2010-10-07 16:01:11 -07005848 /* PCH eDP needs FDI, but CPU eDP does not */
Jesse Barnes4b645f12011-10-12 09:51:31 -07005849 if (!intel_crtc->no_pll) {
5850 if (!has_edp_encoder ||
5851 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5852 I915_WRITE(PCH_FP0(pipe), fp);
5853 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01005854
Jesse Barnes4b645f12011-10-12 09:51:31 -07005855 POSTING_READ(PCH_DPLL(pipe));
5856 udelay(150);
5857 }
5858 } else {
5859 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5860 fp == I915_READ(PCH_FP0(0))) {
5861 intel_crtc->use_pll_a = true;
5862 DRM_DEBUG_KMS("using pipe a dpll\n");
5863 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5864 fp == I915_READ(PCH_FP0(1))) {
5865 intel_crtc->use_pll_a = false;
5866 DRM_DEBUG_KMS("using pipe b dpll\n");
5867 } else {
5868 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5869 return -EINVAL;
5870 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005871 }
5872
5873 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5874 * This is an exception to the general rule that mode_set doesn't turn
5875 * things on.
5876 */
5877 if (is_lvds) {
Eric Anholtfae14982011-03-30 13:01:09 -07005878 temp = I915_READ(PCH_LVDS);
Chris Wilson5eddb702010-09-11 13:48:45 +01005879 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
Jesse Barnes4b645f12011-10-12 09:51:31 -07005880 if (HAS_PCH_CPT(dev))
5881 temp |= PORT_TRANS_SEL_CPT(pipe);
5882 else if (pipe == 1)
5883 temp |= LVDS_PIPEB_SELECT;
5884 else
5885 temp &= ~LVDS_PIPEB_SELECT;
5886
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08005887 /* set the corresponsding LVDS_BORDER bit */
Chris Wilson5eddb702010-09-11 13:48:45 +01005888 temp |= dev_priv->lvds_border_bits;
Jesse Barnes79e53942008-11-07 14:24:08 -08005889 /* Set the B0-B3 data pairs corresponding to whether we're going to
5890 * set the DPLLs for dual-channel mode or not.
5891 */
5892 if (clock.p2 == 7)
Chris Wilson5eddb702010-09-11 13:48:45 +01005893 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
Jesse Barnes79e53942008-11-07 14:24:08 -08005894 else
Chris Wilson5eddb702010-09-11 13:48:45 +01005895 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
Jesse Barnes79e53942008-11-07 14:24:08 -08005896
5897 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5898 * appropriately here, but we need to look more thoroughly into how
5899 * panels behave in the two modes.
5900 */
Bryan Freedaa9b5002011-01-12 13:43:19 -08005901 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5902 lvds_sync |= LVDS_HSYNC_POLARITY;
5903 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5904 lvds_sync |= LVDS_VSYNC_POLARITY;
5905 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5906 != lvds_sync) {
5907 char flags[2] = "-+";
5908 DRM_INFO("Changing LVDS panel from "
5909 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5910 flags[!(temp & LVDS_HSYNC_POLARITY)],
5911 flags[!(temp & LVDS_VSYNC_POLARITY)],
5912 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5913 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5914 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5915 temp |= lvds_sync;
5916 }
Eric Anholtfae14982011-03-30 13:01:09 -07005917 I915_WRITE(PCH_LVDS, temp);
Jesse Barnes79e53942008-11-07 14:24:08 -08005918 }
Jesse Barnes434ed092010-09-07 14:48:06 -07005919
Eric Anholt8febb292011-03-30 13:01:07 -07005920 pipeconf &= ~PIPECONF_DITHER_EN;
5921 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
Jesse Barnes5a354202011-06-24 12:19:22 -07005922 if ((is_lvds && dev_priv->lvds_dither) || dither) {
Eric Anholt8febb292011-03-30 13:01:07 -07005923 pipeconf |= PIPECONF_DITHER_EN;
Daniel Vetterf74974c2011-10-11 17:27:51 +02005924 pipeconf |= PIPECONF_DITHER_TYPE_SP;
Jesse Barnes434ed092010-09-07 14:48:06 -07005925 }
Jesse Barnes5c5313c2010-10-07 16:01:11 -07005926 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07005927 intel_dp_set_m_n(crtc, mode, adjusted_mode);
Eric Anholt8febb292011-03-30 13:01:07 -07005928 } else {
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08005929 /* For non-DP output, clear any trans DP clock recovery setting.*/
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005930 I915_WRITE(TRANSDATA_M1(pipe), 0);
5931 I915_WRITE(TRANSDATA_N1(pipe), 0);
5932 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5933 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
Zhenyu Wang8db9d77b2010-04-07 16:15:54 +08005934 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005935
Jesse Barnes4b645f12011-10-12 09:51:31 -07005936 if (!intel_crtc->no_pll &&
5937 (!has_edp_encoder ||
5938 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
Eric Anholtfae14982011-03-30 13:01:09 -07005939 I915_WRITE(PCH_DPLL(pipe), dpll);
Chris Wilson5eddb702010-09-11 13:48:45 +01005940
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005941 /* Wait for the clocks to stabilize. */
Eric Anholtfae14982011-03-30 13:01:09 -07005942 POSTING_READ(PCH_DPLL(pipe));
Zhenyu Wang32f9d652009-07-24 01:00:32 +08005943 udelay(150);
5944
Eric Anholt8febb292011-03-30 13:01:07 -07005945 /* The pixel multiplier can only be updated once the
5946 * DPLL is enabled and the clocks are stable.
5947 *
5948 * So write it again.
5949 */
Eric Anholtfae14982011-03-30 13:01:09 -07005950 I915_WRITE(PCH_DPLL(pipe), dpll);
Jesse Barnes79e53942008-11-07 14:24:08 -08005951 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005952
Chris Wilson5eddb702010-09-11 13:48:45 +01005953 intel_crtc->lowfreq_avail = false;
Jesse Barnes4b645f12011-10-12 09:51:31 -07005954 if (!intel_crtc->no_pll) {
5955 if (is_lvds && has_reduced_clock && i915_powersave) {
5956 I915_WRITE(PCH_FP1(pipe), fp2);
5957 intel_crtc->lowfreq_avail = true;
5958 if (HAS_PIPE_CXSR(dev)) {
5959 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5960 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5961 }
5962 } else {
5963 I915_WRITE(PCH_FP1(pipe), fp);
5964 if (HAS_PIPE_CXSR(dev)) {
5965 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5966 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5967 }
Jesse Barnes652c3932009-08-17 13:31:43 -07005968 }
5969 }
5970
Krzysztof Halasa734b4152010-05-25 18:41:46 +02005971 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5972 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5973 /* the chip adds 2 halflines automatically */
5974 adjusted_mode->crtc_vdisplay -= 1;
5975 adjusted_mode->crtc_vtotal -= 1;
5976 adjusted_mode->crtc_vblank_start -= 1;
5977 adjusted_mode->crtc_vblank_end -= 1;
5978 adjusted_mode->crtc_vsync_end -= 1;
5979 adjusted_mode->crtc_vsync_start -= 1;
5980 } else
5981 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5982
Chris Wilson5eddb702010-09-11 13:48:45 +01005983 I915_WRITE(HTOTAL(pipe),
5984 (adjusted_mode->crtc_hdisplay - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005985 ((adjusted_mode->crtc_htotal - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005986 I915_WRITE(HBLANK(pipe),
5987 (adjusted_mode->crtc_hblank_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005988 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005989 I915_WRITE(HSYNC(pipe),
5990 (adjusted_mode->crtc_hsync_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005991 ((adjusted_mode->crtc_hsync_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005992
5993 I915_WRITE(VTOTAL(pipe),
5994 (adjusted_mode->crtc_vdisplay - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005995 ((adjusted_mode->crtc_vtotal - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005996 I915_WRITE(VBLANK(pipe),
5997 (adjusted_mode->crtc_vblank_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08005998 ((adjusted_mode->crtc_vblank_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01005999 I915_WRITE(VSYNC(pipe),
6000 (adjusted_mode->crtc_vsync_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08006001 ((adjusted_mode->crtc_vsync_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01006002
Eric Anholt8febb292011-03-30 13:01:07 -07006003 /* pipesrc controls the size that is scaled from, which should
6004 * always be the user's requested size.
Jesse Barnes79e53942008-11-07 14:24:08 -08006005 */
Chris Wilson5eddb702010-09-11 13:48:45 +01006006 I915_WRITE(PIPESRC(pipe),
6007 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
Zhenyu Wang2c072452009-06-05 15:38:42 +08006008
Eric Anholt8febb292011-03-30 13:01:07 -07006009 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6010 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6011 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6012 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08006013
Eric Anholt8febb292011-03-30 13:01:07 -07006014 if (has_edp_encoder &&
6015 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6016 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
Zhenyu Wang2c072452009-06-05 15:38:42 +08006017 }
6018
Chris Wilson5eddb702010-09-11 13:48:45 +01006019 I915_WRITE(PIPECONF(pipe), pipeconf);
6020 POSTING_READ(PIPECONF(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006021
Jesse Barnes9d0498a2010-08-18 13:20:54 -07006022 intel_wait_for_vblank(dev, pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08006023
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01006024 if (IS_GEN5(dev)) {
Zhenyu Wang553bd142009-09-02 10:57:52 +08006025 /* enable address swizzle for tiling buffer */
6026 temp = I915_READ(DISP_ARB_CTL);
6027 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
6028 }
6029
Chris Wilson5eddb702010-09-11 13:48:45 +01006030 I915_WRITE(DSPCNTR(plane), dspcntr);
Jesse Barnesb24e7172011-01-04 15:09:30 -08006031 POSTING_READ(DSPCNTR(plane));
Jesse Barnes79e53942008-11-07 14:24:08 -08006032
Chris Wilson5c3b82e2009-02-11 13:25:09 +00006033 ret = intel_pipe_set_base(crtc, x, y, old_fb);
Shaohua Li7662c8b2009-06-26 11:23:55 +08006034
6035 intel_update_watermarks(dev);
6036
Chris Wilson1f803ee2009-06-06 09:45:59 +01006037 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08006038}
6039
Eric Anholtf5640482011-03-30 13:01:02 -07006040static int intel_crtc_mode_set(struct drm_crtc *crtc,
6041 struct drm_display_mode *mode,
6042 struct drm_display_mode *adjusted_mode,
6043 int x, int y,
6044 struct drm_framebuffer *old_fb)
6045{
6046 struct drm_device *dev = crtc->dev;
6047 struct drm_i915_private *dev_priv = dev->dev_private;
Eric Anholt0b701d22011-03-30 13:01:03 -07006048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6049 int pipe = intel_crtc->pipe;
Eric Anholtf5640482011-03-30 13:01:02 -07006050 int ret;
6051
Eric Anholt0b701d22011-03-30 13:01:03 -07006052 drm_vblank_pre_modeset(dev, pipe);
6053
Eric Anholtf5640482011-03-30 13:01:02 -07006054 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6055 x, y, old_fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08006056 drm_vblank_post_modeset(dev, pipe);
6057
Jesse Barnesd8e70a22011-11-15 10:28:54 -08006058 if (ret)
6059 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6060 else
6061 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
Keith Packard120eced2011-07-27 01:21:40 -07006062
Jesse Barnes79e53942008-11-07 14:24:08 -08006063 return ret;
6064}
6065
Wu Fengguang3a9627f2011-12-09 20:42:19 +08006066static bool intel_eld_uptodate(struct drm_connector *connector,
6067 int reg_eldv, uint32_t bits_eldv,
6068 int reg_elda, uint32_t bits_elda,
6069 int reg_edid)
6070{
6071 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6072 uint8_t *eld = connector->eld;
6073 uint32_t i;
6074
6075 i = I915_READ(reg_eldv);
6076 i &= bits_eldv;
6077
6078 if (!eld[0])
6079 return !i;
6080
6081 if (!i)
6082 return false;
6083
6084 i = I915_READ(reg_elda);
6085 i &= ~bits_elda;
6086 I915_WRITE(reg_elda, i);
6087
6088 for (i = 0; i < eld[2]; i++)
6089 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6090 return false;
6091
6092 return true;
6093}
6094
Wu Fengguange0dac652011-09-05 14:25:34 +08006095static void g4x_write_eld(struct drm_connector *connector,
6096 struct drm_crtc *crtc)
6097{
6098 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6099 uint8_t *eld = connector->eld;
6100 uint32_t eldv;
6101 uint32_t len;
6102 uint32_t i;
6103
6104 i = I915_READ(G4X_AUD_VID_DID);
6105
6106 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6107 eldv = G4X_ELDV_DEVCL_DEVBLC;
6108 else
6109 eldv = G4X_ELDV_DEVCTG;
6110
Wu Fengguang3a9627f2011-12-09 20:42:19 +08006111 if (intel_eld_uptodate(connector,
6112 G4X_AUD_CNTL_ST, eldv,
6113 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6114 G4X_HDMIW_HDMIEDID))
6115 return;
6116
Wu Fengguange0dac652011-09-05 14:25:34 +08006117 i = I915_READ(G4X_AUD_CNTL_ST);
6118 i &= ~(eldv | G4X_ELD_ADDR);
6119 len = (i >> 9) & 0x1f; /* ELD buffer size */
6120 I915_WRITE(G4X_AUD_CNTL_ST, i);
6121
6122 if (!eld[0])
6123 return;
6124
6125 len = min_t(uint8_t, eld[2], len);
6126 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6127 for (i = 0; i < len; i++)
6128 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6129
6130 i = I915_READ(G4X_AUD_CNTL_ST);
6131 i |= eldv;
6132 I915_WRITE(G4X_AUD_CNTL_ST, i);
6133}
6134
6135static void ironlake_write_eld(struct drm_connector *connector,
6136 struct drm_crtc *crtc)
6137{
6138 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6139 uint8_t *eld = connector->eld;
6140 uint32_t eldv;
6141 uint32_t i;
6142 int len;
6143 int hdmiw_hdmiedid;
Wu Fengguangb6daa022012-01-06 14:41:31 -06006144 int aud_config;
Wu Fengguange0dac652011-09-05 14:25:34 +08006145 int aud_cntl_st;
6146 int aud_cntrl_st2;
6147
Wu Fengguangb3f33cb2011-12-09 20:42:17 +08006148 if (HAS_PCH_IBX(connector->dev)) {
Wu Fengguang1202b4c2011-12-09 20:42:18 +08006149 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
Wu Fengguangb6daa022012-01-06 14:41:31 -06006150 aud_config = IBX_AUD_CONFIG_A;
Wu Fengguang1202b4c2011-12-09 20:42:18 +08006151 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6152 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08006153 } else {
Wu Fengguang1202b4c2011-12-09 20:42:18 +08006154 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
Wu Fengguangb6daa022012-01-06 14:41:31 -06006155 aud_config = CPT_AUD_CONFIG_A;
Wu Fengguang1202b4c2011-12-09 20:42:18 +08006156 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6157 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08006158 }
6159
6160 i = to_intel_crtc(crtc)->pipe;
6161 hdmiw_hdmiedid += i * 0x100;
6162 aud_cntl_st += i * 0x100;
Wu Fengguangb6daa022012-01-06 14:41:31 -06006163 aud_config += i * 0x100;
Wu Fengguange0dac652011-09-05 14:25:34 +08006164
6165 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6166
6167 i = I915_READ(aud_cntl_st);
6168 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6169 if (!i) {
6170 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6171 /* operate blindly on all ports */
Wu Fengguang1202b4c2011-12-09 20:42:18 +08006172 eldv = IBX_ELD_VALIDB;
6173 eldv |= IBX_ELD_VALIDB << 4;
6174 eldv |= IBX_ELD_VALIDB << 8;
Wu Fengguange0dac652011-09-05 14:25:34 +08006175 } else {
6176 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
Wu Fengguang1202b4c2011-12-09 20:42:18 +08006177 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
Wu Fengguange0dac652011-09-05 14:25:34 +08006178 }
6179
Wu Fengguang3a9627f2011-12-09 20:42:19 +08006180 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6181 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6182 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
Wu Fengguangb6daa022012-01-06 14:41:31 -06006183 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6184 } else
6185 I915_WRITE(aud_config, 0);
Wu Fengguang3a9627f2011-12-09 20:42:19 +08006186
6187 if (intel_eld_uptodate(connector,
6188 aud_cntrl_st2, eldv,
6189 aud_cntl_st, IBX_ELD_ADDRESS,
6190 hdmiw_hdmiedid))
6191 return;
6192
Wu Fengguange0dac652011-09-05 14:25:34 +08006193 i = I915_READ(aud_cntrl_st2);
6194 i &= ~eldv;
6195 I915_WRITE(aud_cntrl_st2, i);
6196
6197 if (!eld[0])
6198 return;
6199
Wu Fengguange0dac652011-09-05 14:25:34 +08006200 i = I915_READ(aud_cntl_st);
Wu Fengguang1202b4c2011-12-09 20:42:18 +08006201 i &= ~IBX_ELD_ADDRESS;
Wu Fengguange0dac652011-09-05 14:25:34 +08006202 I915_WRITE(aud_cntl_st, i);
6203
6204 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6205 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6206 for (i = 0; i < len; i++)
6207 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6208
6209 i = I915_READ(aud_cntrl_st2);
6210 i |= eldv;
6211 I915_WRITE(aud_cntrl_st2, i);
6212}
6213
6214void intel_write_eld(struct drm_encoder *encoder,
6215 struct drm_display_mode *mode)
6216{
6217 struct drm_crtc *crtc = encoder->crtc;
6218 struct drm_connector *connector;
6219 struct drm_device *dev = encoder->dev;
6220 struct drm_i915_private *dev_priv = dev->dev_private;
6221
6222 connector = drm_select_eld(encoder, mode);
6223 if (!connector)
6224 return;
6225
6226 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6227 connector->base.id,
6228 drm_get_connector_name(connector),
6229 connector->encoder->base.id,
6230 drm_get_encoder_name(connector->encoder));
6231
6232 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6233
6234 if (dev_priv->display.write_eld)
6235 dev_priv->display.write_eld(connector, crtc);
6236}
6237
Jesse Barnes79e53942008-11-07 14:24:08 -08006238/** Loads the palette/gamma unit for the CRTC with the prepared values */
6239void intel_crtc_load_lut(struct drm_crtc *crtc)
6240{
6241 struct drm_device *dev = crtc->dev;
6242 struct drm_i915_private *dev_priv = dev->dev_private;
6243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006244 int palreg = PALETTE(intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08006245 int i;
6246
6247 /* The clocks have to be on to load the palette. */
6248 if (!crtc->enabled)
6249 return;
6250
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006251 /* use legacy palette for Ironlake */
Eric Anholtbad720f2009-10-22 16:11:14 -07006252 if (HAS_PCH_SPLIT(dev))
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006253 palreg = LGC_PALETTE(intel_crtc->pipe);
Zhenyu Wang2c072452009-06-05 15:38:42 +08006254
Jesse Barnes79e53942008-11-07 14:24:08 -08006255 for (i = 0; i < 256; i++) {
6256 I915_WRITE(palreg + 4 * i,
6257 (intel_crtc->lut_r[i] << 16) |
6258 (intel_crtc->lut_g[i] << 8) |
6259 intel_crtc->lut_b[i]);
6260 }
6261}
6262
Chris Wilson560b85b2010-08-07 11:01:38 +01006263static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6264{
6265 struct drm_device *dev = crtc->dev;
6266 struct drm_i915_private *dev_priv = dev->dev_private;
6267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6268 bool visible = base != 0;
6269 u32 cntl;
6270
6271 if (intel_crtc->cursor_visible == visible)
6272 return;
6273
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006274 cntl = I915_READ(_CURACNTR);
Chris Wilson560b85b2010-08-07 11:01:38 +01006275 if (visible) {
6276 /* On these chipsets we can only modify the base whilst
6277 * the cursor is disabled.
6278 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006279 I915_WRITE(_CURABASE, base);
Chris Wilson560b85b2010-08-07 11:01:38 +01006280
6281 cntl &= ~(CURSOR_FORMAT_MASK);
6282 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6283 cntl |= CURSOR_ENABLE |
6284 CURSOR_GAMMA_ENABLE |
6285 CURSOR_FORMAT_ARGB;
6286 } else
6287 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006288 I915_WRITE(_CURACNTR, cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01006289
6290 intel_crtc->cursor_visible = visible;
6291}
6292
6293static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6294{
6295 struct drm_device *dev = crtc->dev;
6296 struct drm_i915_private *dev_priv = dev->dev_private;
6297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6298 int pipe = intel_crtc->pipe;
6299 bool visible = base != 0;
6300
6301 if (intel_crtc->cursor_visible != visible) {
Jesse Barnes548f2452011-02-17 10:40:53 -08006302 uint32_t cntl = I915_READ(CURCNTR(pipe));
Chris Wilson560b85b2010-08-07 11:01:38 +01006303 if (base) {
6304 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6305 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6306 cntl |= pipe << 28; /* Connect to correct pipe */
6307 } else {
6308 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6309 cntl |= CURSOR_MODE_DISABLE;
6310 }
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006311 I915_WRITE(CURCNTR(pipe), cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01006312
6313 intel_crtc->cursor_visible = visible;
6314 }
6315 /* and commit changes on next vblank */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08006316 I915_WRITE(CURBASE(pipe), base);
Chris Wilson560b85b2010-08-07 11:01:38 +01006317}
6318
Jesse Barnes65a21cd2011-10-12 11:10:21 -07006319static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6320{
6321 struct drm_device *dev = crtc->dev;
6322 struct drm_i915_private *dev_priv = dev->dev_private;
6323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6324 int pipe = intel_crtc->pipe;
6325 bool visible = base != 0;
6326
6327 if (intel_crtc->cursor_visible != visible) {
6328 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6329 if (base) {
6330 cntl &= ~CURSOR_MODE;
6331 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6332 } else {
6333 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6334 cntl |= CURSOR_MODE_DISABLE;
6335 }
6336 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6337
6338 intel_crtc->cursor_visible = visible;
6339 }
6340 /* and commit changes on next vblank */
6341 I915_WRITE(CURBASE_IVB(pipe), base);
6342}
6343
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006344/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01006345static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6346 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006347{
6348 struct drm_device *dev = crtc->dev;
6349 struct drm_i915_private *dev_priv = dev->dev_private;
6350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6351 int pipe = intel_crtc->pipe;
6352 int x = intel_crtc->cursor_x;
6353 int y = intel_crtc->cursor_y;
Chris Wilson560b85b2010-08-07 11:01:38 +01006354 u32 base, pos;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006355 bool visible;
6356
6357 pos = 0;
6358
Chris Wilson6b383a72010-09-13 13:54:26 +01006359 if (on && crtc->enabled && crtc->fb) {
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006360 base = intel_crtc->cursor_addr;
6361 if (x > (int) crtc->fb->width)
6362 base = 0;
6363
6364 if (y > (int) crtc->fb->height)
6365 base = 0;
6366 } else
6367 base = 0;
6368
6369 if (x < 0) {
6370 if (x + intel_crtc->cursor_width < 0)
6371 base = 0;
6372
6373 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6374 x = -x;
6375 }
6376 pos |= x << CURSOR_X_SHIFT;
6377
6378 if (y < 0) {
6379 if (y + intel_crtc->cursor_height < 0)
6380 base = 0;
6381
6382 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6383 y = -y;
6384 }
6385 pos |= y << CURSOR_Y_SHIFT;
6386
6387 visible = base != 0;
Chris Wilson560b85b2010-08-07 11:01:38 +01006388 if (!visible && !intel_crtc->cursor_visible)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006389 return;
6390
Jesse Barnes65a21cd2011-10-12 11:10:21 -07006391 if (IS_IVYBRIDGE(dev)) {
6392 I915_WRITE(CURPOS_IVB(pipe), pos);
6393 ivb_update_cursor(crtc, base);
6394 } else {
6395 I915_WRITE(CURPOS(pipe), pos);
6396 if (IS_845G(dev) || IS_I865G(dev))
6397 i845_update_cursor(crtc, base);
6398 else
6399 i9xx_update_cursor(crtc, base);
6400 }
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006401
6402 if (visible)
6403 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6404}
6405
Jesse Barnes79e53942008-11-07 14:24:08 -08006406static int intel_crtc_cursor_set(struct drm_crtc *crtc,
Chris Wilson05394f32010-11-08 19:18:58 +00006407 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08006408 uint32_t handle,
6409 uint32_t width, uint32_t height)
6410{
6411 struct drm_device *dev = crtc->dev;
6412 struct drm_i915_private *dev_priv = dev->dev_private;
6413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson05394f32010-11-08 19:18:58 +00006414 struct drm_i915_gem_object *obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006415 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006416 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08006417
Zhao Yakui28c97732009-10-09 11:39:41 +08006418 DRM_DEBUG_KMS("\n");
Jesse Barnes79e53942008-11-07 14:24:08 -08006419
6420 /* if we want to turn off the cursor ignore width and height */
6421 if (!handle) {
Zhao Yakui28c97732009-10-09 11:39:41 +08006422 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006423 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00006424 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10006425 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006426 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08006427 }
6428
6429 /* Currently we only support 64x64 cursors */
6430 if (width != 64 || height != 64) {
6431 DRM_ERROR("we currently only support 64x64 cursors\n");
6432 return -EINVAL;
6433 }
6434
Chris Wilson05394f32010-11-08 19:18:58 +00006435 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00006436 if (&obj->base == NULL)
Jesse Barnes79e53942008-11-07 14:24:08 -08006437 return -ENOENT;
6438
Chris Wilson05394f32010-11-08 19:18:58 +00006439 if (obj->base.size < width * height * 4) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006440 DRM_ERROR("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10006441 ret = -ENOMEM;
6442 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08006443 }
6444
Dave Airlie71acb5e2008-12-30 20:31:46 +10006445 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006446 mutex_lock(&dev->struct_mutex);
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05006447 if (!dev_priv->info->cursor_needs_physical) {
Chris Wilsond9e86c02010-11-10 16:40:20 +00006448 if (obj->tiling_mode) {
6449 DRM_ERROR("cursor cannot be tiled\n");
6450 ret = -EINVAL;
6451 goto fail_locked;
6452 }
6453
Chris Wilson2da3b9b2011-04-14 09:41:17 +01006454 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01006455 if (ret) {
6456 DRM_ERROR("failed to move cursor bo into the GTT\n");
Chris Wilson2da3b9b2011-04-14 09:41:17 +01006457 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01006458 }
6459
Chris Wilsond9e86c02010-11-10 16:40:20 +00006460 ret = i915_gem_object_put_fence(obj);
6461 if (ret) {
Chris Wilson2da3b9b2011-04-14 09:41:17 +01006462 DRM_ERROR("failed to release fence for cursor");
Chris Wilsond9e86c02010-11-10 16:40:20 +00006463 goto fail_unpin;
6464 }
6465
Chris Wilson05394f32010-11-08 19:18:58 +00006466 addr = obj->gtt_offset;
Dave Airlie71acb5e2008-12-30 20:31:46 +10006467 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01006468 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson05394f32010-11-08 19:18:58 +00006469 ret = i915_gem_attach_phys_object(dev, obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01006470 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6471 align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10006472 if (ret) {
6473 DRM_ERROR("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006474 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10006475 }
Chris Wilson05394f32010-11-08 19:18:58 +00006476 addr = obj->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006477 }
6478
Chris Wilsona6c45cf2010-09-17 00:32:17 +01006479 if (IS_GEN2(dev))
Jesse Barnes14b60392009-05-20 16:47:08 -04006480 I915_WRITE(CURSIZE, (height << 12) | width);
6481
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006482 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006483 if (intel_crtc->cursor_bo) {
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05006484 if (dev_priv->info->cursor_needs_physical) {
Chris Wilson05394f32010-11-08 19:18:58 +00006485 if (intel_crtc->cursor_bo != obj)
Dave Airlie71acb5e2008-12-30 20:31:46 +10006486 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6487 } else
6488 i915_gem_object_unpin(intel_crtc->cursor_bo);
Chris Wilson05394f32010-11-08 19:18:58 +00006489 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006490 }
Jesse Barnes80824002009-09-10 15:28:06 -07006491
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006492 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006493
6494 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00006495 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006496 intel_crtc->cursor_width = width;
6497 intel_crtc->cursor_height = height;
6498
Chris Wilson6b383a72010-09-13 13:54:26 +01006499 intel_crtc_update_cursor(crtc, true);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05006500
Jesse Barnes79e53942008-11-07 14:24:08 -08006501 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01006502fail_unpin:
Chris Wilson05394f32010-11-08 19:18:58 +00006503 i915_gem_object_unpin(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05006504fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10006505 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00006506fail:
Chris Wilson05394f32010-11-08 19:18:58 +00006507 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10006508 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08006509}
6510
6511static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6512{
Jesse Barnes79e53942008-11-07 14:24:08 -08006513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006514
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01006515 intel_crtc->cursor_x = x;
6516 intel_crtc->cursor_y = y;
Jesse Barnes652c3932009-08-17 13:31:43 -07006517
Chris Wilson6b383a72010-09-13 13:54:26 +01006518 intel_crtc_update_cursor(crtc, true);
Jesse Barnes79e53942008-11-07 14:24:08 -08006519
6520 return 0;
6521}
6522
6523/** Sets the color ramps on behalf of RandR */
6524void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6525 u16 blue, int regno)
6526{
6527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6528
6529 intel_crtc->lut_r[regno] = red >> 8;
6530 intel_crtc->lut_g[regno] = green >> 8;
6531 intel_crtc->lut_b[regno] = blue >> 8;
6532}
6533
Dave Airlieb8c00ac2009-10-06 13:54:01 +10006534void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6535 u16 *blue, int regno)
6536{
6537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6538
6539 *red = intel_crtc->lut_r[regno] << 8;
6540 *green = intel_crtc->lut_g[regno] << 8;
6541 *blue = intel_crtc->lut_b[regno] << 8;
6542}
6543
Jesse Barnes79e53942008-11-07 14:24:08 -08006544static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01006545 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08006546{
James Simmons72034252010-08-03 01:33:19 +01006547 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08006548 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08006549
James Simmons72034252010-08-03 01:33:19 +01006550 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08006551 intel_crtc->lut_r[i] = red[i] >> 8;
6552 intel_crtc->lut_g[i] = green[i] >> 8;
6553 intel_crtc->lut_b[i] = blue[i] >> 8;
6554 }
6555
6556 intel_crtc_load_lut(crtc);
6557}
6558
6559/**
6560 * Get a pipe with a simple mode set on it for doing load-based monitor
6561 * detection.
6562 *
6563 * It will be up to the load-detect code to adjust the pipe as appropriate for
Eric Anholtc751ce42010-03-25 11:48:48 -07006564 * its requirements. The pipe will be connected to no other encoders.
Jesse Barnes79e53942008-11-07 14:24:08 -08006565 *
Eric Anholtc751ce42010-03-25 11:48:48 -07006566 * Currently this code will only succeed if there is a pipe with no encoders
Jesse Barnes79e53942008-11-07 14:24:08 -08006567 * configured for it. In the future, it could choose to temporarily disable
6568 * some outputs to free up a pipe for its use.
6569 *
6570 * \return crtc, or NULL if no pipes are available.
6571 */
6572
6573/* VESA 640x480x72Hz mode to set on the pipe */
6574static struct drm_display_mode load_detect_mode = {
6575 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6576 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6577};
6578
Chris Wilsond2dff872011-04-19 08:36:26 +01006579static struct drm_framebuffer *
6580intel_framebuffer_create(struct drm_device *dev,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08006581 struct drm_mode_fb_cmd2 *mode_cmd,
Chris Wilsond2dff872011-04-19 08:36:26 +01006582 struct drm_i915_gem_object *obj)
6583{
6584 struct intel_framebuffer *intel_fb;
6585 int ret;
6586
6587 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6588 if (!intel_fb) {
6589 drm_gem_object_unreference_unlocked(&obj->base);
6590 return ERR_PTR(-ENOMEM);
6591 }
6592
6593 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6594 if (ret) {
6595 drm_gem_object_unreference_unlocked(&obj->base);
6596 kfree(intel_fb);
6597 return ERR_PTR(ret);
6598 }
6599
6600 return &intel_fb->base;
6601}
6602
6603static u32
6604intel_framebuffer_pitch_for_width(int width, int bpp)
6605{
6606 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6607 return ALIGN(pitch, 64);
6608}
6609
6610static u32
6611intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6612{
6613 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6614 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6615}
6616
6617static struct drm_framebuffer *
6618intel_framebuffer_create_for_mode(struct drm_device *dev,
6619 struct drm_display_mode *mode,
6620 int depth, int bpp)
6621{
6622 struct drm_i915_gem_object *obj;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08006623 struct drm_mode_fb_cmd2 mode_cmd;
Chris Wilsond2dff872011-04-19 08:36:26 +01006624
6625 obj = i915_gem_alloc_object(dev,
6626 intel_framebuffer_size_for_mode(mode, bpp));
6627 if (obj == NULL)
6628 return ERR_PTR(-ENOMEM);
6629
6630 mode_cmd.width = mode->hdisplay;
6631 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08006632 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6633 bpp);
6634 mode_cmd.pixel_format = 0;
Chris Wilsond2dff872011-04-19 08:36:26 +01006635
6636 return intel_framebuffer_create(dev, &mode_cmd, obj);
6637}
6638
6639static struct drm_framebuffer *
6640mode_fits_in_fbdev(struct drm_device *dev,
6641 struct drm_display_mode *mode)
6642{
6643 struct drm_i915_private *dev_priv = dev->dev_private;
6644 struct drm_i915_gem_object *obj;
6645 struct drm_framebuffer *fb;
6646
6647 if (dev_priv->fbdev == NULL)
6648 return NULL;
6649
6650 obj = dev_priv->fbdev->ifb.obj;
6651 if (obj == NULL)
6652 return NULL;
6653
6654 fb = &dev_priv->fbdev->ifb.base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02006655 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6656 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01006657 return NULL;
6658
Ville Syrjälä01f2c772011-12-20 00:06:49 +02006659 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01006660 return NULL;
6661
6662 return fb;
6663}
6664
Chris Wilson71731882011-04-19 23:10:58 +01006665bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6666 struct drm_connector *connector,
6667 struct drm_display_mode *mode,
Chris Wilson8261b192011-04-19 23:18:09 +01006668 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08006669{
6670 struct intel_crtc *intel_crtc;
6671 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01006672 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08006673 struct drm_crtc *crtc = NULL;
6674 struct drm_device *dev = encoder->dev;
Chris Wilsond2dff872011-04-19 08:36:26 +01006675 struct drm_framebuffer *old_fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08006676 int i = -1;
6677
Chris Wilsond2dff872011-04-19 08:36:26 +01006678 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6679 connector->base.id, drm_get_connector_name(connector),
6680 encoder->base.id, drm_get_encoder_name(encoder));
6681
Jesse Barnes79e53942008-11-07 14:24:08 -08006682 /*
6683 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01006684 *
Jesse Barnes79e53942008-11-07 14:24:08 -08006685 * - if the connector already has an assigned crtc, use it (but make
6686 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01006687 *
Jesse Barnes79e53942008-11-07 14:24:08 -08006688 * - try to find the first unused crtc that can drive this connector,
6689 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08006690 */
6691
6692 /* See if we already have a CRTC for this connector */
6693 if (encoder->crtc) {
6694 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01006695
Jesse Barnes79e53942008-11-07 14:24:08 -08006696 intel_crtc = to_intel_crtc(crtc);
Chris Wilson8261b192011-04-19 23:18:09 +01006697 old->dpms_mode = intel_crtc->dpms_mode;
6698 old->load_detect_temp = false;
6699
6700 /* Make sure the crtc and connector are running */
Jesse Barnes79e53942008-11-07 14:24:08 -08006701 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
Chris Wilson64927112011-04-20 07:25:26 +01006702 struct drm_encoder_helper_funcs *encoder_funcs;
6703 struct drm_crtc_helper_funcs *crtc_funcs;
6704
Jesse Barnes79e53942008-11-07 14:24:08 -08006705 crtc_funcs = crtc->helper_private;
6706 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
Chris Wilson64927112011-04-20 07:25:26 +01006707
6708 encoder_funcs = encoder->helper_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08006709 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6710 }
Chris Wilson8261b192011-04-19 23:18:09 +01006711
Chris Wilson71731882011-04-19 23:10:58 +01006712 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08006713 }
6714
6715 /* Find an unused one (if possible) */
6716 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6717 i++;
6718 if (!(encoder->possible_crtcs & (1 << i)))
6719 continue;
6720 if (!possible_crtc->enabled) {
6721 crtc = possible_crtc;
6722 break;
6723 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006724 }
6725
6726 /*
6727 * If we didn't find an unused CRTC, don't use any.
6728 */
6729 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01006730 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6731 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006732 }
6733
6734 encoder->crtc = crtc;
Zhenyu Wangc1c43972010-03-30 14:39:30 +08006735 connector->encoder = encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08006736
6737 intel_crtc = to_intel_crtc(crtc);
Chris Wilson8261b192011-04-19 23:18:09 +01006738 old->dpms_mode = intel_crtc->dpms_mode;
6739 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01006740 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08006741
Chris Wilson64927112011-04-20 07:25:26 +01006742 if (!mode)
6743 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08006744
Chris Wilsond2dff872011-04-19 08:36:26 +01006745 old_fb = crtc->fb;
6746
6747 /* We need a framebuffer large enough to accommodate all accesses
6748 * that the plane may generate whilst we perform load detection.
6749 * We can not rely on the fbcon either being present (we get called
6750 * during its initialisation to detect all boot displays, or it may
6751 * not even exist) or that it is large enough to satisfy the
6752 * requested mode.
6753 */
6754 crtc->fb = mode_fits_in_fbdev(dev, mode);
6755 if (crtc->fb == NULL) {
6756 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6757 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6758 old->release_fb = crtc->fb;
6759 } else
6760 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6761 if (IS_ERR(crtc->fb)) {
6762 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6763 crtc->fb = old_fb;
6764 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006765 }
Chris Wilsond2dff872011-04-19 08:36:26 +01006766
6767 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01006768 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01006769 if (old->release_fb)
6770 old->release_fb->funcs->destroy(old->release_fb);
6771 crtc->fb = old_fb;
Chris Wilson64927112011-04-20 07:25:26 +01006772 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08006773 }
Chris Wilson71731882011-04-19 23:10:58 +01006774
Jesse Barnes79e53942008-11-07 14:24:08 -08006775 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07006776 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08006777
Chris Wilson71731882011-04-19 23:10:58 +01006778 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08006779}
6780
Zhenyu Wangc1c43972010-03-30 14:39:30 +08006781void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
Chris Wilson8261b192011-04-19 23:18:09 +01006782 struct drm_connector *connector,
6783 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08006784{
Chris Wilson4ef69c72010-09-09 15:14:28 +01006785 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08006786 struct drm_device *dev = encoder->dev;
6787 struct drm_crtc *crtc = encoder->crtc;
6788 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6789 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6790
Chris Wilsond2dff872011-04-19 08:36:26 +01006791 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6792 connector->base.id, drm_get_connector_name(connector),
6793 encoder->base.id, drm_get_encoder_name(encoder));
6794
Chris Wilson8261b192011-04-19 23:18:09 +01006795 if (old->load_detect_temp) {
Zhenyu Wangc1c43972010-03-30 14:39:30 +08006796 connector->encoder = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08006797 drm_helper_disable_unused_functions(dev);
Chris Wilsond2dff872011-04-19 08:36:26 +01006798
6799 if (old->release_fb)
6800 old->release_fb->funcs->destroy(old->release_fb);
6801
Chris Wilson0622a532011-04-21 09:32:11 +01006802 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08006803 }
6804
Eric Anholtc751ce42010-03-25 11:48:48 -07006805 /* Switch crtc and encoder back off if necessary */
Chris Wilson0622a532011-04-21 09:32:11 +01006806 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6807 encoder_funcs->dpms(encoder, old->dpms_mode);
Chris Wilson8261b192011-04-19 23:18:09 +01006808 crtc_funcs->dpms(crtc, old->dpms_mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08006809 }
6810}
6811
6812/* Returns the clock of the currently programmed mode of the given pipe. */
6813static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6814{
6815 struct drm_i915_private *dev_priv = dev->dev_private;
6816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6817 int pipe = intel_crtc->pipe;
Jesse Barnes548f2452011-02-17 10:40:53 -08006818 u32 dpll = I915_READ(DPLL(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006819 u32 fp;
6820 intel_clock_t clock;
6821
6822 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Chris Wilson39adb7a2011-04-22 22:17:21 +01006823 fp = I915_READ(FP0(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006824 else
Chris Wilson39adb7a2011-04-22 22:17:21 +01006825 fp = I915_READ(FP1(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006826
6827 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006828 if (IS_PINEVIEW(dev)) {
6829 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6830 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08006831 } else {
6832 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6833 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6834 }
6835
Chris Wilsona6c45cf2010-09-17 00:32:17 +01006836 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006837 if (IS_PINEVIEW(dev))
6838 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6839 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08006840 else
6841 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08006842 DPLL_FPA01_P1_POST_DIV_SHIFT);
6843
6844 switch (dpll & DPLL_MODE_MASK) {
6845 case DPLLB_MODE_DAC_SERIAL:
6846 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6847 5 : 10;
6848 break;
6849 case DPLLB_MODE_LVDS:
6850 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6851 7 : 14;
6852 break;
6853 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08006854 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08006855 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6856 return 0;
6857 }
6858
6859 /* XXX: Handle the 100Mhz refclk */
Shaohua Li21778322009-02-23 15:19:16 +08006860 intel_clock(dev, 96000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006861 } else {
6862 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6863
6864 if (is_lvds) {
6865 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6866 DPLL_FPA01_P1_POST_DIV_SHIFT);
6867 clock.p2 = 14;
6868
6869 if ((dpll & PLL_REF_INPUT_MASK) ==
6870 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6871 /* XXX: might not be 66MHz */
Shaohua Li21778322009-02-23 15:19:16 +08006872 intel_clock(dev, 66000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006873 } else
Shaohua Li21778322009-02-23 15:19:16 +08006874 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006875 } else {
6876 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6877 clock.p1 = 2;
6878 else {
6879 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6880 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6881 }
6882 if (dpll & PLL_P2_DIVIDE_BY_4)
6883 clock.p2 = 4;
6884 else
6885 clock.p2 = 2;
6886
Shaohua Li21778322009-02-23 15:19:16 +08006887 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08006888 }
6889 }
6890
6891 /* XXX: It would be nice to validate the clocks, but we can't reuse
6892 * i830PllIsValid() because it relies on the xf86_config connector
6893 * configuration being accurate, which it isn't necessarily.
6894 */
6895
6896 return clock.dot;
6897}
6898
6899/** Returns the currently programmed mode of the given pipe. */
6900struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6901 struct drm_crtc *crtc)
6902{
Jesse Barnes548f2452011-02-17 10:40:53 -08006903 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08006904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6905 int pipe = intel_crtc->pipe;
6906 struct drm_display_mode *mode;
Jesse Barnes548f2452011-02-17 10:40:53 -08006907 int htot = I915_READ(HTOTAL(pipe));
6908 int hsync = I915_READ(HSYNC(pipe));
6909 int vtot = I915_READ(VTOTAL(pipe));
6910 int vsync = I915_READ(VSYNC(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08006911
6912 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6913 if (!mode)
6914 return NULL;
6915
6916 mode->clock = intel_crtc_clock_get(dev, crtc);
6917 mode->hdisplay = (htot & 0xffff) + 1;
6918 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6919 mode->hsync_start = (hsync & 0xffff) + 1;
6920 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6921 mode->vdisplay = (vtot & 0xffff) + 1;
6922 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6923 mode->vsync_start = (vsync & 0xffff) + 1;
6924 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6925
6926 drm_mode_set_name(mode);
6927 drm_mode_set_crtcinfo(mode, 0);
6928
6929 return mode;
6930}
6931
Jesse Barnes652c3932009-08-17 13:31:43 -07006932#define GPU_IDLE_TIMEOUT 500 /* ms */
6933
6934/* When this timer fires, we've been idle for awhile */
6935static void intel_gpu_idle_timer(unsigned long arg)
6936{
6937 struct drm_device *dev = (struct drm_device *)arg;
6938 drm_i915_private_t *dev_priv = dev->dev_private;
6939
Chris Wilsonff7ea4c2010-12-08 09:43:41 +00006940 if (!list_empty(&dev_priv->mm.active_list)) {
6941 /* Still processing requests, so just re-arm the timer. */
6942 mod_timer(&dev_priv->idle_timer, jiffies +
6943 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6944 return;
6945 }
Jesse Barnes652c3932009-08-17 13:31:43 -07006946
Chris Wilsonff7ea4c2010-12-08 09:43:41 +00006947 dev_priv->busy = false;
Eric Anholt01dfba92009-09-06 15:18:53 -07006948 queue_work(dev_priv->wq, &dev_priv->idle_work);
Jesse Barnes652c3932009-08-17 13:31:43 -07006949}
6950
Jesse Barnes652c3932009-08-17 13:31:43 -07006951#define CRTC_IDLE_TIMEOUT 1000 /* ms */
6952
6953static void intel_crtc_idle_timer(unsigned long arg)
6954{
6955 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6956 struct drm_crtc *crtc = &intel_crtc->base;
6957 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
Chris Wilsonff7ea4c2010-12-08 09:43:41 +00006958 struct intel_framebuffer *intel_fb;
6959
6960 intel_fb = to_intel_framebuffer(crtc->fb);
6961 if (intel_fb && intel_fb->obj->active) {
6962 /* The framebuffer is still being accessed by the GPU. */
6963 mod_timer(&intel_crtc->idle_timer, jiffies +
6964 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6965 return;
6966 }
Jesse Barnes652c3932009-08-17 13:31:43 -07006967
Jesse Barnes652c3932009-08-17 13:31:43 -07006968 intel_crtc->busy = false;
Eric Anholt01dfba92009-09-06 15:18:53 -07006969 queue_work(dev_priv->wq, &dev_priv->idle_work);
Jesse Barnes652c3932009-08-17 13:31:43 -07006970}
6971
Daniel Vetter3dec0092010-08-20 21:40:52 +02006972static void intel_increase_pllclock(struct drm_crtc *crtc)
Jesse Barnes652c3932009-08-17 13:31:43 -07006973{
6974 struct drm_device *dev = crtc->dev;
6975 drm_i915_private_t *dev_priv = dev->dev_private;
6976 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6977 int pipe = intel_crtc->pipe;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006978 int dpll_reg = DPLL(pipe);
6979 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07006980
Eric Anholtbad720f2009-10-22 16:11:14 -07006981 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07006982 return;
6983
6984 if (!dev_priv->lvds_downclock_avail)
6985 return;
6986
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006987 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07006988 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08006989 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07006990
6991 /* Unlock panel regs */
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006992 I915_WRITE(PP_CONTROL,
6993 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
Jesse Barnes652c3932009-08-17 13:31:43 -07006994
6995 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6996 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07006997 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08006998
Jesse Barnes652c3932009-08-17 13:31:43 -07006999 dpll = I915_READ(dpll_reg);
7000 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08007001 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07007002
7003 /* ...and lock them again */
7004 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
7005 }
7006
7007 /* Schedule downclock */
Daniel Vetter3dec0092010-08-20 21:40:52 +02007008 mod_timer(&intel_crtc->idle_timer, jiffies +
7009 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
Jesse Barnes652c3932009-08-17 13:31:43 -07007010}
7011
7012static void intel_decrease_pllclock(struct drm_crtc *crtc)
7013{
7014 struct drm_device *dev = crtc->dev;
7015 drm_i915_private_t *dev_priv = dev->dev_private;
7016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7017 int pipe = intel_crtc->pipe;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08007018 int dpll_reg = DPLL(pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07007019 int dpll = I915_READ(dpll_reg);
7020
Eric Anholtbad720f2009-10-22 16:11:14 -07007021 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07007022 return;
7023
7024 if (!dev_priv->lvds_downclock_avail)
7025 return;
7026
7027 /*
7028 * Since this is called by a timer, we should never get here in
7029 * the manual case.
7030 */
7031 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08007032 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07007033
7034 /* Unlock panel regs */
Jesse Barnes4a655f02010-07-22 13:18:18 -07007035 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
7036 PANEL_UNLOCK_REGS);
Jesse Barnes652c3932009-08-17 13:31:43 -07007037
7038 dpll |= DISPLAY_RATE_SELECT_FPA1;
7039 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07007040 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07007041 dpll = I915_READ(dpll_reg);
7042 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08007043 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07007044
7045 /* ...and lock them again */
7046 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
7047 }
7048
7049}
7050
7051/**
7052 * intel_idle_update - adjust clocks for idleness
7053 * @work: work struct
7054 *
7055 * Either the GPU or display (or both) went idle. Check the busy status
7056 * here and adjust the CRTC and GPU clocks as necessary.
7057 */
7058static void intel_idle_update(struct work_struct *work)
7059{
7060 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7061 idle_work);
7062 struct drm_device *dev = dev_priv->dev;
7063 struct drm_crtc *crtc;
7064 struct intel_crtc *intel_crtc;
7065
7066 if (!i915_powersave)
7067 return;
7068
7069 mutex_lock(&dev->struct_mutex);
7070
Jesse Barnes7648fa92010-05-20 14:28:11 -07007071 i915_update_gfx_val(dev_priv);
7072
Jesse Barnes652c3932009-08-17 13:31:43 -07007073 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7074 /* Skip inactive CRTCs */
7075 if (!crtc->fb)
7076 continue;
7077
7078 intel_crtc = to_intel_crtc(crtc);
7079 if (!intel_crtc->busy)
7080 intel_decrease_pllclock(crtc);
7081 }
7082
Li Peng45ac22c2010-06-12 23:38:35 +08007083
Jesse Barnes652c3932009-08-17 13:31:43 -07007084 mutex_unlock(&dev->struct_mutex);
7085}
7086
7087/**
7088 * intel_mark_busy - mark the GPU and possibly the display busy
7089 * @dev: drm device
7090 * @obj: object we're operating on
7091 *
7092 * Callers can use this function to indicate that the GPU is busy processing
7093 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7094 * buffer), we'll also mark the display as busy, so we know to increase its
7095 * clock frequency.
7096 */
Chris Wilson05394f32010-11-08 19:18:58 +00007097void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
Jesse Barnes652c3932009-08-17 13:31:43 -07007098{
7099 drm_i915_private_t *dev_priv = dev->dev_private;
7100 struct drm_crtc *crtc = NULL;
7101 struct intel_framebuffer *intel_fb;
7102 struct intel_crtc *intel_crtc;
7103
Zhenyu Wang5e17ee72009-09-03 09:30:06 +08007104 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7105 return;
7106
Alexander Lam18b21902011-01-03 13:28:56 -05007107 if (!dev_priv->busy)
Chris Wilson28cf7982009-11-30 01:08:56 +00007108 dev_priv->busy = true;
Alexander Lam18b21902011-01-03 13:28:56 -05007109 else
Chris Wilson28cf7982009-11-30 01:08:56 +00007110 mod_timer(&dev_priv->idle_timer, jiffies +
7111 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
Jesse Barnes652c3932009-08-17 13:31:43 -07007112
7113 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7114 if (!crtc->fb)
7115 continue;
7116
7117 intel_crtc = to_intel_crtc(crtc);
7118 intel_fb = to_intel_framebuffer(crtc->fb);
7119 if (intel_fb->obj == obj) {
7120 if (!intel_crtc->busy) {
7121 /* Non-busy -> busy, upclock */
Daniel Vetter3dec0092010-08-20 21:40:52 +02007122 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07007123 intel_crtc->busy = true;
7124 } else {
7125 /* Busy -> busy, put off timer */
7126 mod_timer(&intel_crtc->idle_timer, jiffies +
7127 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7128 }
7129 }
7130 }
7131}
7132
Jesse Barnes79e53942008-11-07 14:24:08 -08007133static void intel_crtc_destroy(struct drm_crtc *crtc)
7134{
7135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02007136 struct drm_device *dev = crtc->dev;
7137 struct intel_unpin_work *work;
7138 unsigned long flags;
7139
7140 spin_lock_irqsave(&dev->event_lock, flags);
7141 work = intel_crtc->unpin_work;
7142 intel_crtc->unpin_work = NULL;
7143 spin_unlock_irqrestore(&dev->event_lock, flags);
7144
7145 if (work) {
7146 cancel_work_sync(&work->work);
7147 kfree(work);
7148 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007149
7150 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02007151
Jesse Barnes79e53942008-11-07 14:24:08 -08007152 kfree(intel_crtc);
7153}
7154
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007155static void intel_unpin_work_fn(struct work_struct *__work)
7156{
7157 struct intel_unpin_work *work =
7158 container_of(__work, struct intel_unpin_work, work);
7159
7160 mutex_lock(&work->dev->struct_mutex);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08007161 i915_gem_object_unpin(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00007162 drm_gem_object_unreference(&work->pending_flip_obj->base);
7163 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00007164
Chris Wilson7782de32011-07-08 12:22:41 +01007165 intel_update_fbc(work->dev);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007166 mutex_unlock(&work->dev->struct_mutex);
7167 kfree(work);
7168}
7169
Jesse Barnes1afe3e92010-03-26 10:35:20 -07007170static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01007171 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007172{
7173 drm_i915_private_t *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7175 struct intel_unpin_work *work;
Chris Wilson05394f32010-11-08 19:18:58 +00007176 struct drm_i915_gem_object *obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007177 struct drm_pending_vblank_event *e;
Mario Kleiner49b14a52010-12-09 07:00:07 +01007178 struct timeval tnow, tvbl;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007179 unsigned long flags;
7180
7181 /* Ignore early vblank irqs */
7182 if (intel_crtc == NULL)
7183 return;
7184
Mario Kleiner49b14a52010-12-09 07:00:07 +01007185 do_gettimeofday(&tnow);
7186
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007187 spin_lock_irqsave(&dev->event_lock, flags);
7188 work = intel_crtc->unpin_work;
7189 if (work == NULL || !work->pending) {
7190 spin_unlock_irqrestore(&dev->event_lock, flags);
7191 return;
7192 }
7193
7194 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007195
7196 if (work->event) {
7197 e = work->event;
Mario Kleiner49b14a52010-12-09 07:00:07 +01007198 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01007199
7200 /* Called before vblank count and timestamps have
7201 * been updated for the vblank interval of flip
7202 * completion? Need to increment vblank count and
7203 * add one videorefresh duration to returned timestamp
Mario Kleiner49b14a52010-12-09 07:00:07 +01007204 * to account for this. We assume this happened if we
7205 * get called over 0.9 frame durations after the last
7206 * timestamped vblank.
7207 *
7208 * This calculation can not be used with vrefresh rates
7209 * below 5Hz (10Hz to be on the safe side) without
7210 * promoting to 64 integers.
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01007211 */
Mario Kleiner49b14a52010-12-09 07:00:07 +01007212 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7213 9 * crtc->framedur_ns) {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01007214 e->event.sequence++;
Mario Kleiner49b14a52010-12-09 07:00:07 +01007215 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7216 crtc->framedur_ns);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01007217 }
7218
Mario Kleiner49b14a52010-12-09 07:00:07 +01007219 e->event.tv_sec = tvbl.tv_sec;
7220 e->event.tv_usec = tvbl.tv_usec;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01007221
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007222 list_add_tail(&e->base.link,
7223 &e->base.file_priv->event_list);
7224 wake_up_interruptible(&e->base.file_priv->event_wait);
7225 }
7226
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01007227 drm_vblank_put(dev, intel_crtc->pipe);
7228
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007229 spin_unlock_irqrestore(&dev->event_lock, flags);
7230
Chris Wilson05394f32010-11-08 19:18:58 +00007231 obj = work->old_fb_obj;
Chris Wilsond9e86c02010-11-10 16:40:20 +00007232
Chris Wilsone59f2ba2010-10-07 17:28:15 +01007233 atomic_clear_mask(1 << intel_crtc->plane,
Chris Wilson05394f32010-11-08 19:18:58 +00007234 &obj->pending_flip.counter);
7235 if (atomic_read(&obj->pending_flip) == 0)
Chris Wilsonf787a5f2010-09-24 16:02:42 +01007236 wake_up(&dev_priv->pending_flip_queue);
Chris Wilsond9e86c02010-11-10 16:40:20 +00007237
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007238 schedule_work(&work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07007239
7240 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007241}
7242
Jesse Barnes1afe3e92010-03-26 10:35:20 -07007243void intel_finish_page_flip(struct drm_device *dev, int pipe)
7244{
7245 drm_i915_private_t *dev_priv = dev->dev_private;
7246 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7247
Mario Kleiner49b14a52010-12-09 07:00:07 +01007248 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07007249}
7250
7251void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7252{
7253 drm_i915_private_t *dev_priv = dev->dev_private;
7254 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7255
Mario Kleiner49b14a52010-12-09 07:00:07 +01007256 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07007257}
7258
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007259void intel_prepare_page_flip(struct drm_device *dev, int plane)
7260{
7261 drm_i915_private_t *dev_priv = dev->dev_private;
7262 struct intel_crtc *intel_crtc =
7263 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7264 unsigned long flags;
7265
7266 spin_lock_irqsave(&dev->event_lock, flags);
Jesse Barnesde3f4402010-01-14 13:18:02 -08007267 if (intel_crtc->unpin_work) {
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01007268 if ((++intel_crtc->unpin_work->pending) > 1)
7269 DRM_ERROR("Prepared flip multiple times\n");
Jesse Barnesde3f4402010-01-14 13:18:02 -08007270 } else {
7271 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7272 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007273 spin_unlock_irqrestore(&dev->event_lock, flags);
7274}
7275
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007276static int intel_gen2_queue_flip(struct drm_device *dev,
7277 struct drm_crtc *crtc,
7278 struct drm_framebuffer *fb,
7279 struct drm_i915_gem_object *obj)
7280{
7281 struct drm_i915_private *dev_priv = dev->dev_private;
7282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7283 unsigned long offset;
7284 u32 flip_mask;
7285 int ret;
7286
7287 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7288 if (ret)
7289 goto out;
7290
7291 /* Offset into the new buffer for cases of shared fbs between CRTCs */
Ville Syrjälä01f2c772011-12-20 00:06:49 +02007292 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007293
7294 ret = BEGIN_LP_RING(6);
7295 if (ret)
7296 goto out;
7297
7298 /* Can't queue multiple flips, so wait for the previous
7299 * one to finish before executing the next.
7300 */
7301 if (intel_crtc->plane)
7302 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7303 else
7304 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7305 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7306 OUT_RING(MI_NOOP);
7307 OUT_RING(MI_DISPLAY_FLIP |
7308 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
Ville Syrjälä01f2c772011-12-20 00:06:49 +02007309 OUT_RING(fb->pitches[0]);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007310 OUT_RING(obj->gtt_offset + offset);
Daniel Vetterc6a32fc2012-01-20 10:43:44 +01007311 OUT_RING(0); /* aux display base address, unused */
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007312 ADVANCE_LP_RING();
7313out:
7314 return ret;
7315}
7316
7317static int intel_gen3_queue_flip(struct drm_device *dev,
7318 struct drm_crtc *crtc,
7319 struct drm_framebuffer *fb,
7320 struct drm_i915_gem_object *obj)
7321{
7322 struct drm_i915_private *dev_priv = dev->dev_private;
7323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7324 unsigned long offset;
7325 u32 flip_mask;
7326 int ret;
7327
7328 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7329 if (ret)
7330 goto out;
7331
7332 /* Offset into the new buffer for cases of shared fbs between CRTCs */
Ville Syrjälä01f2c772011-12-20 00:06:49 +02007333 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007334
7335 ret = BEGIN_LP_RING(6);
7336 if (ret)
7337 goto out;
7338
7339 if (intel_crtc->plane)
7340 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7341 else
7342 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7343 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7344 OUT_RING(MI_NOOP);
7345 OUT_RING(MI_DISPLAY_FLIP_I915 |
7346 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
Ville Syrjälä01f2c772011-12-20 00:06:49 +02007347 OUT_RING(fb->pitches[0]);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007348 OUT_RING(obj->gtt_offset + offset);
7349 OUT_RING(MI_NOOP);
7350
7351 ADVANCE_LP_RING();
7352out:
7353 return ret;
7354}
7355
7356static int intel_gen4_queue_flip(struct drm_device *dev,
7357 struct drm_crtc *crtc,
7358 struct drm_framebuffer *fb,
7359 struct drm_i915_gem_object *obj)
7360{
7361 struct drm_i915_private *dev_priv = dev->dev_private;
7362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7363 uint32_t pf, pipesrc;
7364 int ret;
7365
7366 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7367 if (ret)
7368 goto out;
7369
7370 ret = BEGIN_LP_RING(4);
7371 if (ret)
7372 goto out;
7373
7374 /* i965+ uses the linear or tiled offsets from the
7375 * Display Registers (which do not change across a page-flip)
7376 * so we need only reprogram the base address.
7377 */
7378 OUT_RING(MI_DISPLAY_FLIP |
7379 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
Ville Syrjälä01f2c772011-12-20 00:06:49 +02007380 OUT_RING(fb->pitches[0]);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007381 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7382
7383 /* XXX Enabling the panel-fitter across page-flip is so far
7384 * untested on non-native modes, so ignore it for now.
7385 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7386 */
7387 pf = 0;
7388 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7389 OUT_RING(pf | pipesrc);
7390 ADVANCE_LP_RING();
7391out:
7392 return ret;
7393}
7394
7395static int intel_gen6_queue_flip(struct drm_device *dev,
7396 struct drm_crtc *crtc,
7397 struct drm_framebuffer *fb,
7398 struct drm_i915_gem_object *obj)
7399{
7400 struct drm_i915_private *dev_priv = dev->dev_private;
7401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7402 uint32_t pf, pipesrc;
7403 int ret;
7404
7405 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7406 if (ret)
7407 goto out;
7408
7409 ret = BEGIN_LP_RING(4);
7410 if (ret)
7411 goto out;
7412
7413 OUT_RING(MI_DISPLAY_FLIP |
7414 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
Ville Syrjälä01f2c772011-12-20 00:06:49 +02007415 OUT_RING(fb->pitches[0] | obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007416 OUT_RING(obj->gtt_offset);
7417
7418 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7419 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7420 OUT_RING(pf | pipesrc);
7421 ADVANCE_LP_RING();
7422out:
7423 return ret;
7424}
7425
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007426/*
7427 * On gen7 we currently use the blit ring because (in early silicon at least)
7428 * the render ring doesn't give us interrpts for page flip completion, which
7429 * means clients will hang after the first flip is queued. Fortunately the
7430 * blit ring generates interrupts properly, so use it instead.
7431 */
7432static int intel_gen7_queue_flip(struct drm_device *dev,
7433 struct drm_crtc *crtc,
7434 struct drm_framebuffer *fb,
7435 struct drm_i915_gem_object *obj)
7436{
7437 struct drm_i915_private *dev_priv = dev->dev_private;
7438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7439 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7440 int ret;
7441
7442 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7443 if (ret)
7444 goto out;
7445
7446 ret = intel_ring_begin(ring, 4);
7447 if (ret)
7448 goto out;
7449
7450 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
Ville Syrjälä01f2c772011-12-20 00:06:49 +02007451 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Jesse Barnes7c9017e2011-06-16 12:18:54 -07007452 intel_ring_emit(ring, (obj->gtt_offset));
7453 intel_ring_emit(ring, (MI_NOOP));
7454 intel_ring_advance(ring);
7455out:
7456 return ret;
7457}
7458
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007459static int intel_default_queue_flip(struct drm_device *dev,
7460 struct drm_crtc *crtc,
7461 struct drm_framebuffer *fb,
7462 struct drm_i915_gem_object *obj)
7463{
7464 return -ENODEV;
7465}
7466
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007467static int intel_crtc_page_flip(struct drm_crtc *crtc,
7468 struct drm_framebuffer *fb,
7469 struct drm_pending_vblank_event *event)
7470{
7471 struct drm_device *dev = crtc->dev;
7472 struct drm_i915_private *dev_priv = dev->dev_private;
7473 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00007474 struct drm_i915_gem_object *obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7476 struct intel_unpin_work *work;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007477 unsigned long flags;
Chris Wilson52e68632010-08-08 10:15:59 +01007478 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007479
7480 work = kzalloc(sizeof *work, GFP_KERNEL);
7481 if (work == NULL)
7482 return -ENOMEM;
7483
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007484 work->event = event;
7485 work->dev = crtc->dev;
7486 intel_fb = to_intel_framebuffer(crtc->fb);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08007487 work->old_fb_obj = intel_fb->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007488 INIT_WORK(&work->work, intel_unpin_work_fn);
7489
Jesse Barnes7317c752011-08-29 09:45:28 -07007490 ret = drm_vblank_get(dev, intel_crtc->pipe);
7491 if (ret)
7492 goto free_work;
7493
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007494 /* We borrow the event spin lock for protecting unpin_work */
7495 spin_lock_irqsave(&dev->event_lock, flags);
7496 if (intel_crtc->unpin_work) {
7497 spin_unlock_irqrestore(&dev->event_lock, flags);
7498 kfree(work);
Jesse Barnes7317c752011-08-29 09:45:28 -07007499 drm_vblank_put(dev, intel_crtc->pipe);
Chris Wilson468f0b42010-05-27 13:18:13 +01007500
7501 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007502 return -EBUSY;
7503 }
7504 intel_crtc->unpin_work = work;
7505 spin_unlock_irqrestore(&dev->event_lock, flags);
7506
7507 intel_fb = to_intel_framebuffer(fb);
7508 obj = intel_fb->obj;
7509
Chris Wilson468f0b42010-05-27 13:18:13 +01007510 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007511
Jesse Barnes75dfca80a2010-02-10 15:09:44 -08007512 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00007513 drm_gem_object_reference(&work->old_fb_obj->base);
7514 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007515
7516 crtc->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01007517
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007518 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007519
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01007520 work->enable_stall_check = true;
7521
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007522 /* Block clients from rendering to the new back buffer until
7523 * the flip occurs and the object is no longer visible.
7524 */
Chris Wilson05394f32010-11-08 19:18:58 +00007525 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01007526
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007527 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7528 if (ret)
7529 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007530
Chris Wilson7782de32011-07-08 12:22:41 +01007531 intel_disable_fbc(dev);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007532 mutex_unlock(&dev->struct_mutex);
7533
Jesse Barnese5510fa2010-07-01 16:48:37 -07007534 trace_i915_flip_request(intel_crtc->plane, obj);
7535
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007536 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01007537
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07007538cleanup_pending:
7539 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
Chris Wilson05394f32010-11-08 19:18:58 +00007540 drm_gem_object_unreference(&work->old_fb_obj->base);
7541 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01007542 mutex_unlock(&dev->struct_mutex);
7543
7544 spin_lock_irqsave(&dev->event_lock, flags);
7545 intel_crtc->unpin_work = NULL;
7546 spin_unlock_irqrestore(&dev->event_lock, flags);
7547
Jesse Barnes7317c752011-08-29 09:45:28 -07007548 drm_vblank_put(dev, intel_crtc->pipe);
7549free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +01007550 kfree(work);
7551
7552 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05007553}
7554
Chris Wilson47f1c6c2010-12-03 15:37:31 +00007555static void intel_sanitize_modesetting(struct drm_device *dev,
7556 int pipe, int plane)
7557{
7558 struct drm_i915_private *dev_priv = dev->dev_private;
7559 u32 reg, val;
7560
7561 if (HAS_PCH_SPLIT(dev))
7562 return;
7563
7564 /* Who knows what state these registers were left in by the BIOS or
7565 * grub?
7566 *
7567 * If we leave the registers in a conflicting state (e.g. with the
7568 * display plane reading from the other pipe than the one we intend
7569 * to use) then when we attempt to teardown the active mode, we will
7570 * not disable the pipes and planes in the correct order -- leaving
7571 * a plane reading from a disabled pipe and possibly leading to
7572 * undefined behaviour.
7573 */
7574
7575 reg = DSPCNTR(plane);
7576 val = I915_READ(reg);
7577
7578 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7579 return;
7580 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7581 return;
7582
7583 /* This display plane is active and attached to the other CPU pipe. */
7584 pipe = !pipe;
7585
7586 /* Disable the plane and wait for it to stop reading from the pipe. */
Jesse Barnesb24e7172011-01-04 15:09:30 -08007587 intel_disable_plane(dev_priv, plane, pipe);
7588 intel_disable_pipe(dev_priv, pipe);
Chris Wilson47f1c6c2010-12-03 15:37:31 +00007589}
Jesse Barnes79e53942008-11-07 14:24:08 -08007590
Chris Wilsonf6e5b162011-04-12 18:06:51 +01007591static void intel_crtc_reset(struct drm_crtc *crtc)
7592{
7593 struct drm_device *dev = crtc->dev;
7594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7595
7596 /* Reset flags back to the 'unknown' status so that they
7597 * will be correctly set on the initial modeset.
7598 */
7599 intel_crtc->dpms_mode = -1;
7600
7601 /* We need to fix up any BIOS configuration that conflicts with
7602 * our expectations.
7603 */
7604 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7605}
7606
7607static struct drm_crtc_helper_funcs intel_helper_funcs = {
7608 .dpms = intel_crtc_dpms,
7609 .mode_fixup = intel_crtc_mode_fixup,
7610 .mode_set = intel_crtc_mode_set,
7611 .mode_set_base = intel_pipe_set_base,
7612 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7613 .load_lut = intel_crtc_load_lut,
7614 .disable = intel_crtc_disable,
7615};
7616
7617static const struct drm_crtc_funcs intel_crtc_funcs = {
7618 .reset = intel_crtc_reset,
7619 .cursor_set = intel_crtc_cursor_set,
7620 .cursor_move = intel_crtc_cursor_move,
7621 .gamma_set = intel_crtc_gamma_set,
7622 .set_config = drm_crtc_helper_set_config,
7623 .destroy = intel_crtc_destroy,
7624 .page_flip = intel_crtc_page_flip,
7625};
7626
Hannes Ederb358d0a2008-12-18 21:18:47 +01007627static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08007628{
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08007629 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08007630 struct intel_crtc *intel_crtc;
7631 int i;
7632
7633 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7634 if (intel_crtc == NULL)
7635 return;
7636
7637 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7638
7639 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -08007640 for (i = 0; i < 256; i++) {
7641 intel_crtc->lut_r[i] = i;
7642 intel_crtc->lut_g[i] = i;
7643 intel_crtc->lut_b[i] = i;
7644 }
7645
Jesse Barnes80824002009-09-10 15:28:06 -07007646 /* Swap pipes & planes for FBC on pre-965 */
7647 intel_crtc->pipe = pipe;
7648 intel_crtc->plane = pipe;
Chris Wilsone2e767a2010-09-13 16:53:12 +01007649 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08007650 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +01007651 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07007652 }
7653
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08007654 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7655 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7656 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7657 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7658
Chris Wilson5d1d0cc2011-01-24 15:02:15 +00007659 intel_crtc_reset(&intel_crtc->base);
Chris Wilson04dbff52011-02-10 17:38:35 +00007660 intel_crtc->active = true; /* force the pipe off on setup_init_config */
Jesse Barnes5a354202011-06-24 12:19:22 -07007661 intel_crtc->bpp = 24; /* default for pre-Ironlake */
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07007662
7663 if (HAS_PCH_SPLIT(dev)) {
Jesse Barnes4b645f12011-10-12 09:51:31 -07007664 if (pipe == 2 && IS_IVYBRIDGE(dev))
7665 intel_crtc->no_pll = true;
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07007666 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7667 intel_helper_funcs.commit = ironlake_crtc_commit;
7668 } else {
7669 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7670 intel_helper_funcs.commit = i9xx_crtc_commit;
7671 }
7672
Jesse Barnes79e53942008-11-07 14:24:08 -08007673 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7674
Jesse Barnes652c3932009-08-17 13:31:43 -07007675 intel_crtc->busy = false;
7676
7677 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7678 (unsigned long)intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08007679}
7680
Carl Worth08d7b3d2009-04-29 14:43:54 -07007681int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +00007682 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -07007683{
7684 drm_i915_private_t *dev_priv = dev->dev_private;
7685 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +02007686 struct drm_mode_object *drmmode_obj;
7687 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -07007688
7689 if (!dev_priv) {
7690 DRM_ERROR("called with no initialization\n");
7691 return -EINVAL;
7692 }
7693
Daniel Vetterc05422d2009-08-11 16:05:30 +02007694 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7695 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -07007696
Daniel Vetterc05422d2009-08-11 16:05:30 +02007697 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -07007698 DRM_ERROR("no such CRTC id\n");
7699 return -EINVAL;
7700 }
7701
Daniel Vetterc05422d2009-08-11 16:05:30 +02007702 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7703 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -07007704
Daniel Vetterc05422d2009-08-11 16:05:30 +02007705 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -07007706}
7707
Zhenyu Wangc5e4df32010-03-30 14:39:27 +08007708static int intel_encoder_clones(struct drm_device *dev, int type_mask)
Jesse Barnes79e53942008-11-07 14:24:08 -08007709{
Chris Wilson4ef69c72010-09-09 15:14:28 +01007710 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08007711 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08007712 int entry = 0;
7713
Chris Wilson4ef69c72010-09-09 15:14:28 +01007714 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7715 if (type_mask & encoder->clone_mask)
Jesse Barnes79e53942008-11-07 14:24:08 -08007716 index_mask |= (1 << entry);
7717 entry++;
7718 }
Chris Wilson4ef69c72010-09-09 15:14:28 +01007719
Jesse Barnes79e53942008-11-07 14:24:08 -08007720 return index_mask;
7721}
7722
Chris Wilson4d302442010-12-14 19:21:29 +00007723static bool has_edp_a(struct drm_device *dev)
7724{
7725 struct drm_i915_private *dev_priv = dev->dev_private;
7726
7727 if (!IS_MOBILE(dev))
7728 return false;
7729
7730 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7731 return false;
7732
7733 if (IS_GEN5(dev) &&
7734 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7735 return false;
7736
7737 return true;
7738}
7739
Jesse Barnes79e53942008-11-07 14:24:08 -08007740static void intel_setup_outputs(struct drm_device *dev)
7741{
Eric Anholt725e30a2009-01-22 13:01:02 -08007742 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +01007743 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -04007744 bool dpd_is_edp = false;
Chris Wilsonc5d1b512010-11-29 18:00:23 +00007745 bool has_lvds = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08007746
Zhenyu Wang541998a2009-06-05 15:38:44 +08007747 if (IS_MOBILE(dev) && !IS_I830(dev))
Chris Wilsonc5d1b512010-11-29 18:00:23 +00007748 has_lvds = intel_lvds_init(dev);
7749 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7750 /* disable the panel fitter on everything but LVDS */
7751 I915_WRITE(PFIT_CONTROL, 0);
7752 }
Jesse Barnes79e53942008-11-07 14:24:08 -08007753
Eric Anholtbad720f2009-10-22 16:11:14 -07007754 if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -04007755 dpd_is_edp = intel_dpd_is_edp(dev);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08007756
Chris Wilson4d302442010-12-14 19:21:29 +00007757 if (has_edp_a(dev))
Zhenyu Wang32f9d652009-07-24 01:00:32 +08007758 intel_dp_init(dev, DP_A);
7759
Adam Jacksoncb0953d2010-07-16 14:46:29 -04007760 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7761 intel_dp_init(dev, PCH_DP_D);
7762 }
7763
7764 intel_crt_init(dev);
7765
7766 if (HAS_PCH_SPLIT(dev)) {
7767 int found;
7768
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08007769 if (I915_READ(HDMIB) & PORT_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +08007770 /* PCH SDVOB multiplex with HDMIB */
7771 found = intel_sdvo_init(dev, PCH_SDVOB);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08007772 if (!found)
7773 intel_hdmi_init(dev, HDMIB);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08007774 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7775 intel_dp_init(dev, PCH_DP_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08007776 }
7777
7778 if (I915_READ(HDMIC) & PORT_DETECTED)
7779 intel_hdmi_init(dev, HDMIC);
7780
7781 if (I915_READ(HDMID) & PORT_DETECTED)
7782 intel_hdmi_init(dev, HDMID);
7783
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08007784 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7785 intel_dp_init(dev, PCH_DP_C);
7786
Adam Jacksoncb0953d2010-07-16 14:46:29 -04007787 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08007788 intel_dp_init(dev, PCH_DP_D);
7789
Zhenyu Wang103a1962009-11-27 11:44:36 +08007790 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +08007791 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -08007792
Eric Anholt725e30a2009-01-22 13:01:02 -08007793 if (I915_READ(SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007794 DRM_DEBUG_KMS("probing SDVOB\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08007795 found = intel_sdvo_init(dev, SDVOB);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007796 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7797 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08007798 intel_hdmi_init(dev, SDVOB);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007799 }
Ma Ling27185ae2009-08-24 13:50:23 +08007800
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007801 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7802 DRM_DEBUG_KMS("probing DP_B\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07007803 intel_dp_init(dev, DP_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007804 }
Eric Anholt725e30a2009-01-22 13:01:02 -08007805 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -04007806
7807 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -04007808
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007809 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7810 DRM_DEBUG_KMS("probing SDVOC\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08007811 found = intel_sdvo_init(dev, SDVOC);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007812 }
Ma Ling27185ae2009-08-24 13:50:23 +08007813
7814 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7815
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007816 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7817 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Eric Anholt725e30a2009-01-22 13:01:02 -08007818 intel_hdmi_init(dev, SDVOC);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007819 }
7820 if (SUPPORTS_INTEGRATED_DP(dev)) {
7821 DRM_DEBUG_KMS("probing DP_C\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07007822 intel_dp_init(dev, DP_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007823 }
Eric Anholt725e30a2009-01-22 13:01:02 -08007824 }
Ma Ling27185ae2009-08-24 13:50:23 +08007825
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007826 if (SUPPORTS_INTEGRATED_DP(dev) &&
7827 (I915_READ(DP_D) & DP_DETECTED)) {
7828 DRM_DEBUG_KMS("probing DP_D\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07007829 intel_dp_init(dev, DP_D);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08007830 }
Eric Anholtbad720f2009-10-22 16:11:14 -07007831 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08007832 intel_dvo_init(dev);
7833
Zhenyu Wang103a1962009-11-27 11:44:36 +08007834 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08007835 intel_tv_init(dev);
7836
Chris Wilson4ef69c72010-09-09 15:14:28 +01007837 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7838 encoder->base.possible_crtcs = encoder->crtc_mask;
7839 encoder->base.possible_clones =
7840 intel_encoder_clones(dev, encoder->clone_mask);
Jesse Barnes79e53942008-11-07 14:24:08 -08007841 }
Chris Wilson47356eb2011-01-11 17:06:04 +00007842
Chris Wilson2c7111d2011-03-29 10:40:27 +01007843 /* disable all the possible outputs/crtcs before entering KMS mode */
7844 drm_helper_disable_unused_functions(dev);
Keith Packard9fb526d2011-09-26 22:24:57 -07007845
7846 if (HAS_PCH_SPLIT(dev))
7847 ironlake_init_pch_refclk(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08007848}
7849
7850static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7851{
7852 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08007853
7854 drm_framebuffer_cleanup(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00007855 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08007856
7857 kfree(intel_fb);
7858}
7859
7860static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +00007861 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08007862 unsigned int *handle)
7863{
7864 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00007865 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08007866
Chris Wilson05394f32010-11-08 19:18:58 +00007867 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -08007868}
7869
7870static const struct drm_framebuffer_funcs intel_fb_funcs = {
7871 .destroy = intel_user_framebuffer_destroy,
7872 .create_handle = intel_user_framebuffer_create_handle,
7873};
7874
Dave Airlie38651672010-03-30 05:34:13 +00007875int intel_framebuffer_init(struct drm_device *dev,
7876 struct intel_framebuffer *intel_fb,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08007877 struct drm_mode_fb_cmd2 *mode_cmd,
Chris Wilson05394f32010-11-08 19:18:58 +00007878 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -08007879{
Jesse Barnes79e53942008-11-07 14:24:08 -08007880 int ret;
7881
Chris Wilson05394f32010-11-08 19:18:58 +00007882 if (obj->tiling_mode == I915_TILING_Y)
Chris Wilson57cd6502010-08-08 12:34:44 +01007883 return -EINVAL;
7884
Jesse Barnes308e5bc2011-11-14 14:51:28 -08007885 if (mode_cmd->pitches[0] & 63)
Chris Wilson57cd6502010-08-08 12:34:44 +01007886 return -EINVAL;
7887
Jesse Barnes308e5bc2011-11-14 14:51:28 -08007888 switch (mode_cmd->pixel_format) {
Ville Syrjälä04b39242011-11-17 18:05:13 +02007889 case DRM_FORMAT_RGB332:
7890 case DRM_FORMAT_RGB565:
7891 case DRM_FORMAT_XRGB8888:
7892 case DRM_FORMAT_ARGB8888:
7893 case DRM_FORMAT_XRGB2101010:
7894 case DRM_FORMAT_ARGB2101010:
Jesse Barnes308e5bc2011-11-14 14:51:28 -08007895 /* RGB formats are common across chipsets */
Jesse Barnesb5626742011-06-24 12:19:27 -07007896 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +02007897 case DRM_FORMAT_YUYV:
7898 case DRM_FORMAT_UYVY:
7899 case DRM_FORMAT_YVYU:
7900 case DRM_FORMAT_VYUY:
Chris Wilson57cd6502010-08-08 12:34:44 +01007901 break;
7902 default:
Eugeni Dodonovaca25842012-01-17 15:25:45 -02007903 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7904 mode_cmd->pixel_format);
Chris Wilson57cd6502010-08-08 12:34:44 +01007905 return -EINVAL;
7906 }
7907
Jesse Barnes79e53942008-11-07 14:24:08 -08007908 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7909 if (ret) {
7910 DRM_ERROR("framebuffer init failed %d\n", ret);
7911 return ret;
7912 }
7913
7914 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
Jesse Barnes79e53942008-11-07 14:24:08 -08007915 intel_fb->obj = obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08007916 return 0;
7917}
7918
Jesse Barnes79e53942008-11-07 14:24:08 -08007919static struct drm_framebuffer *
7920intel_user_framebuffer_create(struct drm_device *dev,
7921 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08007922 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -08007923{
Chris Wilson05394f32010-11-08 19:18:58 +00007924 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08007925
Jesse Barnes308e5bc2011-11-14 14:51:28 -08007926 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7927 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +00007928 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +01007929 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -08007930
Chris Wilsond2dff872011-04-19 08:36:26 +01007931 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08007932}
7933
Jesse Barnes79e53942008-11-07 14:24:08 -08007934static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -08007935 .fb_create = intel_user_framebuffer_create,
Dave Airlieeb1f8e42010-05-07 06:42:51 +00007936 .output_poll_changed = intel_fb_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -08007937};
7938
Chris Wilson05394f32010-11-08 19:18:58 +00007939static struct drm_i915_gem_object *
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08007940intel_alloc_context_page(struct drm_device *dev)
Chris Wilson9ea8d052010-01-04 18:57:56 +00007941{
Chris Wilson05394f32010-11-08 19:18:58 +00007942 struct drm_i915_gem_object *ctx;
Chris Wilson9ea8d052010-01-04 18:57:56 +00007943 int ret;
7944
Ben Widawsky2c34b852011-03-19 18:14:26 -07007945 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7946
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08007947 ctx = i915_gem_alloc_object(dev, 4096);
7948 if (!ctx) {
Chris Wilson9ea8d052010-01-04 18:57:56 +00007949 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7950 return NULL;
7951 }
7952
Daniel Vetter75e9e912010-11-04 17:11:09 +01007953 ret = i915_gem_object_pin(ctx, 4096, true);
Chris Wilson9ea8d052010-01-04 18:57:56 +00007954 if (ret) {
7955 DRM_ERROR("failed to pin power context: %d\n", ret);
7956 goto err_unref;
7957 }
7958
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08007959 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
Chris Wilson9ea8d052010-01-04 18:57:56 +00007960 if (ret) {
7961 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7962 goto err_unpin;
7963 }
Chris Wilson9ea8d052010-01-04 18:57:56 +00007964
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08007965 return ctx;
Chris Wilson9ea8d052010-01-04 18:57:56 +00007966
7967err_unpin:
Zou Nan haiaa40d6b2010-06-25 13:40:23 +08007968 i915_gem_object_unpin(ctx);
Chris Wilson9ea8d052010-01-04 18:57:56 +00007969err_unref:
Chris Wilson05394f32010-11-08 19:18:58 +00007970 drm_gem_object_unreference(&ctx->base);
Chris Wilson9ea8d052010-01-04 18:57:56 +00007971 mutex_unlock(&dev->struct_mutex);
7972 return NULL;
7973}
7974
Jesse Barnes7648fa92010-05-20 14:28:11 -07007975bool ironlake_set_drps(struct drm_device *dev, u8 val)
7976{
7977 struct drm_i915_private *dev_priv = dev->dev_private;
7978 u16 rgvswctl;
7979
7980 rgvswctl = I915_READ16(MEMSWCTL);
7981 if (rgvswctl & MEMCTL_CMD_STS) {
7982 DRM_DEBUG("gpu busy, RCS change rejected\n");
7983 return false; /* still busy with another command */
7984 }
7985
7986 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7987 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7988 I915_WRITE16(MEMSWCTL, rgvswctl);
7989 POSTING_READ16(MEMSWCTL);
7990
7991 rgvswctl |= MEMCTL_CMD_STS;
7992 I915_WRITE16(MEMSWCTL, rgvswctl);
7993
7994 return true;
7995}
7996
Jesse Barnesf97108d2010-01-29 11:27:07 -08007997void ironlake_enable_drps(struct drm_device *dev)
7998{
7999 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7648fa92010-05-20 14:28:11 -07008000 u32 rgvmodectl = I915_READ(MEMMODECTL);
Jesse Barnesf97108d2010-01-29 11:27:07 -08008001 u8 fmax, fmin, fstart, vstart;
Jesse Barnesf97108d2010-01-29 11:27:07 -08008002
Jesse Barnesea056c12010-09-10 10:02:13 -07008003 /* Enable temp reporting */
8004 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8005 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8006
Jesse Barnesf97108d2010-01-29 11:27:07 -08008007 /* 100ms RC evaluation intervals */
8008 I915_WRITE(RCUPEI, 100000);
8009 I915_WRITE(RCDNEI, 100000);
8010
8011 /* Set max/min thresholds to 90ms and 80ms respectively */
8012 I915_WRITE(RCBMAXAVG, 90000);
8013 I915_WRITE(RCBMINAVG, 80000);
8014
8015 I915_WRITE(MEMIHYST, 1);
8016
8017 /* Set up min, max, and cur for interrupt handling */
8018 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8019 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8020 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8021 MEMMODE_FSTART_SHIFT;
Jesse Barnes7648fa92010-05-20 14:28:11 -07008022
Jesse Barnesf97108d2010-01-29 11:27:07 -08008023 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8024 PXVFREQ_PX_SHIFT;
8025
Jesse Barnes80dbf4b2010-11-01 14:12:01 -07008026 dev_priv->fmax = fmax; /* IPS callback will increase this */
Jesse Barnes7648fa92010-05-20 14:28:11 -07008027 dev_priv->fstart = fstart;
8028
Jesse Barnes80dbf4b2010-11-01 14:12:01 -07008029 dev_priv->max_delay = fstart;
Jesse Barnesf97108d2010-01-29 11:27:07 -08008030 dev_priv->min_delay = fmin;
8031 dev_priv->cur_delay = fstart;
8032
Jesse Barnes80dbf4b2010-11-01 14:12:01 -07008033 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8034 fmax, fmin, fstart);
Jesse Barnes7648fa92010-05-20 14:28:11 -07008035
Jesse Barnesf97108d2010-01-29 11:27:07 -08008036 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8037
8038 /*
8039 * Interrupts will be enabled in ironlake_irq_postinstall
8040 */
8041
8042 I915_WRITE(VIDSTART, vstart);
8043 POSTING_READ(VIDSTART);
8044
8045 rgvmodectl |= MEMMODE_SWMODE_EN;
8046 I915_WRITE(MEMMODECTL, rgvmodectl);
8047
Chris Wilson481b6af2010-08-23 17:43:35 +01008048 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
Chris Wilson913d8d12010-08-07 11:01:35 +01008049 DRM_ERROR("stuck trying to change perf mode\n");
Jesse Barnesf97108d2010-01-29 11:27:07 -08008050 msleep(1);
8051
Jesse Barnes7648fa92010-05-20 14:28:11 -07008052 ironlake_set_drps(dev, fstart);
Jesse Barnesf97108d2010-01-29 11:27:07 -08008053
Jesse Barnes7648fa92010-05-20 14:28:11 -07008054 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8055 I915_READ(0x112e0);
8056 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8057 dev_priv->last_count2 = I915_READ(0x112f4);
8058 getrawmonotonic(&dev_priv->last_time2);
Jesse Barnesf97108d2010-01-29 11:27:07 -08008059}
8060
8061void ironlake_disable_drps(struct drm_device *dev)
8062{
8063 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7648fa92010-05-20 14:28:11 -07008064 u16 rgvswctl = I915_READ16(MEMSWCTL);
Jesse Barnesf97108d2010-01-29 11:27:07 -08008065
8066 /* Ack interrupts, disable EFC interrupt */
8067 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8068 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8069 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8070 I915_WRITE(DEIIR, DE_PCU_EVENT);
8071 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8072
8073 /* Go back to the starting frequency */
Jesse Barnes7648fa92010-05-20 14:28:11 -07008074 ironlake_set_drps(dev, dev_priv->fstart);
Jesse Barnesf97108d2010-01-29 11:27:07 -08008075 msleep(1);
8076 rgvswctl |= MEMCTL_CMD_STS;
8077 I915_WRITE(MEMSWCTL, rgvswctl);
8078 msleep(1);
8079
8080}
8081
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08008082void gen6_set_rps(struct drm_device *dev, u8 val)
8083{
8084 struct drm_i915_private *dev_priv = dev->dev_private;
8085 u32 swreq;
8086
8087 swreq = (val & 0x3ff) << 25;
8088 I915_WRITE(GEN6_RPNSWREQ, swreq);
8089}
8090
8091void gen6_disable_rps(struct drm_device *dev)
8092{
8093 struct drm_i915_private *dev_priv = dev->dev_private;
8094
8095 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8096 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8097 I915_WRITE(GEN6_PMIER, 0);
Daniel Vetter6fdd4d92011-09-08 14:00:22 +02008098 /* Complete PM interrupt masking here doesn't race with the rps work
8099 * item again unmasking PM interrupts because that is using a different
8100 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8101 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
Ben Widawsky4912d042011-04-25 11:25:20 -07008102
8103 spin_lock_irq(&dev_priv->rps_lock);
8104 dev_priv->pm_iir = 0;
8105 spin_unlock_irq(&dev_priv->rps_lock);
8106
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08008107 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8108}
8109
Jesse Barnes7648fa92010-05-20 14:28:11 -07008110static unsigned long intel_pxfreq(u32 vidfreq)
8111{
8112 unsigned long freq;
8113 int div = (vidfreq & 0x3f0000) >> 16;
8114 int post = (vidfreq & 0x3000) >> 12;
8115 int pre = (vidfreq & 0x7);
8116
8117 if (!pre)
8118 return 0;
8119
8120 freq = ((div * 133333) / ((1<<post) * pre));
8121
8122 return freq;
8123}
8124
8125void intel_init_emon(struct drm_device *dev)
8126{
8127 struct drm_i915_private *dev_priv = dev->dev_private;
8128 u32 lcfuse;
8129 u8 pxw[16];
8130 int i;
8131
8132 /* Disable to program */
8133 I915_WRITE(ECR, 0);
8134 POSTING_READ(ECR);
8135
8136 /* Program energy weights for various events */
8137 I915_WRITE(SDEW, 0x15040d00);
8138 I915_WRITE(CSIEW0, 0x007f0000);
8139 I915_WRITE(CSIEW1, 0x1e220004);
8140 I915_WRITE(CSIEW2, 0x04000004);
8141
8142 for (i = 0; i < 5; i++)
8143 I915_WRITE(PEW + (i * 4), 0);
8144 for (i = 0; i < 3; i++)
8145 I915_WRITE(DEW + (i * 4), 0);
8146
8147 /* Program P-state weights to account for frequency power adjustment */
8148 for (i = 0; i < 16; i++) {
8149 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8150 unsigned long freq = intel_pxfreq(pxvidfreq);
8151 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8152 PXVFREQ_PX_SHIFT;
8153 unsigned long val;
8154
8155 val = vid * vid;
8156 val *= (freq / 1000);
8157 val *= 255;
8158 val /= (127*127*900);
8159 if (val > 0xff)
8160 DRM_ERROR("bad pxval: %ld\n", val);
8161 pxw[i] = val;
8162 }
8163 /* Render standby states get 0 weight */
8164 pxw[14] = 0;
8165 pxw[15] = 0;
8166
8167 for (i = 0; i < 4; i++) {
8168 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8169 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8170 I915_WRITE(PXW + (i * 4), val);
8171 }
8172
8173 /* Adjust magic regs to magic values (more experimental results) */
8174 I915_WRITE(OGW0, 0);
8175 I915_WRITE(OGW1, 0);
8176 I915_WRITE(EG0, 0x00007f00);
8177 I915_WRITE(EG1, 0x0000000e);
8178 I915_WRITE(EG2, 0x000e0000);
8179 I915_WRITE(EG3, 0x68000300);
8180 I915_WRITE(EG4, 0x42000000);
8181 I915_WRITE(EG5, 0x00140031);
8182 I915_WRITE(EG6, 0);
8183 I915_WRITE(EG7, 0);
8184
8185 for (i = 0; i < 8; i++)
8186 I915_WRITE(PXWL + (i * 4), 0);
8187
8188 /* Enable PMON + select events */
8189 I915_WRITE(ECR, 0x80000019);
8190
8191 lcfuse = I915_READ(LCFUSE02);
8192
8193 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8194}
8195
Keith Packardc0f372b32011-11-16 22:24:52 -08008196static bool intel_enable_rc6(struct drm_device *dev)
8197{
8198 /*
8199 * Respect the kernel parameter if it is set
8200 */
8201 if (i915_enable_rc6 >= 0)
8202 return i915_enable_rc6;
8203
8204 /*
8205 * Disable RC6 on Ironlake
8206 */
8207 if (INTEL_INFO(dev)->gen == 5)
8208 return 0;
8209
8210 /*
8211 * Enable rc6 on Sandybridge if DMA remapping is disabled
8212 */
8213 if (INTEL_INFO(dev)->gen == 6) {
8214 DRM_DEBUG_DRIVER("Sandybridge: intel_iommu_enabled %s -- RC6 %sabled\n",
8215 intel_iommu_enabled ? "true" : "false",
8216 !intel_iommu_enabled ? "en" : "dis");
8217 return !intel_iommu_enabled;
8218 }
8219 DRM_DEBUG_DRIVER("RC6 enabled\n");
8220 return 1;
8221}
8222
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08008223void gen6_enable_rps(struct drm_i915_private *dev_priv)
Chris Wilson8fd26852010-12-08 18:40:43 +00008224{
Jesse Barnesa6044e22010-12-20 11:34:20 -08008225 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8226 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
Jesse Barnes7df87212011-03-30 14:08:56 -07008227 u32 pcu_mbox, rc6_mask = 0;
Jesse Barnesa6044e22010-12-20 11:34:20 -08008228 int cur_freq, min_freq, max_freq;
Chris Wilson8fd26852010-12-08 18:40:43 +00008229 int i;
8230
8231 /* Here begins a magic sequence of register writes to enable
8232 * auto-downclocking.
8233 *
8234 * Perhaps there might be some value in exposing these to
8235 * userspace...
8236 */
8237 I915_WRITE(GEN6_RC_STATE, 0);
Ben Widawskyd1ebd812011-04-25 20:11:50 +01008238 mutex_lock(&dev_priv->dev->struct_mutex);
Ben Widawskyfcca7922011-04-25 11:23:07 -07008239 gen6_gt_force_wake_get(dev_priv);
Chris Wilson8fd26852010-12-08 18:40:43 +00008240
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08008241 /* disable the counters and set deterministic thresholds */
Chris Wilson8fd26852010-12-08 18:40:43 +00008242 I915_WRITE(GEN6_RC_CONTROL, 0);
8243
8244 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8245 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8246 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8247 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8248 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8249
8250 for (i = 0; i < I915_NUM_RINGS; i++)
8251 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8252
8253 I915_WRITE(GEN6_RC_SLEEP, 0);
8254 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8255 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8256 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8257 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8258
Keith Packardc0f372b32011-11-16 22:24:52 -08008259 if (intel_enable_rc6(dev_priv->dev))
Jesse Barnes7df87212011-03-30 14:08:56 -07008260 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8261 GEN6_RC_CTL_RC6_ENABLE;
8262
Chris Wilson8fd26852010-12-08 18:40:43 +00008263 I915_WRITE(GEN6_RC_CONTROL,
Jesse Barnes7df87212011-03-30 14:08:56 -07008264 rc6_mask |
Chris Wilson9c3d2f72010-12-17 10:54:26 +00008265 GEN6_RC_CTL_EI_MODE(1) |
Chris Wilson8fd26852010-12-08 18:40:43 +00008266 GEN6_RC_CTL_HW_ENABLE);
8267
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08008268 I915_WRITE(GEN6_RPNSWREQ,
Chris Wilson8fd26852010-12-08 18:40:43 +00008269 GEN6_FREQUENCY(10) |
8270 GEN6_OFFSET(0) |
8271 GEN6_AGGRESSIVE_TURBO);
8272 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8273 GEN6_FREQUENCY(12));
8274
8275 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8276 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8277 18 << 24 |
8278 6 << 16);
Jesse Barnesccab5c82011-01-18 15:49:25 -08008279 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8280 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
Chris Wilson8fd26852010-12-08 18:40:43 +00008281 I915_WRITE(GEN6_RP_UP_EI, 100000);
Jesse Barnesccab5c82011-01-18 15:49:25 -08008282 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
Chris Wilson8fd26852010-12-08 18:40:43 +00008283 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8284 I915_WRITE(GEN6_RP_CONTROL,
8285 GEN6_RP_MEDIA_TURBO |
Ben Widawsky6ed55ee2011-12-12 19:21:59 -08008286 GEN6_RP_MEDIA_HW_MODE |
Chris Wilson8fd26852010-12-08 18:40:43 +00008287 GEN6_RP_MEDIA_IS_GFX |
8288 GEN6_RP_ENABLE |
Jesse Barnesccab5c82011-01-18 15:49:25 -08008289 GEN6_RP_UP_BUSY_AVG |
8290 GEN6_RP_DOWN_IDLE_CONT);
Chris Wilson8fd26852010-12-08 18:40:43 +00008291
8292 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8293 500))
8294 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8295
8296 I915_WRITE(GEN6_PCODE_DATA, 0);
8297 I915_WRITE(GEN6_PCODE_MAILBOX,
8298 GEN6_PCODE_READY |
8299 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8300 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8301 500))
8302 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8303
Jesse Barnesa6044e22010-12-20 11:34:20 -08008304 min_freq = (rp_state_cap & 0xff0000) >> 16;
8305 max_freq = rp_state_cap & 0xff;
8306 cur_freq = (gt_perf_status & 0xff00) >> 8;
8307
8308 /* Check for overclock support */
8309 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8310 500))
8311 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8312 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8313 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8314 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8315 500))
8316 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8317 if (pcu_mbox & (1<<31)) { /* OC supported */
8318 max_freq = pcu_mbox & 0xff;
Jesse Barnese281fca2011-03-18 10:32:07 -07008319 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
Jesse Barnesa6044e22010-12-20 11:34:20 -08008320 }
8321
8322 /* In units of 100MHz */
8323 dev_priv->max_delay = max_freq;
8324 dev_priv->min_delay = min_freq;
8325 dev_priv->cur_delay = cur_freq;
8326
Chris Wilson8fd26852010-12-08 18:40:43 +00008327 /* requires MSI enabled */
8328 I915_WRITE(GEN6_PMIER,
8329 GEN6_PM_MBOX_EVENT |
8330 GEN6_PM_THERMAL_EVENT |
8331 GEN6_PM_RP_DOWN_TIMEOUT |
8332 GEN6_PM_RP_UP_THRESHOLD |
8333 GEN6_PM_RP_DOWN_THRESHOLD |
8334 GEN6_PM_RP_UP_EI_EXPIRED |
8335 GEN6_PM_RP_DOWN_EI_EXPIRED);
Ben Widawsky4912d042011-04-25 11:25:20 -07008336 spin_lock_irq(&dev_priv->rps_lock);
8337 WARN_ON(dev_priv->pm_iir != 0);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08008338 I915_WRITE(GEN6_PMIMR, 0);
Ben Widawsky4912d042011-04-25 11:25:20 -07008339 spin_unlock_irq(&dev_priv->rps_lock);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08008340 /* enable all PM interrupts */
8341 I915_WRITE(GEN6_PMINTRMSK, 0);
Chris Wilson8fd26852010-12-08 18:40:43 +00008342
Ben Widawskyfcca7922011-04-25 11:23:07 -07008343 gen6_gt_force_wake_put(dev_priv);
Ben Widawskyd1ebd812011-04-25 20:11:50 +01008344 mutex_unlock(&dev_priv->dev->struct_mutex);
Chris Wilson8fd26852010-12-08 18:40:43 +00008345}
8346
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07008347void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8348{
8349 int min_freq = 15;
8350 int gpu_freq, ia_freq, max_ia_freq;
8351 int scaling_factor = 180;
8352
8353 max_ia_freq = cpufreq_quick_get_max(0);
8354 /*
8355 * Default to measured freq if none found, PCU will ensure we don't go
8356 * over
8357 */
8358 if (!max_ia_freq)
8359 max_ia_freq = tsc_khz;
8360
8361 /* Convert from kHz to MHz */
8362 max_ia_freq /= 1000;
8363
8364 mutex_lock(&dev_priv->dev->struct_mutex);
8365
8366 /*
8367 * For each potential GPU frequency, load a ring frequency we'd like
8368 * to use for memory access. We do this by specifying the IA frequency
8369 * the PCU should use as a reference to determine the ring frequency.
8370 */
8371 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8372 gpu_freq--) {
8373 int diff = dev_priv->max_delay - gpu_freq;
8374
8375 /*
8376 * For GPU frequencies less than 750MHz, just use the lowest
8377 * ring freq.
8378 */
8379 if (gpu_freq < min_freq)
8380 ia_freq = 800;
8381 else
8382 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8383 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8384
8385 I915_WRITE(GEN6_PCODE_DATA,
8386 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8387 gpu_freq);
8388 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8389 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8390 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8391 GEN6_PCODE_READY) == 0, 10)) {
8392 DRM_ERROR("pcode write of freq table timed out\n");
8393 continue;
8394 }
8395 }
8396
8397 mutex_unlock(&dev_priv->dev->struct_mutex);
8398}
8399
Jesse Barnes6067aae2011-04-28 15:04:31 -07008400static void ironlake_init_clock_gating(struct drm_device *dev)
8401{
8402 struct drm_i915_private *dev_priv = dev->dev_private;
8403 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8404
8405 /* Required for FBC */
8406 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8407 DPFCRUNIT_CLOCK_GATE_DISABLE |
8408 DPFDUNIT_CLOCK_GATE_DISABLE;
8409 /* Required for CxSR */
8410 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8411
8412 I915_WRITE(PCH_3DCGDIS0,
8413 MARIUNIT_CLOCK_GATE_DISABLE |
8414 SVSMUNIT_CLOCK_GATE_DISABLE);
8415 I915_WRITE(PCH_3DCGDIS1,
8416 VFMUNIT_CLOCK_GATE_DISABLE);
8417
8418 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8419
8420 /*
Jesse Barnes6067aae2011-04-28 15:04:31 -07008421 * According to the spec the following bits should be set in
8422 * order to enable memory self-refresh
8423 * The bit 22/21 of 0x42004
8424 * The bit 5 of 0x42020
8425 * The bit 15 of 0x45000
8426 */
8427 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8428 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8429 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8430 I915_WRITE(ILK_DSPCLK_GATE,
8431 (I915_READ(ILK_DSPCLK_GATE) |
8432 ILK_DPARB_CLK_GATE));
8433 I915_WRITE(DISP_ARB_CTL,
8434 (I915_READ(DISP_ARB_CTL) |
8435 DISP_FBC_WM_DIS));
8436 I915_WRITE(WM3_LP_ILK, 0);
8437 I915_WRITE(WM2_LP_ILK, 0);
8438 I915_WRITE(WM1_LP_ILK, 0);
8439
8440 /*
8441 * Based on the document from hardware guys the following bits
8442 * should be set unconditionally in order to enable FBC.
8443 * The bit 22 of 0x42000
8444 * The bit 22 of 0x42004
8445 * The bit 7,8,9 of 0x42020.
8446 */
8447 if (IS_IRONLAKE_M(dev)) {
8448 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8449 I915_READ(ILK_DISPLAY_CHICKEN1) |
8450 ILK_FBCQ_DIS);
8451 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8452 I915_READ(ILK_DISPLAY_CHICKEN2) |
8453 ILK_DPARB_GATE);
8454 I915_WRITE(ILK_DSPCLK_GATE,
8455 I915_READ(ILK_DSPCLK_GATE) |
8456 ILK_DPFC_DIS1 |
8457 ILK_DPFC_DIS2 |
8458 ILK_CLK_FBC);
8459 }
8460
8461 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8462 I915_READ(ILK_DISPLAY_CHICKEN2) |
8463 ILK_ELPIN_409_SELECT);
8464 I915_WRITE(_3D_CHICKEN2,
8465 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8466 _3D_CHICKEN2_WM_READ_PIPELINED);
8467}
8468
8469static void gen6_init_clock_gating(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07008470{
8471 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08008472 int pipe;
Jesse Barnes6067aae2011-04-28 15:04:31 -07008473 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8474
8475 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
Jesse Barnes652c3932009-08-17 13:31:43 -07008476
Jesse Barnes6067aae2011-04-28 15:04:31 -07008477 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8478 I915_READ(ILK_DISPLAY_CHICKEN2) |
8479 ILK_ELPIN_409_SELECT);
Eric Anholt8956c8b2010-03-18 13:21:14 -07008480
Jesse Barnes6067aae2011-04-28 15:04:31 -07008481 I915_WRITE(WM3_LP_ILK, 0);
8482 I915_WRITE(WM2_LP_ILK, 0);
8483 I915_WRITE(WM1_LP_ILK, 0);
Eric Anholt8956c8b2010-03-18 13:21:14 -07008484
Eric Anholt406478d2011-11-07 16:07:04 -08008485 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8486 * gating disable must be set. Failure to set it results in
8487 * flickering pixels due to Z write ordering failures after
8488 * some amount of runtime in the Mesa "fire" demo, and Unigine
8489 * Sanctuary and Tropics, and apparently anything else with
8490 * alpha test or pixel discard.
Eric Anholt9ca1d102011-11-07 16:07:05 -08008491 *
8492 * According to the spec, bit 11 (RCCUNIT) must also be set,
8493 * but we didn't debug actual testcases to find it out.
Eric Anholt406478d2011-11-07 16:07:04 -08008494 */
Eric Anholt9ca1d102011-11-07 16:07:05 -08008495 I915_WRITE(GEN6_UCGCTL2,
8496 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8497 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
Eric Anholt406478d2011-11-07 16:07:04 -08008498
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08008499 /*
Jesse Barnes6067aae2011-04-28 15:04:31 -07008500 * According to the spec the following bits should be
8501 * set in order to enable memory self-refresh and fbc:
8502 * The bit21 and bit22 of 0x42000
8503 * The bit21 and bit22 of 0x42004
8504 * The bit5 and bit7 of 0x42020
8505 * The bit14 of 0x70180
8506 * The bit14 of 0x71180
Jesse Barnes382b0932010-10-07 16:01:25 -07008507 */
Jesse Barnes6067aae2011-04-28 15:04:31 -07008508 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8509 I915_READ(ILK_DISPLAY_CHICKEN1) |
8510 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8511 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8512 I915_READ(ILK_DISPLAY_CHICKEN2) |
8513 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8514 I915_WRITE(ILK_DSPCLK_GATE,
8515 I915_READ(ILK_DSPCLK_GATE) |
8516 ILK_DPARB_CLK_GATE |
8517 ILK_DPFD_CLK_GATE);
Jesse Barnes382b0932010-10-07 16:01:25 -07008518
Keith Packardd74362c2011-07-28 14:47:14 -07008519 for_each_pipe(pipe) {
Jesse Barnes6067aae2011-04-28 15:04:31 -07008520 I915_WRITE(DSPCNTR(pipe),
8521 I915_READ(DSPCNTR(pipe)) |
8522 DISPPLANE_TRICKLE_FEED_DISABLE);
Keith Packardd74362c2011-07-28 14:47:14 -07008523 intel_flush_display_plane(dev_priv, pipe);
8524 }
Jesse Barnes6067aae2011-04-28 15:04:31 -07008525}
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08008526
Jesse Barnes28963a32011-05-11 09:42:30 -07008527static void ivybridge_init_clock_gating(struct drm_device *dev)
8528{
8529 struct drm_i915_private *dev_priv = dev->dev_private;
8530 int pipe;
8531 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
Jesse Barnes652c3932009-08-17 13:31:43 -07008532
Jesse Barnes28963a32011-05-11 09:42:30 -07008533 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08008534
Jesse Barnes28963a32011-05-11 09:42:30 -07008535 I915_WRITE(WM3_LP_ILK, 0);
8536 I915_WRITE(WM2_LP_ILK, 0);
8537 I915_WRITE(WM1_LP_ILK, 0);
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08008538
Jesse Barnes28963a32011-05-11 09:42:30 -07008539 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
Eric Anholtde6e2ea2010-11-06 14:53:32 -07008540
Eric Anholt116ac8d2011-12-21 10:31:09 -08008541 I915_WRITE(IVB_CHICKEN3,
8542 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8543 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8544
Keith Packardd74362c2011-07-28 14:47:14 -07008545 for_each_pipe(pipe) {
Jesse Barnes28963a32011-05-11 09:42:30 -07008546 I915_WRITE(DSPCNTR(pipe),
8547 I915_READ(DSPCNTR(pipe)) |
8548 DISPPLANE_TRICKLE_FEED_DISABLE);
Keith Packardd74362c2011-07-28 14:47:14 -07008549 intel_flush_display_plane(dev_priv, pipe);
8550 }
Jesse Barnes28963a32011-05-11 09:42:30 -07008551}
Eric Anholt67e92af2010-11-06 14:53:33 -07008552
Jesse Barnes6067aae2011-04-28 15:04:31 -07008553static void g4x_init_clock_gating(struct drm_device *dev)
8554{
8555 struct drm_i915_private *dev_priv = dev->dev_private;
8556 uint32_t dspclk_gate;
Chris Wilson8fd26852010-12-08 18:40:43 +00008557
Jesse Barnes6067aae2011-04-28 15:04:31 -07008558 I915_WRITE(RENCLK_GATE_D1, 0);
8559 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8560 GS_UNIT_CLOCK_GATE_DISABLE |
8561 CL_UNIT_CLOCK_GATE_DISABLE);
8562 I915_WRITE(RAMCLK_GATE_D, 0);
8563 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8564 OVRUNIT_CLOCK_GATE_DISABLE |
8565 OVCUNIT_CLOCK_GATE_DISABLE;
8566 if (IS_GM45(dev))
8567 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8568 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8569}
Yuanhan Liu13982612010-12-15 15:42:31 +08008570
Jesse Barnes6067aae2011-04-28 15:04:31 -07008571static void crestline_init_clock_gating(struct drm_device *dev)
8572{
8573 struct drm_i915_private *dev_priv = dev->dev_private;
Yuanhan Liu13982612010-12-15 15:42:31 +08008574
Jesse Barnes6067aae2011-04-28 15:04:31 -07008575 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8576 I915_WRITE(RENCLK_GATE_D2, 0);
8577 I915_WRITE(DSPCLK_GATE_D, 0);
8578 I915_WRITE(RAMCLK_GATE_D, 0);
8579 I915_WRITE16(DEUC, 0);
8580}
Jesse Barnes652c3932009-08-17 13:31:43 -07008581
Jesse Barnes6067aae2011-04-28 15:04:31 -07008582static void broadwater_init_clock_gating(struct drm_device *dev)
8583{
8584 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes652c3932009-08-17 13:31:43 -07008585
Jesse Barnes6067aae2011-04-28 15:04:31 -07008586 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8587 I965_RCC_CLOCK_GATE_DISABLE |
8588 I965_RCPB_CLOCK_GATE_DISABLE |
8589 I965_ISC_CLOCK_GATE_DISABLE |
8590 I965_FBC_CLOCK_GATE_DISABLE);
8591 I915_WRITE(RENCLK_GATE_D2, 0);
8592}
Jesse Barnes652c3932009-08-17 13:31:43 -07008593
Jesse Barnes6067aae2011-04-28 15:04:31 -07008594static void gen3_init_clock_gating(struct drm_device *dev)
8595{
8596 struct drm_i915_private *dev_priv = dev->dev_private;
8597 u32 dstate = I915_READ(D_STATE);
8598
8599 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8600 DSTATE_DOT_CLOCK_GATING;
8601 I915_WRITE(D_STATE, dstate);
8602}
8603
8604static void i85x_init_clock_gating(struct drm_device *dev)
8605{
8606 struct drm_i915_private *dev_priv = dev->dev_private;
8607
8608 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8609}
8610
8611static void i830_init_clock_gating(struct drm_device *dev)
8612{
8613 struct drm_i915_private *dev_priv = dev->dev_private;
8614
8615 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
Jesse Barnes652c3932009-08-17 13:31:43 -07008616}
8617
Jesse Barnes645c62a2011-05-11 09:49:31 -07008618static void ibx_init_clock_gating(struct drm_device *dev)
8619{
8620 struct drm_i915_private *dev_priv = dev->dev_private;
8621
8622 /*
8623 * On Ibex Peak and Cougar Point, we need to disable clock
8624 * gating for the panel power sequencer or it will fail to
8625 * start up when no ports are active.
8626 */
8627 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8628}
8629
8630static void cpt_init_clock_gating(struct drm_device *dev)
8631{
8632 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes3bcf6032011-07-27 11:51:40 -07008633 int pipe;
Jesse Barnes645c62a2011-05-11 09:49:31 -07008634
8635 /*
8636 * On Ibex Peak and Cougar Point, we need to disable clock
8637 * gating for the panel power sequencer or it will fail to
8638 * start up when no ports are active.
8639 */
8640 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8641 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8642 DPLS_EDP_PPS_FIX_DIS);
Jesse Barnes3bcf6032011-07-27 11:51:40 -07008643 /* Without this, mode sets may fail silently on FDI */
8644 for_each_pipe(pipe)
8645 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
Jesse Barnes79e53942008-11-07 14:24:08 -08008646}
8647
Chris Wilsonac668082011-02-09 16:15:32 +00008648static void ironlake_teardown_rc6(struct drm_device *dev)
Chris Wilson0cdab212010-12-05 17:27:06 +00008649{
8650 struct drm_i915_private *dev_priv = dev->dev_private;
8651
8652 if (dev_priv->renderctx) {
Chris Wilsonac668082011-02-09 16:15:32 +00008653 i915_gem_object_unpin(dev_priv->renderctx);
8654 drm_gem_object_unreference(&dev_priv->renderctx->base);
Chris Wilson0cdab212010-12-05 17:27:06 +00008655 dev_priv->renderctx = NULL;
8656 }
8657
8658 if (dev_priv->pwrctx) {
Chris Wilsonac668082011-02-09 16:15:32 +00008659 i915_gem_object_unpin(dev_priv->pwrctx);
8660 drm_gem_object_unreference(&dev_priv->pwrctx->base);
Chris Wilson0cdab212010-12-05 17:27:06 +00008661 dev_priv->pwrctx = NULL;
8662 }
8663}
8664
Jesse Barnesd5bb0812011-01-05 12:01:26 -08008665static void ironlake_disable_rc6(struct drm_device *dev)
8666{
8667 struct drm_i915_private *dev_priv = dev->dev_private;
8668
Chris Wilsonac668082011-02-09 16:15:32 +00008669 if (I915_READ(PWRCTXA)) {
8670 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8671 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8672 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8673 50);
8674
8675 I915_WRITE(PWRCTXA, 0);
8676 POSTING_READ(PWRCTXA);
8677
8678 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8679 POSTING_READ(RSTDBYCTL);
8680 }
8681
Chris Wilson99507302011-02-24 09:42:52 +00008682 ironlake_teardown_rc6(dev);
Chris Wilsonac668082011-02-09 16:15:32 +00008683}
8684
8685static int ironlake_setup_rc6(struct drm_device *dev)
8686{
8687 struct drm_i915_private *dev_priv = dev->dev_private;
8688
8689 if (dev_priv->renderctx == NULL)
8690 dev_priv->renderctx = intel_alloc_context_page(dev);
8691 if (!dev_priv->renderctx)
8692 return -ENOMEM;
8693
8694 if (dev_priv->pwrctx == NULL)
8695 dev_priv->pwrctx = intel_alloc_context_page(dev);
8696 if (!dev_priv->pwrctx) {
8697 ironlake_teardown_rc6(dev);
8698 return -ENOMEM;
8699 }
8700
8701 return 0;
Jesse Barnesd5bb0812011-01-05 12:01:26 -08008702}
8703
8704void ironlake_enable_rc6(struct drm_device *dev)
8705{
8706 struct drm_i915_private *dev_priv = dev->dev_private;
8707 int ret;
8708
Chris Wilsonac668082011-02-09 16:15:32 +00008709 /* rc6 disabled by default due to repeated reports of hanging during
8710 * boot and resume.
8711 */
Keith Packardc0f372b32011-11-16 22:24:52 -08008712 if (!intel_enable_rc6(dev))
Chris Wilsonac668082011-02-09 16:15:32 +00008713 return;
8714
Ben Widawsky2c34b852011-03-19 18:14:26 -07008715 mutex_lock(&dev->struct_mutex);
Chris Wilsonac668082011-02-09 16:15:32 +00008716 ret = ironlake_setup_rc6(dev);
Ben Widawsky2c34b852011-03-19 18:14:26 -07008717 if (ret) {
8718 mutex_unlock(&dev->struct_mutex);
Chris Wilsonac668082011-02-09 16:15:32 +00008719 return;
Ben Widawsky2c34b852011-03-19 18:14:26 -07008720 }
Chris Wilsonac668082011-02-09 16:15:32 +00008721
Jesse Barnesd5bb0812011-01-05 12:01:26 -08008722 /*
8723 * GPU can automatically power down the render unit if given a page
8724 * to save state.
8725 */
8726 ret = BEGIN_LP_RING(6);
8727 if (ret) {
Chris Wilsonac668082011-02-09 16:15:32 +00008728 ironlake_teardown_rc6(dev);
Ben Widawsky2c34b852011-03-19 18:14:26 -07008729 mutex_unlock(&dev->struct_mutex);
Jesse Barnesd5bb0812011-01-05 12:01:26 -08008730 return;
8731 }
Chris Wilsonac668082011-02-09 16:15:32 +00008732
Jesse Barnesd5bb0812011-01-05 12:01:26 -08008733 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8734 OUT_RING(MI_SET_CONTEXT);
8735 OUT_RING(dev_priv->renderctx->gtt_offset |
8736 MI_MM_SPACE_GTT |
8737 MI_SAVE_EXT_STATE_EN |
8738 MI_RESTORE_EXT_STATE_EN |
8739 MI_RESTORE_INHIBIT);
8740 OUT_RING(MI_SUSPEND_FLUSH);
8741 OUT_RING(MI_NOOP);
8742 OUT_RING(MI_FLUSH);
8743 ADVANCE_LP_RING();
8744
Ben Widawsky4a246cf2011-03-19 18:14:28 -07008745 /*
8746 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8747 * does an implicit flush, combined with MI_FLUSH above, it should be
8748 * safe to assume that renderctx is valid
8749 */
8750 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8751 if (ret) {
8752 DRM_ERROR("failed to enable ironlake power power savings\n");
8753 ironlake_teardown_rc6(dev);
8754 mutex_unlock(&dev->struct_mutex);
8755 return;
8756 }
8757
Jesse Barnesd5bb0812011-01-05 12:01:26 -08008758 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8759 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
Ben Widawsky2c34b852011-03-19 18:14:26 -07008760 mutex_unlock(&dev->struct_mutex);
Jesse Barnesd5bb0812011-01-05 12:01:26 -08008761}
8762
Jesse Barnes645c62a2011-05-11 09:49:31 -07008763void intel_init_clock_gating(struct drm_device *dev)
8764{
8765 struct drm_i915_private *dev_priv = dev->dev_private;
8766
8767 dev_priv->display.init_clock_gating(dev);
8768
8769 if (dev_priv->display.init_pch_clock_gating)
8770 dev_priv->display.init_pch_clock_gating(dev);
8771}
Chris Wilsonac668082011-02-09 16:15:32 +00008772
Jesse Barnese70236a2009-09-21 10:42:27 -07008773/* Set up chip specific display functions */
8774static void intel_init_display(struct drm_device *dev)
8775{
8776 struct drm_i915_private *dev_priv = dev->dev_private;
8777
8778 /* We always want a DPMS function */
Eric Anholtf5640482011-03-30 13:01:02 -07008779 if (HAS_PCH_SPLIT(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008780 dev_priv->display.dpms = ironlake_crtc_dpms;
Eric Anholtf5640482011-03-30 13:01:02 -07008781 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
Jesse Barnes17638cd2011-06-24 12:19:23 -07008782 dev_priv->display.update_plane = ironlake_update_plane;
Eric Anholtf5640482011-03-30 13:01:02 -07008783 } else {
Jesse Barnese70236a2009-09-21 10:42:27 -07008784 dev_priv->display.dpms = i9xx_crtc_dpms;
Eric Anholtf5640482011-03-30 13:01:02 -07008785 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
Jesse Barnes17638cd2011-06-24 12:19:23 -07008786 dev_priv->display.update_plane = i9xx_update_plane;
Eric Anholtf5640482011-03-30 13:01:02 -07008787 }
Jesse Barnese70236a2009-09-21 10:42:27 -07008788
Adam Jacksonee5382a2010-04-23 11:17:39 -04008789 if (I915_HAS_FBC(dev)) {
Yuanhan Liu9c04f012010-12-15 15:42:32 +08008790 if (HAS_PCH_SPLIT(dev)) {
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08008791 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8792 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8793 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8794 } else if (IS_GM45(dev)) {
Jesse Barnes74dff282009-09-14 15:39:40 -07008795 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8796 dev_priv->display.enable_fbc = g4x_enable_fbc;
8797 dev_priv->display.disable_fbc = g4x_disable_fbc;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01008798 } else if (IS_CRESTLINE(dev)) {
Jesse Barnese70236a2009-09-21 10:42:27 -07008799 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8800 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8801 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8802 }
Jesse Barnes74dff282009-09-14 15:39:40 -07008803 /* 855GM needs testing */
Jesse Barnese70236a2009-09-21 10:42:27 -07008804 }
8805
8806 /* Returns the core display clock speed */
Akshay Joshi0206e352011-08-16 15:34:10 -04008807 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -07008808 dev_priv->display.get_display_clock_speed =
8809 i945_get_display_clock_speed;
8810 else if (IS_I915G(dev))
8811 dev_priv->display.get_display_clock_speed =
8812 i915_get_display_clock_speed;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05008813 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07008814 dev_priv->display.get_display_clock_speed =
8815 i9xx_misc_get_display_clock_speed;
8816 else if (IS_I915GM(dev))
8817 dev_priv->display.get_display_clock_speed =
8818 i915gm_get_display_clock_speed;
8819 else if (IS_I865G(dev))
8820 dev_priv->display.get_display_clock_speed =
8821 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +02008822 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07008823 dev_priv->display.get_display_clock_speed =
8824 i855_get_display_clock_speed;
8825 else /* 852, 830 */
8826 dev_priv->display.get_display_clock_speed =
8827 i830_get_display_clock_speed;
8828
8829 /* For FIFO watermark updates */
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08008830 if (HAS_PCH_SPLIT(dev)) {
Keith Packard8d715f02011-11-18 20:39:01 -08008831 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8832 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8833
8834 /* IVB configs may use multi-threaded forcewake */
8835 if (IS_IVYBRIDGE(dev)) {
8836 u32 ecobus;
8837
Keith Packardc7dffff2011-12-09 11:33:00 -08008838 /* A small trick here - if the bios hasn't configured MT forcewake,
8839 * and if the device is in RC6, then force_wake_mt_get will not wake
8840 * the device and the ECOBUS read will return zero. Which will be
8841 * (correctly) interpreted by the test below as MT forcewake being
8842 * disabled.
8843 */
Keith Packard8d715f02011-11-18 20:39:01 -08008844 mutex_lock(&dev->struct_mutex);
8845 __gen6_gt_force_wake_mt_get(dev_priv);
Keith Packardc7dffff2011-12-09 11:33:00 -08008846 ecobus = I915_READ_NOTRACE(ECOBUS);
Keith Packard8d715f02011-11-18 20:39:01 -08008847 __gen6_gt_force_wake_mt_put(dev_priv);
8848 mutex_unlock(&dev->struct_mutex);
8849
8850 if (ecobus & FORCEWAKE_MT_ENABLE) {
8851 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8852 dev_priv->display.force_wake_get =
8853 __gen6_gt_force_wake_mt_get;
8854 dev_priv->display.force_wake_put =
8855 __gen6_gt_force_wake_mt_put;
8856 }
8857 }
8858
Jesse Barnes645c62a2011-05-11 09:49:31 -07008859 if (HAS_PCH_IBX(dev))
8860 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8861 else if (HAS_PCH_CPT(dev))
8862 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8863
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01008864 if (IS_GEN5(dev)) {
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08008865 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8866 dev_priv->display.update_wm = ironlake_update_wm;
8867 else {
8868 DRM_DEBUG_KMS("Failed to get proper latency. "
8869 "Disable CxSR\n");
8870 dev_priv->display.update_wm = NULL;
8871 }
Jesse Barnes674cf962011-04-28 14:27:04 -07008872 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Jesse Barnes6067aae2011-04-28 15:04:31 -07008873 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
Wu Fengguange0dac652011-09-05 14:25:34 +08008874 dev_priv->display.write_eld = ironlake_write_eld;
Yuanhan Liu13982612010-12-15 15:42:31 +08008875 } else if (IS_GEN6(dev)) {
8876 if (SNB_READ_WM0_LATENCY()) {
8877 dev_priv->display.update_wm = sandybridge_update_wm;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08008878 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
Yuanhan Liu13982612010-12-15 15:42:31 +08008879 } else {
8880 DRM_DEBUG_KMS("Failed to read display plane latency. "
8881 "Disable CxSR\n");
8882 dev_priv->display.update_wm = NULL;
8883 }
Jesse Barnes674cf962011-04-28 14:27:04 -07008884 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Jesse Barnes6067aae2011-04-28 15:04:31 -07008885 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
Wu Fengguange0dac652011-09-05 14:25:34 +08008886 dev_priv->display.write_eld = ironlake_write_eld;
Jesse Barnes357555c2011-04-28 15:09:55 -07008887 } else if (IS_IVYBRIDGE(dev)) {
8888 /* FIXME: detect B0+ stepping and use auto training */
8889 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Jesse Barnesfe100d42011-04-28 14:29:45 -07008890 if (SNB_READ_WM0_LATENCY()) {
8891 dev_priv->display.update_wm = sandybridge_update_wm;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08008892 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
Jesse Barnesfe100d42011-04-28 14:29:45 -07008893 } else {
8894 DRM_DEBUG_KMS("Failed to read display plane latency. "
8895 "Disable CxSR\n");
8896 dev_priv->display.update_wm = NULL;
8897 }
Jesse Barnes28963a32011-05-11 09:42:30 -07008898 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
Wu Fengguange0dac652011-09-05 14:25:34 +08008899 dev_priv->display.write_eld = ironlake_write_eld;
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08008900 } else
8901 dev_priv->display.update_wm = NULL;
8902 } else if (IS_PINEVIEW(dev)) {
Zhao Yakuid4294342010-03-22 22:45:36 +08008903 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
Li Peng95534262010-05-18 18:58:44 +08008904 dev_priv->is_ddr3,
Zhao Yakuid4294342010-03-22 22:45:36 +08008905 dev_priv->fsb_freq,
8906 dev_priv->mem_freq)) {
8907 DRM_INFO("failed to find known CxSR latency "
Li Peng95534262010-05-18 18:58:44 +08008908 "(found ddr%s fsb freq %d, mem freq %d), "
Zhao Yakuid4294342010-03-22 22:45:36 +08008909 "disabling CxSR\n",
Akshay Joshi0206e352011-08-16 15:34:10 -04008910 (dev_priv->is_ddr3 == 1) ? "3" : "2",
Zhao Yakuid4294342010-03-22 22:45:36 +08008911 dev_priv->fsb_freq, dev_priv->mem_freq);
8912 /* Disable CxSR and never update its watermark again */
8913 pineview_disable_cxsr(dev);
8914 dev_priv->display.update_wm = NULL;
8915 } else
8916 dev_priv->display.update_wm = pineview_update_wm;
Jason Stubbs95e0ee92011-05-28 14:26:48 +10008917 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
Jesse Barnes6067aae2011-04-28 15:04:31 -07008918 } else if (IS_G4X(dev)) {
Wu Fengguange0dac652011-09-05 14:25:34 +08008919 dev_priv->display.write_eld = g4x_write_eld;
Jesse Barnese70236a2009-09-21 10:42:27 -07008920 dev_priv->display.update_wm = g4x_update_wm;
Jesse Barnes6067aae2011-04-28 15:04:31 -07008921 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8922 } else if (IS_GEN4(dev)) {
Jesse Barnese70236a2009-09-21 10:42:27 -07008923 dev_priv->display.update_wm = i965_update_wm;
Jesse Barnes6067aae2011-04-28 15:04:31 -07008924 if (IS_CRESTLINE(dev))
8925 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8926 else if (IS_BROADWATER(dev))
8927 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8928 } else if (IS_GEN3(dev)) {
Jesse Barnese70236a2009-09-21 10:42:27 -07008929 dev_priv->display.update_wm = i9xx_update_wm;
8930 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
Jesse Barnes6067aae2011-04-28 15:04:31 -07008931 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8932 } else if (IS_I865G(dev)) {
8933 dev_priv->display.update_wm = i830_update_wm;
8934 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8935 dev_priv->display.get_fifo_size = i830_get_fifo_size;
Adam Jackson8f4695e2010-04-16 18:20:57 -04008936 } else if (IS_I85X(dev)) {
8937 dev_priv->display.update_wm = i9xx_update_wm;
8938 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
Jesse Barnes6067aae2011-04-28 15:04:31 -07008939 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
Jesse Barnese70236a2009-09-21 10:42:27 -07008940 } else {
Adam Jackson8f4695e2010-04-16 18:20:57 -04008941 dev_priv->display.update_wm = i830_update_wm;
Jesse Barnes6067aae2011-04-28 15:04:31 -07008942 dev_priv->display.init_clock_gating = i830_init_clock_gating;
Adam Jackson8f4695e2010-04-16 18:20:57 -04008943 if (IS_845G(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07008944 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8945 else
8946 dev_priv->display.get_fifo_size = i830_get_fifo_size;
Jesse Barnese70236a2009-09-21 10:42:27 -07008947 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008948
8949 /* Default just returns -ENODEV to indicate unsupported */
8950 dev_priv->display.queue_flip = intel_default_queue_flip;
8951
8952 switch (INTEL_INFO(dev)->gen) {
8953 case 2:
8954 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8955 break;
8956
8957 case 3:
8958 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8959 break;
8960
8961 case 4:
8962 case 5:
8963 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8964 break;
8965
8966 case 6:
8967 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8968 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07008969 case 7:
8970 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8971 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07008972 }
Jesse Barnese70236a2009-09-21 10:42:27 -07008973}
8974
Jesse Barnesb690e962010-07-19 13:53:12 -07008975/*
8976 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8977 * resume, or other times. This quirk makes sure that's the case for
8978 * affected systems.
8979 */
Akshay Joshi0206e352011-08-16 15:34:10 -04008980static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -07008981{
8982 struct drm_i915_private *dev_priv = dev->dev_private;
8983
8984 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8985 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8986}
8987
Keith Packard435793d2011-07-12 14:56:22 -07008988/*
8989 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8990 */
8991static void quirk_ssc_force_disable(struct drm_device *dev)
8992{
8993 struct drm_i915_private *dev_priv = dev->dev_private;
8994 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8995}
8996
Jesse Barnesb690e962010-07-19 13:53:12 -07008997struct intel_quirk {
8998 int device;
8999 int subsystem_vendor;
9000 int subsystem_device;
9001 void (*hook)(struct drm_device *dev);
9002};
9003
9004struct intel_quirk intel_quirks[] = {
9005 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
9006 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
9007 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -04009008 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -07009009
9010 /* Thinkpad R31 needs pipe A force quirk */
9011 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9012 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9013 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9014
9015 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9016 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
9017 /* ThinkPad X40 needs pipe A force quirk */
9018
9019 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9020 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9021
9022 /* 855 & before need to leave pipe A & dpll A up */
9023 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9024 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Keith Packard435793d2011-07-12 14:56:22 -07009025
9026 /* Lenovo U160 cannot use SSC on LVDS */
9027 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +02009028
9029 /* Sony Vaio Y cannot use SSC on LVDS */
9030 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Jesse Barnesb690e962010-07-19 13:53:12 -07009031};
9032
9033static void intel_init_quirks(struct drm_device *dev)
9034{
9035 struct pci_dev *d = dev->pdev;
9036 int i;
9037
9038 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9039 struct intel_quirk *q = &intel_quirks[i];
9040
9041 if (d->device == q->device &&
9042 (d->subsystem_vendor == q->subsystem_vendor ||
9043 q->subsystem_vendor == PCI_ANY_ID) &&
9044 (d->subsystem_device == q->subsystem_device ||
9045 q->subsystem_device == PCI_ANY_ID))
9046 q->hook(dev);
9047 }
9048}
9049
Jesse Barnes9cce37f2010-08-13 15:11:26 -07009050/* Disable the VGA plane that we never use */
9051static void i915_disable_vga(struct drm_device *dev)
9052{
9053 struct drm_i915_private *dev_priv = dev->dev_private;
9054 u8 sr1;
9055 u32 vga_reg;
9056
9057 if (HAS_PCH_SPLIT(dev))
9058 vga_reg = CPU_VGACNTRL;
9059 else
9060 vga_reg = VGACNTRL;
9061
9062 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9063 outb(1, VGA_SR_INDEX);
9064 sr1 = inb(VGA_SR_DATA);
9065 outb(sr1 | 1<<5, VGA_SR_DATA);
9066 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9067 udelay(300);
9068
9069 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9070 POSTING_READ(vga_reg);
9071}
9072
Jesse Barnes79e53942008-11-07 14:24:08 -08009073void intel_modeset_init(struct drm_device *dev)
9074{
Jesse Barnes652c3932009-08-17 13:31:43 -07009075 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08009076 int i, ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08009077
9078 drm_mode_config_init(dev);
9079
9080 dev->mode_config.min_width = 0;
9081 dev->mode_config.min_height = 0;
9082
9083 dev->mode_config.funcs = (void *)&intel_mode_funcs;
9084
Jesse Barnesb690e962010-07-19 13:53:12 -07009085 intel_init_quirks(dev);
9086
Jesse Barnese70236a2009-09-21 10:42:27 -07009087 intel_init_display(dev);
9088
Chris Wilsona6c45cf2010-09-17 00:32:17 +01009089 if (IS_GEN2(dev)) {
9090 dev->mode_config.max_width = 2048;
9091 dev->mode_config.max_height = 2048;
9092 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -07009093 dev->mode_config.max_width = 4096;
9094 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -08009095 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +01009096 dev->mode_config.max_width = 8192;
9097 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -08009098 }
Chris Wilson35c30472010-12-22 14:07:12 +00009099 dev->mode_config.fb_base = dev->agp->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08009100
Zhao Yakui28c97732009-10-09 11:39:41 +08009101 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Dave Airliea3524f12010-06-06 18:59:41 +10009102 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -08009103
Dave Airliea3524f12010-06-06 18:59:41 +10009104 for (i = 0; i < dev_priv->num_pipe; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08009105 intel_crtc_init(dev, i);
Jesse Barnesb840d907f2011-12-13 13:19:38 -08009106 if (HAS_PCH_SPLIT(dev)) {
9107 ret = intel_plane_init(dev, i);
9108 if (ret)
9109 DRM_ERROR("plane %d init failed: %d\n",
9110 i, ret);
9111 }
Jesse Barnes79e53942008-11-07 14:24:08 -08009112 }
9113
Jesse Barnes9cce37f2010-08-13 15:11:26 -07009114 /* Just disable it once at startup */
9115 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08009116 intel_setup_outputs(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07009117
Jesse Barnes645c62a2011-05-11 09:49:31 -07009118 intel_init_clock_gating(dev);
Jesse Barnes9cce37f2010-08-13 15:11:26 -07009119
Jesse Barnes7648fa92010-05-20 14:28:11 -07009120 if (IS_IRONLAKE_M(dev)) {
Jesse Barnesf97108d2010-01-29 11:27:07 -08009121 ironlake_enable_drps(dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07009122 intel_init_emon(dev);
9123 }
Jesse Barnesf97108d2010-01-29 11:27:07 -08009124
Jesse Barnes1c70c0c2011-06-29 13:34:36 -07009125 if (IS_GEN6(dev) || IS_GEN7(dev)) {
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08009126 gen6_enable_rps(dev_priv);
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07009127 gen6_update_ring_freq(dev_priv);
9128 }
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08009129
Jesse Barnes652c3932009-08-17 13:31:43 -07009130 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9131 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9132 (unsigned long)dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01009133}
9134
9135void intel_modeset_gem_init(struct drm_device *dev)
9136{
9137 if (IS_IRONLAKE_M(dev))
9138 ironlake_enable_rc6(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +02009139
9140 intel_setup_overlay(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08009141}
9142
9143void intel_modeset_cleanup(struct drm_device *dev)
9144{
Jesse Barnes652c3932009-08-17 13:31:43 -07009145 struct drm_i915_private *dev_priv = dev->dev_private;
9146 struct drm_crtc *crtc;
9147 struct intel_crtc *intel_crtc;
9148
Keith Packardf87ea762010-10-03 19:36:26 -07009149 drm_kms_helper_poll_fini(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07009150 mutex_lock(&dev->struct_mutex);
9151
Jesse Barnes723bfd72010-10-07 16:01:13 -07009152 intel_unregister_dsm_handler();
9153
9154
Jesse Barnes652c3932009-08-17 13:31:43 -07009155 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9156 /* Skip inactive CRTCs */
9157 if (!crtc->fb)
9158 continue;
9159
9160 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3dec0092010-08-20 21:40:52 +02009161 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07009162 }
9163
Chris Wilson973d04f2011-07-08 12:22:37 +01009164 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -07009165
Jesse Barnesf97108d2010-01-29 11:27:07 -08009166 if (IS_IRONLAKE_M(dev))
9167 ironlake_disable_drps(dev);
Jesse Barnes1c70c0c2011-06-29 13:34:36 -07009168 if (IS_GEN6(dev) || IS_GEN7(dev))
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08009169 gen6_disable_rps(dev);
Jesse Barnesf97108d2010-01-29 11:27:07 -08009170
Jesse Barnesd5bb0812011-01-05 12:01:26 -08009171 if (IS_IRONLAKE_M(dev))
9172 ironlake_disable_rc6(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +00009173
Kristian Høgsberg69341a52009-11-11 12:19:17 -05009174 mutex_unlock(&dev->struct_mutex);
9175
Daniel Vetter6c0d93502010-08-20 18:26:46 +02009176 /* Disable the irq before mode object teardown, for the irq might
9177 * enqueue unpin/hotplug work. */
9178 drm_irq_uninstall(dev);
9179 cancel_work_sync(&dev_priv->hotplug_work);
Daniel Vetter6fdd4d92011-09-08 14:00:22 +02009180 cancel_work_sync(&dev_priv->rps_work);
Daniel Vetter6c0d93502010-08-20 18:26:46 +02009181
Chris Wilson1630fe72011-07-08 12:22:42 +01009182 /* flush any delayed tasks or pending work */
9183 flush_scheduled_work();
9184
Daniel Vetter3dec0092010-08-20 21:40:52 +02009185 /* Shut off idle work before the crtcs get freed. */
9186 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9187 intel_crtc = to_intel_crtc(crtc);
9188 del_timer_sync(&intel_crtc->idle_timer);
9189 }
9190 del_timer_sync(&dev_priv->idle_timer);
9191 cancel_work_sync(&dev_priv->idle_work);
9192
Jesse Barnes79e53942008-11-07 14:24:08 -08009193 drm_mode_config_cleanup(dev);
9194}
9195
Dave Airlie28d52042009-09-21 14:33:58 +10009196/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +08009197 * Return which encoder is currently attached for connector.
9198 */
Chris Wilsondf0e9242010-09-09 16:20:55 +01009199struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -08009200{
Chris Wilsondf0e9242010-09-09 16:20:55 +01009201 return &intel_attached_encoder(connector)->base;
9202}
Jesse Barnes79e53942008-11-07 14:24:08 -08009203
Chris Wilsondf0e9242010-09-09 16:20:55 +01009204void intel_connector_attach_encoder(struct intel_connector *connector,
9205 struct intel_encoder *encoder)
9206{
9207 connector->encoder = encoder;
9208 drm_mode_connector_attach_encoder(&connector->base,
9209 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08009210}
Dave Airlie28d52042009-09-21 14:33:58 +10009211
9212/*
9213 * set vga decode state - true == enable VGA decode
9214 */
9215int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9216{
9217 struct drm_i915_private *dev_priv = dev->dev_private;
9218 u16 gmch_ctrl;
9219
9220 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9221 if (state)
9222 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9223 else
9224 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9225 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9226 return 0;
9227}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009228
9229#ifdef CONFIG_DEBUG_FS
9230#include <linux/seq_file.h>
9231
9232struct intel_display_error_state {
9233 struct intel_cursor_error_state {
9234 u32 control;
9235 u32 position;
9236 u32 base;
9237 u32 size;
9238 } cursor[2];
9239
9240 struct intel_pipe_error_state {
9241 u32 conf;
9242 u32 source;
9243
9244 u32 htotal;
9245 u32 hblank;
9246 u32 hsync;
9247 u32 vtotal;
9248 u32 vblank;
9249 u32 vsync;
9250 } pipe[2];
9251
9252 struct intel_plane_error_state {
9253 u32 control;
9254 u32 stride;
9255 u32 size;
9256 u32 pos;
9257 u32 addr;
9258 u32 surface;
9259 u32 tile_offset;
9260 } plane[2];
9261};
9262
9263struct intel_display_error_state *
9264intel_display_capture_error_state(struct drm_device *dev)
9265{
Akshay Joshi0206e352011-08-16 15:34:10 -04009266 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009267 struct intel_display_error_state *error;
9268 int i;
9269
9270 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9271 if (error == NULL)
9272 return NULL;
9273
9274 for (i = 0; i < 2; i++) {
9275 error->cursor[i].control = I915_READ(CURCNTR(i));
9276 error->cursor[i].position = I915_READ(CURPOS(i));
9277 error->cursor[i].base = I915_READ(CURBASE(i));
9278
9279 error->plane[i].control = I915_READ(DSPCNTR(i));
9280 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9281 error->plane[i].size = I915_READ(DSPSIZE(i));
Akshay Joshi0206e352011-08-16 15:34:10 -04009282 error->plane[i].pos = I915_READ(DSPPOS(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00009283 error->plane[i].addr = I915_READ(DSPADDR(i));
9284 if (INTEL_INFO(dev)->gen >= 4) {
9285 error->plane[i].surface = I915_READ(DSPSURF(i));
9286 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9287 }
9288
9289 error->pipe[i].conf = I915_READ(PIPECONF(i));
9290 error->pipe[i].source = I915_READ(PIPESRC(i));
9291 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9292 error->pipe[i].hblank = I915_READ(HBLANK(i));
9293 error->pipe[i].hsync = I915_READ(HSYNC(i));
9294 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9295 error->pipe[i].vblank = I915_READ(VBLANK(i));
9296 error->pipe[i].vsync = I915_READ(VSYNC(i));
9297 }
9298
9299 return error;
9300}
9301
9302void
9303intel_display_print_error_state(struct seq_file *m,
9304 struct drm_device *dev,
9305 struct intel_display_error_state *error)
9306{
9307 int i;
9308
9309 for (i = 0; i < 2; i++) {
9310 seq_printf(m, "Pipe [%d]:\n", i);
9311 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9312 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9313 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9314 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9315 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9316 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9317 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9318 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9319
9320 seq_printf(m, "Plane [%d]:\n", i);
9321 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9322 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9323 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9324 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9325 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9326 if (INTEL_INFO(dev)->gen >= 4) {
9327 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9328 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9329 }
9330
9331 seq_printf(m, "Cursor [%d]:\n", i);
9332 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9333 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9334 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9335 }
9336}
9337#endif