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Kumar Gala10b35d92005-09-23 14:08:58 -05001#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
David Gibson3ddfbcf2005-11-10 12:56:55 +11004#include <asm/asm-compat.h>
Kumar Gala10b35d92005-09-23 14:08:58 -05005
6#define PPC_FEATURE_32 0x80000000
7#define PPC_FEATURE_64 0x40000000
8#define PPC_FEATURE_601_INSTR 0x20000000
9#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10#define PPC_FEATURE_HAS_FPU 0x08000000
11#define PPC_FEATURE_HAS_MMU 0x04000000
12#define PPC_FEATURE_HAS_4xxMAC 0x02000000
13#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14#define PPC_FEATURE_HAS_SPE 0x00800000
15#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
16#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
Paul Mackerras98599012005-10-22 16:51:34 +100017#define PPC_FEATURE_NO_TB 0x00100000
Paul Mackerrasa7ddc5e2005-11-10 14:29:18 +110018#define PPC_FEATURE_POWER4 0x00080000
19#define PPC_FEATURE_POWER5 0x00040000
20#define PPC_FEATURE_POWER5_PLUS 0x00020000
21#define PPC_FEATURE_CELL 0x00010000
Paul Mackerras80f15dc2006-01-14 10:11:39 +110022#define PPC_FEATURE_BOOKE 0x00008000
Kumar Gala10b35d92005-09-23 14:08:58 -050023
24#ifdef __KERNEL__
25#ifndef __ASSEMBLY__
26
27/* This structure can grow, it's real size is used by head.S code
28 * via the mkdefs mechanism.
29 */
30struct cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -050031
Kumar Gala10b35d92005-09-23 14:08:58 -050032typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
Kumar Gala10b35d92005-09-23 14:08:58 -050033
Anton Blanchard32a33992006-01-09 15:41:31 +110034enum powerpc_oprofile_type {
Andy Whitcroft7a45fb12006-01-13 12:35:49 +000035 PPC_OPROFILE_INVALID = 0,
36 PPC_OPROFILE_RS64 = 1,
37 PPC_OPROFILE_POWER4 = 2,
38 PPC_OPROFILE_G4 = 3,
39 PPC_OPROFILE_BOOKE = 4,
Anton Blanchard32a33992006-01-09 15:41:31 +110040};
41
Kumar Gala10b35d92005-09-23 14:08:58 -050042struct cpu_spec {
43 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
44 unsigned int pvr_mask;
45 unsigned int pvr_value;
46
47 char *cpu_name;
48 unsigned long cpu_features; /* Kernel features */
49 unsigned int cpu_user_features; /* Userland features */
50
51 /* cache line sizes */
52 unsigned int icache_bsize;
53 unsigned int dcache_bsize;
54
55 /* number of performance monitor counters */
56 unsigned int num_pmcs;
57
58 /* this is called to initialize various CPU bits like L1 cache,
59 * BHT, SPD, etc... from head.S before branching to identify_machine
60 */
61 cpu_setup_t cpu_setup;
Kumar Gala10b35d92005-09-23 14:08:58 -050062
63 /* Used by oprofile userspace to select the right counters */
64 char *oprofile_cpu_type;
65
66 /* Processor specific oprofile operations */
Anton Blanchard32a33992006-01-09 15:41:31 +110067 enum powerpc_oprofile_type oprofile_type;
Paul Mackerras80f15dc2006-01-14 10:11:39 +110068
69 /* Name of processor class, for the ELF AT_PLATFORM entry */
70 char *platform;
Kumar Gala10b35d92005-09-23 14:08:58 -050071};
72
Kumar Gala10b35d92005-09-23 14:08:58 -050073extern struct cpu_spec *cur_cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -050074
Paul Mackerras9b6b5632005-10-06 12:06:20 +100075extern void identify_cpu(unsigned long offset, unsigned long cpu);
76extern void do_cpu_ftr_fixups(unsigned long offset);
77
Kumar Gala10b35d92005-09-23 14:08:58 -050078#endif /* __ASSEMBLY__ */
79
80/* CPU kernel features */
81
82/* Retain the 32b definitions all use bottom half of word */
83#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
84#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
85#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
86#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
87#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
88#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
89#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
90#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
91#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
92#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
93#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
94#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
95#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
96#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
97#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
98#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
99#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
100#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
101#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
102#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
Benjamin Herrenschmidt5daf9072005-11-18 14:09:41 +1100103#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500104
105#ifdef __powerpc64__
106/* Add the 64b processor unique features in the top half of the word */
107#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
108#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
109#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
110#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500111#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
112#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
113#define CPU_FTR_CTRL ASM_CONST(0x0000008000000000)
114#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
115#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
116#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
117#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100118#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000)
Arnd Bergmannc902be72006-01-04 19:55:53 +0000119#define CPU_FTR_PAUSE_ZERO ASM_CONST(0x0000200000000000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500120#else
121/* ensure on 32b processors the flags are available for compiling but
122 * don't do anything */
123#define CPU_FTR_SLB ASM_CONST(0x0)
124#define CPU_FTR_16M_PAGE ASM_CONST(0x0)
125#define CPU_FTR_TLBIEL ASM_CONST(0x0)
126#define CPU_FTR_NOEXECUTE ASM_CONST(0x0)
Kumar Gala10b35d92005-09-23 14:08:58 -0500127#define CPU_FTR_IABR ASM_CONST(0x0)
128#define CPU_FTR_MMCRA ASM_CONST(0x0)
129#define CPU_FTR_CTRL ASM_CONST(0x0)
130#define CPU_FTR_SMT ASM_CONST(0x0)
131#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0)
132#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0)
133#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0)
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100134#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0)
Kumar Gala10b35d92005-09-23 14:08:58 -0500135#endif
136
137#ifndef __ASSEMBLY__
138
Kumar Gala10b35d92005-09-23 14:08:58 -0500139#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
140 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
141 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
142
143/* iSeries doesn't support large pages */
144#ifdef CONFIG_PPC_ISERIES
145#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
146#else
147#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
148#endif /* CONFIG_PPC_ISERIES */
149
150/* We only set the altivec features if the kernel was compiled with altivec
151 * support
152 */
153#ifdef CONFIG_ALTIVEC
154#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
155#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
156#else
157#define CPU_FTR_ALTIVEC_COMP 0
158#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
159#endif
160
161/* We need to mark all pages as being coherent if we're SMP or we
Kumar Gala1775dbb2006-02-22 09:46:02 -0600162 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
163 * it for PCI "streaming/prefetch" to work properly.
Kumar Gala10b35d92005-09-23 14:08:58 -0500164 */
Kumar Gala1775dbb2006-02-22 09:46:02 -0600165#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
166 || defined(CONFIG_PPC_83xx)
Kumar Gala10b35d92005-09-23 14:08:58 -0500167#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
168#else
169#define CPU_FTR_COMMON 0
170#endif
171
172/* The powersave features NAP & DOZE seems to confuse BDI when
173 debugging. So if a BDI is used, disable theses
174 */
175#ifndef CONFIG_BDI_SWITCH
176#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
177#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
178#else
179#define CPU_FTR_MAYBE_CAN_DOZE 0
180#define CPU_FTR_MAYBE_CAN_NAP 0
181#endif
182
183#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
184 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
185 !defined(CONFIG_BOOKE))
186
187enum {
188 CPU_FTRS_PPC601 = CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
189 CPU_FTRS_603 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
190 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
191 CPU_FTR_MAYBE_CAN_NAP,
192 CPU_FTRS_604 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
193 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
194 CPU_FTRS_740_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
195 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
196 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
197 CPU_FTRS_740 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
198 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
199 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
200 CPU_FTRS_750 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
201 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
202 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
203 CPU_FTRS_750FX1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
204 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
205 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
206 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
207 CPU_FTRS_750FX2 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
208 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
209 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
210 CPU_FTR_NO_DPM,
211 CPU_FTRS_750FX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
212 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
213 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
214 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
215 CPU_FTRS_750GX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
216 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
217 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
218 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
219 CPU_FTRS_7400_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
220 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
221 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
222 CPU_FTR_MAYBE_CAN_NAP,
223 CPU_FTRS_7400 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
224 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
225 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
226 CPU_FTR_MAYBE_CAN_NAP,
227 CPU_FTRS_7450_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
228 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
229 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
230 CPU_FTR_NEED_COHERENT,
231 CPU_FTRS_7450_21 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
232 CPU_FTR_USE_TB |
233 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
234 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
235 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
236 CPU_FTR_NEED_COHERENT,
237 CPU_FTRS_7450_23 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
238 CPU_FTR_USE_TB |
239 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
240 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
241 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
242 CPU_FTRS_7455_1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
243 CPU_FTR_USE_TB |
244 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
245 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
246 CPU_FTR_NEED_COHERENT,
247 CPU_FTRS_7455_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
248 CPU_FTR_USE_TB |
249 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
250 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
251 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
252 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
253 CPU_FTRS_7455 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
254 CPU_FTR_USE_TB |
255 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
256 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
257 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
258 CPU_FTR_NEED_COHERENT,
259 CPU_FTRS_7447_10 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
260 CPU_FTR_USE_TB |
261 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
262 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
263 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
264 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
265 CPU_FTRS_7447 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
266 CPU_FTR_USE_TB |
267 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
268 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
269 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
270 CPU_FTR_NEED_COHERENT,
271 CPU_FTRS_7447A = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
272 CPU_FTR_USE_TB |
273 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
274 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
275 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
276 CPU_FTR_NEED_COHERENT,
277 CPU_FTRS_82XX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
278 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
279 CPU_FTRS_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
280 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
281 CPU_FTRS_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
Kumar Gala1775dbb2006-02-22 09:46:02 -0600282 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS |
283 CPU_FTR_COMMON,
Kumar Gala10b35d92005-09-23 14:08:58 -0500284 CPU_FTRS_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
285 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
286 CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
287 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
288 CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
Benjamin Herrenschmidt5daf9072005-11-18 14:09:41 +1100289 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_NODSISRALIGN,
Kumar Gala10b35d92005-09-23 14:08:58 -0500290 CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
291 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
Benjamin Herrenschmidt5daf9072005-11-18 14:09:41 +1100292 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN,
Kumar Gala10b35d92005-09-23 14:08:58 -0500293 CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
Benjamin Herrenschmidt5daf9072005-11-18 14:09:41 +1100294 CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
295 CPU_FTR_NODSISRALIGN,
296 CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
297 CPU_FTR_NODSISRALIGN,
298 CPU_FTRS_E200 = CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN,
299 CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
300 CPU_FTR_NODSISRALIGN,
Kumar Gala10b35d92005-09-23 14:08:58 -0500301 CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
Benjamin Herrenschmidt5daf9072005-11-18 14:09:41 +1100302 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN,
303 CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN,
Kumar Gala10b35d92005-09-23 14:08:58 -0500304#ifdef __powerpc64__
305 CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
306 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
307 CPU_FTRS_RS64 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
308 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
309 CPU_FTR_MMCRA | CPU_FTR_CTRL,
310 CPU_FTRS_POWER4 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
311 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
312 CPU_FTRS_PPC970 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
313 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
314 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
315 CPU_FTRS_POWER5 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
316 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
317 CPU_FTR_MMCRA | CPU_FTR_SMT |
318 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
319 CPU_FTR_MMCRA_SIHV,
320 CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
321 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
Arnd Bergmannc902be72006-01-04 19:55:53 +0000322 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT |
323 CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO,
Kumar Gala10b35d92005-09-23 14:08:58 -0500324 CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
325 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
326#endif
327
328 CPU_FTRS_POSSIBLE =
Anton Blanchard2406f602005-12-13 07:45:33 +1100329#ifdef __powerpc64__
330 CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |
331 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL |
332 CPU_FTR_CI_LARGE_PAGE |
333#else
Kumar Gala10b35d92005-09-23 14:08:58 -0500334#if CLASSIC_PPC
335 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
336 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
337 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
338 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
339 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
340 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
341 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
342 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
343#else
344 CPU_FTRS_GENERIC_32 |
345#endif
346#ifdef CONFIG_PPC64BRIDGE
347 CPU_FTRS_POWER3_32 |
348#endif
349#ifdef CONFIG_POWER4
350 CPU_FTRS_POWER4_32 | CPU_FTRS_970_32 |
351#endif
352#ifdef CONFIG_8xx
353 CPU_FTRS_8XX |
354#endif
355#ifdef CONFIG_40x
356 CPU_FTRS_40X |
357#endif
358#ifdef CONFIG_44x
359 CPU_FTRS_44X |
360#endif
361#ifdef CONFIG_E200
362 CPU_FTRS_E200 |
363#endif
364#ifdef CONFIG_E500
365 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
366#endif
Anton Blanchard2406f602005-12-13 07:45:33 +1100367#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500368 0,
369
370 CPU_FTRS_ALWAYS =
Anton Blanchard2406f602005-12-13 07:45:33 +1100371#ifdef __powerpc64__
372 CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &
373 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL &
374#else
Kumar Gala10b35d92005-09-23 14:08:58 -0500375#if CLASSIC_PPC
376 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
377 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
378 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
379 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
380 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
381 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
382 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
383 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
384#else
385 CPU_FTRS_GENERIC_32 &
386#endif
387#ifdef CONFIG_PPC64BRIDGE
388 CPU_FTRS_POWER3_32 &
389#endif
390#ifdef CONFIG_POWER4
391 CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 &
392#endif
393#ifdef CONFIG_8xx
394 CPU_FTRS_8XX &
395#endif
396#ifdef CONFIG_40x
397 CPU_FTRS_40X &
398#endif
399#ifdef CONFIG_44x
400 CPU_FTRS_44X &
401#endif
402#ifdef CONFIG_E200
403 CPU_FTRS_E200 &
404#endif
405#ifdef CONFIG_E500
406 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
407#endif
Anton Blanchard2406f602005-12-13 07:45:33 +1100408#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500409 CPU_FTRS_POSSIBLE,
410};
411
412static inline int cpu_has_feature(unsigned long feature)
413{
414 return (CPU_FTRS_ALWAYS & feature) ||
415 (CPU_FTRS_POSSIBLE
Kumar Gala10b35d92005-09-23 14:08:58 -0500416 & cur_cpu_spec->cpu_features
Kumar Gala10b35d92005-09-23 14:08:58 -0500417 & feature);
418}
419
420#endif /* !__ASSEMBLY__ */
421
422#ifdef __ASSEMBLY__
423
424#define BEGIN_FTR_SECTION 98:
425
426#ifndef __powerpc64__
427#define END_FTR_SECTION(msk, val) \
42899: \
429 .section __ftr_fixup,"a"; \
430 .align 2; \
431 .long msk; \
432 .long val; \
433 .long 98b; \
434 .long 99b; \
435 .previous
436#else /* __powerpc64__ */
437#define END_FTR_SECTION(msk, val) \
43899: \
439 .section __ftr_fixup,"a"; \
440 .align 3; \
441 .llong msk; \
442 .llong val; \
443 .llong 98b; \
444 .llong 99b; \
445 .previous
446#endif /* __powerpc64__ */
447
448#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
449#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
450#endif /* __ASSEMBLY__ */
451
452#endif /* __KERNEL__ */
453#endif /* __ASM_POWERPC_CPUTABLE_H */