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gerrit-public.fairphone.software / kernel / msm / 18f2190d796198fbb5d4bc4c87511acf3ced7d47 / . / include / asm-powerpc / cputable.h
blob: 762d15e488791d39464fbcc74c0ccf1d19138f31 [file] [log] [blame]
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
David Gibson3ddfbcf2005-11-10 12:56:55 +1100[diff] [blame]4#include <asm/asm-compat.h>
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]5
6#define PPC_FEATURE_32 0x80000000
7#define PPC_FEATURE_64 0x40000000
8#define PPC_FEATURE_601_INSTR 0x20000000
9#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10#define PPC_FEATURE_HAS_FPU 0x08000000
11#define PPC_FEATURE_HAS_MMU 0x04000000
12#define PPC_FEATURE_HAS_4xxMAC 0x02000000
13#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14#define PPC_FEATURE_HAS_SPE 0x00800000
15#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
16#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
Paul Mackerras98599012005-10-22 16:51:34 +1000[diff] [blame]17#define PPC_FEATURE_NO_TB 0x00100000
Paul Mackerrasa7ddc5e2005-11-10 14:29:18 +1100[diff] [blame]18#define PPC_FEATURE_POWER4 0x00080000
19#define PPC_FEATURE_POWER5 0x00040000
20#define PPC_FEATURE_POWER5_PLUS 0x00020000
21#define PPC_FEATURE_CELL 0x00010000
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]22#define PPC_FEATURE_BOOKE 0x00008000
Benjamin Herrenschmidtaa5cb022006-03-01 15:07:07 +1100[diff] [blame]23#define PPC_FEATURE_SMT 0x00004000
24#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]25#define PPC_FEATURE_ARCH_2_05 0x00001000
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame]26#define PPC_FEATURE_PA6T 0x00000800
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]27
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]28#define PPC_FEATURE_TRUE_LE 0x00000002
29#define PPC_FEATURE_PPC_LE 0x00000001
30
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]31#ifdef __KERNEL__
32#ifndef __ASSEMBLY__
33
34/* This structure can grow, it's real size is used by head.S code
35 * via the mkdefs mechanism.
36 */
37struct cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]38
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]39typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
Olof Johanssonf39b7a52006-08-11 00:07:08 -0500[diff] [blame]40typedef void (*cpu_restore_t)(void);
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]41
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]42enum powerpc_oprofile_type {
Andy Whitcroft7a45fb12006-01-13 12:35:49 +0000[diff] [blame]43 PPC_OPROFILE_INVALID = 0,
44 PPC_OPROFILE_RS64 = 1,
45 PPC_OPROFILE_POWER4 = 2,
46 PPC_OPROFILE_G4 = 3,
47 PPC_OPROFILE_BOOKE = 4,
Maynard Johnson18f21902006-11-20 18:45:16 +0100[diff] [blame^]48 PPC_OPROFILE_CELL = 5,
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]49};
50
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]51struct cpu_spec {
52 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
53 unsigned int pvr_mask;
54 unsigned int pvr_value;
55
56 char *cpu_name;
57 unsigned long cpu_features; /* Kernel features */
58 unsigned int cpu_user_features; /* Userland features */
59
60 /* cache line sizes */
61 unsigned int icache_bsize;
62 unsigned int dcache_bsize;
63
64 /* number of performance monitor counters */
65 unsigned int num_pmcs;
66
67 /* this is called to initialize various CPU bits like L1 cache,
68 * BHT, SPD, etc... from head.S before branching to identify_machine
69 */
70 cpu_setup_t cpu_setup;
Olof Johanssonf39b7a52006-08-11 00:07:08 -0500[diff] [blame]71 /* Used to restore cpu setup on secondary processors and at resume */
72 cpu_restore_t cpu_restore;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]73
74 /* Used by oprofile userspace to select the right counters */
75 char *oprofile_cpu_type;
76
77 /* Processor specific oprofile operations */
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]78 enum powerpc_oprofile_type oprofile_type;
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]79
Michael Neulinge78dbc82006-06-08 14:42:34 +1000[diff] [blame]80 /* Bit locations inside the mmcra change */
81 unsigned long oprofile_mmcra_sihv;
82 unsigned long oprofile_mmcra_sipr;
83
84 /* Bits to clear during an oprofile exception */
85 unsigned long oprofile_mmcra_clear;
86
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]87 /* Name of processor class, for the ELF AT_PLATFORM entry */
88 char *platform;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]89};
90
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]91extern struct cpu_spec *cur_cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]92
Benjamin Herrenschmidt42c4aaa2006-10-24 16:42:40 +1000[diff] [blame]93extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
94
95extern struct cpu_spec *identify_cpu(unsigned long offset);
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]96extern void do_feature_fixups(unsigned long value, void *fixup_start,
97 void *fixup_end);
Paul Mackerras9b6b5632005-10-06 12:06:20 +1000[diff] [blame]98
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]99#endif /* __ASSEMBLY__ */
100
101/* CPU kernel features */
102
103/* Retain the 32b definitions all use bottom half of word */
104#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
105#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
106#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
107#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
108#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
109#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
110#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
111#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
112#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
113#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
114#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
115#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
116#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
117#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
118#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
119#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
120#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
121#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
122#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
123#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
Michael Ellerman3d159102006-03-21 20:45:58 +1100[diff] [blame]124#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]125#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
126#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]127
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]128/*
129 * Add the 64-bit processor unique features in the top half of the word;
130 * on 32-bit, make the names available but defined to be 0.
131 */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]132#ifdef __powerpc64__
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]133#define LONG_ASM_CONST(x) ASM_CONST(x)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]134#else
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]135#define LONG_ASM_CONST(x) 0
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]136#endif
137
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]138#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
139#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
140#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
141#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
142#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
143#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
144#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
145#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
146#define CPU_FTR_COHERENT_ICACHE LONG_ASM_CONST(0x0000020000000000)
147#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
148#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
149#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
150#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000[diff] [blame]151#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]152
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]153#ifndef __ASSEMBLY__
154
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]155#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
156 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]157 CPU_FTR_NODSISRALIGN)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]158
159/* iSeries doesn't support large pages */
160#ifdef CONFIG_PPC_ISERIES
161#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
162#else
163#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
164#endif /* CONFIG_PPC_ISERIES */
165
166/* We only set the altivec features if the kernel was compiled with altivec
167 * support
168 */
169#ifdef CONFIG_ALTIVEC
170#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
171#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
172#else
173#define CPU_FTR_ALTIVEC_COMP 0
174#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
175#endif
176
177/* We need to mark all pages as being coherent if we're SMP or we
Kumar Gala1775dbb2006-02-22 09:46:02 -0600[diff] [blame]178 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
179 * it for PCI "streaming/prefetch" to work properly.
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]180 */
Kumar Gala1775dbb2006-02-22 09:46:02 -0600[diff] [blame]181#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
182 || defined(CONFIG_PPC_83xx)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]183#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
184#else
185#define CPU_FTR_COMMON 0
186#endif
187
188/* The powersave features NAP & DOZE seems to confuse BDI when
189 debugging. So if a BDI is used, disable theses
190 */
191#ifndef CONFIG_BDI_SWITCH
192#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
193#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
194#else
195#define CPU_FTR_MAYBE_CAN_DOZE 0
196#define CPU_FTR_MAYBE_CAN_NAP 0
197#endif
198
199#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
200 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
201 !defined(CONFIG_BOOKE))
202
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]203#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
204#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
205 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]206 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]207#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]208 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
209 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]210#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
211 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]212 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]213#define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
214 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]215 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
216 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]217#define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
218 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]219 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
220 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]221#define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
222 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
223 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]224 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]225#define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
226 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
227 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]228 CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]229#define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
230 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
231 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]232 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]233#define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
234 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \
235 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]236 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]237#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
238 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
239 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]240 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]241#define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
242 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
243 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]244 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]245#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
246 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
247 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]248 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]249#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
250 CPU_FTR_USE_TB | \
251 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
252 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
253 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]254 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]255#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
256 CPU_FTR_USE_TB | \
257 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
258 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]259 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]260#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
261 CPU_FTR_USE_TB | \
262 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
263 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]264 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]265#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
266 CPU_FTR_USE_TB | \
267 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
268 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
269 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]270 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]271#define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
272 CPU_FTR_USE_TB | \
273 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
274 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
275 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]276 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]277#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
278 CPU_FTR_USE_TB | \
279 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
280 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
281 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]282 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]283#define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
284 CPU_FTR_USE_TB | \
285 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
286 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
287 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]288 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]289#define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
290 CPU_FTR_USE_TB | \
291 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
292 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
293 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]294 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]295#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
296 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
297#define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
298 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
299#define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
300 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
301 CPU_FTR_COMMON)
302#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
303 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]304#define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
305#define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
306 CPU_FTR_NODSISRALIGN)
307#define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
308 CPU_FTR_NODSISRALIGN)
309#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
310#define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
311 CPU_FTR_NODSISRALIGN)
312#define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
313 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
314#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]315#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]316#define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]317 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]318#define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
319 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
320 CPU_FTR_MMCRA | CPU_FTR_CTRL)
321#define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]322 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
323 CPU_FTR_MMCRA)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]324#define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]325 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]326 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
327#define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]328 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]329 CPU_FTR_MMCRA | CPU_FTR_SMT | \
330 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
Michael Neulinge78dbc82006-06-08 14:42:34 +1000[diff] [blame]331 CPU_FTR_PURR)
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]332#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]333 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]334 CPU_FTR_MMCRA | CPU_FTR_SMT | \
335 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]336 CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_REAL_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]337#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]338 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]339 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000[diff] [blame]340 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame]341#define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
342 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
343 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
344 CPU_FTR_PURR | CPU_FTR_REAL_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]345#define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
346 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]347#endif
348
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]349#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]350#define CPU_FTRS_POSSIBLE \
351 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]352 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame]353 CPU_FTRS_CELL | CPU_FTRS_PA6T)
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]354#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]355enum {
356 CPU_FTRS_POSSIBLE =
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]357#if CLASSIC_PPC
358 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
359 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
360 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
361 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
362 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
363 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
364 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
365 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
366#else
367 CPU_FTRS_GENERIC_32 |
368#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]369#ifdef CONFIG_8xx
370 CPU_FTRS_8XX |
371#endif
372#ifdef CONFIG_40x
373 CPU_FTRS_40X |
374#endif
375#ifdef CONFIG_44x
376 CPU_FTRS_44X |
377#endif
378#ifdef CONFIG_E200
379 CPU_FTRS_E200 |
380#endif
381#ifdef CONFIG_E500
382 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
383#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]384 0,
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]385};
386#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]387
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]388#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]389#define CPU_FTRS_ALWAYS \
390 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]391 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame]392 CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]393#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]394enum {
395 CPU_FTRS_ALWAYS =
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]396#if CLASSIC_PPC
397 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
398 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
399 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
400 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
401 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
402 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
403 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
404 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
405#else
406 CPU_FTRS_GENERIC_32 &
407#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]408#ifdef CONFIG_8xx
409 CPU_FTRS_8XX &
410#endif
411#ifdef CONFIG_40x
412 CPU_FTRS_40X &
413#endif
414#ifdef CONFIG_44x
415 CPU_FTRS_44X &
416#endif
417#ifdef CONFIG_E200
418 CPU_FTRS_E200 &
419#endif
420#ifdef CONFIG_E500
421 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
422#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]423 CPU_FTRS_POSSIBLE,
424};
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]425#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]426
427static inline int cpu_has_feature(unsigned long feature)
428{
429 return (CPU_FTRS_ALWAYS & feature) ||
430 (CPU_FTRS_POSSIBLE
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]431 & cur_cpu_spec->cpu_features
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]432 & feature);
433}
434
435#endif /* !__ASSEMBLY__ */
436
437#ifdef __ASSEMBLY__
438
Benjamin Herrenschmidt7aeb7322006-10-20 11:47:16 +1000[diff] [blame]439#define BEGIN_FTR_SECTION_NESTED(label) label:
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]440#define BEGIN_FTR_SECTION BEGIN_FTR_SECTION_NESTED(97)
Benjamin Herrenschmidt7aeb7322006-10-20 11:47:16 +1000[diff] [blame]441#define END_FTR_SECTION_NESTED(msk, val, label) \
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]442 MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
Benjamin Herrenschmidt7aeb7322006-10-20 11:47:16 +1000[diff] [blame]443#define END_FTR_SECTION(msk, val) \
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]444 END_FTR_SECTION_NESTED(msk, val, 97)
Benjamin Herrenschmidt7aeb7322006-10-20 11:47:16 +1000[diff] [blame]445
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]446#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
447#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
448#endif /* __ASSEMBLY__ */
449
450#endif /* __KERNEL__ */
451#endif /* __ASM_POWERPC_CPUTABLE_H */