blob: 4ce947c19623d34733393f5fadccb1327e220440 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
3 *
4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
Hyok S. Choid090ddd2006-06-28 14:10:01 +01006 * hacked for non-paged-MM by Hyok S. Choi, 2003.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 *
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm1020e.
25 *
26 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
27 */
28#include <linux/linkage.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029#include <linux/init.h>
30#include <asm/assembler.h>
Sam Ravnborge6ae7442005-09-09 21:08:59 +020031#include <asm/asm-offsets.h>
Russell King5ec94072008-09-07 19:15:31 +010032#include <asm/hwcap.h>
Russell King74945c82006-03-16 14:44:36 +000033#include <asm/pgtable-hwdef.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#include <asm/pgtable.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070035#include <asm/ptrace.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036
Russell King00eb0f62006-07-03 12:36:07 +010037#include "proc-macros.S"
38
Linus Torvalds1da177e2005-04-16 15:20:36 -070039/*
40 * This is the maximum size of an area which will be invalidated
41 * using the single invalidate entry instructions. Anything larger
42 * than this, and we go for the whole cache.
43 *
44 * This value should be chosen such that we choose the cheapest
45 * alternative.
46 */
47#define MAX_AREA_SIZE 32768
48
49/*
50 * The size of one data cache line.
51 */
52#define CACHE_DLINESIZE 32
53
54/*
55 * The number of data cache segments.
56 */
57#define CACHE_DSEGMENTS 16
58
59/*
60 * The number of lines in a cache segment.
61 */
62#define CACHE_DENTRIES 64
63
64/*
65 * This is the size at which it becomes more efficient to
66 * clean the whole cache, rather than using the individual
Lucas De Marchi25985ed2011-03-30 22:57:33 -030067 * cache line maintenance instructions.
Linus Torvalds1da177e2005-04-16 15:20:36 -070068 */
69#define CACHE_DLIMIT 32768
70
71 .text
72/*
73 * cpu_arm1020e_proc_init()
74 */
75ENTRY(cpu_arm1020e_proc_init)
76 mov pc, lr
77
78/*
79 * cpu_arm1020e_proc_fin()
80 */
81ENTRY(cpu_arm1020e_proc_fin)
Linus Torvalds1da177e2005-04-16 15:20:36 -070082 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
83 bic r0, r0, #0x1000 @ ...i............
84 bic r0, r0, #0x000e @ ............wca.
85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
Russell King9ca03a22010-07-26 12:22:12 +010086 mov pc, lr
Linus Torvalds1da177e2005-04-16 15:20:36 -070087
88/*
89 * cpu_arm1020e_reset(loc)
90 *
91 * Perform a soft reset of the system. Put the CPU into the
92 * same state as it would be if it had been reset, and branch
93 * to what would be the reset vector.
94 *
95 * loc: location to jump to for soft reset
96 */
97 .align 5
98ENTRY(cpu_arm1020e_reset)
99 mov ip, #0
100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
101 mcr p15, 0, ip, c7, c10, 4 @ drain WB
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100102#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700103 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100104#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
106 bic ip, ip, #0x000f @ ............wcam
107 bic ip, ip, #0x1100 @ ...i...s........
108 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
109 mov pc, r0
110
111/*
112 * cpu_arm1020e_do_idle()
113 */
114 .align 5
115ENTRY(cpu_arm1020e_do_idle)
116 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
117 mov pc, lr
118
119/* ================================= CACHE ================================ */
120
121 .align 5
Mika Westerbergc8c90862010-10-28 11:27:40 +0100122
123/*
124 * flush_icache_all()
125 *
126 * Unconditionally clean and invalidate the entire icache.
127 */
128ENTRY(arm1020e_flush_icache_all)
129#ifndef CONFIG_CPU_ICACHE_DISABLE
130 mov r0, #0
131 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
132#endif
133 mov pc, lr
134ENDPROC(arm1020e_flush_icache_all)
135
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136/*
137 * flush_user_cache_all()
138 *
139 * Invalidate all cache entries in a particular address
140 * space.
141 */
142ENTRY(arm1020e_flush_user_cache_all)
143 /* FALLTHROUGH */
144/*
145 * flush_kern_cache_all()
146 *
147 * Clean and invalidate the entire cache.
148 */
149ENTRY(arm1020e_flush_kern_cache_all)
150 mov r2, #VM_EXEC
151 mov ip, #0
152__flush_whole_cache:
153#ifndef CONFIG_CPU_DCACHE_DISABLE
154 mcr p15, 0, ip, c7, c10, 4 @ drain WB
155 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
1561: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
1572: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
158 subs r3, r3, #1 << 26
159 bcs 2b @ entries 63 to 0
160 subs r1, r1, #1 << 5
161 bcs 1b @ segments 15 to 0
162#endif
163 tst r2, #VM_EXEC
164#ifndef CONFIG_CPU_ICACHE_DISABLE
165 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
166#endif
167 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
168 mov pc, lr
169
170/*
171 * flush_user_cache_range(start, end, flags)
172 *
173 * Invalidate a range of cache entries in the specified
174 * address space.
175 *
176 * - start - start address (inclusive)
177 * - end - end address (exclusive)
178 * - flags - vm_flags for this space
179 */
180ENTRY(arm1020e_flush_user_cache_range)
181 mov ip, #0
182 sub r3, r1, r0 @ calculate total size
183 cmp r3, #CACHE_DLIMIT
184 bhs __flush_whole_cache
185
186#ifndef CONFIG_CPU_DCACHE_DISABLE
1871: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
188 add r0, r0, #CACHE_DLINESIZE
189 cmp r0, r1
190 blo 1b
191#endif
192 tst r2, #VM_EXEC
193#ifndef CONFIG_CPU_ICACHE_DISABLE
194 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
195#endif
196 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
197 mov pc, lr
198
199/*
200 * coherent_kern_range(start, end)
201 *
202 * Ensure coherency between the Icache and the Dcache in the
203 * region described by start. If you have non-snooping
204 * Harvard caches, you need to implement this function.
205 *
206 * - start - virtual start address
207 * - end - virtual end address
208 */
209ENTRY(arm1020e_coherent_kern_range)
210 /* FALLTHROUGH */
211/*
212 * coherent_user_range(start, end)
213 *
214 * Ensure coherency between the Icache and the Dcache in the
215 * region described by start. If you have non-snooping
216 * Harvard caches, you need to implement this function.
217 *
218 * - start - virtual start address
219 * - end - virtual end address
220 */
221ENTRY(arm1020e_coherent_user_range)
222 mov ip, #0
223 bic r0, r0, #CACHE_DLINESIZE - 1
2241:
225#ifndef CONFIG_CPU_DCACHE_DISABLE
226 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
227#endif
228#ifndef CONFIG_CPU_ICACHE_DISABLE
229 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
230#endif
231 add r0, r0, #CACHE_DLINESIZE
232 cmp r0, r1
233 blo 1b
234 mcr p15, 0, ip, c7, c10, 4 @ drain WB
235 mov pc, lr
236
237/*
Russell King2c9b9c82009-11-26 12:56:21 +0000238 * flush_kern_dcache_area(void *addr, size_t size)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239 *
240 * Ensure no D cache aliasing occurs, either with itself or
241 * the I cache
242 *
Russell King2c9b9c82009-11-26 12:56:21 +0000243 * - addr - kernel address
244 * - size - region size
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245 */
Russell King2c9b9c82009-11-26 12:56:21 +0000246ENTRY(arm1020e_flush_kern_dcache_area)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247 mov ip, #0
248#ifndef CONFIG_CPU_DCACHE_DISABLE
Russell King2c9b9c82009-11-26 12:56:21 +0000249 add r1, r0, r1
Linus Torvalds1da177e2005-04-16 15:20:36 -07002501: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
251 add r0, r0, #CACHE_DLINESIZE
252 cmp r0, r1
253 blo 1b
254#endif
255 mcr p15, 0, ip, c7, c10, 4 @ drain WB
256 mov pc, lr
257
258/*
259 * dma_inv_range(start, end)
260 *
261 * Invalidate (discard) the specified virtual address range.
262 * May not write back any entries. If 'start' or 'end'
263 * are not cache line aligned, those lines must be written
264 * back.
265 *
266 * - start - virtual start address
267 * - end - virtual end address
268 *
269 * (same as v4wb)
270 */
Russell King702b94b2009-11-26 16:24:19 +0000271arm1020e_dma_inv_range:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272 mov ip, #0
273#ifndef CONFIG_CPU_DCACHE_DISABLE
274 tst r0, #CACHE_DLINESIZE - 1
275 bic r0, r0, #CACHE_DLINESIZE - 1
276 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
277 tst r1, #CACHE_DLINESIZE - 1
278 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
2791: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
280 add r0, r0, #CACHE_DLINESIZE
281 cmp r0, r1
282 blo 1b
283#endif
284 mcr p15, 0, ip, c7, c10, 4 @ drain WB
285 mov pc, lr
286
287/*
288 * dma_clean_range(start, end)
289 *
290 * Clean the specified virtual address range.
291 *
292 * - start - virtual start address
293 * - end - virtual end address
294 *
295 * (same as v4wb)
296 */
Russell King702b94b2009-11-26 16:24:19 +0000297arm1020e_dma_clean_range:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298 mov ip, #0
299#ifndef CONFIG_CPU_DCACHE_DISABLE
300 bic r0, r0, #CACHE_DLINESIZE - 1
3011: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
302 add r0, r0, #CACHE_DLINESIZE
303 cmp r0, r1
304 blo 1b
305#endif
306 mcr p15, 0, ip, c7, c10, 4 @ drain WB
307 mov pc, lr
308
309/*
310 * dma_flush_range(start, end)
311 *
312 * Clean and invalidate the specified virtual address range.
313 *
314 * - start - virtual start address
315 * - end - virtual end address
316 */
317ENTRY(arm1020e_dma_flush_range)
318 mov ip, #0
319#ifndef CONFIG_CPU_DCACHE_DISABLE
320 bic r0, r0, #CACHE_DLINESIZE - 1
3211: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
322 add r0, r0, #CACHE_DLINESIZE
323 cmp r0, r1
324 blo 1b
325#endif
326 mcr p15, 0, ip, c7, c10, 4 @ drain WB
327 mov pc, lr
328
Russell Kinga9c91472009-11-26 16:19:58 +0000329/*
330 * dma_map_area(start, size, dir)
331 * - start - kernel virtual start address
332 * - size - size of region
333 * - dir - DMA direction
334 */
335ENTRY(arm1020e_dma_map_area)
336 add r1, r1, r0
337 cmp r2, #DMA_TO_DEVICE
338 beq arm1020e_dma_clean_range
339 bcs arm1020e_dma_inv_range
340 b arm1020e_dma_flush_range
341ENDPROC(arm1020e_dma_map_area)
342
343/*
344 * dma_unmap_area(start, size, dir)
345 * - start - kernel virtual start address
346 * - size - size of region
347 * - dir - DMA direction
348 */
349ENTRY(arm1020e_dma_unmap_area)
350 mov pc, lr
351ENDPROC(arm1020e_dma_unmap_area)
352
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353ENTRY(arm1020e_cache_fns)
Mika Westerbergc8c90862010-10-28 11:27:40 +0100354 .long arm1020e_flush_icache_all
Linus Torvalds1da177e2005-04-16 15:20:36 -0700355 .long arm1020e_flush_kern_cache_all
356 .long arm1020e_flush_user_cache_all
357 .long arm1020e_flush_user_cache_range
358 .long arm1020e_coherent_kern_range
359 .long arm1020e_coherent_user_range
Russell King2c9b9c82009-11-26 12:56:21 +0000360 .long arm1020e_flush_kern_dcache_area
Russell Kinga9c91472009-11-26 16:19:58 +0000361 .long arm1020e_dma_map_area
362 .long arm1020e_dma_unmap_area
Linus Torvalds1da177e2005-04-16 15:20:36 -0700363 .long arm1020e_dma_flush_range
364
365 .align 5
366ENTRY(cpu_arm1020e_dcache_clean_area)
367#ifndef CONFIG_CPU_DCACHE_DISABLE
368 mov ip, #0
3691: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
370 add r0, r0, #CACHE_DLINESIZE
371 subs r1, r1, #CACHE_DLINESIZE
372 bhi 1b
373#endif
374 mov pc, lr
375
376/* =============================== PageTable ============================== */
377
378/*
379 * cpu_arm1020e_switch_mm(pgd)
380 *
381 * Set the translation base pointer to be as described by pgd.
382 *
383 * pgd: new page tables
384 */
385 .align 5
386ENTRY(cpu_arm1020e_switch_mm)
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100387#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388#ifndef CONFIG_CPU_DCACHE_DISABLE
389 mcr p15, 0, r3, c7, c10, 4
390 mov r1, #0xF @ 16 segments
3911: mov r3, #0x3F @ 64 entries
3922: mov ip, r3, LSL #26 @ shift up entry
393 orr ip, ip, r1, LSL #5 @ shift in/up index
394 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
395 mov ip, #0
396 subs r3, r3, #1
397 cmp r3, #0
398 bge 2b @ entries 3F to 0
399 subs r1, r1, #1
400 cmp r1, #0
401 bge 1b @ segments 15 to 0
402
403#endif
404 mov r1, #0
405#ifndef CONFIG_CPU_ICACHE_DISABLE
406 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
407#endif
408 mcr p15, 0, r1, c7, c10, 4 @ drain WB
409 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
410 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100411#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412 mov pc, lr
413
414/*
415 * cpu_arm1020e_set_pte(ptep, pte)
416 *
417 * Set a PTE and flush it out
418 */
419 .align 5
Russell Kingad1ae2f2006-12-13 14:34:43 +0000420ENTRY(cpu_arm1020e_set_pte_ext)
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100421#ifdef CONFIG_MMU
Russell Kingda091652008-09-06 17:19:08 +0100422 armv3_set_pte_ext
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423 mov r0, r0
424#ifndef CONFIG_CPU_DCACHE_DISABLE
425 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
426#endif
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100427#endif /* CONFIG_MMU */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428 mov pc, lr
429
Russell King5085f3f2010-10-01 15:37:05 +0100430 __CPUINIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431
432 .type __arm1020e_setup, #function
433__arm1020e_setup:
434 mov r0, #0
435 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
436 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100437#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100439#endif
Russell King22b19082006-06-29 15:09:57 +0100440 adr r5, arm1020e_crval
441 ldmia r5, {r5, r6}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442 mrc p15, 0, r0, c1, c0 @ get control register v4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443 bic r0, r0, r5
Russell King22b19082006-06-29 15:09:57 +0100444 orr r0, r0, r6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
446 orr r0, r0, #0x4000 @ .R.. .... .... ....
447#endif
448 mov pc, lr
449 .size __arm1020e_setup, . - __arm1020e_setup
450
451 /*
452 * R
453 * .RVI ZFRS BLDP WCAM
Catalin Marinasabaf48a2005-06-30 17:04:14 +0100454 * .011 1001 ..11 0101
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455 */
Russell King22b19082006-06-29 15:09:57 +0100456 .type arm1020e_crval, #object
457arm1020e_crval:
458 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459
460 __INITDATA
461
462/*
463 * Purpose : Function pointers used to access above functions - all calls
464 * come through these
465 */
466 .type arm1020e_processor_functions, #object
467arm1020e_processor_functions:
468 .word v4t_early_abort
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100469 .word legacy_pabort
Linus Torvalds1da177e2005-04-16 15:20:36 -0700470 .word cpu_arm1020e_proc_init
471 .word cpu_arm1020e_proc_fin
472 .word cpu_arm1020e_reset
473 .word cpu_arm1020e_do_idle
474 .word cpu_arm1020e_dcache_clean_area
475 .word cpu_arm1020e_switch_mm
Russell Kingad1ae2f2006-12-13 14:34:43 +0000476 .word cpu_arm1020e_set_pte_ext
Russell Kingf6b0fa02011-02-06 15:48:39 +0000477 .word 0
478 .word 0
479 .word 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700480 .size arm1020e_processor_functions, . - arm1020e_processor_functions
481
482 .section ".rodata"
483
484 .type cpu_arch_name, #object
485cpu_arch_name:
486 .asciz "armv5te"
487 .size cpu_arch_name, . - cpu_arch_name
488
489 .type cpu_elf_name, #object
490cpu_elf_name:
491 .asciz "v5"
492 .size cpu_elf_name, . - cpu_elf_name
493
494 .type cpu_arm1020e_name, #object
495cpu_arm1020e_name:
Russell King264edb32006-06-29 15:03:09 +0100496 .asciz "ARM1020E"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700497 .size cpu_arm1020e_name, . - cpu_arm1020e_name
498
499 .align
500
Ben Dooks02b7dd12005-09-20 16:35:03 +0100501 .section ".proc.info.init", #alloc, #execinstr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502
503 .type __arm1020e_proc_info,#object
504__arm1020e_proc_info:
505 .long 0x4105a200 @ ARM 1020TE (Architecture v5TE)
506 .long 0xff0ffff0
507 .long PMD_TYPE_SECT | \
508 PMD_BIT4 | \
509 PMD_SECT_AP_WRITE | \
510 PMD_SECT_AP_READ
Russell King8799ee92006-06-29 18:24:21 +0100511 .long PMD_TYPE_SECT | \
512 PMD_BIT4 | \
513 PMD_SECT_AP_WRITE | \
514 PMD_SECT_AP_READ
Linus Torvalds1da177e2005-04-16 15:20:36 -0700515 b __arm1020e_setup
516 .long cpu_arch_name
517 .long cpu_elf_name
518 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
519 .long cpu_arm1020e_name
520 .long arm1020e_processor_functions
521 .long v4wbi_tlb_fns
522 .long v4wb_user_fns
523 .long arm1020e_cache_fns
524 .size __arm1020e_proc_info, . - __arm1020e_proc_info