blob: 475ed40c6bda6494d52f9a8df621b631bb689acc [file] [log] [blame]
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -07001/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13/include/ "skeleton.dtsi"
Mitchel Humpherys52ffaec2012-10-09 15:40:13 -070014/include/ "msm8226-ion.dtsi"
Patrick Dalye8977aa2012-11-06 15:25:58 -080015/include/ "msm-gdsc.dtsi"
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -070016
17/ {
18 model = "Qualcomm MSM 8226";
19 compatible = "qcom,msm8226";
20 interrupt-parent = <&intc>;
21
22 intc: interrupt-controller@f9000000 {
23 compatible = "qcom,msm-qgic2";
24 interrupt-controller;
25 #interrupt-cells = <3>;
26 reg = <0xF9000000 0x1000>,
27 <0xF9002000 0x1000>;
28 };
29
30 msmgpio: gpio@fd510000 {
31 compatible = "qcom,msm-gpio";
32 interrupt-controller;
33 #interrupt-cells = <2>;
34 reg = <0xfd510000 0x4000>;
Syed Rameez Mustafa86cccfc2012-12-10 18:06:08 -080035 gpio-controller;
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -070036 #gpio-cells = <2>;
Rohit Vaswanid2001522012-12-05 19:23:44 -080037 interrupts = <0 208 0>;
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -070038 };
39
40 timer {
Syed Rameez Mustafa0824d6c2012-11-29 18:53:56 -080041 compatible = "arm,armv7-timer";
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -070042 interrupts = <1 2 0 1 3 0>;
43 clock-frequency = <19200000>;
44 };
45
46 serial@f991f000 {
47 compatible = "qcom,msm-lsuart-v14";
48 reg = <0xf991f000 0x1000>;
49 interrupts = <0 109 0>;
50 status = "disabled";
51 };
52
53 serial@f995e000 {
54 compatible = "qcom,msm-lsuart-v14";
55 reg = <0xf995e000 0x1000>;
56 interrupts = <0 114 0>;
57 status = "disabled";
58 };
59
Yan He7c06ce32012-12-03 17:12:31 -080060 qcom,sps@f9984000 {
61 compatible = "qcom,msm_sps";
62 reg = <0xf9984000 0x15000>,
63 <0xf9999000 0xb000>;
64 interrupts = <0 94 0>;
65 };
66
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -070067 usb@f9a55000 {
68 compatible = "qcom,hsusb-otg";
69 reg = <0xf9a55000 0x400>;
70 interrupts = <0 134 0>;
71 interrupt-names = "core_irq";
Mayank Rana891350a2012-10-19 15:26:10 +053072 HSUSB_VDDCX-supply = <&pm8026_s1>;
73 HSUSB_1p8-supply = <&pm8026_l10>;
74 HSUSB_3p3-supply = <&pm8026_l20>;
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -070075
76 qcom,hsusb-otg-phy-type = <2>;
77 qcom,hsusb-otg-mode = <1>;
78 qcom,hsusb-otg-otg-control = <1>;
79 qcom,hsusb-otg-disable-reset;
80 };
81
82 android_usb {
83 compatible = "qcom,android-usb";
84 };
85
Mitchel Humpherys5fe1c9b2012-10-09 17:30:19 -070086 qcom,wdt@f9017000 {
87 compatible = "qcom,msm-watchdog";
88 reg = <0xf9017000 0x1000>;
89 interrupts = <0 3 0>, <0 4 0>;
90 qcom,bark-time = <11000>;
91 qcom,pet-time = <10000>;
92 qcom,ipi-ping = <1>;
93 };
94
Jeff Hugo7f9705b62012-10-12 10:38:26 -060095 qcom,smem@fa00000 {
96 compatible = "qcom,smem";
97 reg = <0xfa00000 0x200000>,
98 <0xfa006000 0x1000>,
99 <0xfc428000 0x4000>;
100 reg-names = "smem", "irq-reg-base", "aux-mem1";
101
102 qcom,smd-modem {
103 compatible = "qcom,smd";
104 qcom,smd-edge = <0>;
105 qcom,smd-irq-offset = <0x8>;
106 qcom,smd-irq-bitmask = <0x1000>;
107 qcom,pil-string = "modem";
108 interrupts = <0 25 1>;
David Ngb715e322012-12-01 12:57:08 -0800109 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600110
111 qcom,smsm-modem {
112 compatible = "qcom,smsm";
113 qcom,smsm-edge = <0>;
114 qcom,smsm-irq-offset = <0x8>;
115 qcom,smsm-irq-bitmask = <0x2000>;
116 interrupts = <0 26 1>;
David Ngb715e322012-12-01 12:57:08 -0800117 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600118
119 qcom,smd-adsp {
120 compatible = "qcom,smd";
121 qcom,smd-edge = <1>;
122 qcom,smd-irq-offset = <0x8>;
123 qcom,smd-irq-bitmask = <0x100>;
124 qcom,pil-string = "adsp";
125 interrupts = <0 156 1>;
David Ngb715e322012-12-01 12:57:08 -0800126 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600127
128 qcom,smsm-adsp {
129 compatible = "qcom,smsm";
130 qcom,smsm-edge = <1>;
131 qcom,smsm-irq-offset = <0x8>;
132 qcom,smsm-irq-bitmask = <0x200>;
133 interrupts = <0 157 1>;
David Ngb715e322012-12-01 12:57:08 -0800134 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600135
136 qcom,smd-wcnss {
137 compatible = "qcom,smd";
138 qcom,smd-edge = <6>;
139 qcom,smd-irq-offset = <0x8>;
140 qcom,smd-irq-bitmask = <0x20000>;
141 qcom,pil-string = "wcnss";
142 interrupts = <0 142 1>;
David Ngb715e322012-12-01 12:57:08 -0800143 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600144
145 qcom,smsm-wcnss {
146 compatible = "qcom,smsm";
147 qcom,smsm-edge = <6>;
148 qcom,smsm-irq-offset = <0x8>;
149 qcom,smsm-irq-bitmask = <0x80000>;
150 interrupts = <0 144 1>;
David Ngb715e322012-12-01 12:57:08 -0800151 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600152
153 qcom,smd-rpm {
154 compatible = "qcom,smd";
155 qcom,smd-edge = <15>;
156 qcom,smd-irq-offset = <0x8>;
157 qcom,smd-irq-bitmask = <0x1>;
158 interrupts = <0 168 1>;
159 qcom,irq-no-suspend;
David Ngb715e322012-12-01 12:57:08 -0800160 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600161 };
162
Asutosh Das99912e62012-12-06 12:38:46 +0530163 sdcc1: qcom,sdcc@f9824000 {
164 cell-index = <1>; /* SDC1 eMMC slot */
165 compatible = "qcom,msm-sdcc";
166
Asutosh Das6b82fc52012-11-23 12:00:26 +0530167 reg = <0xf9824000 0x800>,
168 <0xf9824800 0x100>,
169 <0xf9804000 0x7000>;
170 reg-names = "core_mem", "dml_mem", "bam_mem";
171 interrupts = <0 123 0>, <0 137 0>;
172 interrupt-names = "core_irq", "bam_irq";
Asutosh Das99912e62012-12-06 12:38:46 +0530173
174 qcom,bus-width = <8>;
175 status = "disabled";
176 };
177
178 sdcc2: qcom,sdcc@f98a4000 {
179 cell-index = <2>; /* SDC2 SD card slot */
180 compatible = "qcom,msm-sdcc";
181
Asutosh Das6b82fc52012-11-23 12:00:26 +0530182 reg = <0xf98a4000 0x800>,
183 <0xf98a4800 0x100>,
184 <0xf9884000 0x7000>;
185 reg-names = "core_mem", "dml_mem", "bam_mem";
186 interrupts = <0 125 0>, <0 220 0>;
187 interrupt-names = "core_irq", "bam_irq";
Asutosh Das99912e62012-12-06 12:38:46 +0530188
189 qcom,bus-width = <4>;
190 status = "disabled";
191 };
Kenneth Heitkee5804002012-11-15 17:50:07 -0700192
193 spmi_bus: qcom,spmi@fc4c0000 {
194 cell-index = <0>;
195 compatible = "qcom,spmi-pmic-arb";
196 reg = <0xfc4cf000 0x1000>,
197 <0Xfc4cb000 0x1000>;
198 /* 190,ee0_krait_hlos_spmi_periph_irq */
199 /* 187,channel_0_krait_hlos_trans_done_irq */
200 interrupts = <0 190 0>, <0 187 0>;
201 qcom,not-wakeup;
202 qcom,pmic-arb-ee = <0>;
203 qcom,pmic-arb-channel = <0>;
204 qcom,pmic-arb-ppid-map = <0x001000a0>, /* PM8026_0 */
205 <0x005000a2>, /* INTERRUPT */
206 <0x006000a3>, /* SPMI_0 */
207 <0x00800000>, /* PON0 */
208 <0x00a000a5>, /* VREF_LPDDR3 */
209 <0x01000001>, /* SMBB_CHG */
210 <0x01100002>, /* SMBB_BUCK */
211 <0x01200003>, /* SMBB_BIF */
212 <0x01300004>, /* SMBB_USB */
213 <0x01500005>, /* SMBB_BOOST */
214 <0x01600006>, /* SMBB_MISC */
215 <0x02800009>, /* COINCELL */
216 <0x02c000a6>, /* MBG */
217 <0x0310000a>, /* VADC1_USR */
218 <0x03200041>, /* VADC1_MDM */
219 <0x0330000b>, /* VADC1_BMS */
220 <0x0340000c>, /* VADC2_BTM */
221 <0x0360000d>, /* IADC1_USR */
222 <0x03700042>, /* IADC1_MDM */
223 <0x0380000e>, /* IADC1_BMS */
224 <0x0400000f>, /* BMS_1 */
225 <0x050000a7>, /* SHARED_XO */
226 <0x051000a8>, /* BB_CLK1 */
227 <0x05200010>, /* BB_CLK2 */
228 <0x05a000ac>, /* SLEEP_CLK */
229 <0x06000045>, /* RTC_RW */
230 <0x06100012>, /* RTC_ALARM */
231 <0x070000ae>, /* PBS_CORE */
232 <0x071000af>, /* PBS_CLIENT_1 */
233 <0x072000b0>, /* PBS_CLIENT_2 */
234 <0x073000b1>, /* PBS_CLIENT_3 */
235 <0x074000b2>, /* PBS_CLIENT_4 */
236 <0x075000b3>, /* PBS_CLIENT_5 */
237 <0x076000b4>, /* PBS_CLIENT_6 */
238 <0x07700046>, /* PBS_CLIENT_7 */
239 <0x07800047>, /* PBS_CLIENT_8 */
240 <0x079000b5>, /* PBS_CLIENT_9 */
241 <0x07a000b6>, /* PBS_CLIENT_10 */
242 <0x07b000b7>, /* PBS_CLIENT_11 */
243 <0x07c000b8>, /* PBS_CLIENT_12 */
244 <0x07d000b9>, /* PBS_CLIENT_13 */
245 <0x07e000ba>, /* PBS_CLIENT_14 */
246 <0x07f000bb>, /* PBS_CLIENT_15 */
247 <0x0a0000bd>, /* MPP_1 */
248 <0x0a100014>, /* MPP_2 */
249 <0x0a200015>, /* MPP_3 */
250 <0x0a300016>, /* MPP_4 */
251 <0x0a400048>, /* MPP_5 */
252 <0x0a500017>, /* MPP_6 */
253 <0x0a600018>, /* MPP_7 */
254 <0x0a700049>, /* MPP_8 */
255 <0x0c000019>, /* GPIO_1 */
256 <0x0c10001a>, /* GPIO_2 */
257 <0x0c20004a>, /* GPIO_3 */
258 <0x0c30004b>, /* GPIO_4 */
259 <0x0c40001b>, /* GPIO_5 */
260 <0x0c50001c>, /* GPIO_6 */
261 <0x0c60001d>, /* GPIO_7 */
262 <0x0c70004c>, /* GPIO_8 */
263 <0x0fe000be>, /* TRIM_0 */
264 <0x110000bf>, /* BUCK_CMN_1 */
265 <0x114000c0>, /* SMPS1 */
266 <0x115000c1>, /* FTPS1_1 */
267 <0x116000c2>, /* BUCK_FREQ_1 */
268 <0x1170001e>, /* SMPS2 */
269 <0x1180001f>, /* FTPS1_2 */
270 <0x11900020>, /* BUCK_FREQ_2 */
271 <0x11a000c3>, /* SMPS3 */
272 <0x11b000c4>, /* SMPS_3_PS1 */
273 <0x11c000c5>, /* BUCK_FREQ_3 */
274 <0x11d000c6>, /* SMPS4 */
275 <0x11e000c7>, /* SMPS_4_PS1 */
276 <0x11f000c8>, /* BUCK_FREQ_4 */
277 <0x120000c9>, /* SMPS5 */
278 <0x121000ca>, /* SMPS_5_PS1 */
279 <0x122000cb>, /* BUCK_FREQ_5 */
280 <0x140000cc>, /* LDO_1 */
281 <0x141000cd>, /* LDO_2 */
282 <0x142000ce>, /* LDO_3 */
283 <0x143000cf>, /* LDO_4 */
284 <0x144000d0>, /* LDO_5 */
285 <0x145000d1>, /* LDO_6 */
286 <0x146000d2>, /* LDO_7 */
287 <0x147000d3>, /* LDO_8 */
288 <0x148000d4>, /* LDO_9 */
289 <0x149000d5>, /* LDO_10 */
290 <0x14a000d6>, /* LDO_11 */
291 <0x14b000d7>, /* LDO_12 */
292 <0x14c000d8>, /* LDO_13 */
293 <0x14d000d9>, /* LDO_14 */
294 <0x14e000da>, /* LDO_15 */
295 <0x14f000db>, /* LDO_16 */
296 <0x150000dc>, /* LDO_17 */
297 <0x151000dd>, /* LDO_18 */
298 <0x152000de>, /* LDO_19 */
299 <0x153000df>, /* LDO_20 */
300 <0x154000e0>, /* LDO_21 */
301 <0x155000e1>, /* LDO_22 */
302 <0x156000e2>, /* LDO_23 */
303 <0x157000e3>, /* LDO_24 */
304 <0x158000e4>, /* LDO_25 */
305 <0x159000e5>, /* LDO_26 */
306 <0x15a000e6>, /* LDO_27 */
307 <0x15b000e7>, /* LDO_28 */
308 <0x180000e8>, /* LVS_1 */
309 <0x1b0000e9>, /* LPG_LUT */
310 <0x1b1000ea>, /* LPG_CHAN_1 */
311 <0x1b200023>, /* LPG_CHAN_2 */
312 <0x1b300024>, /* LPG_CHAN_3 */
313 <0x1b400025>, /* LPG_CHAN_4 */
314 <0x1b500026>, /* LPG_CHAN_5 */
315 <0x1b600027>, /* LPG_CHAN_6 */
316 <0x1bc00028>, /* PWM_3D */
317 <0x1c000029>, /* VIB1 */
318 <0x1d30002a>, /* FLASH_DRV */
319 <0x1d80002b>; /* WLED */
320 };
321
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700322};
David Collins37ddb972012-10-17 15:00:26 -0700323
Patrick Dalye8977aa2012-11-06 15:25:58 -0800324&gdsc_venus {
325 status = "ok";
326};
327
328&gdsc_mdss {
329 status = "ok";
330};
331
332&gdsc_jpeg {
333 status = "ok";
334};
335
336&gdsc_vfe {
337 status = "ok";
338};
339
340&gdsc_oxili_cx {
341 status = "ok";
342};
343
344&gdsc_usb_hsic {
345 status = "ok";
346};
347
David Collins37ddb972012-10-17 15:00:26 -0700348/include/ "msm8226-regulator.dtsi"
Kenneth Heitkee5804002012-11-15 17:50:07 -0700349/include/ "msm-pm8026.dtsi"