blob: f89bdfde16d067469528557f0036dbaf5304a65e [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * pata_optidma.c - Opti DMA PATA for new ATA layer
3 * (C) 2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * The Opti DMA controllers are related to the older PIO PCI controllers
7 * and indeed the VLB ones. The main differences are that the timing
8 * numbers are now based off PCI clocks not VLB and differ, and that
9 * MWDMA is supported.
10 *
11 * This driver should support Viper-N+, FireStar, FireStar Plus.
12 *
13 * These devices support virtual DMA for read (aka the CS5520). Later
14 * chips support UDMA33, but only if the rest of the board logic does,
15 * so you have to get this right. We don't support the virtual DMA
16 * but we do handle UDMA.
17 *
18 * Bits that are worth knowing
19 * Most control registers are shadowed into I/O registers
20 * 0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
21 * Virtual DMA registers *move* between rev 0x02 and rev 0x10
22 * UDMA requires a 66MHz FSB
23 *
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <linux/blkdev.h>
31#include <linux/delay.h>
32#include <scsi/scsi_host.h>
33#include <linux/libata.h>
34
35#define DRV_NAME "pata_optidma"
Alan Cox5c25bf02007-03-26 21:43:43 -080036#define DRV_VERSION "0.3.2"
Jeff Garzik669a5db2006-08-29 18:12:40 -040037
38enum {
39 READ_REG = 0, /* index of Read cycle timing register */
40 WRITE_REG = 1, /* index of Write cycle timing register */
41 CNTRL_REG = 3, /* index of Control register */
42 STRAP_REG = 5, /* index of Strap register */
43 MISC_REG = 6 /* index of Miscellaneous register */
44};
45
46static int pci_clock; /* 0 = 33 1 = 25 */
47
48/**
49 * optidma_pre_reset - probe begin
50 * @ap: ATA port
Tejun Heod4b2bab2007-02-02 16:50:52 +090051 * @deadline: deadline jiffies for the operation
Jeff Garzik669a5db2006-08-29 18:12:40 -040052 *
53 * Set up cable type and use generic probe init
54 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040055
Tejun Heod4b2bab2007-02-02 16:50:52 +090056static int optidma_pre_reset(struct ata_port *ap, unsigned long deadline)
Jeff Garzik669a5db2006-08-29 18:12:40 -040057{
58 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Jeff Garzik85cd7252006-08-31 00:03:49 -040059 static const struct pci_bits optidma_enable_bits = {
Jeff Garzik669a5db2006-08-29 18:12:40 -040060 0x40, 1, 0x08, 0x00
61 };
62
Alan Coxc9619222006-09-26 17:53:38 +010063 if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits))
64 return -ENOENT;
65
Tejun Heod4b2bab2007-02-02 16:50:52 +090066 return ata_std_prereset(ap, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -040067}
68
69/**
70 * optidma_probe_reset - probe reset
71 * @ap: ATA port
72 *
73 * Perform the ATA probe and bus reset sequence plus specific handling
74 * for this hardware. The Opti needs little handling - we have no UDMA66
75 * capability that needs cable detection. All we must do is check the port
76 * is enabled.
77 */
78
79static void optidma_error_handler(struct ata_port *ap)
80{
81 ata_bmdma_drive_eh(ap, optidma_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
82}
83
84/**
85 * optidma_unlock - unlock control registers
86 * @ap: ATA port
87 *
88 * Unlock the control register block for this adapter. Registers must not
89 * be unlocked in a situation where libata might look at them.
90 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040091
Jeff Garzik669a5db2006-08-29 18:12:40 -040092static void optidma_unlock(struct ata_port *ap)
93{
Tejun Heo0d5ff562007-02-01 15:06:36 +090094 void __iomem *regio = ap->ioaddr.cmd_addr;
Jeff Garzik85cd7252006-08-31 00:03:49 -040095
Jeff Garzik669a5db2006-08-29 18:12:40 -040096 /* These 3 unlock the control register access */
Tejun Heo0d5ff562007-02-01 15:06:36 +090097 ioread16(regio + 1);
98 ioread16(regio + 1);
99 iowrite8(3, regio + 2);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400100}
101
102/**
103 * optidma_lock - issue temporary relock
104 * @ap: ATA port
105 *
106 * Re-lock the configuration register settings.
107 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400108
Jeff Garzik669a5db2006-08-29 18:12:40 -0400109static void optidma_lock(struct ata_port *ap)
110{
Tejun Heo0d5ff562007-02-01 15:06:36 +0900111 void __iomem *regio = ap->ioaddr.cmd_addr;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400112
Jeff Garzik669a5db2006-08-29 18:12:40 -0400113 /* Relock */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900114 iowrite8(0x83, regio + 2);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400115}
116
117/**
Alan Cox5c25bf02007-03-26 21:43:43 -0800118 * optidma_mode_setup - set mode data
Jeff Garzik669a5db2006-08-29 18:12:40 -0400119 * @ap: ATA interface
120 * @adev: ATA device
121 * @mode: Mode to set
122 *
123 * Called to do the DMA or PIO mode setup. Timing numbers are all
124 * pre computed to keep the code clean. There are two tables depending
125 * on the hardware clock speed.
126 *
127 * WARNING: While we do this the IDE registers vanish. If we take an
128 * IRQ here we depend on the host set locking to avoid catastrophe.
129 */
130
Alan Cox5c25bf02007-03-26 21:43:43 -0800131static void optidma_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400132{
133 struct ata_device *pair = ata_dev_pair(adev);
134 int pio = adev->pio_mode - XFER_PIO_0;
135 int dma = adev->dma_mode - XFER_MW_DMA_0;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900136 void __iomem *regio = ap->ioaddr.cmd_addr;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400137 u8 addr;
138
139 /* Address table precomputed with a DCLK of 2 */
140 static const u8 addr_timing[2][5] = {
141 { 0x30, 0x20, 0x20, 0x10, 0x10 },
142 { 0x20, 0x20, 0x10, 0x10, 0x10 }
143 };
144 static const u8 data_rec_timing[2][5] = {
145 { 0x59, 0x46, 0x30, 0x20, 0x20 },
146 { 0x46, 0x32, 0x20, 0x20, 0x10 }
147 };
148 static const u8 dma_data_rec_timing[2][3] = {
149 { 0x76, 0x20, 0x20 },
150 { 0x54, 0x20, 0x10 }
151 };
152
153 /* Switch from IDE to control mode */
154 optidma_unlock(ap);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400155
Jeff Garzik669a5db2006-08-29 18:12:40 -0400156
157 /*
158 * As with many controllers the address setup time is shared
159 * and must suit both devices if present. FIXME: Check if we
160 * need to look at slowest of PIO/DMA mode of either device
161 */
162
163 if (mode >= XFER_MW_DMA_0)
164 addr = 0;
165 else
166 addr = addr_timing[pci_clock][pio];
Jeff Garzik85cd7252006-08-31 00:03:49 -0400167
Jeff Garzik669a5db2006-08-29 18:12:40 -0400168 if (pair) {
169 u8 pair_addr;
170 /* Hardware constraint */
171 if (pair->dma_mode)
172 pair_addr = 0;
173 else
174 pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0];
175 if (pair_addr > addr)
176 addr = pair_addr;
177 }
Jeff Garzik85cd7252006-08-31 00:03:49 -0400178
Jeff Garzik669a5db2006-08-29 18:12:40 -0400179 /* Commence primary programming sequence */
180 /* First we load the device number into the timing select */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900181 iowrite8(adev->devno, regio + MISC_REG);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400182 /* Now we load the data timings into read data/write data */
183 if (mode < XFER_MW_DMA_0) {
Tejun Heo0d5ff562007-02-01 15:06:36 +0900184 iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG);
185 iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400186 } else if (mode < XFER_UDMA_0) {
Tejun Heo0d5ff562007-02-01 15:06:36 +0900187 iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
188 iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400189 }
190 /* Finally we load the address setup into the misc register */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900191 iowrite8(addr | adev->devno, regio + MISC_REG);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400192
193 /* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900194 iowrite8(0x85, regio + CNTRL_REG);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400195
Jeff Garzik669a5db2006-08-29 18:12:40 -0400196 /* Switch back to IDE mode */
197 optidma_lock(ap);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400198
Jeff Garzik669a5db2006-08-29 18:12:40 -0400199 /* Note: at this point our programming is incomplete. We are
200 not supposed to program PCI 0x43 "things we hacked onto the chip"
201 until we've done both sets of PIO/DMA timings */
202}
203
204/**
Alan Cox5c25bf02007-03-26 21:43:43 -0800205 * optiplus_mode_setup - DMA setup for Firestar Plus
Jeff Garzik669a5db2006-08-29 18:12:40 -0400206 * @ap: ATA port
207 * @adev: device
208 * @mode: desired mode
209 *
210 * The Firestar plus has additional UDMA functionality for UDMA0-2 and
211 * requires we do some additional work. Because the base work we must do
212 * is mostly shared we wrap the Firestar setup functionality in this
213 * one
214 */
215
Alan Cox5c25bf02007-03-26 21:43:43 -0800216static void optiplus_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400217{
218 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
219 u8 udcfg;
220 u8 udslave;
221 int dev2 = 2 * adev->devno;
222 int unit = 2 * ap->port_no + adev->devno;
223 int udma = mode - XFER_UDMA_0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400224
Jeff Garzik669a5db2006-08-29 18:12:40 -0400225 pci_read_config_byte(pdev, 0x44, &udcfg);
226 if (mode <= XFER_UDMA_0) {
227 udcfg &= ~(1 << unit);
Alan Cox5c25bf02007-03-26 21:43:43 -0800228 optidma_mode_setup(ap, adev, adev->dma_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400229 } else {
230 udcfg |= (1 << unit);
231 if (ap->port_no) {
232 pci_read_config_byte(pdev, 0x45, &udslave);
233 udslave &= ~(0x03 << dev2);
234 udslave |= (udma << dev2);
235 pci_write_config_byte(pdev, 0x45, udslave);
236 } else {
237 udcfg &= ~(0x30 << dev2);
238 udcfg |= (udma << dev2);
239 }
240 }
241 pci_write_config_byte(pdev, 0x44, udcfg);
242}
243
244/**
245 * optidma_set_pio_mode - PIO setup callback
246 * @ap: ATA port
247 * @adev: Device
248 *
249 * The libata core provides separate functions for handling PIO and
250 * DMA programming. The architecture of the Firestar makes it easier
251 * for us to have a common function so we provide wrappers
252 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400253
Jeff Garzik669a5db2006-08-29 18:12:40 -0400254static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
255{
Alan Cox5c25bf02007-03-26 21:43:43 -0800256 optidma_mode_setup(ap, adev, adev->pio_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400257}
258
259/**
260 * optidma_set_dma_mode - DMA setup callback
261 * @ap: ATA port
262 * @adev: Device
263 *
264 * The libata core provides separate functions for handling PIO and
265 * DMA programming. The architecture of the Firestar makes it easier
266 * for us to have a common function so we provide wrappers
267 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400268
Jeff Garzik669a5db2006-08-29 18:12:40 -0400269static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
270{
Alan Cox5c25bf02007-03-26 21:43:43 -0800271 optidma_mode_setup(ap, adev, adev->dma_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400272}
273
274/**
275 * optiplus_set_pio_mode - PIO setup callback
276 * @ap: ATA port
277 * @adev: Device
278 *
279 * The libata core provides separate functions for handling PIO and
280 * DMA programming. The architecture of the Firestar makes it easier
281 * for us to have a common function so we provide wrappers
282 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400283
Jeff Garzik669a5db2006-08-29 18:12:40 -0400284static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
285{
Alan Cox5c25bf02007-03-26 21:43:43 -0800286 optiplus_mode_setup(ap, adev, adev->pio_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400287}
288
289/**
290 * optiplus_set_dma_mode - DMA setup callback
291 * @ap: ATA port
292 * @adev: Device
293 *
294 * The libata core provides separate functions for handling PIO and
295 * DMA programming. The architecture of the Firestar makes it easier
296 * for us to have a common function so we provide wrappers
297 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400298
Jeff Garzik669a5db2006-08-29 18:12:40 -0400299static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
300{
Alan Cox5c25bf02007-03-26 21:43:43 -0800301 optiplus_mode_setup(ap, adev, adev->dma_mode);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400302}
303
304/**
305 * optidma_make_bits - PCI setup helper
306 * @adev: ATA device
307 *
308 * Turn the ATA device setup into PCI configuration bits
309 * for register 0x43 and return the two bits needed.
310 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400311
Jeff Garzik669a5db2006-08-29 18:12:40 -0400312static u8 optidma_make_bits43(struct ata_device *adev)
313{
314 static const u8 bits43[5] = {
315 0, 0, 0, 1, 2
316 };
317 if (!ata_dev_enabled(adev))
318 return 0;
319 if (adev->dma_mode)
320 return adev->dma_mode - XFER_MW_DMA_0;
321 return bits43[adev->pio_mode - XFER_PIO_0];
322}
323
324/**
Alan Cox5c25bf02007-03-26 21:43:43 -0800325 * optidma_set_mode - mode setup
Jeff Garzik669a5db2006-08-29 18:12:40 -0400326 * @ap: port to set up
327 *
Alan Cox5c25bf02007-03-26 21:43:43 -0800328 * Use the standard setup to tune the chipset and then finalise the
329 * configuration by writing the nibble of extra bits of data into
330 * the chip.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400331 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400332
Alan Cox5c25bf02007-03-26 21:43:43 -0800333static int optidma_set_mode(struct ata_port *ap, struct ata_device **r_failed)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400334{
335 u8 r;
336 int nybble = 4 * ap->port_no;
337 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Alan Cox5c25bf02007-03-26 21:43:43 -0800338 int rc = ata_do_set_mode(ap, r_failed);
339 if (rc == 0) {
340 pci_read_config_byte(pdev, 0x43, &r);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400341
Alan Cox5c25bf02007-03-26 21:43:43 -0800342 r &= (0x0F << nybble);
343 r |= (optidma_make_bits43(&ap->device[0]) +
344 (optidma_make_bits43(&ap->device[0]) << 2)) << nybble;
345 pci_write_config_byte(pdev, 0x43, r);
346 }
347 return rc;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400348}
349
350static struct scsi_host_template optidma_sht = {
351 .module = THIS_MODULE,
352 .name = DRV_NAME,
353 .ioctl = ata_scsi_ioctl,
354 .queuecommand = ata_scsi_queuecmd,
355 .can_queue = ATA_DEF_QUEUE,
356 .this_id = ATA_SHT_THIS_ID,
357 .sg_tablesize = LIBATA_MAX_PRD,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400358 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
359 .emulated = ATA_SHT_EMULATED,
360 .use_clustering = ATA_SHT_USE_CLUSTERING,
361 .proc_name = DRV_NAME,
362 .dma_boundary = ATA_DMA_BOUNDARY,
363 .slave_configure = ata_scsi_slave_config,
Tejun Heoafdfe892006-11-29 11:26:47 +0900364 .slave_destroy = ata_scsi_slave_destroy,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400365 .bios_param = ata_std_bios_param,
366};
367
368static struct ata_port_operations optidma_port_ops = {
369 .port_disable = ata_port_disable,
370 .set_piomode = optidma_set_pio_mode,
371 .set_dmamode = optidma_set_dma_mode,
372
373 .tf_load = ata_tf_load,
374 .tf_read = ata_tf_read,
375 .check_status = ata_check_status,
376 .exec_command = ata_exec_command,
377 .dev_select = ata_std_dev_select,
378
379 .freeze = ata_bmdma_freeze,
380 .thaw = ata_bmdma_thaw,
381 .post_internal_cmd = ata_bmdma_post_internal_cmd,
382 .error_handler = optidma_error_handler,
Alan Cox5c25bf02007-03-26 21:43:43 -0800383 .set_mode = optidma_set_mode,
384 .cable_detect = ata_cable_40wire,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400385
386 .bmdma_setup = ata_bmdma_setup,
387 .bmdma_start = ata_bmdma_start,
388 .bmdma_stop = ata_bmdma_stop,
389 .bmdma_status = ata_bmdma_status,
390
391 .qc_prep = ata_qc_prep,
392 .qc_issue = ata_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400393
Tejun Heo0d5ff562007-02-01 15:06:36 +0900394 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400395
396 .irq_handler = ata_interrupt,
397 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900398 .irq_on = ata_irq_on,
399 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400400
401 .port_start = ata_port_start,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400402};
403
404static struct ata_port_operations optiplus_port_ops = {
405 .port_disable = ata_port_disable,
406 .set_piomode = optiplus_set_pio_mode,
407 .set_dmamode = optiplus_set_dma_mode,
408
409 .tf_load = ata_tf_load,
410 .tf_read = ata_tf_read,
411 .check_status = ata_check_status,
412 .exec_command = ata_exec_command,
413 .dev_select = ata_std_dev_select,
414
415 .freeze = ata_bmdma_freeze,
416 .thaw = ata_bmdma_thaw,
417 .post_internal_cmd = ata_bmdma_post_internal_cmd,
418 .error_handler = optidma_error_handler,
Alan Cox5c25bf02007-03-26 21:43:43 -0800419 .set_mode = optidma_set_mode,
420 .cable_detect = ata_cable_40wire,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400421
422 .bmdma_setup = ata_bmdma_setup,
423 .bmdma_start = ata_bmdma_start,
424 .bmdma_stop = ata_bmdma_stop,
425 .bmdma_status = ata_bmdma_status,
426
427 .qc_prep = ata_qc_prep,
428 .qc_issue = ata_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400429
Tejun Heo0d5ff562007-02-01 15:06:36 +0900430 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400431
432 .irq_handler = ata_interrupt,
433 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900434 .irq_on = ata_irq_on,
435 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400436
437 .port_start = ata_port_start,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400438};
439
440/**
441 * optiplus_with_udma - Look for UDMA capable setup
442 * @pdev; ATA controller
443 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400444
Jeff Garzik669a5db2006-08-29 18:12:40 -0400445static int optiplus_with_udma(struct pci_dev *pdev)
446{
447 u8 r;
448 int ret = 0;
449 int ioport = 0x22;
450 struct pci_dev *dev1;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400451
Jeff Garzik669a5db2006-08-29 18:12:40 -0400452 /* Find function 1 */
453 dev1 = pci_get_device(0x1045, 0xC701, NULL);
454 if(dev1 == NULL)
455 return 0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400456
Jeff Garzik669a5db2006-08-29 18:12:40 -0400457 /* Rev must be >= 0x10 */
458 pci_read_config_byte(dev1, 0x08, &r);
459 if (r < 0x10)
460 goto done_nomsg;
461 /* Read the chipset system configuration to check our mode */
462 pci_read_config_byte(dev1, 0x5F, &r);
463 ioport |= (r << 8);
464 outb(0x10, ioport);
465 /* Must be 66Mhz sync */
466 if ((inb(ioport + 2) & 1) == 0)
467 goto done;
468
469 /* Check the ATA arbitration/timing is suitable */
470 pci_read_config_byte(pdev, 0x42, &r);
471 if ((r & 0x36) != 0x36)
472 goto done;
473 pci_read_config_byte(dev1, 0x52, &r);
474 if (r & 0x80) /* IDEDIR disabled */
475 ret = 1;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400476done:
Jeff Garzik669a5db2006-08-29 18:12:40 -0400477 printk(KERN_WARNING "UDMA not supported in this configuration.\n");
478done_nomsg: /* Wrong chip revision */
479 pci_dev_put(dev1);
480 return ret;
481}
482
483static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id)
484{
Tejun Heo1626aeb2007-05-04 12:43:58 +0200485 static const struct ata_port_info info_82c700 = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400486 .sht = &optidma_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400487 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400488 .pio_mask = 0x1f,
489 .mwdma_mask = 0x07,
490 .port_ops = &optidma_port_ops
491 };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200492 static const struct ata_port_info info_82c700_udma = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400493 .sht = &optidma_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400494 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400495 .pio_mask = 0x1f,
496 .mwdma_mask = 0x07,
497 .udma_mask = 0x07,
498 .port_ops = &optiplus_port_ops
499 };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200500 const struct ata_port_info *ppi[] = { &info_82c700, NULL };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400501 static int printed_version;
502
503 if (!printed_version++)
504 dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
505
506 /* Fixed location chipset magic */
507 inw(0x1F1);
508 inw(0x1F1);
509 pci_clock = inb(0x1F5) & 1; /* 0 = 33Mhz, 1 = 25Mhz */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400510
Jeff Garzik669a5db2006-08-29 18:12:40 -0400511 if (optiplus_with_udma(dev))
Tejun Heo1626aeb2007-05-04 12:43:58 +0200512 ppi[0] = &info_82c700_udma;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400513
Tejun Heo1626aeb2007-05-04 12:43:58 +0200514 return ata_pci_init_one(dev, ppi);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400515}
516
517static const struct pci_device_id optidma[] = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400518 { PCI_VDEVICE(OPTI, 0xD568), }, /* Opti 82C700 */
519
520 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400521};
522
523static struct pci_driver optidma_pci_driver = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400524 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400525 .id_table = optidma,
526 .probe = optidma_init_one,
Alan30ced0f2006-11-22 16:57:36 +0000527 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900528#ifdef CONFIG_PM
Alan30ced0f2006-11-22 16:57:36 +0000529 .suspend = ata_pci_device_suspend,
530 .resume = ata_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900531#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -0400532};
533
534static int __init optidma_init(void)
535{
536 return pci_register_driver(&optidma_pci_driver);
537}
538
Jeff Garzik669a5db2006-08-29 18:12:40 -0400539static void __exit optidma_exit(void)
540{
541 pci_unregister_driver(&optidma_pci_driver);
542}
543
Jeff Garzik669a5db2006-08-29 18:12:40 -0400544MODULE_AUTHOR("Alan Cox");
545MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus");
546MODULE_LICENSE("GPL");
547MODULE_DEVICE_TABLE(pci, optidma);
548MODULE_VERSION(DRV_VERSION);
549
550module_init(optidma_init);
551module_exit(optidma_exit);