Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame^] | 1 | #ifndef _MXSER_H |
| 2 | #define _MXSER_H |
| 3 | |
| 4 | /* |
| 5 | * Semi-public control interfaces |
| 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * MOXA ioctls |
| 10 | */ |
| 11 | |
| 12 | #define MOXA 0x400 |
| 13 | #define MOXA_GETDATACOUNT (MOXA + 23) |
| 14 | #define MOXA_GET_CONF (MOXA + 35) |
| 15 | #define MOXA_DIAGNOSE (MOXA + 50) |
| 16 | #define MOXA_CHKPORTENABLE (MOXA + 60) |
| 17 | #define MOXA_HighSpeedOn (MOXA + 61) |
| 18 | #define MOXA_GET_MAJOR (MOXA + 63) |
| 19 | #define MOXA_GET_CUMAJOR (MOXA + 64) |
| 20 | #define MOXA_GETMSTATUS (MOXA + 65) |
| 21 | #define MOXA_SET_OP_MODE (MOXA + 66) |
| 22 | #define MOXA_GET_OP_MODE (MOXA + 67) |
| 23 | |
| 24 | #define RS232_MODE 0 |
| 25 | #define RS485_2WIRE_MODE 1 |
| 26 | #define RS422_MODE 2 |
| 27 | #define RS485_4WIRE_MODE 3 |
| 28 | #define OP_MODE_MASK 3 |
| 29 | // above add by Victor Yu. 01-05-2004 |
| 30 | |
| 31 | #define TTY_THRESHOLD_THROTTLE 128 |
| 32 | |
| 33 | #define LO_WATER (TTY_FLIPBUF_SIZE) |
| 34 | #define HI_WATER (TTY_FLIPBUF_SIZE*2*3/4) |
| 35 | |
| 36 | // added by James. 03-11-2004. |
| 37 | #define MOXA_SDS_GETICOUNTER (MOXA + 68) |
| 38 | #define MOXA_SDS_RSTICOUNTER (MOXA + 69) |
| 39 | // (above) added by James. |
| 40 | |
| 41 | #define MOXA_ASPP_OQUEUE (MOXA + 70) |
| 42 | #define MOXA_ASPP_SETBAUD (MOXA + 71) |
| 43 | #define MOXA_ASPP_GETBAUD (MOXA + 72) |
| 44 | #define MOXA_ASPP_MON (MOXA + 73) |
| 45 | #define MOXA_ASPP_LSTATUS (MOXA + 74) |
| 46 | #define MOXA_ASPP_MON_EXT (MOXA + 75) |
| 47 | #define MOXA_SET_BAUD_METHOD (MOXA + 76) |
| 48 | |
| 49 | |
| 50 | /* --------------------------------------------------- */ |
| 51 | |
| 52 | #define NPPI_NOTIFY_PARITY 0x01 |
| 53 | #define NPPI_NOTIFY_FRAMING 0x02 |
| 54 | #define NPPI_NOTIFY_HW_OVERRUN 0x04 |
| 55 | #define NPPI_NOTIFY_SW_OVERRUN 0x08 |
| 56 | #define NPPI_NOTIFY_BREAK 0x10 |
| 57 | |
| 58 | #define NPPI_NOTIFY_CTSHOLD 0x01 // Tx hold by CTS low |
| 59 | #define NPPI_NOTIFY_DSRHOLD 0x02 // Tx hold by DSR low |
| 60 | #define NPPI_NOTIFY_XOFFHOLD 0x08 // Tx hold by Xoff received |
| 61 | #define NPPI_NOTIFY_XOFFXENT 0x10 // Xoff Sent |
| 62 | |
| 63 | //CheckIsMoxaMust return value |
| 64 | #define MOXA_OTHER_UART 0x00 |
| 65 | #define MOXA_MUST_MU150_HWID 0x01 |
| 66 | #define MOXA_MUST_MU860_HWID 0x02 |
| 67 | |
| 68 | // follow just for Moxa Must chip define. |
| 69 | // |
| 70 | // when LCR register (offset 0x03) write following value, |
| 71 | // the Must chip will enter enchance mode. And write value |
| 72 | // on EFR (offset 0x02) bit 6,7 to change bank. |
| 73 | #define MOXA_MUST_ENTER_ENCHANCE 0xBF |
| 74 | |
| 75 | // when enhance mode enable, access on general bank register |
| 76 | #define MOXA_MUST_GDL_REGISTER 0x07 |
| 77 | #define MOXA_MUST_GDL_MASK 0x7F |
| 78 | #define MOXA_MUST_GDL_HAS_BAD_DATA 0x80 |
| 79 | |
| 80 | #define MOXA_MUST_LSR_RERR 0x80 // error in receive FIFO |
| 81 | // enchance register bank select and enchance mode setting register |
| 82 | // when LCR register equal to 0xBF |
| 83 | #define MOXA_MUST_EFR_REGISTER 0x02 |
| 84 | // enchance mode enable |
| 85 | #define MOXA_MUST_EFR_EFRB_ENABLE 0x10 |
| 86 | // enchance reister bank set 0, 1, 2 |
| 87 | #define MOXA_MUST_EFR_BANK0 0x00 |
| 88 | #define MOXA_MUST_EFR_BANK1 0x40 |
| 89 | #define MOXA_MUST_EFR_BANK2 0x80 |
| 90 | #define MOXA_MUST_EFR_BANK3 0xC0 |
| 91 | #define MOXA_MUST_EFR_BANK_MASK 0xC0 |
| 92 | |
| 93 | // set XON1 value register, when LCR=0xBF and change to bank0 |
| 94 | #define MOXA_MUST_XON1_REGISTER 0x04 |
| 95 | |
| 96 | // set XON2 value register, when LCR=0xBF and change to bank0 |
| 97 | #define MOXA_MUST_XON2_REGISTER 0x05 |
| 98 | |
| 99 | // set XOFF1 value register, when LCR=0xBF and change to bank0 |
| 100 | #define MOXA_MUST_XOFF1_REGISTER 0x06 |
| 101 | |
| 102 | // set XOFF2 value register, when LCR=0xBF and change to bank0 |
| 103 | #define MOXA_MUST_XOFF2_REGISTER 0x07 |
| 104 | |
| 105 | #define MOXA_MUST_RBRTL_REGISTER 0x04 |
| 106 | #define MOXA_MUST_RBRTH_REGISTER 0x05 |
| 107 | #define MOXA_MUST_RBRTI_REGISTER 0x06 |
| 108 | #define MOXA_MUST_THRTL_REGISTER 0x07 |
| 109 | #define MOXA_MUST_ENUM_REGISTER 0x04 |
| 110 | #define MOXA_MUST_HWID_REGISTER 0x05 |
| 111 | #define MOXA_MUST_ECR_REGISTER 0x06 |
| 112 | #define MOXA_MUST_CSR_REGISTER 0x07 |
| 113 | |
| 114 | // good data mode enable |
| 115 | #define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 |
| 116 | // only good data put into RxFIFO |
| 117 | #define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 |
| 118 | |
| 119 | // enable CTS interrupt |
| 120 | #define MOXA_MUST_IER_ECTSI 0x80 |
| 121 | // eanble RTS interrupt |
| 122 | #define MOXA_MUST_IER_ERTSI 0x40 |
| 123 | // enable Xon/Xoff interrupt |
| 124 | #define MOXA_MUST_IER_XINT 0x20 |
| 125 | // enable GDA interrupt |
| 126 | #define MOXA_MUST_IER_EGDAI 0x10 |
| 127 | |
| 128 | #define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI) |
| 129 | |
| 130 | // GDA interrupt pending |
| 131 | #define MOXA_MUST_IIR_GDA 0x1C |
| 132 | #define MOXA_MUST_IIR_RDA 0x04 |
| 133 | #define MOXA_MUST_IIR_RTO 0x0C |
| 134 | #define MOXA_MUST_IIR_LSR 0x06 |
| 135 | |
| 136 | // recieved Xon/Xoff or specical interrupt pending |
| 137 | #define MOXA_MUST_IIR_XSC 0x10 |
| 138 | |
| 139 | // RTS/CTS change state interrupt pending |
| 140 | #define MOXA_MUST_IIR_RTSCTS 0x20 |
| 141 | #define MOXA_MUST_IIR_MASK 0x3E |
| 142 | |
| 143 | #define MOXA_MUST_MCR_XON_FLAG 0x40 |
| 144 | #define MOXA_MUST_MCR_XON_ANY 0x80 |
| 145 | #define MOXA_MUST_MCR_TX_XON 0x08 |
| 146 | |
| 147 | |
| 148 | // software flow control on chip mask value |
| 149 | #define MOXA_MUST_EFR_SF_MASK 0x0F |
| 150 | // send Xon1/Xoff1 |
| 151 | #define MOXA_MUST_EFR_SF_TX1 0x08 |
| 152 | // send Xon2/Xoff2 |
| 153 | #define MOXA_MUST_EFR_SF_TX2 0x04 |
| 154 | // send Xon1,Xon2/Xoff1,Xoff2 |
| 155 | #define MOXA_MUST_EFR_SF_TX12 0x0C |
| 156 | // don't send Xon/Xoff |
| 157 | #define MOXA_MUST_EFR_SF_TX_NO 0x00 |
| 158 | // Tx software flow control mask |
| 159 | #define MOXA_MUST_EFR_SF_TX_MASK 0x0C |
| 160 | // don't receive Xon/Xoff |
| 161 | #define MOXA_MUST_EFR_SF_RX_NO 0x00 |
| 162 | // receive Xon1/Xoff1 |
| 163 | #define MOXA_MUST_EFR_SF_RX1 0x02 |
| 164 | // receive Xon2/Xoff2 |
| 165 | #define MOXA_MUST_EFR_SF_RX2 0x01 |
| 166 | // receive Xon1,Xon2/Xoff1,Xoff2 |
| 167 | #define MOXA_MUST_EFR_SF_RX12 0x03 |
| 168 | // Rx software flow control mask |
| 169 | #define MOXA_MUST_EFR_SF_RX_MASK 0x03 |
| 170 | |
| 171 | //#define MOXA_MUST_MIN_XOFFLIMIT 66 |
| 172 | //#define MOXA_MUST_MIN_XONLIMIT 20 |
| 173 | //#define ID1_RX_TRIG 120 |
| 174 | |
| 175 | |
| 176 | #define CHECK_MOXA_MUST_XOFFLIMIT(info) { \ |
| 177 | if ( (info)->IsMoxaMustChipFlag && \ |
| 178 | (info)->HandFlow.XoffLimit < MOXA_MUST_MIN_XOFFLIMIT ) { \ |
| 179 | (info)->HandFlow.XoffLimit = MOXA_MUST_MIN_XOFFLIMIT; \ |
| 180 | (info)->HandFlow.XonLimit = MOXA_MUST_MIN_XONLIMIT; \ |
| 181 | } \ |
| 182 | } |
| 183 | |
| 184 | #define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) { \ |
| 185 | u8 __oldlcr, __efr; \ |
| 186 | __oldlcr = inb((baseio)+UART_LCR); \ |
| 187 | outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ |
| 188 | __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 189 | __efr |= MOXA_MUST_EFR_EFRB_ENABLE; \ |
| 190 | outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 191 | outb(__oldlcr, (baseio)+UART_LCR); \ |
| 192 | } |
| 193 | |
| 194 | #define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) { \ |
| 195 | u8 __oldlcr, __efr; \ |
| 196 | __oldlcr = inb((baseio)+UART_LCR); \ |
| 197 | outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ |
| 198 | __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 199 | __efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \ |
| 200 | outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 201 | outb(__oldlcr, (baseio)+UART_LCR); \ |
| 202 | } |
| 203 | |
| 204 | #define SET_MOXA_MUST_XON1_VALUE(baseio, Value) { \ |
| 205 | u8 __oldlcr, __efr; \ |
| 206 | __oldlcr = inb((baseio)+UART_LCR); \ |
| 207 | outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ |
| 208 | __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 209 | __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ |
| 210 | __efr |= MOXA_MUST_EFR_BANK0; \ |
| 211 | outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 212 | outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \ |
| 213 | outb(__oldlcr, (baseio)+UART_LCR); \ |
| 214 | } |
| 215 | |
| 216 | #define SET_MOXA_MUST_XON2_VALUE(baseio, Value) { \ |
| 217 | u8 __oldlcr, __efr; \ |
| 218 | __oldlcr = inb((baseio)+UART_LCR); \ |
| 219 | outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ |
| 220 | __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 221 | __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ |
| 222 | __efr |= MOXA_MUST_EFR_BANK0; \ |
| 223 | outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 224 | outb((u8)(Value), (baseio)+MOXA_MUST_XON2_REGISTER); \ |
| 225 | outb(__oldlcr, (baseio)+UART_LCR); \ |
| 226 | } |
| 227 | |
| 228 | #define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) { \ |
| 229 | u8 __oldlcr, __efr; \ |
| 230 | __oldlcr = inb((baseio)+UART_LCR); \ |
| 231 | outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ |
| 232 | __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 233 | __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ |
| 234 | __efr |= MOXA_MUST_EFR_BANK0; \ |
| 235 | outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 236 | outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \ |
| 237 | outb(__oldlcr, (baseio)+UART_LCR); \ |
| 238 | } |
| 239 | |
| 240 | #define SET_MOXA_MUST_XOFF2_VALUE(baseio, Value) { \ |
| 241 | u8 __oldlcr, __efr; \ |
| 242 | __oldlcr = inb((baseio)+UART_LCR); \ |
| 243 | outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ |
| 244 | __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 245 | __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ |
| 246 | __efr |= MOXA_MUST_EFR_BANK0; \ |
| 247 | outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 248 | outb((u8)(Value), (baseio)+MOXA_MUST_XOFF2_REGISTER); \ |
| 249 | outb(__oldlcr, (baseio)+UART_LCR); \ |
| 250 | } |
| 251 | |
| 252 | #define SET_MOXA_MUST_RBRTL_VALUE(baseio, Value) { \ |
| 253 | u8 __oldlcr, __efr; \ |
| 254 | __oldlcr = inb((baseio)+UART_LCR); \ |
| 255 | outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ |
| 256 | __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 257 | __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ |
| 258 | __efr |= MOXA_MUST_EFR_BANK1; \ |
| 259 | outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 260 | outb((u8)(Value), (baseio)+MOXA_MUST_RBRTL_REGISTER); \ |
| 261 | outb(__oldlcr, (baseio)+UART_LCR); \ |
| 262 | } |
| 263 | |
| 264 | #define SET_MOXA_MUST_RBRTH_VALUE(baseio, Value) { \ |
| 265 | u8 __oldlcr, __efr; \ |
| 266 | __oldlcr = inb((baseio)+UART_LCR); \ |
| 267 | outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ |
| 268 | __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 269 | __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ |
| 270 | __efr |= MOXA_MUST_EFR_BANK1; \ |
| 271 | outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 272 | outb((u8)(Value), (baseio)+MOXA_MUST_RBRTH_REGISTER); \ |
| 273 | outb(__oldlcr, (baseio)+UART_LCR); \ |
| 274 | } |
| 275 | |
| 276 | #define SET_MOXA_MUST_RBRTI_VALUE(baseio, Value) { \ |
| 277 | u8 __oldlcr, __efr; \ |
| 278 | __oldlcr = inb((baseio)+UART_LCR); \ |
| 279 | outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ |
| 280 | __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 281 | __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ |
| 282 | __efr |= MOXA_MUST_EFR_BANK1; \ |
| 283 | outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 284 | outb((u8)(Value), (baseio)+MOXA_MUST_RBRTI_REGISTER); \ |
| 285 | outb(__oldlcr, (baseio)+UART_LCR); \ |
| 286 | } |
| 287 | |
| 288 | #define SET_MOXA_MUST_THRTL_VALUE(baseio, Value) { \ |
| 289 | u8 __oldlcr, __efr; \ |
| 290 | __oldlcr = inb((baseio)+UART_LCR); \ |
| 291 | outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ |
| 292 | __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 293 | __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ |
| 294 | __efr |= MOXA_MUST_EFR_BANK1; \ |
| 295 | outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 296 | outb((u8)(Value), (baseio)+MOXA_MUST_THRTL_REGISTER); \ |
| 297 | outb(__oldlcr, (baseio)+UART_LCR); \ |
| 298 | } |
| 299 | |
| 300 | //#define MOXA_MUST_RBRL_VALUE 4 |
| 301 | #define SET_MOXA_MUST_FIFO_VALUE(info) { \ |
| 302 | u8 __oldlcr, __efr; \ |
| 303 | __oldlcr = inb((info)->base+UART_LCR); \ |
| 304 | outb(MOXA_MUST_ENTER_ENCHANCE, (info)->base+UART_LCR); \ |
| 305 | __efr = inb((info)->base+MOXA_MUST_EFR_REGISTER); \ |
| 306 | __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ |
| 307 | __efr |= MOXA_MUST_EFR_BANK1; \ |
| 308 | outb(__efr, (info)->base+MOXA_MUST_EFR_REGISTER); \ |
| 309 | outb((u8)((info)->rx_high_water), (info)->base+MOXA_MUST_RBRTH_REGISTER); \ |
| 310 | outb((u8)((info)->rx_trigger), (info)->base+MOXA_MUST_RBRTI_REGISTER); \ |
| 311 | outb((u8)((info)->rx_low_water), (info)->base+MOXA_MUST_RBRTL_REGISTER); \ |
| 312 | outb(__oldlcr, (info)->base+UART_LCR); \ |
| 313 | } |
| 314 | |
| 315 | |
| 316 | |
| 317 | #define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) { \ |
| 318 | u8 __oldlcr, __efr; \ |
| 319 | __oldlcr = inb((baseio)+UART_LCR); \ |
| 320 | outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ |
| 321 | __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 322 | __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ |
| 323 | __efr |= MOXA_MUST_EFR_BANK2; \ |
| 324 | outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 325 | outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER); \ |
| 326 | outb(__oldlcr, (baseio)+UART_LCR); \ |
| 327 | } |
| 328 | |
| 329 | #define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) { \ |
| 330 | u8 __oldlcr, __efr; \ |
| 331 | __oldlcr = inb((baseio)+UART_LCR); \ |
| 332 | outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ |
| 333 | __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 334 | __efr &= ~MOXA_MUST_EFR_BANK_MASK; \ |
| 335 | __efr |= MOXA_MUST_EFR_BANK2; \ |
| 336 | outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 337 | *pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \ |
| 338 | outb(__oldlcr, (baseio)+UART_LCR); \ |
| 339 | } |
| 340 | |
| 341 | #define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) { \ |
| 342 | u8 __oldlcr, __efr; \ |
| 343 | __oldlcr = inb((baseio)+UART_LCR); \ |
| 344 | outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ |
| 345 | __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 346 | __efr &= ~MOXA_MUST_EFR_SF_MASK; \ |
| 347 | outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 348 | outb(__oldlcr, (baseio)+UART_LCR); \ |
| 349 | } |
| 350 | |
| 351 | #define SET_MOXA_MUST_JUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \ |
| 352 | u8 __oldlcr, __efr; \ |
| 353 | __oldlcr = inb((baseio)+UART_LCR); \ |
| 354 | outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ |
| 355 | __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 356 | __efr &= ~MOXA_MUST_EFR_SF_MASK; \ |
| 357 | __efr |= MOXA_MUST_EFR_SF_TX1; \ |
| 358 | outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 359 | outb(__oldlcr, (baseio)+UART_LCR); \ |
| 360 | } |
| 361 | |
| 362 | #define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \ |
| 363 | u8 __oldlcr, __efr; \ |
| 364 | __oldlcr = inb((baseio)+UART_LCR); \ |
| 365 | outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ |
| 366 | __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 367 | __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \ |
| 368 | __efr |= MOXA_MUST_EFR_SF_TX1; \ |
| 369 | outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 370 | outb(__oldlcr, (baseio)+UART_LCR); \ |
| 371 | } |
| 372 | |
| 373 | #define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) { \ |
| 374 | u8 __oldlcr, __efr; \ |
| 375 | __oldlcr = inb((baseio)+UART_LCR); \ |
| 376 | outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ |
| 377 | __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 378 | __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \ |
| 379 | outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 380 | outb(__oldlcr, (baseio)+UART_LCR); \ |
| 381 | } |
| 382 | |
| 383 | #define SET_MOXA_MUST_JUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \ |
| 384 | u8 __oldlcr, __efr; \ |
| 385 | __oldlcr = inb((baseio)+UART_LCR); \ |
| 386 | outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ |
| 387 | __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 388 | __efr &= ~MOXA_MUST_EFR_SF_MASK; \ |
| 389 | __efr |= MOXA_MUST_EFR_SF_RX1; \ |
| 390 | outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 391 | outb(__oldlcr, (baseio)+UART_LCR); \ |
| 392 | } |
| 393 | |
| 394 | #define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \ |
| 395 | u8 __oldlcr, __efr; \ |
| 396 | __oldlcr = inb((baseio)+UART_LCR); \ |
| 397 | outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ |
| 398 | __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 399 | __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \ |
| 400 | __efr |= MOXA_MUST_EFR_SF_RX1; \ |
| 401 | outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 402 | outb(__oldlcr, (baseio)+UART_LCR); \ |
| 403 | } |
| 404 | |
| 405 | #define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) { \ |
| 406 | u8 __oldlcr, __efr; \ |
| 407 | __oldlcr = inb((baseio)+UART_LCR); \ |
| 408 | outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ |
| 409 | __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 410 | __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \ |
| 411 | outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 412 | outb(__oldlcr, (baseio)+UART_LCR); \ |
| 413 | } |
| 414 | |
| 415 | #define ENABLE_MOXA_MUST_TX_RX_SOFTWARE_FLOW_CONTROL(baseio) { \ |
| 416 | u8 __oldlcr, __efr; \ |
| 417 | __oldlcr = inb((baseio)+UART_LCR); \ |
| 418 | outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \ |
| 419 | __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 420 | __efr &= ~MOXA_MUST_EFR_SF_MASK; \ |
| 421 | __efr |= (MOXA_MUST_EFR_SF_RX1|MOXA_MUST_EFR_SF_TX1); \ |
| 422 | outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \ |
| 423 | outb(__oldlcr, (baseio)+UART_LCR); \ |
| 424 | } |
| 425 | |
| 426 | #define ENABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(baseio) { \ |
| 427 | u8 __oldmcr; \ |
| 428 | __oldmcr = inb((baseio)+UART_MCR); \ |
| 429 | __oldmcr |= MOXA_MUST_MCR_XON_ANY; \ |
| 430 | outb(__oldmcr, (baseio)+UART_MCR); \ |
| 431 | } |
| 432 | |
| 433 | #define DISABLE_MOXA_MUST_XON_ANY_FLOW_CONTROL(baseio) { \ |
| 434 | u8 __oldmcr; \ |
| 435 | __oldmcr = inb((baseio)+UART_MCR); \ |
| 436 | __oldmcr &= ~MOXA_MUST_MCR_XON_ANY; \ |
| 437 | outb(__oldmcr, (baseio)+UART_MCR); \ |
| 438 | } |
| 439 | |
| 440 | #define READ_MOXA_MUST_GDL(baseio) inb((baseio)+MOXA_MUST_GDL_REGISTER) |
| 441 | |
| 442 | |
| 443 | #ifndef INIT_WORK |
| 444 | #define INIT_WORK(_work, _func, _data){ \ |
| 445 | _data->tqueue.routine = _func;\ |
| 446 | _data->tqueue.data = _data;\ |
| 447 | } |
| 448 | #endif |
| 449 | |
| 450 | #endif |