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gerrit-public.fairphone.software / kernel / msm / 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 / . / include / asm-ppc / mpc52xx.h
blob: e5f80c22fbfcfc7d80095ef7c8397709136acb9c [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame^]1/*
2 * include/asm-ppc/mpc52xx.h
3 *
4 * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
5 * May need to be cleaned as the port goes on ...
6 *
7 *
8 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
9 *
10 * Originally written by Dale Farnsworth <dfarnsworth@mvista.com>
11 * for the 2.4 kernel.
12 *
13 * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
14 * Copyright (C) 2003 MontaVista, Software, Inc.
15 *
16 * This file is licensed under the terms of the GNU General Public License
17 * version 2. This program is licensed "as is" without any warranty of any
18 * kind, whether express or implied.
19 */
20
21#ifndef __ASM_MPC52xx_H__
22#define __ASM_MPC52xx_H__
23
24#ifndef __ASSEMBLY__
25#include <asm/ppcboot.h>
26#include <asm/types.h>
27
28struct pt_regs;
29#endif /* __ASSEMBLY__ */
30
31
32/* ======================================================================== */
33/* PPC Sys devices definition */
34/* ======================================================================== */
35
36enum ppc_sys_devices {
37 MPC52xx_MSCAN1,
38 MPC52xx_MSCAN2,
39 MPC52xx_SPI,
40 MPC52xx_USB,
41 MPC52xx_BDLC,
42 MPC52xx_PSC1,
43 MPC52xx_PSC2,
44 MPC52xx_PSC3,
45 MPC52xx_PSC4,
46 MPC52xx_PSC5,
47 MPC52xx_PSC6,
48 MPC52xx_FEC,
49 MPC52xx_ATA,
50 MPC52xx_I2C1,
51 MPC52xx_I2C2,
52};
53
54
55/* ======================================================================== */
56/* Main registers/struct addresses */
57/* ======================================================================== */
58
59/* MBAR position */
60#define MPC52xx_MBAR 0xf0000000 /* Phys address */
61#define MPC52xx_MBAR_VIRT 0xf0000000 /* Virt address */
62#define MPC52xx_MBAR_SIZE 0x00010000
63
64#define MPC52xx_PA(x) ((phys_addr_t)(MPC52xx_MBAR + (x)))
65#define MPC52xx_VA(x) ((void __iomem *)(MPC52xx_MBAR_VIRT + (x)))
66
67/* Registers zone offset/size */
68#define MPC52xx_MMAP_CTL_OFFSET 0x0000
69#define MPC52xx_MMAP_CTL_SIZE 0x068
70#define MPC52xx_SDRAM_OFFSET 0x0100
71#define MPC52xx_SDRAM_SIZE 0x010
72#define MPC52xx_CDM_OFFSET 0x0200
73#define MPC52xx_CDM_SIZE 0x038
74#define MPC52xx_INTR_OFFSET 0x0500
75#define MPC52xx_INTR_SIZE 0x04c
76#define MPC52xx_GPTx_OFFSET(x) (0x0600 + ((x)<<4))
77#define MPC52xx_GPT_SIZE 0x010
78#define MPC52xx_RTC_OFFSET 0x0800
79#define MPC52xx_RTC_SIZE 0x024
80#define MPC52xx_GPIO_OFFSET 0x0b00
81#define MPC52xx_GPIO_SIZE 0x040
82#define MPC52xx_GPIO_WKUP_OFFSET 0x0c00
83#define MPC52xx_GPIO_WKUP_SIZE 0x028
84#define MPC52xx_PCI_OFFSET 0x0d00
85#define MPC52xx_PCI_SIZE 0x100
86#define MPC52xx_SDMA_OFFSET 0x1200
87#define MPC52xx_SDMA_SIZE 0x100
88#define MPC52xx_XLB_OFFSET 0x1f00
89#define MPC52xx_XLB_SIZE 0x100
90#define MPC52xx_PSCx_OFFSET(x) (((x)!=6)?(0x1e00+((x)<<9)):0x2c00)
91#define MPC52xx_PSC_SIZE 0x0a0
92
93/* SRAM used for SDMA */
94#define MPC52xx_SRAM_OFFSET 0x8000
95#define MPC52xx_SRAM_SIZE 0x4000
96
97
98/* ======================================================================== */
99/* IRQ mapping */
100/* ======================================================================== */
101/* Be sure to look at mpc52xx_pic.h if you wish for whatever reason to change
102 * this
103 */
104
105#define MPC52xx_CRIT_IRQ_NUM 4
106#define MPC52xx_MAIN_IRQ_NUM 17
107#define MPC52xx_SDMA_IRQ_NUM 17
108#define MPC52xx_PERP_IRQ_NUM 23
109
110#define MPC52xx_CRIT_IRQ_BASE 0
111#define MPC52xx_MAIN_IRQ_BASE (MPC52xx_CRIT_IRQ_BASE + MPC52xx_CRIT_IRQ_NUM)
112#define MPC52xx_SDMA_IRQ_BASE (MPC52xx_MAIN_IRQ_BASE + MPC52xx_MAIN_IRQ_NUM)
113#define MPC52xx_PERP_IRQ_BASE (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM)
114
115#define MPC52xx_IRQ0 (MPC52xx_CRIT_IRQ_BASE + 0)
116#define MPC52xx_SLICE_TIMER_0_IRQ (MPC52xx_CRIT_IRQ_BASE + 1)
117#define MPC52xx_HI_INT_IRQ (MPC52xx_CRIT_IRQ_BASE + 2)
118#define MPC52xx_CCS_IRQ (MPC52xx_CRIT_IRQ_BASE + 3)
119
120#define MPC52xx_IRQ1 (MPC52xx_MAIN_IRQ_BASE + 1)
121#define MPC52xx_IRQ2 (MPC52xx_MAIN_IRQ_BASE + 2)
122#define MPC52xx_IRQ3 (MPC52xx_MAIN_IRQ_BASE + 3)
123
124#define MPC52xx_SDMA_IRQ (MPC52xx_PERP_IRQ_BASE + 0)
125#define MPC52xx_PSC1_IRQ (MPC52xx_PERP_IRQ_BASE + 1)
126#define MPC52xx_PSC2_IRQ (MPC52xx_PERP_IRQ_BASE + 2)
127#define MPC52xx_PSC3_IRQ (MPC52xx_PERP_IRQ_BASE + 3)
128#define MPC52xx_PSC6_IRQ (MPC52xx_PERP_IRQ_BASE + 4)
129#define MPC52xx_IRDA_IRQ (MPC52xx_PERP_IRQ_BASE + 4)
130#define MPC52xx_FEC_IRQ (MPC52xx_PERP_IRQ_BASE + 5)
131#define MPC52xx_USB_IRQ (MPC52xx_PERP_IRQ_BASE + 6)
132#define MPC52xx_ATA_IRQ (MPC52xx_PERP_IRQ_BASE + 7)
133#define MPC52xx_PCI_CNTRL_IRQ (MPC52xx_PERP_IRQ_BASE + 8)
134#define MPC52xx_PCI_SCIRX_IRQ (MPC52xx_PERP_IRQ_BASE + 9)
135#define MPC52xx_PCI_SCITX_IRQ (MPC52xx_PERP_IRQ_BASE + 10)
136#define MPC52xx_PSC4_IRQ (MPC52xx_PERP_IRQ_BASE + 11)
137#define MPC52xx_PSC5_IRQ (MPC52xx_PERP_IRQ_BASE + 12)
138#define MPC52xx_SPI_MODF_IRQ (MPC52xx_PERP_IRQ_BASE + 13)
139#define MPC52xx_SPI_SPIF_IRQ (MPC52xx_PERP_IRQ_BASE + 14)
140#define MPC52xx_I2C1_IRQ (MPC52xx_PERP_IRQ_BASE + 15)
141#define MPC52xx_I2C2_IRQ (MPC52xx_PERP_IRQ_BASE + 16)
142#define MPC52xx_MSCAN1_IRQ (MPC52xx_PERP_IRQ_BASE + 17)
143#define MPC52xx_MSCAN2_IRQ (MPC52xx_PERP_IRQ_BASE + 18)
144#define MPC52xx_IR_RX_IRQ (MPC52xx_PERP_IRQ_BASE + 19)
145#define MPC52xx_IR_TX_IRQ (MPC52xx_PERP_IRQ_BASE + 20)
146#define MPC52xx_XLB_ARB_IRQ (MPC52xx_PERP_IRQ_BASE + 21)
147#define MPC52xx_BDLC_IRQ (MPC52xx_PERP_IRQ_BASE + 22)
148
149
150
151/* ======================================================================== */
152/* Structures mapping of some unit register set */
153/* ======================================================================== */
154
155#ifndef __ASSEMBLY__
156
157/* Memory Mapping Control */
158struct mpc52xx_mmap_ctl {
159 u32 mbar; /* MMAP_CTRL + 0x00 */
160
161 u32 cs0_start; /* MMAP_CTRL + 0x04 */
162 u32 cs0_stop; /* MMAP_CTRL + 0x08 */
163 u32 cs1_start; /* MMAP_CTRL + 0x0c */
164 u32 cs1_stop; /* MMAP_CTRL + 0x10 */
165 u32 cs2_start; /* MMAP_CTRL + 0x14 */
166 u32 cs2_stop; /* MMAP_CTRL + 0x18 */
167 u32 cs3_start; /* MMAP_CTRL + 0x1c */
168 u32 cs3_stop; /* MMAP_CTRL + 0x20 */
169 u32 cs4_start; /* MMAP_CTRL + 0x24 */
170 u32 cs4_stop; /* MMAP_CTRL + 0x28 */
171 u32 cs5_start; /* MMAP_CTRL + 0x2c */
172 u32 cs5_stop; /* MMAP_CTRL + 0x30 */
173
174 u32 sdram0; /* MMAP_CTRL + 0x34 */
175 u32 sdram1; /* MMAP_CTRL + 0X38 */
176
177 u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */
178
179 u32 boot_start; /* MMAP_CTRL + 0x4c */
180 u32 boot_stop; /* MMAP_CTRL + 0x50 */
181
182 u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */
183
184 u32 cs6_start; /* MMAP_CTRL + 0x58 */
185 u32 cs6_stop; /* MMAP_CTRL + 0x5c */
186 u32 cs7_start; /* MMAP_CTRL + 0x60 */
187 u32 cs7_stop; /* MMAP_CTRL + 0x64 */
188};
189
190/* SDRAM control */
191struct mpc52xx_sdram {
192 u32 mode; /* SDRAM + 0x00 */
193 u32 ctrl; /* SDRAM + 0x04 */
194 u32 config1; /* SDRAM + 0x08 */
195 u32 config2; /* SDRAM + 0x0c */
196};
197
198/* Interrupt controller */
199struct mpc52xx_intr {
200 u32 per_mask; /* INTR + 0x00 */
201 u32 per_pri1; /* INTR + 0x04 */
202 u32 per_pri2; /* INTR + 0x08 */
203 u32 per_pri3; /* INTR + 0x0c */
204 u32 ctrl; /* INTR + 0x10 */
205 u32 main_mask; /* INTR + 0x14 */
206 u32 main_pri1; /* INTR + 0x18 */
207 u32 main_pri2; /* INTR + 0x1c */
208 u32 reserved1; /* INTR + 0x20 */
209 u32 enc_status; /* INTR + 0x24 */
210 u32 crit_status; /* INTR + 0x28 */
211 u32 main_status; /* INTR + 0x2c */
212 u32 per_status; /* INTR + 0x30 */
213 u32 reserved2; /* INTR + 0x34 */
214 u32 per_error; /* INTR + 0x38 */
215};
216
217/* SDMA */
218struct mpc52xx_sdma {
219 u32 taskBar; /* SDMA + 0x00 */
220 u32 currentPointer; /* SDMA + 0x04 */
221 u32 endPointer; /* SDMA + 0x08 */
222 u32 variablePointer;/* SDMA + 0x0c */
223
224 u8 IntVect1; /* SDMA + 0x10 */
225 u8 IntVect2; /* SDMA + 0x11 */
226 u16 PtdCntrl; /* SDMA + 0x12 */
227
228 u32 IntPend; /* SDMA + 0x14 */
229 u32 IntMask; /* SDMA + 0x18 */
230
231 u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */
232
233 u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */
234
235 u32 cReqSelect; /* SDMA + 0x5c */
236 u32 task_size0; /* SDMA + 0x60 */
237 u32 task_size1; /* SDMA + 0x64 */
238 u32 MDEDebug; /* SDMA + 0x68 */
239 u32 ADSDebug; /* SDMA + 0x6c */
240 u32 Value1; /* SDMA + 0x70 */
241 u32 Value2; /* SDMA + 0x74 */
242 u32 Control; /* SDMA + 0x78 */
243 u32 Status; /* SDMA + 0x7c */
244 u32 PTDDebug; /* SDMA + 0x80 */
245};
246
247/* GPT */
248struct mpc52xx_gpt {
249 u32 mode; /* GPTx + 0x00 */
250 u32 count; /* GPTx + 0x04 */
251 u32 pwm; /* GPTx + 0x08 */
252 u32 status; /* GPTx + 0X0c */
253};
254
255/* RTC */
256struct mpc52xx_rtc {
257 u32 time_set; /* RTC + 0x00 */
258 u32 date_set; /* RTC + 0x04 */
259 u32 stopwatch; /* RTC + 0x08 */
260 u32 int_enable; /* RTC + 0x0c */
261 u32 time; /* RTC + 0x10 */
262 u32 date; /* RTC + 0x14 */
263 u32 stopwatch_intr; /* RTC + 0x18 */
264 u32 bus_error; /* RTC + 0x1c */
265 u32 dividers; /* RTC + 0x20 */
266};
267
268/* GPIO */
269struct mpc52xx_gpio {
270 u32 port_config; /* GPIO + 0x00 */
271 u32 simple_gpioe; /* GPIO + 0x04 */
272 u32 simple_ode; /* GPIO + 0x08 */
273 u32 simple_ddr; /* GPIO + 0x0c */
274 u32 simple_dvo; /* GPIO + 0x10 */
275 u32 simple_ival; /* GPIO + 0x14 */
276 u8 outo_gpioe; /* GPIO + 0x18 */
277 u8 reserved1[3]; /* GPIO + 0x19 */
278 u8 outo_dvo; /* GPIO + 0x1c */
279 u8 reserved2[3]; /* GPIO + 0x1d */
280 u8 sint_gpioe; /* GPIO + 0x20 */
281 u8 reserved3[3]; /* GPIO + 0x21 */
282 u8 sint_ode; /* GPIO + 0x24 */
283 u8 reserved4[3]; /* GPIO + 0x25 */
284 u8 sint_ddr; /* GPIO + 0x28 */
285 u8 reserved5[3]; /* GPIO + 0x29 */
286 u8 sint_dvo; /* GPIO + 0x2c */
287 u8 reserved6[3]; /* GPIO + 0x2d */
288 u8 sint_inten; /* GPIO + 0x30 */
289 u8 reserved7[3]; /* GPIO + 0x31 */
290 u16 sint_itype; /* GPIO + 0x34 */
291 u16 reserved8; /* GPIO + 0x36 */
292 u8 gpio_control; /* GPIO + 0x38 */
293 u8 reserved9[3]; /* GPIO + 0x39 */
294 u8 sint_istat; /* GPIO + 0x3c */
295 u8 sint_ival; /* GPIO + 0x3d */
296 u8 bus_errs; /* GPIO + 0x3e */
297 u8 reserved10; /* GPIO + 0x3f */
298};
299
300#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
301#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5
302#define MPC52xx_GPIO_PCI_DIS (1<<15)
303
304/* GPIO with WakeUp*/
305struct mpc52xx_gpio_wkup {
306 u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */
307 u8 reserved1[3]; /* GPIO_WKUP + 0x03 */
308 u8 wkup_ode; /* GPIO_WKUP + 0x04 */
309 u8 reserved2[3]; /* GPIO_WKUP + 0x05 */
310 u8 wkup_ddr; /* GPIO_WKUP + 0x08 */
311 u8 reserved3[3]; /* GPIO_WKUP + 0x09 */
312 u8 wkup_dvo; /* GPIO_WKUP + 0x0C */
313 u8 reserved4[3]; /* GPIO_WKUP + 0x0D */
314 u8 wkup_inten; /* GPIO_WKUP + 0x10 */
315 u8 reserved5[3]; /* GPIO_WKUP + 0x11 */
316 u8 wkup_iinten; /* GPIO_WKUP + 0x14 */
317 u8 reserved6[3]; /* GPIO_WKUP + 0x15 */
318 u16 wkup_itype; /* GPIO_WKUP + 0x18 */
319 u8 reserved7[2]; /* GPIO_WKUP + 0x1A */
320 u8 wkup_maste; /* GPIO_WKUP + 0x1C */
321 u8 reserved8[3]; /* GPIO_WKUP + 0x1D */
322 u8 wkup_ival; /* GPIO_WKUP + 0x20 */
323 u8 reserved9[3]; /* GPIO_WKUP + 0x21 */
324 u8 wkup_istat; /* GPIO_WKUP + 0x24 */
325 u8 reserved10[3]; /* GPIO_WKUP + 0x25 */
326};
327
328/* XLB Bus control */
329struct mpc52xx_xlb {
330 u8 reserved[0x40];
331 u32 config; /* XLB + 0x40 */
332 u32 version; /* XLB + 0x44 */
333 u32 status; /* XLB + 0x48 */
334 u32 int_enable; /* XLB + 0x4c */
335 u32 addr_capture; /* XLB + 0x50 */
336 u32 bus_sig_capture; /* XLB + 0x54 */
337 u32 addr_timeout; /* XLB + 0x58 */
338 u32 data_timeout; /* XLB + 0x5c */
339 u32 bus_act_timeout; /* XLB + 0x60 */
340 u32 master_pri_enable; /* XLB + 0x64 */
341 u32 master_priority; /* XLB + 0x68 */
342 u32 base_address; /* XLB + 0x6c */
343 u32 snoop_window; /* XLB + 0x70 */
344};
345
346#define MPC52xx_XLB_CFG_SNOOP (1 << 15)
347
348/* Clock Distribution control */
349struct mpc52xx_cdm {
350 u32 jtag_id; /* CDM + 0x00 reg0 read only */
351 u32 rstcfg; /* CDM + 0x04 reg1 read only */
352 u32 breadcrumb; /* CDM + 0x08 reg2 */
353
354 u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */
355 u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */
356 u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */
357 u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */
358
359 u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */
360 u8 fd_enable; /* CDM + 0x11 reg4 byte1 */
361 u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */
362
363 u32 clk_enables; /* CDM + 0x14 reg5 */
364
365 u8 osc_disable; /* CDM + 0x18 reg6 byte0 */
366 u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */
367
368 u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */
369 u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */
370 u8 reserved1; /* CDM + 0x1e reg7 byte2 */
371 u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */
372
373 u8 soft_reset; /* CDM + 0x20 u8 byte0 */
374 u8 no_ckstp; /* CDM + 0x21 u8 byte0 */
375 u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */
376
377 u8 pll_lock; /* CDM + 0x24 reg9 byte0 */
378 u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */
379 u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */
380 u8 reserved3; /* CDM + 0x27 reg9 byte3 */
381
382 u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */
383 u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */
384
385 u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */
386 u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */
387
388 u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */
389 u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */
390
391 u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */
392 u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */
393};
394
395#endif /* __ASSEMBLY__ */
396
397
398/* ========================================================================= */
399/* Prototypes for MPC52xx syslib */
400/* ========================================================================= */
401
402#ifndef __ASSEMBLY__
403
404extern void mpc52xx_init_irq(void);
405extern int mpc52xx_get_irq(struct pt_regs *regs);
406
407extern unsigned long mpc52xx_find_end_of_memory(void);
408extern void mpc52xx_set_bat(void);
409extern void mpc52xx_map_io(void);
410extern void mpc52xx_restart(char *cmd);
411extern void mpc52xx_halt(void);
412extern void mpc52xx_power_off(void);
413extern void mpc52xx_progress(char *s, unsigned short hex);
414extern void mpc52xx_calibrate_decr(void);
415
416extern void mpc52xx_find_bridges(void);
417
418
419 /* Matching of PSC function */
420struct mpc52xx_psc_func {
421 int id;
422 char *func;
423};
424
425extern int mpc52xx_match_psc_function(int psc_idx, const char *func);
426extern struct mpc52xx_psc_func mpc52xx_psc_functions[];
427 /* This array is to be defined in platform file */
428
429#endif /* __ASSEMBLY__ */
430
431
432/* ========================================================================= */
433/* Platform configuration */
434/* ========================================================================= */
435
436/* The U-Boot platform information struct */
437extern bd_t __res;
438
439/* Platform options */
440#if defined(CONFIG_LITE5200)
441#include <platforms/lite5200.h>
442#endif
443
444
445#endif /* __ASM_MPC52xx_H__ */