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Linus Torvalds1da177e2005-04-16 15:20:36 -07001#ifndef __ASM_ARM_SYSTEM_H
2#define __ASM_ARM_SYSTEM_H
3
4#ifdef __KERNEL__
5
Lennert Buytenhek398e6922007-03-31 12:03:20 +01006#include <asm/memory.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07007
8#define CPU_ARCH_UNKNOWN 0
9#define CPU_ARCH_ARMv3 1
10#define CPU_ARCH_ARMv4 2
11#define CPU_ARCH_ARMv4T 3
12#define CPU_ARCH_ARMv5 4
13#define CPU_ARCH_ARMv5T 5
14#define CPU_ARCH_ARMv5TE 6
15#define CPU_ARCH_ARMv5TEJ 7
16#define CPU_ARCH_ARMv6 8
17
18/*
19 * CR1 bits (CP#15 CR1)
20 */
21#define CR_M (1 << 0) /* MMU enable */
22#define CR_A (1 << 1) /* Alignment abort enable */
23#define CR_C (1 << 2) /* Dcache enable */
24#define CR_W (1 << 3) /* Write buffer enable */
25#define CR_P (1 << 4) /* 32-bit exception handler */
26#define CR_D (1 << 5) /* 32-bit data address range */
27#define CR_L (1 << 6) /* Implementation defined */
28#define CR_B (1 << 7) /* Big endian */
29#define CR_S (1 << 8) /* System MMU protection */
30#define CR_R (1 << 9) /* ROM MMU protection */
31#define CR_F (1 << 10) /* Implementation defined */
32#define CR_Z (1 << 11) /* Implementation defined */
33#define CR_I (1 << 12) /* Icache enable */
34#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
35#define CR_RR (1 << 14) /* Round Robin cache replacement */
36#define CR_L4 (1 << 15) /* LDR pc can set T bit */
37#define CR_DT (1 << 16)
38#define CR_IT (1 << 18)
39#define CR_ST (1 << 19)
40#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
41#define CR_U (1 << 22) /* Unaligned access operation */
42#define CR_XP (1 << 23) /* Extended page tables */
43#define CR_VE (1 << 24) /* Vectored interrupts */
44
45#define CPUID_ID 0
46#define CPUID_CACHETYPE 1
47#define CPUID_TCM 2
48#define CPUID_TLBTYPE 3
49
Hyok S. Choif12d0d72006-09-26 17:36:37 +090050#ifdef CONFIG_CPU_CP15
Linus Torvalds1da177e2005-04-16 15:20:36 -070051#define read_cpuid(reg) \
52 ({ \
53 unsigned int __val; \
54 asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
55 : "=r" (__val) \
56 : \
57 : "cc"); \
58 __val; \
59 })
Hyok S. Choif12d0d72006-09-26 17:36:37 +090060#else
61#define read_cpuid(reg) (processor_id)
62#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070063
64/*
65 * This is used to ensure the compiler did actually allocate the register we
66 * asked it for some inline assembly sequences. Apparently we can't trust
67 * the compiler from one version to another so a bit of paranoia won't hurt.
68 * This string is meant to be concatenated with the inline asm string and
69 * will cause compilation to stop on mismatch.
70 * (for details, see gcc PR 15089)
71 */
72#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
73
74#ifndef __ASSEMBLY__
75
76#include <linux/linkage.h>
Russell King255d1f82006-12-18 00:12:47 +000077#include <linux/irqflags.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070078
Russell King7ab3f8d2007-03-02 15:01:36 +000079#define __exception __attribute__((section(".exception.text")))
80
Linus Torvalds1da177e2005-04-16 15:20:36 -070081struct thread_info;
82struct task_struct;
83
84/* information about the system we're running on */
85extern unsigned int system_rev;
86extern unsigned int system_serial_low;
87extern unsigned int system_serial_high;
88extern unsigned int mem_fclk_21285;
89
90struct pt_regs;
91
92void die(const char *msg, struct pt_regs *regs, int err)
93 __attribute__((noreturn));
94
Russell Kingcfb08102005-06-30 11:06:49 +010095struct siginfo;
96void notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
97 unsigned long err, unsigned long trap);
Linus Torvalds1da177e2005-04-16 15:20:36 -070098
99void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
100 struct pt_regs *),
101 int sig, const char *name);
102
Linus Torvalds1da177e2005-04-16 15:20:36 -0700103#define xchg(ptr,x) \
104 ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
105
106#define tas(ptr) (xchg((ptr),1))
107
108extern asmlinkage void __backtrace(void);
Russell King652a12e2005-04-17 15:50:36 +0100109extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
Russell King5470dc62005-11-16 18:36:49 +0000110
111struct mm_struct;
Russell King652a12e2005-04-17 15:50:36 +0100112extern void show_pte(struct mm_struct *mm, unsigned long addr);
113extern void __show_regs(struct pt_regs *);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114
115extern int cpu_architecture(void);
Russell King36c5ed22005-06-19 18:39:33 +0100116extern void cpu_init(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117
Richard Purdie74617fb2006-06-19 19:57:12 +0100118void arm_machine_restart(char mode);
119extern void (*arm_pm_restart)(char str);
120
Lennert Buytenhek23bdf862006-03-28 21:00:40 +0100121/*
122 * Intel's XScale3 core supports some v6 features (supersections, L2)
123 * but advertises itself as v5 as it does not support the v6 ISA. For
124 * this reason, we need a way to explicitly test for this type of CPU.
125 */
126#ifndef CONFIG_CPU_XSC3
127#define cpu_is_xsc3() 0
128#else
129static inline int cpu_is_xsc3(void)
130{
131 extern unsigned int processor_id;
132
133 if ((processor_id & 0xffffe000) == 0x69056000)
134 return 1;
135
136 return 0;
137}
138#endif
139
Deepak Saxena5cedae92006-05-31 16:14:05 -0700140#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
141#define cpu_is_xscale() 0
142#else
143#define cpu_is_xscale() 1
144#endif
145
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146#define UDBG_UNDEFINED (1 << 0)
147#define UDBG_SYSCALL (1 << 1)
148#define UDBG_BADABORT (1 << 2)
149#define UDBG_SEGV (1 << 3)
150#define UDBG_BUS (1 << 4)
151
152extern unsigned int user_debug;
153
154#if __LINUX_ARM_ARCH__ >= 4
155#define vectors_high() (cr_alignment & CR_V)
156#else
157#define vectors_high() (0)
158#endif
159
Lennert Buytenhek398e6922007-03-31 12:03:20 +0100160#if defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ >= 6
Catalin Marinasdcda7e42007-02-05 14:47:35 +0100161#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
162 : : "r" (0) : "memory")
163#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
164 : : "r" (0) : "memory")
165#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
166 : : "r" (0) : "memory")
Russell King6d9b37a2005-07-26 19:44:26 +0100167#else
Catalin Marinasdcda7e42007-02-05 14:47:35 +0100168#define isb() __asm__ __volatile__ ("" : : : "memory")
169#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
170 : : "r" (0) : "memory")
171#define dmb() __asm__ __volatile__ ("" : : : "memory")
Russell King6d9b37a2005-07-26 19:44:26 +0100172#endif
Catalin Marinas9623b372007-02-28 12:30:38 +0100173
Lennert Buytenhek398e6922007-03-31 12:03:20 +0100174#ifndef CONFIG_SMP
175#define mb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
176#define rmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
177#define wmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
178#define smp_mb() barrier()
179#define smp_rmb() barrier()
180#define smp_wmb() barrier()
Catalin Marinas9623b372007-02-28 12:30:38 +0100181#else
Lennert Buytenhek398e6922007-03-31 12:03:20 +0100182#define mb() dmb()
183#define rmb() dmb()
184#define wmb() dmb()
185#define smp_mb() dmb()
186#define smp_rmb() dmb()
187#define smp_wmb() dmb()
188#endif
189#define read_barrier_depends() do { } while(0)
190#define smp_read_barrier_depends() do { } while(0)
Catalin Marinas9623b372007-02-28 12:30:38 +0100191
192#define set_mb(var, value) do { var = value; smp_mb(); } while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
194
Catalin Marinas56660fa2007-02-05 14:48:02 +0100195extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
196extern unsigned long cr_alignment; /* defined in entry-armv.S */
197
198static inline unsigned int get_cr(void)
199{
200 unsigned int val;
201 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
202 return val;
203}
204
205static inline void set_cr(unsigned int val)
206{
207 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
208 : : "r" (val) : "cc");
209 isb();
210}
211
212#ifndef CONFIG_SMP
213extern void adjust_cr(unsigned long mask, unsigned long set);
214#endif
215
216#define CPACC_FULL(n) (3 << (n * 2))
217#define CPACC_SVC(n) (1 << (n * 2))
218#define CPACC_DISABLE(n) (0 << (n * 2))
219
220static inline unsigned int get_copro_access(void)
221{
222 unsigned int val;
223 asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
224 : "=r" (val) : : "cc");
225 return val;
226}
227
228static inline void set_copro_access(unsigned int val)
229{
230 asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
231 : : "r" (val) : "cc");
232 isb();
233}
234
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235/*
Nick Piggin4866cde2005-06-25 14:57:23 -0700236 * switch_mm() may do a full cache flush over the context switch,
237 * so enable interrupts over the context switch to avoid high
238 * latency.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239 */
Nick Piggin4866cde2005-06-25 14:57:23 -0700240#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241
242/*
243 * switch_to(prev, next) should switch from task `prev' to `next'
244 * `prev' will never be the same as `next'. schedule() itself
245 * contains the memory barrier to tell GCC not to cache `current'.
246 */
247extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
248
249#define switch_to(prev,next,last) \
250do { \
Al Viroe7c1b322006-01-12 01:05:56 -0800251 last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700252} while (0)
253
254/*
Ingo Molnar4dc7a0b2006-01-12 01:05:27 -0800255 * On SMP systems, when the scheduler does migration-cost autodetection,
256 * it needs a way to flush as much of the CPU's caches as possible.
257 *
258 * TODO: fill this in!
259 */
260static inline void sched_cacheflush(void)
261{
262}
263
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
265/*
266 * On the StrongARM, "swp" is terminally broken since it bypasses the
267 * cache totally. This means that the cache becomes inconsistent, and,
268 * since we use normal loads/stores as well, this is really bad.
269 * Typically, this causes oopsen in filp_close, but could have other,
270 * more disasterous effects. There are two work-arounds:
271 * 1. Disable interrupts and emulate the atomic swap
272 * 2. Clean the cache, perform atomic swap, flush the cache
273 *
274 * We choose (1) since its the "easiest" to achieve here and is not
275 * dependent on the processor type.
Russell King053a7b52005-06-28 19:22:25 +0100276 *
277 * NOTE that this solution won't work on an SMP system, so explcitly
278 * forbid it here.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700279 */
280#define swp_is_buggy
281#endif
282
283static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
284{
285 extern void __bad_xchg(volatile void *, int);
286 unsigned long ret;
287#ifdef swp_is_buggy
288 unsigned long flags;
289#endif
Russell King95607822005-07-26 19:39:31 +0100290#if __LINUX_ARM_ARCH__ >= 6
291 unsigned int tmp;
292#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293
294 switch (size) {
Russell King95607822005-07-26 19:39:31 +0100295#if __LINUX_ARM_ARCH__ >= 6
296 case 1:
297 asm volatile("@ __xchg1\n"
298 "1: ldrexb %0, [%3]\n"
299 " strexb %1, %2, [%3]\n"
300 " teq %1, #0\n"
301 " bne 1b"
302 : "=&r" (ret), "=&r" (tmp)
303 : "r" (x), "r" (ptr)
304 : "memory", "cc");
305 break;
306 case 4:
307 asm volatile("@ __xchg4\n"
308 "1: ldrex %0, [%3]\n"
309 " strex %1, %2, [%3]\n"
310 " teq %1, #0\n"
311 " bne 1b"
312 : "=&r" (ret), "=&r" (tmp)
313 : "r" (x), "r" (ptr)
314 : "memory", "cc");
315 break;
316#elif defined(swp_is_buggy)
317#ifdef CONFIG_SMP
318#error SMP is not supported on this platform
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319#endif
Russell King95607822005-07-26 19:39:31 +0100320 case 1:
Lennert Buytenheke7cc2c52006-09-21 03:35:20 +0100321 raw_local_irq_save(flags);
Russell King95607822005-07-26 19:39:31 +0100322 ret = *(volatile unsigned char *)ptr;
323 *(volatile unsigned char *)ptr = x;
Lennert Buytenheke7cc2c52006-09-21 03:35:20 +0100324 raw_local_irq_restore(flags);
Russell King95607822005-07-26 19:39:31 +0100325 break;
326
327 case 4:
Lennert Buytenheke7cc2c52006-09-21 03:35:20 +0100328 raw_local_irq_save(flags);
Russell King95607822005-07-26 19:39:31 +0100329 ret = *(volatile unsigned long *)ptr;
330 *(volatile unsigned long *)ptr = x;
Lennert Buytenheke7cc2c52006-09-21 03:35:20 +0100331 raw_local_irq_restore(flags);
Russell King95607822005-07-26 19:39:31 +0100332 break;
333#else
334 case 1:
335 asm volatile("@ __xchg1\n"
336 " swpb %0, %1, [%2]"
337 : "=&r" (ret)
338 : "r" (x), "r" (ptr)
339 : "memory", "cc");
340 break;
341 case 4:
342 asm volatile("@ __xchg4\n"
343 " swp %0, %1, [%2]"
344 : "=&r" (ret)
345 : "r" (x), "r" (ptr)
346 : "memory", "cc");
347 break;
348#endif
349 default:
350 __bad_xchg(ptr, size), ret = 0;
351 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352 }
353
354 return ret;
355}
356
Ben Dooksdabaeff2006-03-15 23:17:26 +0000357extern void disable_hlt(void);
358extern void enable_hlt(void);
359
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360#endif /* __ASSEMBLY__ */
361
362#define arch_align_stack(x) (x)
363
364#endif /* __KERNEL__ */
365
366#endif