Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm / 1f21ad2a4f7f66855dae600ddd635ff5fb299bbd / . / drivers / net / wireless / b43 / wa.c
blob: b70992aa66bc4bb2783f083558fce155502dfac6 [file] [log] [blame]
Stefano Brivio61bca6e2007-11-06 22:49:05 +0100[diff] [blame]1/*
2
3 Broadcom B43 wireless driver
4
5 PHY workarounds.
6
Stefano Brivio1f21ad22007-11-06 22:49:20 +0100[diff] [blame^]7 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
Stefano Brivio61bca6e2007-11-06 22:49:05 +0100[diff] [blame]8 Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
Stefano Brivio61bca6e2007-11-06 22:49:05 +0100[diff] [blame]9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; see the file COPYING. If not, write to
22 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
23 Boston, MA 02110-1301, USA.
24
25*/
26
27#include "b43.h"
28#include "main.h"
29#include "tables.h"
30#include "phy.h"
31#include "wa.h"
32
33static void b43_wa_papd(struct b43_wldev *dev)
34{
35 u16 backup;
36
37 backup = b43_ofdmtab_read16(dev, B43_OFDMTAB_PWRDYN2, 0);
38 b43_ofdmtab_write16(dev, B43_OFDMTAB_PWRDYN2, 0, 7);
39 b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_APHY, 0, 0);
40 b43_dummy_transmission(dev);
41 b43_ofdmtab_write16(dev, B43_OFDMTAB_PWRDYN2, 0, backup);
42}
43
44static void b43_wa_auxclipthr(struct b43_wldev *dev)
45{
46 b43_phy_write(dev, B43_PHY_OFDM(0x8E), 0x3800);
47}
48
49static void b43_wa_afcdac(struct b43_wldev *dev)
50{
51 b43_phy_write(dev, 0x0035, 0x03FF);
52 b43_phy_write(dev, 0x0036, 0x0400);
53}
54
55static void b43_wa_txdc_offset(struct b43_wldev *dev)
56{
57 b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 0, 0x0051);
58}
59
60void b43_wa_initgains(struct b43_wldev *dev)
61{
62 struct b43_phy *phy = &dev->phy;
63
64 b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9);
65 b43_phy_write(dev, B43_PHY_LPFGAINCTL,
66 b43_phy_read(dev, B43_PHY_LPFGAINCTL) & 0xFF0F);
67 if (phy->rev <= 2)
68 b43_ofdmtab_write16(dev, B43_OFDMTAB_LPFGAIN, 0, 0x1FBF);
69 b43_radio_write16(dev, 0x0002, 0x1FBF);
70
71 b43_phy_write(dev, 0x0024, 0x4680);
72 b43_phy_write(dev, 0x0020, 0x0003);
73 b43_phy_write(dev, 0x001D, 0x0F40);
74 b43_phy_write(dev, 0x001F, 0x1C00);
75 if (phy->rev <= 3)
76 b43_phy_write(dev, 0x002A,
77 (b43_phy_read(dev, 0x002A) & 0x00FF) | 0x0400);
78 else if (phy->rev == 5) {
79 b43_phy_write(dev, 0x002A,
80 (b43_phy_read(dev, 0x002A) & 0x00FF) | 0x1A00);
81 b43_phy_write(dev, 0x00CC, 0x2121);
82 }
83 if (phy->rev >= 3)
84 b43_phy_write(dev, 0x00BA, 0x3ED5);
85}
86
87static void b43_wa_divider(struct b43_wldev *dev)
88{
89 b43_phy_write(dev, 0x002B, b43_phy_read(dev, 0x002B) & ~0x0100);
90 b43_phy_write(dev, 0x008E, 0x58C1);
91}
92
93static void b43_wa_gt(struct b43_wldev *dev) /* Gain table. */
94{
95 if (dev->phy.rev <= 2) {
96 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 0, 15);
97 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 1, 31);
98 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 2, 42);
99 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 3, 48);
100 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 4, 58);
101 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 0, 19);
102 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 1, 19);
103 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 2, 19);
104 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 3, 19);
105 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 4, 21);
106 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 5, 21);
107 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 6, 25);
108 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 0, 3);
109 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 1, 3);
110 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 2, 7);
111 } else {
112 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 0, 19);
113 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 1, 19);
114 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 2, 19);
115 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 3, 19);
116 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 4, 21);
117 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 5, 21);
118 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 6, 25);
119 }
120}
121
122static void b43_wa_rssi_lt(struct b43_wldev *dev) /* RSSI lookup table */
123{
124 int i;
125
126 for (i = 0; i < 8; i++)
127 b43_ofdmtab_write16(dev, B43_OFDMTAB_RSSI, i, i + 8);
128 for (i = 8; i < 16; i++)
129 b43_ofdmtab_write16(dev, B43_OFDMTAB_RSSI, i, i - 8);
130}
131
132static void b43_wa_analog(struct b43_wldev *dev)
133{
134 struct b43_phy *phy = &dev->phy;
135
136 if (phy->analog > 2) {
137 if (phy->type == B43_PHYTYPE_A)
138 b43_phy_write(dev, B43_PHY_PWRDOWN, 0x1808);
139 else
140 b43_phy_write(dev, B43_PHY_PWRDOWN, 0x1000);
141 } else {
142 b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 3, 0x1044);
143 b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 4, 0x7201);
144 b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 6, 0x0040);
145 }
146}
147
148static void b43_wa_dac(struct b43_wldev *dev)
149{
150 if (dev->phy.analog == 1)
151 b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1,
152 (b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 1) & ~0x0034) | 0x0008);
153 else
154 b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1,
155 (b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 1) & ~0x0078) | 0x0010);
156}
157
158static void b43_wa_fft(struct b43_wldev *dev) /* Fine frequency table */
159{
160 int i;
161
162 if (dev->phy.type == B43_PHYTYPE_A)
163 for (i = 0; i < B43_TAB_FINEFREQA_SIZE; i++)
164 b43_ofdmtab_write16(dev, B43_OFDMTAB_DACRFPABB, i, b43_tab_finefreqa[i]);
165 else
166 for (i = 0; i < B43_TAB_FINEFREQG_SIZE; i++)
167 b43_ofdmtab_write16(dev, B43_OFDMTAB_DACRFPABB, i, b43_tab_finefreqg[i]);
168}
169
170static void b43_wa_nft(struct b43_wldev *dev) /* Noise figure table */
171{
172 struct b43_phy *phy = &dev->phy;
173 int i;
174
175 if (phy->type == B43_PHYTYPE_A) {
176 if (phy->rev == 2)
177 for (i = 0; i < B43_TAB_NOISEA2_SIZE; i++)
178 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noisea2[i]);
179 else
180 for (i = 0; i < B43_TAB_NOISEA3_SIZE; i++)
181 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noisea3[i]);
182 } else {
183 if (phy->rev == 1)
184 for (i = 0; i < B43_TAB_NOISEG1_SIZE; i++)
185 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noiseg1[i]);
186 else
187 for (i = 0; i < B43_TAB_NOISEG2_SIZE; i++)
188 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noiseg2[i]);
189 }
190}
191
192static void b43_wa_rt(struct b43_wldev *dev) /* Rotor table */
193{
194 int i;
195
196 for (i = 0; i < B43_TAB_ROTOR_SIZE; i++)
197 b43_ofdmtab_write32(dev, B43_OFDMTAB_ROTOR, i, b43_tab_rotor[i]);
198}
199
200static void b43_wa_nst(struct b43_wldev *dev) /* Noise scale table */
201{
202 struct b43_phy *phy = &dev->phy;
203 int i;
204
205 if (phy->type == B43_PHYTYPE_A) {
206 if (phy->rev <= 1)
207 for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
208 b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
209 i, 0);
210 else if (phy->rev == 2)
211 for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
212 b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
213 i, b43_tab_noisescalea2[i]);
214 else if (phy->rev == 3)
215 for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
216 b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
217 i, b43_tab_noisescalea3[i]);
218 else
219 for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
220 b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
221 i, b43_tab_noisescaleg3[i]);
222 } else {
223 if (phy->rev >= 6) {
224 if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN)
225 for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
226 b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
227 i, b43_tab_noisescaleg3[i]);
228 else
229 for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
230 b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
231 i, b43_tab_noisescaleg2[i]);
232 } else {
233 for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
234 b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
235 i, b43_tab_noisescaleg1[i]);
236 }
237 }
238}
239
240static void b43_wa_art(struct b43_wldev *dev) /* ADV retard table */
241{
242 int i;
243
244 for (i = 0; i < B43_TAB_RETARD_SIZE; i++)
245 b43_ofdmtab_write32(dev, B43_OFDMTAB_ADVRETARD,
246 i, b43_tab_retard[i]);
247}
248
249static void b43_wa_txlna_gain(struct b43_wldev *dev)
250{
251 b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 13, 0x0000);
252}
253
254static void b43_wa_crs_reset(struct b43_wldev *dev)
255{
256 b43_phy_write(dev, 0x002C, 0x0064);
257}
258
259static void b43_wa_2060txlna_gain(struct b43_wldev *dev)
260{
261 b43_hf_write(dev, b43_hf_read(dev) |
262 B43_HF_2060W);
263}
264
265static void b43_wa_lms(struct b43_wldev *dev)
266{
267 b43_phy_write(dev, 0x0055,
268 (b43_phy_read(dev, 0x0055) & 0xFFC0) | 0x0004);
269}
270
271static void b43_wa_mixedsignal(struct b43_wldev *dev)
272{
273 b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1, 3);
274}
275
276static void b43_wa_msst(struct b43_wldev *dev) /* Min sigma square table */
277{
278 struct b43_phy *phy = &dev->phy;
279 int i;
280 const u16 *tab;
281
282 if (phy->type == B43_PHYTYPE_A) {
283 tab = b43_tab_sigmasqr1;
284 } else if (phy->type == B43_PHYTYPE_G) {
285 tab = b43_tab_sigmasqr2;
286 } else {
287 B43_WARN_ON(1);
288 return;
289 }
290
291 for (i = 0; i < B43_TAB_SIGMASQR_SIZE; i++) {
292 b43_ofdmtab_write16(dev, B43_OFDMTAB_MINSIGSQ,
293 i, tab[i]);
294 }
295}
296
297static void b43_wa_iqadc(struct b43_wldev *dev)
298{
299 if (dev->phy.analog == 4)
300 b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 0,
301 b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 0) & ~0xF000);
302}
303
304static void b43_wa_crs_ed(struct b43_wldev *dev)
305{
306 struct b43_phy *phy = &dev->phy;
307
308 if (phy->rev == 1) {
309 b43_phy_write(dev, B43_PHY_CRSTHRES1, 0x4F19);
310 } else if (phy->rev == 2) {
311 b43_phy_write(dev, B43_PHY_CRSTHRES1_R1, 0x1861);
312 b43_phy_write(dev, B43_PHY_CRSTHRES2_R1, 0x1861);
313 b43_phy_write(dev, B43_PHY_ANTDWELL,
314 b43_phy_read(dev, B43_PHY_ANTDWELL)
315 | 0x0800);
316 } else {
317 b43_phy_write(dev, B43_PHY_CRSTHRES1_R1, 0x0098);
318 b43_phy_write(dev, B43_PHY_CRSTHRES2_R1, 0x0070);
319 b43_phy_write(dev, B43_PHY_OFDM(0xC9), 0x0080);
320 b43_phy_write(dev, B43_PHY_ANTDWELL,
321 b43_phy_read(dev, B43_PHY_ANTDWELL)
322 | 0x0800);
323 }
324}
325
326static void b43_wa_crs_thr(struct b43_wldev *dev)
327{
328 b43_phy_write(dev, B43_PHY_CRS0,
329 (b43_phy_read(dev, B43_PHY_CRS0) & ~0x03C0) | 0xD000);
330}
331
332static void b43_wa_crs_blank(struct b43_wldev *dev)
333{
334 b43_phy_write(dev, B43_PHY_OFDM(0x2C), 0x005A);
335}
336
337static void b43_wa_cck_shiftbits(struct b43_wldev *dev)
338{
339 b43_phy_write(dev, B43_PHY_CCKSHIFTBITS, 0x0026);
340}
341
342static void b43_wa_wrssi_offset(struct b43_wldev *dev)
343{
344 int i;
345
346 if (dev->phy.rev == 1) {
347 for (i = 0; i < 16; i++) {
348 b43_ofdmtab_write16(dev, B43_OFDMTAB_WRSSI_R1,
349 i, 0x0020);
350 }
351 } else {
352 for (i = 0; i < 32; i++) {
353 b43_ofdmtab_write16(dev, B43_OFDMTAB_WRSSI,
354 i, 0x0820);
355 }
356 }
357}
358
359static void b43_wa_txpuoff_rxpuon(struct b43_wldev *dev)
360{
361 b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_0F, 2, 15);
362 b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_0F, 3, 20);
363}
364
365static void b43_wa_altagc(struct b43_wldev *dev)
366{
367 struct b43_phy *phy = &dev->phy;
368
369 if (phy->rev == 1) {
370 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 254);
371 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 1, 13);
372 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 2, 19);
373 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 3, 25);
374 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 0, 0x2710);
375 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 1, 0x9B83);
376 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 2, 0x9B83);
377 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 3, 0x0F8D);
378 b43_phy_write(dev, B43_PHY_LMS, 4);
379 } else {
380 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0, 254);
381 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 1, 13);
382 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 2, 19);
383 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 3, 25);
384 }
385
386 b43_phy_write(dev, B43_PHY_CCKSHIFTBITS_WA,
387 (b43_phy_read(dev, B43_PHY_CCKSHIFTBITS_WA) & ~0xFF00) | 0x5700);
388 b43_phy_write(dev, B43_PHY_OFDM(0x1A),
389 (b43_phy_read(dev, B43_PHY_OFDM(0x1A)) & ~0x007F) | 0x000F);
390 b43_phy_write(dev, B43_PHY_OFDM(0x1A),
391 (b43_phy_read(dev, B43_PHY_OFDM(0x1A)) & ~0x3F80) | 0x2B80);
392 b43_phy_write(dev, B43_PHY_ANTWRSETT,
393 (b43_phy_read(dev, B43_PHY_ANTWRSETT) & 0xF0FF) | 0x0300);
394 b43_radio_write16(dev, 0x7A,
395 b43_radio_read16(dev, 0x7A) | 0x0008);
396 b43_phy_write(dev, B43_PHY_N1P1GAIN,
397 (b43_phy_read(dev, B43_PHY_N1P1GAIN) & ~0x000F) | 0x0008);
398 b43_phy_write(dev, B43_PHY_P1P2GAIN,
399 (b43_phy_read(dev, B43_PHY_P1P2GAIN) & ~0x0F00) | 0x0600);
400 b43_phy_write(dev, B43_PHY_N1N2GAIN,
401 (b43_phy_read(dev, B43_PHY_N1N2GAIN) & ~0x0F00) | 0x0700);
402 b43_phy_write(dev, B43_PHY_N1P1GAIN,
403 (b43_phy_read(dev, B43_PHY_N1P1GAIN) & ~0x0F00) | 0x0100);
404 if (phy->rev == 1) {
405 b43_phy_write(dev, B43_PHY_N1N2GAIN,
406 (b43_phy_read(dev, B43_PHY_N1N2GAIN)
407 & ~0x000F) | 0x0007);
408 }
409 b43_phy_write(dev, B43_PHY_OFDM(0x88),
410 (b43_phy_read(dev, B43_PHY_OFDM(0x88)) & ~0x00FF) | 0x001C);
411 b43_phy_write(dev, B43_PHY_OFDM(0x88),
412 (b43_phy_read(dev, B43_PHY_OFDM(0x88)) & ~0x3F00) | 0x0200);
413 b43_phy_write(dev, B43_PHY_OFDM(0x96),
414 (b43_phy_read(dev, B43_PHY_OFDM(0x96)) & ~0x00FF) | 0x001C);
415 b43_phy_write(dev, B43_PHY_OFDM(0x89),
416 (b43_phy_read(dev, B43_PHY_OFDM(0x89)) & ~0x00FF) | 0x0020);
417 b43_phy_write(dev, B43_PHY_OFDM(0x89),
418 (b43_phy_read(dev, B43_PHY_OFDM(0x89)) & ~0x3F00) | 0x0200);
419 b43_phy_write(dev, B43_PHY_OFDM(0x82),
420 (b43_phy_read(dev, B43_PHY_OFDM(0x82)) & ~0x00FF) | 0x002E);
421 b43_phy_write(dev, B43_PHY_OFDM(0x96),
422 (b43_phy_read(dev, B43_PHY_OFDM(0x96)) & ~0xFF00) | 0x1A00);
423 b43_phy_write(dev, B43_PHY_OFDM(0x81),
424 (b43_phy_read(dev, B43_PHY_OFDM(0x81)) & ~0x00FF) | 0x0028);
425 b43_phy_write(dev, B43_PHY_OFDM(0x81),
426 (b43_phy_read(dev, B43_PHY_OFDM(0x81)) & ~0xFF00) | 0x2C00);
427 if (phy->rev == 1) {
428 b43_phy_write(dev, B43_PHY_PEAK_COUNT, 0x092B);
429 b43_phy_write(dev, B43_PHY_OFDM(0x1B),
430 (b43_phy_read(dev, B43_PHY_OFDM(0x1B)) & ~0x001E) | 0x0002);
431 } else {
432 b43_phy_write(dev, B43_PHY_OFDM(0x1B),
433 b43_phy_read(dev, B43_PHY_OFDM(0x1B)) & ~0x001E);
434 b43_phy_write(dev, B43_PHY_OFDM(0x1F), 0x287A);
435 b43_phy_write(dev, B43_PHY_LPFGAINCTL,
436 (b43_phy_read(dev, B43_PHY_LPFGAINCTL) & ~0x000F) | 0x0004);
437 if (phy->rev >= 6) {
438 b43_phy_write(dev, B43_PHY_OFDM(0x22), 0x287A);
439 b43_phy_write(dev, B43_PHY_LPFGAINCTL,
440 (b43_phy_read(dev, B43_PHY_LPFGAINCTL) & ~0xF000) | 0x3000);
441 }
442 }
443 b43_phy_write(dev, B43_PHY_DIVSRCHIDX,
444 (b43_phy_read(dev, B43_PHY_DIVSRCHIDX) & 0x7F7F) | 0x7874);
445 b43_phy_write(dev, B43_PHY_OFDM(0x8E), 0x1C00);
446 if (phy->rev == 1) {
447 b43_phy_write(dev, B43_PHY_DIVP1P2GAIN,
448 (b43_phy_read(dev, B43_PHY_DIVP1P2GAIN) & ~0x0F00) | 0x0600);
449 b43_phy_write(dev, B43_PHY_OFDM(0x8B), 0x005E);
450 b43_phy_write(dev, B43_PHY_ANTWRSETT,
451 (b43_phy_read(dev, B43_PHY_ANTWRSETT) & ~0x00FF) | 0x001E);
452 b43_phy_write(dev, B43_PHY_OFDM(0x8D), 0x0002);
453 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 0, 0);
454 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 1, 7);
455 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 2, 16);
456 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 3, 28);
457 } else {
458 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 0, 0);
459 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 1, 7);
460 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 2, 16);
461 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 3, 28);
462 }
463 if (phy->rev >= 6) {
464 b43_phy_write(dev, B43_PHY_OFDM(0x26),
465 b43_phy_read(dev, B43_PHY_OFDM(0x26)) & ~0x0003);
466 b43_phy_write(dev, B43_PHY_OFDM(0x26),
467 b43_phy_read(dev, B43_PHY_OFDM(0x26)) & ~0x1000);
468 }
469}
470
471static void b43_wa_tr_ltov(struct b43_wldev *dev) /* TR Lookup Table Original Values */
472{
473 b43_gtab_write(dev, B43_GTAB_ORIGTR, 0, 0xC480);
474}
475
476static void b43_wa_cpll_nonpilot(struct b43_wldev *dev)
477{
478 b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_11, 0, 0);
479 b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_11, 1, 0);
480}
481
482static void b43_wa_rssi_adc(struct b43_wldev *dev)
483{
484 if (dev->phy.analog == 4)
485 b43_phy_write(dev, 0x00DC, 0x7454);
486}
487
488static void b43_wa_boards_a(struct b43_wldev *dev)
489{
490 struct ssb_bus *bus = dev->dev->bus;
491
492 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
493 bus->boardinfo.type == SSB_BOARD_BU4306 &&
494 bus->boardinfo.rev < 0x30) {
495 b43_phy_write(dev, 0x0010, 0xE000);
496 b43_phy_write(dev, 0x0013, 0x0140);
497 b43_phy_write(dev, 0x0014, 0x0280);
498 } else {
499 if (bus->boardinfo.type == SSB_BOARD_MP4318 &&
500 bus->boardinfo.rev < 0x20) {
501 b43_phy_write(dev, 0x0013, 0x0210);
502 b43_phy_write(dev, 0x0014, 0x0840);
503 } else {
504 b43_phy_write(dev, 0x0013, 0x0140);
505 b43_phy_write(dev, 0x0014, 0x0280);
506 }
507 if (dev->phy.rev <= 4)
508 b43_phy_write(dev, 0x0010, 0xE000);
509 else
510 b43_phy_write(dev, 0x0010, 0x2000);
511 b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 1, 0x0039);
512 b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_APHY, 7, 0x0040);
513 }
514}
515
516static void b43_wa_boards_g(struct b43_wldev *dev)
517{
518 struct ssb_bus *bus = dev->dev->bus;
519 struct b43_phy *phy = &dev->phy;
520
521 if (bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM ||
522 bus->boardinfo.type != SSB_BOARD_BU4306 ||
523 bus->boardinfo.rev != 0x17) {
524 if (phy->rev < 2) {
525 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 1, 0x0002);
526 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 2, 0x0001);
527 } else {
528 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 1, 0x0002);
529 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 2, 0x0001);
530 if ((bus->sprom.r1.boardflags_lo & B43_BFL_EXTLNA) &&
531 (phy->rev >= 7)) {
532 b43_phy_write(dev, B43_PHY_EXTG(0x11),
533 b43_phy_read(dev, B43_PHY_EXTG(0x11)) & 0xF7FF);
534 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0020, 0x0001);
535 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0021, 0x0001);
536 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0022, 0x0001);
537 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0023, 0x0000);
538 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0000, 0x0000);
539 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0003, 0x0002);
540 }
541 }
542 }
543 if (bus->sprom.r1.boardflags_lo & B43_BFL_FEM) {
544 b43_phy_write(dev, B43_PHY_GTABCTL, 0x3120);
545 b43_phy_write(dev, B43_PHY_GTABDATA, 0xC480);
546 }
547}
548
549void b43_wa_all(struct b43_wldev *dev)
550{
551 struct b43_phy *phy = &dev->phy;
552
553 if (phy->type == B43_PHYTYPE_A) {
554 switch (phy->rev) {
555 case 2:
556 b43_wa_papd(dev);
557 b43_wa_auxclipthr(dev);
558 b43_wa_afcdac(dev);
559 b43_wa_txdc_offset(dev);
560 b43_wa_initgains(dev);
561 b43_wa_divider(dev);
562 b43_wa_gt(dev);
563 b43_wa_rssi_lt(dev);
564 b43_wa_analog(dev);
565 b43_wa_dac(dev);
566 b43_wa_fft(dev);
567 b43_wa_nft(dev);
568 b43_wa_rt(dev);
569 b43_wa_nst(dev);
570 b43_wa_art(dev);
571 b43_wa_txlna_gain(dev);
572 b43_wa_crs_reset(dev);
573 b43_wa_2060txlna_gain(dev);
574 b43_wa_lms(dev);
575 break;
576 case 3:
577 b43_wa_papd(dev);
578 b43_wa_mixedsignal(dev);
579 b43_wa_rssi_lt(dev);
580 b43_wa_txdc_offset(dev);
581 b43_wa_initgains(dev);
582 b43_wa_dac(dev);
583 b43_wa_nft(dev);
584 b43_wa_nst(dev);
585 b43_wa_msst(dev);
586 b43_wa_analog(dev);
587 b43_wa_gt(dev);
588 b43_wa_txpuoff_rxpuon(dev);
589 b43_wa_txlna_gain(dev);
590 break;
591 case 5:
592 b43_wa_iqadc(dev);
593 case 6:
594 b43_wa_papd(dev);
595 b43_wa_rssi_lt(dev);
596 b43_wa_txdc_offset(dev);
597 b43_wa_initgains(dev);
598 b43_wa_dac(dev);
599 b43_wa_nft(dev);
600 b43_wa_nst(dev);
601 b43_wa_msst(dev);
602 b43_wa_analog(dev);
603 b43_wa_gt(dev);
604 b43_wa_txpuoff_rxpuon(dev);
605 b43_wa_txlna_gain(dev);
606 break;
607 case 7:
608 b43_wa_iqadc(dev);
609 b43_wa_papd(dev);
610 b43_wa_rssi_lt(dev);
611 b43_wa_txdc_offset(dev);
612 b43_wa_initgains(dev);
613 b43_wa_dac(dev);
614 b43_wa_nft(dev);
615 b43_wa_nst(dev);
616 b43_wa_msst(dev);
617 b43_wa_analog(dev);
618 b43_wa_gt(dev);
619 b43_wa_txpuoff_rxpuon(dev);
620 b43_wa_txlna_gain(dev);
621 b43_wa_rssi_adc(dev);
622 default:
623 B43_WARN_ON(1);
624 }
625 b43_wa_boards_a(dev);
626 } else if (phy->type == B43_PHYTYPE_G) {
627 switch (phy->rev) {
628 case 1://XXX review rev1
629 b43_wa_crs_ed(dev);
630 b43_wa_crs_thr(dev);
631 b43_wa_crs_blank(dev);
632 b43_wa_cck_shiftbits(dev);
633 b43_wa_fft(dev);
634 b43_wa_nft(dev);
635 b43_wa_rt(dev);
636 b43_wa_nst(dev);
637 b43_wa_art(dev);
638 b43_wa_wrssi_offset(dev);
639 b43_wa_altagc(dev);
640 break;
641 case 2:
642 case 6:
643 case 7:
644 case 8:
645 b43_wa_tr_ltov(dev);
646 b43_wa_crs_ed(dev);
647 b43_wa_rssi_lt(dev);
648 b43_wa_nft(dev);
649 b43_wa_nst(dev);
650 b43_wa_msst(dev);
651 b43_wa_wrssi_offset(dev);
652 b43_wa_altagc(dev);
653 b43_wa_analog(dev);
654 b43_wa_txpuoff_rxpuon(dev);
655 break;
656 default:
657 B43_WARN_ON(1);
658 }
659 b43_wa_boards_g(dev);
660 } else { /* No N PHY support so far */
661 B43_WARN_ON(1);
662 }
663
664 b43_wa_cpll_nonpilot(dev);
665}