blob: c729e6988bbb17db928de1cd903682cfc3dc2802 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04004 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020042#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050043#include <linux/device.h>
Tejun Heoedc93052007-10-25 14:59:16 +090044#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050046#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <linux/libata.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
49#define DRV_NAME "ahci"
Tejun Heo7d50b602007-09-23 13:19:54 +090050#define DRV_VERSION "3.0"
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
Tejun Heoa22e6442008-03-10 10:25:25 +090052static int ahci_skip_host_reset;
53module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
Kristen Carlson Accardi31556592007-10-25 01:33:26 -040056static int ahci_enable_alpm(struct ata_port *ap,
57 enum link_pm policy);
58static void ahci_disable_alpm(struct ata_port *ap);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -070059static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
60static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
61 size_t size);
62static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
63 ssize_t size);
64#define MAX_SLOTS 8
Linus Torvalds1da177e2005-04-16 15:20:36 -070065
66enum {
67 AHCI_PCI_BAR = 5,
Tejun Heo648a88b2006-11-09 15:08:40 +090068 AHCI_MAX_PORTS = 32,
Linus Torvalds1da177e2005-04-16 15:20:36 -070069 AHCI_MAX_SG = 168, /* hardware max is 64K */
70 AHCI_DMA_BOUNDARY = 0xffffffff,
Tejun Heo12fad3f2006-05-15 21:03:55 +090071 AHCI_MAX_CMDS = 32,
Tejun Heodd410ff2006-05-15 21:03:50 +090072 AHCI_CMD_SZ = 32,
Tejun Heo12fad3f2006-05-15 21:03:55 +090073 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
Linus Torvalds1da177e2005-04-16 15:20:36 -070074 AHCI_RX_FIS_SZ = 256,
Jeff Garzika0ea7322005-06-04 01:13:15 -040075 AHCI_CMD_TBL_CDB = 0x40,
Tejun Heodd410ff2006-05-15 21:03:50 +090076 AHCI_CMD_TBL_HDR_SZ = 0x80,
77 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
78 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
79 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
Linus Torvalds1da177e2005-04-16 15:20:36 -070080 AHCI_RX_FIS_SZ,
81 AHCI_IRQ_ON_SG = (1 << 31),
82 AHCI_CMD_ATAPI = (1 << 5),
83 AHCI_CMD_WRITE = (1 << 6),
Tejun Heo4b10e552006-03-12 11:25:27 +090084 AHCI_CMD_PREFETCH = (1 << 7),
Tejun Heo22b49982006-01-23 21:38:44 +090085 AHCI_CMD_RESET = (1 << 8),
86 AHCI_CMD_CLR_BUSY = (1 << 10),
Linus Torvalds1da177e2005-04-16 15:20:36 -070087
88 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
Tejun Heo0291f952007-01-25 19:16:28 +090089 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
Tejun Heo78cd52d2006-05-15 20:58:29 +090090 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
Linus Torvalds1da177e2005-04-16 15:20:36 -070091
92 board_ahci = 0,
Tejun Heo7a234af2007-09-03 12:44:57 +090093 board_ahci_vt8251 = 1,
94 board_ahci_ign_iferr = 2,
95 board_ahci_sb600 = 3,
96 board_ahci_mv = 4,
Shane Huange39fc8c2008-02-22 05:00:31 -080097 board_ahci_sb700 = 5,
Tejun Heoe297d992008-06-10 00:13:04 +090098 board_ahci_mcp65 = 6,
Tejun Heo9a3b1032008-06-18 20:56:58 -040099 board_ahci_nopmp = 7,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100
101 /* global controller registers */
102 HOST_CAP = 0x00, /* host capabilities */
103 HOST_CTL = 0x04, /* global host control */
104 HOST_IRQ_STAT = 0x08, /* interrupt status */
105 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
106 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700107 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
108 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109
110 /* HOST_CTL bits */
111 HOST_RESET = (1 << 0), /* reset controller; self-clear */
112 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
113 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
114
115 /* HOST_CAP bits */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700116 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900117 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
Tejun Heo7d50b602007-09-23 13:19:54 +0900118 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
Tejun Heo22b49982006-01-23 21:38:44 +0900119 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400120 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900121 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900122 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
Tejun Heo979db802006-05-15 21:03:52 +0900123 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
Tejun Heodd410ff2006-05-15 21:03:50 +0900124 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125
126 /* registers for each SATA port */
127 PORT_LST_ADDR = 0x00, /* command list DMA addr */
128 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
129 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
130 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
131 PORT_IRQ_STAT = 0x10, /* interrupt status */
132 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
133 PORT_CMD = 0x18, /* port command */
134 PORT_TFDATA = 0x20, /* taskfile data */
135 PORT_SIG = 0x24, /* device TF signature */
136 PORT_CMD_ISSUE = 0x38, /* command issue */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
138 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
139 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
140 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900141 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142
143 /* PORT_IRQ_{STAT,MASK} bits */
144 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
145 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
146 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
147 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
148 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
149 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
150 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
151 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
152
153 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
154 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
155 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
156 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
157 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
158 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
159 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
160 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
161 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
162
Tejun Heo78cd52d2006-05-15 20:58:29 +0900163 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
164 PORT_IRQ_IF_ERR |
165 PORT_IRQ_CONNECT |
Tejun Heo42969712006-05-31 18:28:18 +0900166 PORT_IRQ_PHYRDY |
Tejun Heo7d50b602007-09-23 13:19:54 +0900167 PORT_IRQ_UNK_FIS |
168 PORT_IRQ_BAD_PMP,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900169 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
170 PORT_IRQ_TF_ERR |
171 PORT_IRQ_HBUS_DATA_ERR,
172 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
173 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
174 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175
176 /* PORT_CMD bits */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400177 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
178 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
Jeff Garzik02eaa662005-11-12 01:32:19 -0500179 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
Tejun Heo7d50b602007-09-23 13:19:54 +0900180 PORT_CMD_PMP = (1 << 17), /* PMP attached */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
182 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
183 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
Tejun Heo22b49982006-01-23 21:38:44 +0900184 PORT_CMD_CLO = (1 << 3), /* Command list override */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
186 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
187 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
188
Tejun Heo0be0aa92006-07-26 15:59:26 +0900189 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700190 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
191 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
192 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
Jeff Garzik4b0060f2005-06-04 00:50:22 -0400193
Tejun Heo417a1a62007-09-23 13:19:55 +0900194 /* hpriv->flags bits */
195 AHCI_HFLAG_NO_NCQ = (1 << 0),
196 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
197 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
198 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
199 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
200 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
Tejun Heo6949b912007-09-23 13:19:55 +0900201 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400202 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
Jeff Garzika8785392008-02-28 15:43:48 -0500203 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
Tejun Heoe297d992008-06-10 00:13:04 +0900204 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
Tejun Heo417a1a62007-09-23 13:19:55 +0900205
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200206 /* ap->flags bits */
Tejun Heo1188c0d2007-04-23 02:41:05 +0900207
208 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
209 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400210 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
211 ATA_FLAG_IPM,
Tejun Heoc4f77922007-12-06 15:09:43 +0900212
213 ICH_MAP = 0x90, /* ICH MAP register */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700214
215 /* em_ctl bits */
216 EM_CTL_RST = (1 << 9), /* Reset */
217 EM_CTL_TM = (1 << 8), /* Transmit Message */
218 EM_CTL_ALHD = (1 << 26), /* Activity LED */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219};
220
221struct ahci_cmd_hdr {
Al Viro4ca4e432007-12-30 09:32:22 +0000222 __le32 opts;
223 __le32 status;
224 __le32 tbl_addr;
225 __le32 tbl_addr_hi;
226 __le32 reserved[4];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227};
228
229struct ahci_sg {
Al Viro4ca4e432007-12-30 09:32:22 +0000230 __le32 addr;
231 __le32 addr_hi;
232 __le32 reserved;
233 __le32 flags_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234};
235
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700236struct ahci_em_priv {
237 enum sw_activity blink_policy;
238 struct timer_list timer;
239 unsigned long saved_activity;
240 unsigned long activity;
241 unsigned long led_state;
242};
243
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244struct ahci_host_priv {
Tejun Heo417a1a62007-09-23 13:19:55 +0900245 unsigned int flags; /* AHCI_HFLAG_* */
Tejun Heod447df12007-03-18 22:15:33 +0900246 u32 cap; /* cap to use */
247 u32 port_map; /* port map to use */
248 u32 saved_cap; /* saved initial cap */
249 u32 saved_port_map; /* saved initial port_map */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700250 u32 em_loc; /* enclosure management location */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251};
252
253struct ahci_port_priv {
Tejun Heo7d50b602007-09-23 13:19:54 +0900254 struct ata_link *active_link;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700255 struct ahci_cmd_hdr *cmd_slot;
256 dma_addr_t cmd_slot_dma;
257 void *cmd_tbl;
258 dma_addr_t cmd_tbl_dma;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259 void *rx_fis;
260 dma_addr_t rx_fis_dma;
Tejun Heo0291f952007-01-25 19:16:28 +0900261 /* for NCQ spurious interrupt analysis */
Tejun Heo0291f952007-01-25 19:16:28 +0900262 unsigned int ncq_saw_d2h:1;
263 unsigned int ncq_saw_dmas:1;
Tejun Heoafb2d552007-02-27 13:24:19 +0900264 unsigned int ncq_saw_sdb:1;
Kristen Carlson Accardia7384922007-08-09 14:23:41 -0700265 u32 intr_mask; /* interrupts to enable */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700266 struct ahci_em_priv em_priv[MAX_SLOTS];/* enclosure management info
267 * per PM slot */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268};
269
Tejun Heoda3dbb12007-07-16 14:29:40 +0900270static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
271static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400272static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900273static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
Tejun Heo4c9bf4e2008-04-07 22:47:20 +0900274static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275static int ahci_port_start(struct ata_port *ap);
276static void ahci_port_stop(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700277static void ahci_qc_prep(struct ata_queued_cmd *qc);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900278static void ahci_freeze(struct ata_port *ap);
279static void ahci_thaw(struct ata_port *ap);
Tejun Heo7d50b602007-09-23 13:19:54 +0900280static void ahci_pmp_attach(struct ata_port *ap);
281static void ahci_pmp_detach(struct ata_port *ap);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900282static int ahci_softreset(struct ata_link *link, unsigned int *class,
283 unsigned long deadline);
Shane Huangbd172432008-06-10 15:52:04 +0800284static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
285 unsigned long deadline);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900286static int ahci_hardreset(struct ata_link *link, unsigned int *class,
287 unsigned long deadline);
288static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
289 unsigned long deadline);
290static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
291 unsigned long deadline);
292static void ahci_postreset(struct ata_link *link, unsigned int *class);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900293static void ahci_error_handler(struct ata_port *ap);
294static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -0400295static int ahci_port_resume(struct ata_port *ap);
Jeff Garzika8785392008-02-28 15:43:48 -0500296static void ahci_dev_config(struct ata_device *dev);
Jeff Garzikdab632e2007-05-28 08:33:01 -0400297static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
298static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
299 u32 opts);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900300#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900301static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
Tejun Heoc1332872006-07-26 15:59:26 +0900302static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
303static int ahci_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900304#endif
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700305static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
306static ssize_t ahci_activity_store(struct ata_device *dev,
307 enum sw_activity val);
308static void ahci_init_sw_activity(struct ata_link *link);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700309
Tony Jonesee959b02008-02-22 00:13:36 +0100310static struct device_attribute *ahci_shost_attrs[] = {
311 &dev_attr_link_power_management_policy,
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700312 &dev_attr_em_message_type,
313 &dev_attr_em_message,
314 NULL
315};
316
317static struct device_attribute *ahci_sdev_attrs[] = {
318 &dev_attr_sw_activity,
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400319 NULL
320};
321
Jeff Garzik193515d2005-11-07 00:59:37 -0500322static struct scsi_host_template ahci_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900323 ATA_NCQ_SHT(DRV_NAME),
Tejun Heo12fad3f2006-05-15 21:03:55 +0900324 .can_queue = AHCI_MAX_CMDS - 1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325 .sg_tablesize = AHCI_MAX_SG,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326 .dma_boundary = AHCI_DMA_BOUNDARY,
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400327 .shost_attrs = ahci_shost_attrs,
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700328 .sdev_attrs = ahci_sdev_attrs,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700329};
330
Tejun Heo029cfd62008-03-25 12:22:49 +0900331static struct ata_port_operations ahci_ops = {
332 .inherits = &sata_pmp_port_ops,
333
Tejun Heo7d50b602007-09-23 13:19:54 +0900334 .qc_defer = sata_pmp_qc_defer_cmd_switch,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335 .qc_prep = ahci_qc_prep,
336 .qc_issue = ahci_qc_issue,
Tejun Heo4c9bf4e2008-04-07 22:47:20 +0900337 .qc_fill_rtf = ahci_qc_fill_rtf,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338
Tejun Heo78cd52d2006-05-15 20:58:29 +0900339 .freeze = ahci_freeze,
340 .thaw = ahci_thaw,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900341 .softreset = ahci_softreset,
342 .hardreset = ahci_hardreset,
343 .postreset = ahci_postreset,
Tejun Heo071f44b2008-04-07 22:47:22 +0900344 .pmp_softreset = ahci_softreset,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900345 .error_handler = ahci_error_handler,
346 .post_internal_cmd = ahci_post_internal_cmd,
Tejun Heo029cfd62008-03-25 12:22:49 +0900347 .dev_config = ahci_dev_config,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900348
Tejun Heo029cfd62008-03-25 12:22:49 +0900349 .scr_read = ahci_scr_read,
350 .scr_write = ahci_scr_write,
Tejun Heo7d50b602007-09-23 13:19:54 +0900351 .pmp_attach = ahci_pmp_attach,
352 .pmp_detach = ahci_pmp_detach,
Tejun Heo7d50b602007-09-23 13:19:54 +0900353
Tejun Heo029cfd62008-03-25 12:22:49 +0900354 .enable_pm = ahci_enable_alpm,
355 .disable_pm = ahci_disable_alpm,
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700356 .em_show = ahci_led_show,
357 .em_store = ahci_led_store,
358 .sw_activity_show = ahci_activity_show,
359 .sw_activity_store = ahci_activity_store,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900360#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900361 .port_suspend = ahci_port_suspend,
362 .port_resume = ahci_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900363#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364 .port_start = ahci_port_start,
365 .port_stop = ahci_port_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366};
367
Tejun Heo029cfd62008-03-25 12:22:49 +0900368static struct ata_port_operations ahci_vt8251_ops = {
369 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900370 .hardreset = ahci_vt8251_hardreset,
Tejun Heoad616ff2006-11-01 18:00:24 +0900371};
372
Tejun Heo029cfd62008-03-25 12:22:49 +0900373static struct ata_port_operations ahci_p5wdh_ops = {
374 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900375 .hardreset = ahci_p5wdh_hardreset,
Tejun Heoedc93052007-10-25 14:59:16 +0900376};
377
Shane Huangbd172432008-06-10 15:52:04 +0800378static struct ata_port_operations ahci_sb600_ops = {
379 .inherits = &ahci_ops,
380 .softreset = ahci_sb600_softreset,
381 .pmp_softreset = ahci_sb600_softreset,
382};
383
Tejun Heo417a1a62007-09-23 13:19:55 +0900384#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
385
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100386static const struct ata_port_info ahci_port_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387 /* board_ahci */
388 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900389 .flags = AHCI_FLAG_COMMON,
Brett Russ7da79312005-09-01 21:53:34 -0400390 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400391 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392 .port_ops = &ahci_ops,
393 },
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200394 /* board_ahci_vt8251 */
395 {
Tejun Heo6949b912007-09-23 13:19:55 +0900396 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
Tejun Heo417a1a62007-09-23 13:19:55 +0900397 .flags = AHCI_FLAG_COMMON,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200398 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400399 .udma_mask = ATA_UDMA6,
Tejun Heoad616ff2006-11-01 18:00:24 +0900400 .port_ops = &ahci_vt8251_ops,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200401 },
Tejun Heo41669552006-11-29 11:33:14 +0900402 /* board_ahci_ign_iferr */
403 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900404 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
405 .flags = AHCI_FLAG_COMMON,
Tejun Heo41669552006-11-29 11:33:14 +0900406 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400407 .udma_mask = ATA_UDMA6,
Tejun Heo41669552006-11-29 11:33:14 +0900408 .port_ops = &ahci_ops,
409 },
Conke Hu55a61602007-03-27 18:33:05 +0800410 /* board_ahci_sb600 */
411 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900412 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
Tejun Heo22b5e7a2008-04-29 16:09:22 +0900413 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
Shane Huangbd172432008-06-10 15:52:04 +0800414 AHCI_HFLAG_SECT255),
Tejun Heo417a1a62007-09-23 13:19:55 +0900415 .flags = AHCI_FLAG_COMMON,
Conke Hu55a61602007-03-27 18:33:05 +0800416 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400417 .udma_mask = ATA_UDMA6,
Shane Huangbd172432008-06-10 15:52:04 +0800418 .port_ops = &ahci_sb600_ops,
Conke Hu55a61602007-03-27 18:33:05 +0800419 },
Jeff Garzikcd70c262007-07-08 02:29:42 -0400420 /* board_ahci_mv */
421 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900422 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
423 AHCI_HFLAG_MV_PATA),
Jeff Garzikcd70c262007-07-08 02:29:42 -0400424 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Tejun Heo417a1a62007-09-23 13:19:55 +0900425 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
Jeff Garzikcd70c262007-07-08 02:29:42 -0400426 .pio_mask = 0x1f, /* pio0-4 */
427 .udma_mask = ATA_UDMA6,
428 .port_ops = &ahci_ops,
429 },
Shane Huange39fc8c2008-02-22 05:00:31 -0800430 /* board_ahci_sb700 */
431 {
Shane Huangbd172432008-06-10 15:52:04 +0800432 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
Shane Huange39fc8c2008-02-22 05:00:31 -0800433 .flags = AHCI_FLAG_COMMON,
Shane Huange39fc8c2008-02-22 05:00:31 -0800434 .pio_mask = 0x1f, /* pio0-4 */
435 .udma_mask = ATA_UDMA6,
Shane Huangbd172432008-06-10 15:52:04 +0800436 .port_ops = &ahci_sb600_ops,
Shane Huange39fc8c2008-02-22 05:00:31 -0800437 },
Tejun Heoe297d992008-06-10 00:13:04 +0900438 /* board_ahci_mcp65 */
439 {
440 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
441 .flags = AHCI_FLAG_COMMON,
442 .pio_mask = 0x1f, /* pio0-4 */
443 .udma_mask = ATA_UDMA6,
444 .port_ops = &ahci_ops,
445 },
Tejun Heo9a3b1032008-06-18 20:56:58 -0400446 /* board_ahci_nopmp */
447 {
448 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
449 .flags = AHCI_FLAG_COMMON,
450 .pio_mask = 0x1f, /* pio0-4 */
451 .udma_mask = ATA_UDMA6,
452 .port_ops = &ahci_ops,
453 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454};
455
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500456static const struct pci_device_id ahci_pci_tbl[] = {
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400457 /* Intel */
Jeff Garzik54bb3a92006-09-27 22:20:11 -0400458 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
459 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
460 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
461 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
462 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
Tejun Heo82490c02007-01-23 15:13:39 +0900463 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
Jeff Garzik54bb3a92006-09-27 22:20:11 -0400464 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
465 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
466 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
467 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
Tejun Heo7a234af2007-09-03 12:44:57 +0900468 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
469 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
470 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
471 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
472 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
473 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
474 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
475 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
476 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
477 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
478 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
479 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
480 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
481 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
482 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
483 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
484 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
Jason Gastond4155e62007-09-20 17:35:00 -0400485 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
486 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800487 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
488 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700489 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
490 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400491
Tejun Heoe34bb372007-02-26 20:24:03 +0900492 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
493 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
494 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400495
496 /* ATI */
Conke Huc65ec1c2007-04-11 18:23:14 +0800497 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
Shane Huange39fc8c2008-02-22 05:00:31 -0800498 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
499 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
500 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
501 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
502 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
503 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400504
505 /* VIA */
Jeff Garzik54bb3a92006-09-27 22:20:11 -0400506 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
Tejun Heobf335542007-04-11 17:27:14 +0900507 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400508
509 /* NVIDIA */
Tejun Heoe297d992008-06-10 00:13:04 +0900510 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
511 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
512 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
513 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
514 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
515 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
516 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
517 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
Peer Chen6fbf5ba2006-12-20 14:18:00 -0500518 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
519 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
520 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
521 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
Peer Chen895663c2006-11-02 17:59:46 -0500522 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
523 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
524 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
525 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
526 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
527 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
528 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
529 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
Peer Chen0522b282007-06-07 18:05:12 +0800530 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
531 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
532 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
533 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
534 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
535 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
536 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
537 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
538 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
539 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
540 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
541 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
542 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
543 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
544 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
545 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
546 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
547 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
548 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
549 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
550 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
551 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
552 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
553 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
peerchen6ba86952007-12-03 22:20:37 +0800554 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
555 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
556 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
557 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
Peer Chen71008192007-09-24 10:16:25 +0800558 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
559 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
560 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
561 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
562 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
563 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
564 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
565 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
peerchen70d562c2008-03-06 21:22:41 +0800566 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
567 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
568 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
569 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
570 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
571 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
572 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
573 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
peerchen3072c372008-05-19 14:44:57 +0800574 { PCI_VDEVICE(NVIDIA, 0x0bc4), board_ahci }, /* MCP7B */
575 { PCI_VDEVICE(NVIDIA, 0x0bc5), board_ahci }, /* MCP7B */
576 { PCI_VDEVICE(NVIDIA, 0x0bc6), board_ahci }, /* MCP7B */
577 { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400578
Jeff Garzik95916ed2006-07-29 04:10:14 -0400579 /* SiS */
Tejun Heo20e2de42008-08-01 12:51:43 +0900580 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
581 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
582 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
Jeff Garzik95916ed2006-07-29 04:10:14 -0400583
Jeff Garzikcd70c262007-07-08 02:29:42 -0400584 /* Marvell */
585 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100586 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
Jeff Garzikcd70c262007-07-08 02:29:42 -0400587
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500588 /* Generic, PCI class code for AHCI */
589 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Conke Huc9f89472007-01-09 05:32:51 -0500590 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500591
Linus Torvalds1da177e2005-04-16 15:20:36 -0700592 { } /* terminate list */
593};
594
595
596static struct pci_driver ahci_pci_driver = {
597 .name = DRV_NAME,
598 .id_table = ahci_pci_tbl,
599 .probe = ahci_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900600 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900601#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900602 .suspend = ahci_pci_device_suspend,
603 .resume = ahci_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900604#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700605};
606
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700607static int ahci_em_messages = 1;
608module_param(ahci_em_messages, int, 0444);
609/* add other LED protocol types when they become supported */
610MODULE_PARM_DESC(ahci_em_messages,
611 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700612
Tejun Heo98fa4b62006-11-02 12:17:23 +0900613static inline int ahci_nr_ports(u32 cap)
614{
615 return (cap & 0x1f) + 1;
616}
617
Jeff Garzikdab632e2007-05-28 08:33:01 -0400618static inline void __iomem *__ahci_port_base(struct ata_host *host,
619 unsigned int port_no)
620{
621 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
622
623 return mmio + 0x100 + (port_no * 0x80);
624}
625
Tejun Heo4447d352007-04-17 23:44:08 +0900626static inline void __iomem *ahci_port_base(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627{
Jeff Garzikdab632e2007-05-28 08:33:01 -0400628 return __ahci_port_base(ap->host, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700629}
630
Tejun Heob710a1f2008-01-05 23:11:57 +0900631static void ahci_enable_ahci(void __iomem *mmio)
632{
Tejun Heo15fe9822008-04-23 20:52:58 +0900633 int i;
Tejun Heob710a1f2008-01-05 23:11:57 +0900634 u32 tmp;
635
636 /* turn on AHCI_EN */
637 tmp = readl(mmio + HOST_CTL);
Tejun Heo15fe9822008-04-23 20:52:58 +0900638 if (tmp & HOST_AHCI_EN)
639 return;
640
641 /* Some controllers need AHCI_EN to be written multiple times.
642 * Try a few times before giving up.
643 */
644 for (i = 0; i < 5; i++) {
Tejun Heob710a1f2008-01-05 23:11:57 +0900645 tmp |= HOST_AHCI_EN;
646 writel(tmp, mmio + HOST_CTL);
647 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
Tejun Heo15fe9822008-04-23 20:52:58 +0900648 if (tmp & HOST_AHCI_EN)
649 return;
650 msleep(10);
Tejun Heob710a1f2008-01-05 23:11:57 +0900651 }
Tejun Heo15fe9822008-04-23 20:52:58 +0900652
653 WARN_ON(1);
Tejun Heob710a1f2008-01-05 23:11:57 +0900654}
655
Tejun Heod447df12007-03-18 22:15:33 +0900656/**
657 * ahci_save_initial_config - Save and fixup initial config values
Tejun Heo4447d352007-04-17 23:44:08 +0900658 * @pdev: target PCI device
Tejun Heo4447d352007-04-17 23:44:08 +0900659 * @hpriv: host private area to store config values
Tejun Heod447df12007-03-18 22:15:33 +0900660 *
661 * Some registers containing configuration info might be setup by
662 * BIOS and might be cleared on reset. This function saves the
663 * initial values of those registers into @hpriv such that they
664 * can be restored after controller reset.
665 *
666 * If inconsistent, config values are fixed up by this function.
667 *
668 * LOCKING:
669 * None.
670 */
Tejun Heo4447d352007-04-17 23:44:08 +0900671static void ahci_save_initial_config(struct pci_dev *pdev,
Tejun Heo4447d352007-04-17 23:44:08 +0900672 struct ahci_host_priv *hpriv)
Tejun Heod447df12007-03-18 22:15:33 +0900673{
Tejun Heo4447d352007-04-17 23:44:08 +0900674 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +0900675 u32 cap, port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900676 int i;
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100677 int mv;
Tejun Heod447df12007-03-18 22:15:33 +0900678
Tejun Heob710a1f2008-01-05 23:11:57 +0900679 /* make sure AHCI mode is enabled before accessing CAP */
680 ahci_enable_ahci(mmio);
681
Tejun Heod447df12007-03-18 22:15:33 +0900682 /* Values prefixed with saved_ are written back to host after
683 * reset. Values without are used for driver operation.
684 */
685 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
686 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
687
Tejun Heo274c1fd2007-07-16 14:29:40 +0900688 /* some chips have errata preventing 64bit use */
Tejun Heo417a1a62007-09-23 13:19:55 +0900689 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
Tejun Heoc7a42152007-05-18 16:23:19 +0200690 dev_printk(KERN_INFO, &pdev->dev,
691 "controller can't do 64bit DMA, forcing 32bit\n");
692 cap &= ~HOST_CAP_64;
693 }
694
Tejun Heo417a1a62007-09-23 13:19:55 +0900695 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
Tejun Heo274c1fd2007-07-16 14:29:40 +0900696 dev_printk(KERN_INFO, &pdev->dev,
697 "controller can't do NCQ, turning off CAP_NCQ\n");
698 cap &= ~HOST_CAP_NCQ;
699 }
700
Tejun Heoe297d992008-06-10 00:13:04 +0900701 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
702 dev_printk(KERN_INFO, &pdev->dev,
703 "controller can do NCQ, turning on CAP_NCQ\n");
704 cap |= HOST_CAP_NCQ;
705 }
706
Roel Kluin258cd842008-03-09 21:42:40 +0100707 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
Tejun Heo6949b912007-09-23 13:19:55 +0900708 dev_printk(KERN_INFO, &pdev->dev,
709 "controller can't do PMP, turning off CAP_PMP\n");
710 cap &= ~HOST_CAP_PMP;
711 }
712
Tejun Heod799e082008-06-17 12:46:30 +0900713 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
714 port_map != 1) {
715 dev_printk(KERN_INFO, &pdev->dev,
716 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
717 port_map, 1);
718 port_map = 1;
719 }
720
Jeff Garzikcd70c262007-07-08 02:29:42 -0400721 /*
722 * Temporary Marvell 6145 hack: PATA port presence
723 * is asserted through the standard AHCI port
724 * presence register, as bit 4 (counting from 0)
725 */
Tejun Heo417a1a62007-09-23 13:19:55 +0900726 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100727 if (pdev->device == 0x6121)
728 mv = 0x3;
729 else
730 mv = 0xf;
Jeff Garzikcd70c262007-07-08 02:29:42 -0400731 dev_printk(KERN_ERR, &pdev->dev,
732 "MV_AHCI HACK: port_map %x -> %x\n",
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100733 port_map,
734 port_map & mv);
Jeff Garzikcd70c262007-07-08 02:29:42 -0400735
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100736 port_map &= mv;
Jeff Garzikcd70c262007-07-08 02:29:42 -0400737 }
738
Tejun Heo17199b12007-03-18 22:26:53 +0900739 /* cross check port_map and cap.n_ports */
Tejun Heo7a234af2007-09-03 12:44:57 +0900740 if (port_map) {
Tejun Heo837f5f82008-02-06 15:13:51 +0900741 int map_ports = 0;
Tejun Heo17199b12007-03-18 22:26:53 +0900742
Tejun Heo837f5f82008-02-06 15:13:51 +0900743 for (i = 0; i < AHCI_MAX_PORTS; i++)
744 if (port_map & (1 << i))
745 map_ports++;
Tejun Heo17199b12007-03-18 22:26:53 +0900746
Tejun Heo837f5f82008-02-06 15:13:51 +0900747 /* If PI has more ports than n_ports, whine, clear
748 * port_map and let it be generated from n_ports.
Tejun Heo17199b12007-03-18 22:26:53 +0900749 */
Tejun Heo837f5f82008-02-06 15:13:51 +0900750 if (map_ports > ahci_nr_ports(cap)) {
Tejun Heo4447d352007-04-17 23:44:08 +0900751 dev_printk(KERN_WARNING, &pdev->dev,
Tejun Heo837f5f82008-02-06 15:13:51 +0900752 "implemented port map (0x%x) contains more "
753 "ports than nr_ports (%u), using nr_ports\n",
754 port_map, ahci_nr_ports(cap));
Tejun Heo7a234af2007-09-03 12:44:57 +0900755 port_map = 0;
756 }
757 }
758
759 /* fabricate port_map from cap.nr_ports */
760 if (!port_map) {
Tejun Heo17199b12007-03-18 22:26:53 +0900761 port_map = (1 << ahci_nr_ports(cap)) - 1;
Tejun Heo7a234af2007-09-03 12:44:57 +0900762 dev_printk(KERN_WARNING, &pdev->dev,
763 "forcing PORTS_IMPL to 0x%x\n", port_map);
764
765 /* write the fixed up value to the PI register */
766 hpriv->saved_port_map = port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900767 }
768
Tejun Heod447df12007-03-18 22:15:33 +0900769 /* record values to use during operation */
770 hpriv->cap = cap;
771 hpriv->port_map = port_map;
772}
773
774/**
775 * ahci_restore_initial_config - Restore initial config
Tejun Heo4447d352007-04-17 23:44:08 +0900776 * @host: target ATA host
Tejun Heod447df12007-03-18 22:15:33 +0900777 *
778 * Restore initial config stored by ahci_save_initial_config().
779 *
780 * LOCKING:
781 * None.
782 */
Tejun Heo4447d352007-04-17 23:44:08 +0900783static void ahci_restore_initial_config(struct ata_host *host)
Tejun Heod447df12007-03-18 22:15:33 +0900784{
Tejun Heo4447d352007-04-17 23:44:08 +0900785 struct ahci_host_priv *hpriv = host->private_data;
786 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
787
Tejun Heod447df12007-03-18 22:15:33 +0900788 writel(hpriv->saved_cap, mmio + HOST_CAP);
789 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
790 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
791}
792
Tejun Heo203ef6c2007-07-16 14:29:40 +0900793static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794{
Tejun Heo203ef6c2007-07-16 14:29:40 +0900795 static const int offset[] = {
796 [SCR_STATUS] = PORT_SCR_STAT,
797 [SCR_CONTROL] = PORT_SCR_CTL,
798 [SCR_ERROR] = PORT_SCR_ERR,
799 [SCR_ACTIVE] = PORT_SCR_ACT,
800 [SCR_NOTIFICATION] = PORT_SCR_NTF,
801 };
802 struct ahci_host_priv *hpriv = ap->host->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700803
Tejun Heo203ef6c2007-07-16 14:29:40 +0900804 if (sc_reg < ARRAY_SIZE(offset) &&
805 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
806 return offset[sc_reg];
Tejun Heoda3dbb12007-07-16 14:29:40 +0900807 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700808}
809
Tejun Heo203ef6c2007-07-16 14:29:40 +0900810static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700811{
Tejun Heo203ef6c2007-07-16 14:29:40 +0900812 void __iomem *port_mmio = ahci_port_base(ap);
813 int offset = ahci_scr_offset(ap, sc_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814
Tejun Heo203ef6c2007-07-16 14:29:40 +0900815 if (offset) {
816 *val = readl(port_mmio + offset);
817 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700818 }
Tejun Heo203ef6c2007-07-16 14:29:40 +0900819 return -EINVAL;
820}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700821
Tejun Heo203ef6c2007-07-16 14:29:40 +0900822static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
823{
824 void __iomem *port_mmio = ahci_port_base(ap);
825 int offset = ahci_scr_offset(ap, sc_reg);
826
827 if (offset) {
828 writel(val, port_mmio + offset);
829 return 0;
830 }
831 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700832}
833
Tejun Heo4447d352007-04-17 23:44:08 +0900834static void ahci_start_engine(struct ata_port *ap)
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900835{
Tejun Heo4447d352007-04-17 23:44:08 +0900836 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900837 u32 tmp;
838
Tejun Heod8fcd112006-07-26 15:59:25 +0900839 /* start DMA */
Tejun Heo9f592052006-07-26 15:59:26 +0900840 tmp = readl(port_mmio + PORT_CMD);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900841 tmp |= PORT_CMD_START;
842 writel(tmp, port_mmio + PORT_CMD);
843 readl(port_mmio + PORT_CMD); /* flush */
844}
845
Tejun Heo4447d352007-04-17 23:44:08 +0900846static int ahci_stop_engine(struct ata_port *ap)
Tejun Heo254950c2006-07-26 15:59:25 +0900847{
Tejun Heo4447d352007-04-17 23:44:08 +0900848 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo254950c2006-07-26 15:59:25 +0900849 u32 tmp;
850
851 tmp = readl(port_mmio + PORT_CMD);
852
Tejun Heod8fcd112006-07-26 15:59:25 +0900853 /* check if the HBA is idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900854 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
855 return 0;
856
Tejun Heod8fcd112006-07-26 15:59:25 +0900857 /* setting HBA to idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900858 tmp &= ~PORT_CMD_START;
859 writel(tmp, port_mmio + PORT_CMD);
860
Tejun Heod8fcd112006-07-26 15:59:25 +0900861 /* wait for engine to stop. This could be as long as 500 msec */
Tejun Heo254950c2006-07-26 15:59:25 +0900862 tmp = ata_wait_register(port_mmio + PORT_CMD,
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400863 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
Tejun Heod8fcd112006-07-26 15:59:25 +0900864 if (tmp & PORT_CMD_LIST_ON)
Tejun Heo254950c2006-07-26 15:59:25 +0900865 return -EIO;
866
867 return 0;
868}
869
Tejun Heo4447d352007-04-17 23:44:08 +0900870static void ahci_start_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900871{
Tejun Heo4447d352007-04-17 23:44:08 +0900872 void __iomem *port_mmio = ahci_port_base(ap);
873 struct ahci_host_priv *hpriv = ap->host->private_data;
874 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo0be0aa92006-07-26 15:59:26 +0900875 u32 tmp;
876
877 /* set FIS registers */
Tejun Heo4447d352007-04-17 23:44:08 +0900878 if (hpriv->cap & HOST_CAP_64)
879 writel((pp->cmd_slot_dma >> 16) >> 16,
880 port_mmio + PORT_LST_ADDR_HI);
881 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900882
Tejun Heo4447d352007-04-17 23:44:08 +0900883 if (hpriv->cap & HOST_CAP_64)
884 writel((pp->rx_fis_dma >> 16) >> 16,
885 port_mmio + PORT_FIS_ADDR_HI);
886 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900887
888 /* enable FIS reception */
889 tmp = readl(port_mmio + PORT_CMD);
890 tmp |= PORT_CMD_FIS_RX;
891 writel(tmp, port_mmio + PORT_CMD);
892
893 /* flush */
894 readl(port_mmio + PORT_CMD);
895}
896
Tejun Heo4447d352007-04-17 23:44:08 +0900897static int ahci_stop_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900898{
Tejun Heo4447d352007-04-17 23:44:08 +0900899 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900900 u32 tmp;
901
902 /* disable FIS reception */
903 tmp = readl(port_mmio + PORT_CMD);
904 tmp &= ~PORT_CMD_FIS_RX;
905 writel(tmp, port_mmio + PORT_CMD);
906
907 /* wait for completion, spec says 500ms, give it 1000 */
908 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
909 PORT_CMD_FIS_ON, 10, 1000);
910 if (tmp & PORT_CMD_FIS_ON)
911 return -EBUSY;
912
913 return 0;
914}
915
Tejun Heo4447d352007-04-17 23:44:08 +0900916static void ahci_power_up(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900917{
Tejun Heo4447d352007-04-17 23:44:08 +0900918 struct ahci_host_priv *hpriv = ap->host->private_data;
919 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900920 u32 cmd;
921
922 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
923
924 /* spin up device */
Tejun Heo4447d352007-04-17 23:44:08 +0900925 if (hpriv->cap & HOST_CAP_SSS) {
Tejun Heo0be0aa92006-07-26 15:59:26 +0900926 cmd |= PORT_CMD_SPIN_UP;
927 writel(cmd, port_mmio + PORT_CMD);
928 }
929
930 /* wake up link */
931 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
932}
933
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400934static void ahci_disable_alpm(struct ata_port *ap)
935{
936 struct ahci_host_priv *hpriv = ap->host->private_data;
937 void __iomem *port_mmio = ahci_port_base(ap);
938 u32 cmd;
939 struct ahci_port_priv *pp = ap->private_data;
940
941 /* IPM bits should be disabled by libata-core */
942 /* get the existing command bits */
943 cmd = readl(port_mmio + PORT_CMD);
944
945 /* disable ALPM and ASP */
946 cmd &= ~PORT_CMD_ASP;
947 cmd &= ~PORT_CMD_ALPE;
948
949 /* force the interface back to active */
950 cmd |= PORT_CMD_ICC_ACTIVE;
951
952 /* write out new cmd value */
953 writel(cmd, port_mmio + PORT_CMD);
954 cmd = readl(port_mmio + PORT_CMD);
955
956 /* wait 10ms to be sure we've come out of any low power state */
957 msleep(10);
958
959 /* clear out any PhyRdy stuff from interrupt status */
960 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
961
962 /* go ahead and clean out PhyRdy Change from Serror too */
963 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
964
965 /*
966 * Clear flag to indicate that we should ignore all PhyRdy
967 * state changes
968 */
969 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
970
971 /*
972 * Enable interrupts on Phy Ready.
973 */
974 pp->intr_mask |= PORT_IRQ_PHYRDY;
975 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
976
977 /*
978 * don't change the link pm policy - we can be called
979 * just to turn of link pm temporarily
980 */
981}
982
983static int ahci_enable_alpm(struct ata_port *ap,
984 enum link_pm policy)
985{
986 struct ahci_host_priv *hpriv = ap->host->private_data;
987 void __iomem *port_mmio = ahci_port_base(ap);
988 u32 cmd;
989 struct ahci_port_priv *pp = ap->private_data;
990 u32 asp;
991
992 /* Make sure the host is capable of link power management */
993 if (!(hpriv->cap & HOST_CAP_ALPM))
994 return -EINVAL;
995
996 switch (policy) {
997 case MAX_PERFORMANCE:
998 case NOT_AVAILABLE:
999 /*
1000 * if we came here with NOT_AVAILABLE,
1001 * it just means this is the first time we
1002 * have tried to enable - default to max performance,
1003 * and let the user go to lower power modes on request.
1004 */
1005 ahci_disable_alpm(ap);
1006 return 0;
1007 case MIN_POWER:
1008 /* configure HBA to enter SLUMBER */
1009 asp = PORT_CMD_ASP;
1010 break;
1011 case MEDIUM_POWER:
1012 /* configure HBA to enter PARTIAL */
1013 asp = 0;
1014 break;
1015 default:
1016 return -EINVAL;
1017 }
1018
1019 /*
1020 * Disable interrupts on Phy Ready. This keeps us from
1021 * getting woken up due to spurious phy ready interrupts
1022 * TBD - Hot plug should be done via polling now, is
1023 * that even supported?
1024 */
1025 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1026 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1027
1028 /*
1029 * Set a flag to indicate that we should ignore all PhyRdy
1030 * state changes since these can happen now whenever we
1031 * change link state
1032 */
1033 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1034
1035 /* get the existing command bits */
1036 cmd = readl(port_mmio + PORT_CMD);
1037
1038 /*
1039 * Set ASP based on Policy
1040 */
1041 cmd |= asp;
1042
1043 /*
1044 * Setting this bit will instruct the HBA to aggressively
1045 * enter a lower power link state when it's appropriate and
1046 * based on the value set above for ASP
1047 */
1048 cmd |= PORT_CMD_ALPE;
1049
1050 /* write out new cmd value */
1051 writel(cmd, port_mmio + PORT_CMD);
1052 cmd = readl(port_mmio + PORT_CMD);
1053
1054 /* IPM bits should be set by libata-core */
1055 return 0;
1056}
1057
Tejun Heo438ac6d2007-03-02 17:31:26 +09001058#ifdef CONFIG_PM
Tejun Heo4447d352007-04-17 23:44:08 +09001059static void ahci_power_down(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001060{
Tejun Heo4447d352007-04-17 23:44:08 +09001061 struct ahci_host_priv *hpriv = ap->host->private_data;
1062 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001063 u32 cmd, scontrol;
1064
Tejun Heo4447d352007-04-17 23:44:08 +09001065 if (!(hpriv->cap & HOST_CAP_SSS))
Tejun Heo07c53da2007-01-21 02:10:11 +09001066 return;
1067
1068 /* put device into listen mode, first set PxSCTL.DET to 0 */
1069 scontrol = readl(port_mmio + PORT_SCR_CTL);
1070 scontrol &= ~0xf;
1071 writel(scontrol, port_mmio + PORT_SCR_CTL);
1072
1073 /* then set PxCMD.SUD to 0 */
Tejun Heo0be0aa92006-07-26 15:59:26 +09001074 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
Tejun Heo07c53da2007-01-21 02:10:11 +09001075 cmd &= ~PORT_CMD_SPIN_UP;
1076 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001077}
Tejun Heo438ac6d2007-03-02 17:31:26 +09001078#endif
Tejun Heo0be0aa92006-07-26 15:59:26 +09001079
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001080static void ahci_start_port(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001081{
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001082 struct ahci_port_priv *pp = ap->private_data;
1083 struct ata_link *link;
1084 struct ahci_em_priv *emp;
1085
Tejun Heo0be0aa92006-07-26 15:59:26 +09001086 /* enable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +09001087 ahci_start_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001088
1089 /* enable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +09001090 ahci_start_engine(ap);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001091
1092 /* turn on LEDs */
1093 if (ap->flags & ATA_FLAG_EM) {
1094 ata_port_for_each_link(link, ap) {
1095 emp = &pp->em_priv[link->pmp];
1096 ahci_transmit_led_message(ap, emp->led_state, 4);
1097 }
1098 }
1099
1100 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
1101 ata_port_for_each_link(link, ap)
1102 ahci_init_sw_activity(link);
1103
Tejun Heo0be0aa92006-07-26 15:59:26 +09001104}
1105
Tejun Heo4447d352007-04-17 23:44:08 +09001106static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001107{
1108 int rc;
1109
1110 /* disable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +09001111 rc = ahci_stop_engine(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001112 if (rc) {
1113 *emsg = "failed to stop engine";
1114 return rc;
1115 }
1116
1117 /* disable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +09001118 rc = ahci_stop_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001119 if (rc) {
1120 *emsg = "failed stop FIS RX";
1121 return rc;
1122 }
1123
Tejun Heo0be0aa92006-07-26 15:59:26 +09001124 return 0;
1125}
1126
Tejun Heo4447d352007-04-17 23:44:08 +09001127static int ahci_reset_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +09001128{
Tejun Heo4447d352007-04-17 23:44:08 +09001129 struct pci_dev *pdev = to_pci_dev(host->dev);
Tejun Heo49f29092007-11-19 16:03:44 +09001130 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo4447d352007-04-17 23:44:08 +09001131 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +09001132 u32 tmp;
Tejun Heod91542c2006-07-26 15:59:26 +09001133
Jeff Garzik3cc3eb12007-09-26 00:02:41 -04001134 /* we must be in AHCI mode, before using anything
1135 * AHCI-specific, such as HOST_RESET.
1136 */
Tejun Heob710a1f2008-01-05 23:11:57 +09001137 ahci_enable_ahci(mmio);
Jeff Garzik3cc3eb12007-09-26 00:02:41 -04001138
1139 /* global controller reset */
Tejun Heoa22e6442008-03-10 10:25:25 +09001140 if (!ahci_skip_host_reset) {
1141 tmp = readl(mmio + HOST_CTL);
1142 if ((tmp & HOST_RESET) == 0) {
1143 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1144 readl(mmio + HOST_CTL); /* flush */
1145 }
Tejun Heod91542c2006-07-26 15:59:26 +09001146
Zhang Rui24920c82008-07-04 13:32:17 +08001147 /*
1148 * to perform host reset, OS should set HOST_RESET
1149 * and poll until this bit is read to be "0".
1150 * reset must complete within 1 second, or
Tejun Heoa22e6442008-03-10 10:25:25 +09001151 * the hardware should be considered fried.
1152 */
Zhang Rui24920c82008-07-04 13:32:17 +08001153 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1154 HOST_RESET, 10, 1000);
Tejun Heod91542c2006-07-26 15:59:26 +09001155
Tejun Heoa22e6442008-03-10 10:25:25 +09001156 if (tmp & HOST_RESET) {
1157 dev_printk(KERN_ERR, host->dev,
1158 "controller reset failed (0x%x)\n", tmp);
1159 return -EIO;
1160 }
Tejun Heod91542c2006-07-26 15:59:26 +09001161
Tejun Heoa22e6442008-03-10 10:25:25 +09001162 /* turn on AHCI mode */
1163 ahci_enable_ahci(mmio);
Tejun Heo98fa4b62006-11-02 12:17:23 +09001164
Tejun Heoa22e6442008-03-10 10:25:25 +09001165 /* Some registers might be cleared on reset. Restore
1166 * initial values.
1167 */
1168 ahci_restore_initial_config(host);
1169 } else
1170 dev_printk(KERN_INFO, host->dev,
1171 "skipping global host reset\n");
Tejun Heod91542c2006-07-26 15:59:26 +09001172
1173 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1174 u16 tmp16;
1175
1176 /* configure PCS */
1177 pci_read_config_word(pdev, 0x92, &tmp16);
Tejun Heo49f29092007-11-19 16:03:44 +09001178 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1179 tmp16 |= hpriv->port_map;
1180 pci_write_config_word(pdev, 0x92, tmp16);
1181 }
Tejun Heod91542c2006-07-26 15:59:26 +09001182 }
1183
1184 return 0;
1185}
1186
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001187static void ahci_sw_activity(struct ata_link *link)
1188{
1189 struct ata_port *ap = link->ap;
1190 struct ahci_port_priv *pp = ap->private_data;
1191 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1192
1193 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1194 return;
1195
1196 emp->activity++;
1197 if (!timer_pending(&emp->timer))
1198 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1199}
1200
1201static void ahci_sw_activity_blink(unsigned long arg)
1202{
1203 struct ata_link *link = (struct ata_link *)arg;
1204 struct ata_port *ap = link->ap;
1205 struct ahci_port_priv *pp = ap->private_data;
1206 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1207 unsigned long led_message = emp->led_state;
1208 u32 activity_led_state;
1209
1210 led_message &= 0xffff0000;
1211 led_message |= ap->port_no | (link->pmp << 8);
1212
1213 /* check to see if we've had activity. If so,
1214 * toggle state of LED and reset timer. If not,
1215 * turn LED to desired idle state.
1216 */
1217 if (emp->saved_activity != emp->activity) {
1218 emp->saved_activity = emp->activity;
1219 /* get the current LED state */
1220 activity_led_state = led_message & 0x00010000;
1221
1222 if (activity_led_state)
1223 activity_led_state = 0;
1224 else
1225 activity_led_state = 1;
1226
1227 /* clear old state */
1228 led_message &= 0xfff8ffff;
1229
1230 /* toggle state */
1231 led_message |= (activity_led_state << 16);
1232 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1233 } else {
1234 /* switch to idle */
1235 led_message &= 0xfff8ffff;
1236 if (emp->blink_policy == BLINK_OFF)
1237 led_message |= (1 << 16);
1238 }
1239 ahci_transmit_led_message(ap, led_message, 4);
1240}
1241
1242static void ahci_init_sw_activity(struct ata_link *link)
1243{
1244 struct ata_port *ap = link->ap;
1245 struct ahci_port_priv *pp = ap->private_data;
1246 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1247
1248 /* init activity stats, setup timer */
1249 emp->saved_activity = emp->activity = 0;
1250 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1251
1252 /* check our blink policy and set flag for link if it's enabled */
1253 if (emp->blink_policy)
1254 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1255}
1256
1257static int ahci_reset_em(struct ata_host *host)
1258{
1259 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1260 u32 em_ctl;
1261
1262 em_ctl = readl(mmio + HOST_EM_CTL);
1263 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1264 return -EINVAL;
1265
1266 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1267 return 0;
1268}
1269
1270static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1271 ssize_t size)
1272{
1273 struct ahci_host_priv *hpriv = ap->host->private_data;
1274 struct ahci_port_priv *pp = ap->private_data;
1275 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1276 u32 em_ctl;
1277 u32 message[] = {0, 0};
Linus Torvalds93082f02008-07-25 10:56:36 -07001278 unsigned long flags;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001279 int pmp;
1280 struct ahci_em_priv *emp;
1281
1282 /* get the slot number from the message */
1283 pmp = (state & 0x0000ff00) >> 8;
1284 if (pmp < MAX_SLOTS)
1285 emp = &pp->em_priv[pmp];
1286 else
1287 return -EINVAL;
1288
1289 spin_lock_irqsave(ap->lock, flags);
1290
1291 /*
1292 * if we are still busy transmitting a previous message,
1293 * do not allow
1294 */
1295 em_ctl = readl(mmio + HOST_EM_CTL);
1296 if (em_ctl & EM_CTL_TM) {
1297 spin_unlock_irqrestore(ap->lock, flags);
1298 return -EINVAL;
1299 }
1300
1301 /*
1302 * create message header - this is all zero except for
1303 * the message size, which is 4 bytes.
1304 */
1305 message[0] |= (4 << 8);
1306
1307 /* ignore 0:4 of byte zero, fill in port info yourself */
1308 message[1] = ((state & 0xfffffff0) | ap->port_no);
1309
1310 /* write message to EM_LOC */
1311 writel(message[0], mmio + hpriv->em_loc);
1312 writel(message[1], mmio + hpriv->em_loc+4);
1313
1314 /* save off new led state for port/slot */
1315 emp->led_state = message[1];
1316
1317 /*
1318 * tell hardware to transmit the message
1319 */
1320 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1321
1322 spin_unlock_irqrestore(ap->lock, flags);
1323 return size;
1324}
1325
1326static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1327{
1328 struct ahci_port_priv *pp = ap->private_data;
1329 struct ata_link *link;
1330 struct ahci_em_priv *emp;
1331 int rc = 0;
1332
1333 ata_port_for_each_link(link, ap) {
1334 emp = &pp->em_priv[link->pmp];
1335 rc += sprintf(buf, "%lx\n", emp->led_state);
1336 }
1337 return rc;
1338}
1339
1340static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1341 size_t size)
1342{
1343 int state;
1344 int pmp;
1345 struct ahci_port_priv *pp = ap->private_data;
1346 struct ahci_em_priv *emp;
1347
1348 state = simple_strtoul(buf, NULL, 0);
1349
1350 /* get the slot number from the message */
1351 pmp = (state & 0x0000ff00) >> 8;
1352 if (pmp < MAX_SLOTS)
1353 emp = &pp->em_priv[pmp];
1354 else
1355 return -EINVAL;
1356
1357 /* mask off the activity bits if we are in sw_activity
1358 * mode, user should turn off sw_activity before setting
1359 * activity led through em_message
1360 */
1361 if (emp->blink_policy)
1362 state &= 0xfff8ffff;
1363
1364 return ahci_transmit_led_message(ap, state, size);
1365}
1366
1367static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1368{
1369 struct ata_link *link = dev->link;
1370 struct ata_port *ap = link->ap;
1371 struct ahci_port_priv *pp = ap->private_data;
1372 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1373 u32 port_led_state = emp->led_state;
1374
1375 /* save the desired Activity LED behavior */
1376 if (val == OFF) {
1377 /* clear LFLAG */
1378 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1379
1380 /* set the LED to OFF */
1381 port_led_state &= 0xfff80000;
1382 port_led_state |= (ap->port_no | (link->pmp << 8));
1383 ahci_transmit_led_message(ap, port_led_state, 4);
1384 } else {
1385 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1386 if (val == BLINK_OFF) {
1387 /* set LED to ON for idle */
1388 port_led_state &= 0xfff80000;
1389 port_led_state |= (ap->port_no | (link->pmp << 8));
1390 port_led_state |= 0x00010000; /* check this */
1391 ahci_transmit_led_message(ap, port_led_state, 4);
1392 }
1393 }
1394 emp->blink_policy = val;
1395 return 0;
1396}
1397
1398static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1399{
1400 struct ata_link *link = dev->link;
1401 struct ata_port *ap = link->ap;
1402 struct ahci_port_priv *pp = ap->private_data;
1403 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1404
1405 /* display the saved value of activity behavior for this
1406 * disk.
1407 */
1408 return sprintf(buf, "%d\n", emp->blink_policy);
1409}
1410
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001411static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1412 int port_no, void __iomem *mmio,
1413 void __iomem *port_mmio)
1414{
1415 const char *emsg = NULL;
1416 int rc;
1417 u32 tmp;
1418
1419 /* make sure port is not active */
1420 rc = ahci_deinit_port(ap, &emsg);
1421 if (rc)
1422 dev_printk(KERN_WARNING, &pdev->dev,
1423 "%s (%d)\n", emsg, rc);
1424
1425 /* clear SError */
1426 tmp = readl(port_mmio + PORT_SCR_ERR);
1427 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1428 writel(tmp, port_mmio + PORT_SCR_ERR);
1429
1430 /* clear port IRQ */
1431 tmp = readl(port_mmio + PORT_IRQ_STAT);
1432 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1433 if (tmp)
1434 writel(tmp, port_mmio + PORT_IRQ_STAT);
1435
1436 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1437}
1438
Tejun Heo4447d352007-04-17 23:44:08 +09001439static void ahci_init_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +09001440{
Tejun Heo417a1a62007-09-23 13:19:55 +09001441 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo4447d352007-04-17 23:44:08 +09001442 struct pci_dev *pdev = to_pci_dev(host->dev);
1443 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001444 int i;
Jeff Garzikcd70c262007-07-08 02:29:42 -04001445 void __iomem *port_mmio;
Tejun Heod91542c2006-07-26 15:59:26 +09001446 u32 tmp;
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +01001447 int mv;
Tejun Heod91542c2006-07-26 15:59:26 +09001448
Tejun Heo417a1a62007-09-23 13:19:55 +09001449 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +01001450 if (pdev->device == 0x6121)
1451 mv = 2;
1452 else
1453 mv = 4;
1454 port_mmio = __ahci_port_base(host, mv);
Jeff Garzikcd70c262007-07-08 02:29:42 -04001455
1456 writel(0, port_mmio + PORT_IRQ_MASK);
1457
1458 /* clear port IRQ */
1459 tmp = readl(port_mmio + PORT_IRQ_STAT);
1460 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1461 if (tmp)
1462 writel(tmp, port_mmio + PORT_IRQ_STAT);
1463 }
1464
Tejun Heo4447d352007-04-17 23:44:08 +09001465 for (i = 0; i < host->n_ports; i++) {
1466 struct ata_port *ap = host->ports[i];
Tejun Heod91542c2006-07-26 15:59:26 +09001467
Jeff Garzikcd70c262007-07-08 02:29:42 -04001468 port_mmio = ahci_port_base(ap);
Tejun Heo4447d352007-04-17 23:44:08 +09001469 if (ata_port_is_dummy(ap))
Tejun Heod91542c2006-07-26 15:59:26 +09001470 continue;
Tejun Heod91542c2006-07-26 15:59:26 +09001471
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001472 ahci_port_init(pdev, ap, i, mmio, port_mmio);
Tejun Heod91542c2006-07-26 15:59:26 +09001473 }
1474
1475 tmp = readl(mmio + HOST_CTL);
1476 VPRINTK("HOST_CTL 0x%x\n", tmp);
1477 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1478 tmp = readl(mmio + HOST_CTL);
1479 VPRINTK("HOST_CTL 0x%x\n", tmp);
1480}
1481
Jeff Garzika8785392008-02-28 15:43:48 -05001482static void ahci_dev_config(struct ata_device *dev)
1483{
1484 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1485
Jeff Garzik4cde32f2008-03-24 22:40:40 -04001486 if (hpriv->flags & AHCI_HFLAG_SECT255) {
Jeff Garzika8785392008-02-28 15:43:48 -05001487 dev->max_sectors = 255;
Jeff Garzik4cde32f2008-03-24 22:40:40 -04001488 ata_dev_printk(dev, KERN_INFO,
1489 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1490 }
Jeff Garzika8785392008-02-28 15:43:48 -05001491}
1492
Tejun Heo422b7592005-12-19 22:37:17 +09001493static unsigned int ahci_dev_classify(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001494{
Tejun Heo4447d352007-04-17 23:44:08 +09001495 void __iomem *port_mmio = ahci_port_base(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001496 struct ata_taskfile tf;
Tejun Heo422b7592005-12-19 22:37:17 +09001497 u32 tmp;
1498
1499 tmp = readl(port_mmio + PORT_SIG);
1500 tf.lbah = (tmp >> 24) & 0xff;
1501 tf.lbam = (tmp >> 16) & 0xff;
1502 tf.lbal = (tmp >> 8) & 0xff;
1503 tf.nsect = (tmp) & 0xff;
1504
1505 return ata_dev_classify(&tf);
1506}
1507
Tejun Heo12fad3f2006-05-15 21:03:55 +09001508static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1509 u32 opts)
Tejun Heocc9278e2006-02-10 17:25:47 +09001510{
Tejun Heo12fad3f2006-05-15 21:03:55 +09001511 dma_addr_t cmd_tbl_dma;
1512
1513 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1514
1515 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1516 pp->cmd_slot[tag].status = 0;
1517 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1518 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
Tejun Heocc9278e2006-02-10 17:25:47 +09001519}
1520
Tejun Heod2e75df2007-07-16 14:29:39 +09001521static int ahci_kick_engine(struct ata_port *ap, int force_restart)
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001522{
Tejun Heo350756f2008-04-07 22:47:21 +09001523 void __iomem *port_mmio = ahci_port_base(ap);
Jeff Garzikcca39742006-08-24 03:19:22 -04001524 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo520d06f2008-04-07 22:47:21 +09001525 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001526 u32 tmp;
Tejun Heod2e75df2007-07-16 14:29:39 +09001527 int busy, rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001528
Tejun Heod2e75df2007-07-16 14:29:39 +09001529 /* do we need to kick the port? */
Tejun Heo520d06f2008-04-07 22:47:21 +09001530 busy = status & (ATA_BUSY | ATA_DRQ);
Tejun Heod2e75df2007-07-16 14:29:39 +09001531 if (!busy && !force_restart)
1532 return 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001533
Tejun Heod2e75df2007-07-16 14:29:39 +09001534 /* stop engine */
1535 rc = ahci_stop_engine(ap);
1536 if (rc)
1537 goto out_restart;
1538
1539 /* need to do CLO? */
1540 if (!busy) {
1541 rc = 0;
1542 goto out_restart;
1543 }
1544
1545 if (!(hpriv->cap & HOST_CAP_CLO)) {
1546 rc = -EOPNOTSUPP;
1547 goto out_restart;
1548 }
1549
1550 /* perform CLO */
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001551 tmp = readl(port_mmio + PORT_CMD);
1552 tmp |= PORT_CMD_CLO;
1553 writel(tmp, port_mmio + PORT_CMD);
1554
Tejun Heod2e75df2007-07-16 14:29:39 +09001555 rc = 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001556 tmp = ata_wait_register(port_mmio + PORT_CMD,
1557 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1558 if (tmp & PORT_CMD_CLO)
Tejun Heod2e75df2007-07-16 14:29:39 +09001559 rc = -EIO;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001560
Tejun Heod2e75df2007-07-16 14:29:39 +09001561 /* restart engine */
1562 out_restart:
1563 ahci_start_engine(ap);
1564 return rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001565}
1566
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001567static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1568 struct ata_taskfile *tf, int is_cmd, u16 flags,
1569 unsigned long timeout_msec)
1570{
1571 const u32 cmd_fis_len = 5; /* five dwords */
1572 struct ahci_port_priv *pp = ap->private_data;
1573 void __iomem *port_mmio = ahci_port_base(ap);
1574 u8 *fis = pp->cmd_tbl;
1575 u32 tmp;
1576
1577 /* prep the command */
1578 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1579 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1580
1581 /* issue & wait */
1582 writel(1, port_mmio + PORT_CMD_ISSUE);
1583
1584 if (timeout_msec) {
1585 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1586 1, timeout_msec);
1587 if (tmp & 0x1) {
1588 ahci_kick_engine(ap, 1);
1589 return -EBUSY;
1590 }
1591 } else
1592 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1593
1594 return 0;
1595}
1596
Shane Huangbd172432008-06-10 15:52:04 +08001597static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1598 int pmp, unsigned long deadline,
1599 int (*check_ready)(struct ata_link *link))
Tejun Heo4658f792006-03-22 21:07:03 +09001600{
Tejun Heocc0680a2007-08-06 18:36:23 +09001601 struct ata_port *ap = link->ap;
Tejun Heo4658f792006-03-22 21:07:03 +09001602 const char *reason = NULL;
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001603 unsigned long now, msecs;
Tejun Heo4658f792006-03-22 21:07:03 +09001604 struct ata_taskfile tf;
Tejun Heo4658f792006-03-22 21:07:03 +09001605 int rc;
1606
1607 DPRINTK("ENTER\n");
1608
1609 /* prepare for SRST (AHCI-1.1 10.4.1) */
Tejun Heod2e75df2007-07-16 14:29:39 +09001610 rc = ahci_kick_engine(ap, 1);
Tejun Heo994056d2007-12-06 15:02:48 +09001611 if (rc && rc != -EOPNOTSUPP)
Tejun Heocc0680a2007-08-06 18:36:23 +09001612 ata_link_printk(link, KERN_WARNING,
Tejun Heo994056d2007-12-06 15:02:48 +09001613 "failed to reset engine (errno=%d)\n", rc);
Tejun Heo4658f792006-03-22 21:07:03 +09001614
Tejun Heocc0680a2007-08-06 18:36:23 +09001615 ata_tf_init(link->device, &tf);
Tejun Heo4658f792006-03-22 21:07:03 +09001616
1617 /* issue the first D2H Register FIS */
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001618 msecs = 0;
1619 now = jiffies;
1620 if (time_after(now, deadline))
1621 msecs = jiffies_to_msecs(deadline - now);
1622
Tejun Heo4658f792006-03-22 21:07:03 +09001623 tf.ctl |= ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001624 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001625 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
Tejun Heo4658f792006-03-22 21:07:03 +09001626 rc = -EIO;
1627 reason = "1st FIS failed";
1628 goto fail;
1629 }
1630
1631 /* spec says at least 5us, but be generous and sleep for 1ms */
1632 msleep(1);
1633
1634 /* issue the second D2H Register FIS */
Tejun Heo4658f792006-03-22 21:07:03 +09001635 tf.ctl &= ~ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001636 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
Tejun Heo4658f792006-03-22 21:07:03 +09001637
Tejun Heo705e76b2008-04-07 22:47:19 +09001638 /* wait for link to become ready */
Shane Huangbd172432008-06-10 15:52:04 +08001639 rc = ata_wait_after_reset(link, deadline, check_ready);
Tejun Heo9b893912007-02-02 16:50:52 +09001640 /* link occupied, -ENODEV too is an error */
1641 if (rc) {
1642 reason = "device not ready";
1643 goto fail;
Tejun Heo4658f792006-03-22 21:07:03 +09001644 }
Tejun Heo9b893912007-02-02 16:50:52 +09001645 *class = ahci_dev_classify(ap);
Tejun Heo4658f792006-03-22 21:07:03 +09001646
1647 DPRINTK("EXIT, class=%u\n", *class);
1648 return 0;
1649
Tejun Heo4658f792006-03-22 21:07:03 +09001650 fail:
Tejun Heocc0680a2007-08-06 18:36:23 +09001651 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
Tejun Heo4658f792006-03-22 21:07:03 +09001652 return rc;
1653}
1654
Shane Huangbd172432008-06-10 15:52:04 +08001655static int ahci_check_ready(struct ata_link *link)
1656{
1657 void __iomem *port_mmio = ahci_port_base(link->ap);
1658 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1659
1660 return ata_check_ready(status);
1661}
1662
1663static int ahci_softreset(struct ata_link *link, unsigned int *class,
1664 unsigned long deadline)
1665{
1666 int pmp = sata_srst_pmp(link);
1667
1668 DPRINTK("ENTER\n");
1669
1670 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1671}
1672
1673static int ahci_sb600_check_ready(struct ata_link *link)
1674{
1675 void __iomem *port_mmio = ahci_port_base(link->ap);
1676 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1677 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1678
1679 /*
1680 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1681 * which can save timeout delay.
1682 */
1683 if (irq_status & PORT_IRQ_BAD_PMP)
1684 return -EIO;
1685
1686 return ata_check_ready(status);
1687}
1688
1689static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1690 unsigned long deadline)
1691{
1692 struct ata_port *ap = link->ap;
1693 void __iomem *port_mmio = ahci_port_base(ap);
1694 int pmp = sata_srst_pmp(link);
1695 int rc;
1696 u32 irq_sts;
1697
1698 DPRINTK("ENTER\n");
1699
1700 rc = ahci_do_softreset(link, class, pmp, deadline,
1701 ahci_sb600_check_ready);
1702
1703 /*
1704 * Soft reset fails on some ATI chips with IPMS set when PMP
1705 * is enabled but SATA HDD/ODD is connected to SATA port,
1706 * do soft reset again to port 0.
1707 */
1708 if (rc == -EIO) {
1709 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1710 if (irq_sts & PORT_IRQ_BAD_PMP) {
1711 ata_link_printk(link, KERN_WARNING,
1712 "failed due to HW bug, retry pmp=0\n");
1713 rc = ahci_do_softreset(link, class, 0, deadline,
1714 ahci_check_ready);
1715 }
1716 }
1717
1718 return rc;
1719}
1720
Tejun Heocc0680a2007-08-06 18:36:23 +09001721static int ahci_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +09001722 unsigned long deadline)
Tejun Heo422b7592005-12-19 22:37:17 +09001723{
Tejun Heo9dadd452008-04-07 22:47:19 +09001724 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
Tejun Heocc0680a2007-08-06 18:36:23 +09001725 struct ata_port *ap = link->ap;
Tejun Heo42969712006-05-31 18:28:18 +09001726 struct ahci_port_priv *pp = ap->private_data;
1727 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1728 struct ata_taskfile tf;
Tejun Heo9dadd452008-04-07 22:47:19 +09001729 bool online;
Tejun Heo4bd00f62006-02-11 16:26:02 +09001730 int rc;
1731
1732 DPRINTK("ENTER\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001733
Tejun Heo4447d352007-04-17 23:44:08 +09001734 ahci_stop_engine(ap);
Tejun Heo42969712006-05-31 18:28:18 +09001735
1736 /* clear D2H reception area to properly wait for D2H FIS */
Tejun Heocc0680a2007-08-06 18:36:23 +09001737 ata_tf_init(link->device, &tf);
Tejun Heodfd7a3d2007-01-26 15:37:20 +09001738 tf.command = 0x80;
Tejun Heo99771262007-07-16 14:29:38 +09001739 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
Tejun Heo42969712006-05-31 18:28:18 +09001740
Tejun Heo9dadd452008-04-07 22:47:19 +09001741 rc = sata_link_hardreset(link, timing, deadline, &online,
1742 ahci_check_ready);
Tejun Heo42969712006-05-31 18:28:18 +09001743
Tejun Heo4447d352007-04-17 23:44:08 +09001744 ahci_start_engine(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001745
Tejun Heo9dadd452008-04-07 22:47:19 +09001746 if (online)
Tejun Heo4bd00f62006-02-11 16:26:02 +09001747 *class = ahci_dev_classify(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001748
Tejun Heo4bd00f62006-02-11 16:26:02 +09001749 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1750 return rc;
1751}
1752
Tejun Heocc0680a2007-08-06 18:36:23 +09001753static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +09001754 unsigned long deadline)
Tejun Heoad616ff2006-11-01 18:00:24 +09001755{
Tejun Heocc0680a2007-08-06 18:36:23 +09001756 struct ata_port *ap = link->ap;
Tejun Heo9dadd452008-04-07 22:47:19 +09001757 bool online;
Tejun Heoad616ff2006-11-01 18:00:24 +09001758 int rc;
1759
1760 DPRINTK("ENTER\n");
1761
Tejun Heo4447d352007-04-17 23:44:08 +09001762 ahci_stop_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001763
Tejun Heocc0680a2007-08-06 18:36:23 +09001764 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +09001765 deadline, &online, NULL);
Tejun Heoad616ff2006-11-01 18:00:24 +09001766
Tejun Heo4447d352007-04-17 23:44:08 +09001767 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001768
1769 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1770
1771 /* vt8251 doesn't clear BSY on signature FIS reception,
1772 * request follow-up softreset.
1773 */
Tejun Heo9dadd452008-04-07 22:47:19 +09001774 return online ? -EAGAIN : rc;
Tejun Heoad616ff2006-11-01 18:00:24 +09001775}
1776
Tejun Heoedc93052007-10-25 14:59:16 +09001777static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1778 unsigned long deadline)
1779{
1780 struct ata_port *ap = link->ap;
1781 struct ahci_port_priv *pp = ap->private_data;
1782 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1783 struct ata_taskfile tf;
Tejun Heo9dadd452008-04-07 22:47:19 +09001784 bool online;
Tejun Heoedc93052007-10-25 14:59:16 +09001785 int rc;
1786
1787 ahci_stop_engine(ap);
1788
1789 /* clear D2H reception area to properly wait for D2H FIS */
1790 ata_tf_init(link->device, &tf);
1791 tf.command = 0x80;
1792 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1793
1794 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +09001795 deadline, &online, NULL);
Tejun Heoedc93052007-10-25 14:59:16 +09001796
1797 ahci_start_engine(ap);
1798
Tejun Heoedc93052007-10-25 14:59:16 +09001799 /* The pseudo configuration device on SIMG4726 attached to
1800 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1801 * hardreset if no device is attached to the first downstream
1802 * port && the pseudo device locks up on SRST w/ PMP==0. To
1803 * work around this, wait for !BSY only briefly. If BSY isn't
1804 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1805 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1806 *
1807 * Wait for two seconds. Devices attached to downstream port
1808 * which can't process the following IDENTIFY after this will
1809 * have to be reset again. For most cases, this should
1810 * suffice while making probing snappish enough.
1811 */
Tejun Heo9dadd452008-04-07 22:47:19 +09001812 if (online) {
1813 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1814 ahci_check_ready);
1815 if (rc)
1816 ahci_kick_engine(ap, 0);
1817 }
Tejun Heo9dadd452008-04-07 22:47:19 +09001818 return rc;
Tejun Heoedc93052007-10-25 14:59:16 +09001819}
1820
Tejun Heocc0680a2007-08-06 18:36:23 +09001821static void ahci_postreset(struct ata_link *link, unsigned int *class)
Tejun Heo4bd00f62006-02-11 16:26:02 +09001822{
Tejun Heocc0680a2007-08-06 18:36:23 +09001823 struct ata_port *ap = link->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09001824 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001825 u32 new_tmp, tmp;
1826
Tejun Heo203c75b2008-04-07 22:47:18 +09001827 ata_std_postreset(link, class);
Jeff Garzik02eaa662005-11-12 01:32:19 -05001828
1829 /* Make sure port's ATAPI bit is set appropriately */
1830 new_tmp = tmp = readl(port_mmio + PORT_CMD);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001831 if (*class == ATA_DEV_ATAPI)
Jeff Garzik02eaa662005-11-12 01:32:19 -05001832 new_tmp |= PORT_CMD_ATAPI;
1833 else
1834 new_tmp &= ~PORT_CMD_ATAPI;
1835 if (new_tmp != tmp) {
1836 writel(new_tmp, port_mmio + PORT_CMD);
1837 readl(port_mmio + PORT_CMD); /* flush */
1838 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001839}
1840
Tejun Heo12fad3f2006-05-15 21:03:55 +09001841static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001842{
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001843 struct scatterlist *sg;
Tejun Heoff2aeb12007-12-05 16:43:11 +09001844 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1845 unsigned int si;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001846
1847 VPRINTK("ENTER\n");
1848
1849 /*
1850 * Next, the S/G list.
1851 */
Tejun Heoff2aeb12007-12-05 16:43:11 +09001852 for_each_sg(qc->sg, sg, qc->n_elem, si) {
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001853 dma_addr_t addr = sg_dma_address(sg);
1854 u32 sg_len = sg_dma_len(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001855
Tejun Heoff2aeb12007-12-05 16:43:11 +09001856 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1857 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1858 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001859 }
Jeff Garzik828d09d2005-11-12 01:27:07 -05001860
Tejun Heoff2aeb12007-12-05 16:43:11 +09001861 return si;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001862}
1863
1864static void ahci_qc_prep(struct ata_queued_cmd *qc)
1865{
Jeff Garzika0ea7322005-06-04 01:13:15 -04001866 struct ata_port *ap = qc->ap;
1867 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo405e66b2007-11-27 19:28:53 +09001868 int is_atapi = ata_is_atapi(qc->tf.protocol);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001869 void *cmd_tbl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001870 u32 opts;
1871 const u32 cmd_fis_len = 5; /* five dwords */
Jeff Garzik828d09d2005-11-12 01:27:07 -05001872 unsigned int n_elem;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001873
1874 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001875 * Fill in command table information. First, the header,
1876 * a SATA Register - Host to Device command FIS.
1877 */
Tejun Heo12fad3f2006-05-15 21:03:55 +09001878 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1879
Tejun Heo7d50b602007-09-23 13:19:54 +09001880 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
Tejun Heocc9278e2006-02-10 17:25:47 +09001881 if (is_atapi) {
Tejun Heo12fad3f2006-05-15 21:03:55 +09001882 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1883 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
Jeff Garzika0ea7322005-06-04 01:13:15 -04001884 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001885
Tejun Heocc9278e2006-02-10 17:25:47 +09001886 n_elem = 0;
1887 if (qc->flags & ATA_QCFLAG_DMAMAP)
Tejun Heo12fad3f2006-05-15 21:03:55 +09001888 n_elem = ahci_fill_sg(qc, cmd_tbl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001889
Tejun Heocc9278e2006-02-10 17:25:47 +09001890 /*
1891 * Fill in command slot information.
1892 */
Tejun Heo7d50b602007-09-23 13:19:54 +09001893 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
Tejun Heocc9278e2006-02-10 17:25:47 +09001894 if (qc->tf.flags & ATA_TFLAG_WRITE)
1895 opts |= AHCI_CMD_WRITE;
1896 if (is_atapi)
Tejun Heo4b10e552006-03-12 11:25:27 +09001897 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
Jeff Garzik828d09d2005-11-12 01:27:07 -05001898
Tejun Heo12fad3f2006-05-15 21:03:55 +09001899 ahci_fill_cmd_slot(pp, qc->tag, opts);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001900}
1901
Tejun Heo78cd52d2006-05-15 20:58:29 +09001902static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001903{
Tejun Heo417a1a62007-09-23 13:19:55 +09001904 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001905 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09001906 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1907 struct ata_link *link = NULL;
1908 struct ata_queued_cmd *active_qc;
1909 struct ata_eh_info *active_ehi;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001910 u32 serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001911
Tejun Heo7d50b602007-09-23 13:19:54 +09001912 /* determine active link */
1913 ata_port_for_each_link(link, ap)
1914 if (ata_link_active(link))
1915 break;
1916 if (!link)
1917 link = &ap->link;
1918
1919 active_qc = ata_qc_from_tag(ap, link->active_tag);
1920 active_ehi = &link->eh_info;
1921
1922 /* record irq stat */
1923 ata_ehi_clear_desc(host_ehi);
1924 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
Jeff Garzik9f68a242005-11-15 14:03:47 -05001925
Tejun Heo78cd52d2006-05-15 20:58:29 +09001926 /* AHCI needs SError cleared; otherwise, it might lock up */
Tejun Heoda3dbb12007-07-16 14:29:40 +09001927 ahci_scr_read(ap, SCR_ERROR, &serror);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001928 ahci_scr_write(ap, SCR_ERROR, serror);
Tejun Heo7d50b602007-09-23 13:19:54 +09001929 host_ehi->serror |= serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001930
Tejun Heo41669552006-11-29 11:33:14 +09001931 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
Tejun Heo417a1a62007-09-23 13:19:55 +09001932 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
Tejun Heo41669552006-11-29 11:33:14 +09001933 irq_stat &= ~PORT_IRQ_IF_ERR;
1934
Conke Hu55a61602007-03-27 18:33:05 +08001935 if (irq_stat & PORT_IRQ_TF_ERR) {
Tejun Heo7d50b602007-09-23 13:19:54 +09001936 /* If qc is active, charge it; otherwise, the active
1937 * link. There's no active qc on NCQ errors. It will
1938 * be determined by EH by reading log page 10h.
1939 */
1940 if (active_qc)
1941 active_qc->err_mask |= AC_ERR_DEV;
1942 else
1943 active_ehi->err_mask |= AC_ERR_DEV;
1944
Tejun Heo417a1a62007-09-23 13:19:55 +09001945 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
Tejun Heo7d50b602007-09-23 13:19:54 +09001946 host_ehi->serror &= ~SERR_INTERNAL;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001947 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001948
Tejun Heo78cd52d2006-05-15 20:58:29 +09001949 if (irq_stat & PORT_IRQ_UNK_FIS) {
1950 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001951
Tejun Heo7d50b602007-09-23 13:19:54 +09001952 active_ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09001953 active_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09001954 ata_ehi_push_desc(active_ehi,
1955 "unknown FIS %08x %08x %08x %08x" ,
Tejun Heo78cd52d2006-05-15 20:58:29 +09001956 unk[0], unk[1], unk[2], unk[3]);
1957 }
Jeff Garzikb8f61532005-08-25 22:01:20 -04001958
Tejun Heo071f44b2008-04-07 22:47:22 +09001959 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
Tejun Heo7d50b602007-09-23 13:19:54 +09001960 active_ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09001961 active_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09001962 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1963 }
Tejun Heo78cd52d2006-05-15 20:58:29 +09001964
Tejun Heo7d50b602007-09-23 13:19:54 +09001965 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1966 host_ehi->err_mask |= AC_ERR_HOST_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09001967 host_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09001968 ata_ehi_push_desc(host_ehi, "host bus error");
1969 }
1970
1971 if (irq_stat & PORT_IRQ_IF_ERR) {
1972 host_ehi->err_mask |= AC_ERR_ATA_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09001973 host_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09001974 ata_ehi_push_desc(host_ehi, "interface fatal error");
1975 }
1976
1977 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1978 ata_ehi_hotplugged(host_ehi);
1979 ata_ehi_push_desc(host_ehi, "%s",
1980 irq_stat & PORT_IRQ_CONNECT ?
1981 "connection status changed" : "PHY RDY changed");
1982 }
1983
1984 /* okay, let's hand over to EH */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001985
Tejun Heo78cd52d2006-05-15 20:58:29 +09001986 if (irq_stat & PORT_IRQ_FREEZE)
1987 ata_port_freeze(ap);
1988 else
1989 ata_port_abort(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001990}
1991
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001992static void ahci_port_intr(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001993{
Tejun Heo350756f2008-04-07 22:47:21 +09001994 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo9af5c9c2007-08-06 18:36:22 +09001995 struct ata_eh_info *ehi = &ap->link.eh_info;
Tejun Heo0291f952007-01-25 19:16:28 +09001996 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo5f226c62007-10-09 15:02:23 +09001997 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heob06ce3e2007-10-09 15:06:48 +09001998 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001999 u32 status, qc_active;
Tejun Heo459ad682007-12-07 12:46:23 +09002000 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002001
2002 status = readl(port_mmio + PORT_IRQ_STAT);
2003 writel(status, port_mmio + PORT_IRQ_STAT);
2004
Tejun Heob06ce3e2007-10-09 15:06:48 +09002005 /* ignore BAD_PMP while resetting */
2006 if (unlikely(resetting))
2007 status &= ~PORT_IRQ_BAD_PMP;
2008
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04002009 /* If we are getting PhyRdy, this is
2010 * just a power state change, we should
2011 * clear out this, plus the PhyRdy/Comm
2012 * Wake bits from Serror
2013 */
2014 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2015 (status & PORT_IRQ_PHYRDY)) {
2016 status &= ~PORT_IRQ_PHYRDY;
2017 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
2018 }
2019
Tejun Heo78cd52d2006-05-15 20:58:29 +09002020 if (unlikely(status & PORT_IRQ_ERROR)) {
2021 ahci_error_intr(ap, status);
2022 return;
2023 }
2024
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04002025 if (status & PORT_IRQ_SDB_FIS) {
Tejun Heo5f226c62007-10-09 15:02:23 +09002026 /* If SNotification is available, leave notification
2027 * handling to sata_async_notification(). If not,
2028 * emulate it by snooping SDB FIS RX area.
2029 *
2030 * Snooping FIS RX area is probably cheaper than
2031 * poking SNotification but some constrollers which
2032 * implement SNotification, ICH9 for example, don't
2033 * store AN SDB FIS into receive area.
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04002034 */
Tejun Heo5f226c62007-10-09 15:02:23 +09002035 if (hpriv->cap & HOST_CAP_SNTF)
Tejun Heo7d77b242007-09-23 13:14:13 +09002036 sata_async_notification(ap);
Tejun Heo5f226c62007-10-09 15:02:23 +09002037 else {
2038 /* If the 'N' bit in word 0 of the FIS is set,
2039 * we just received asynchronous notification.
2040 * Tell libata about it.
2041 */
2042 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2043 u32 f0 = le32_to_cpu(f[0]);
2044
2045 if (f0 & (1 << 15))
2046 sata_async_notification(ap);
2047 }
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04002048 }
2049
Tejun Heo7d50b602007-09-23 13:19:54 +09002050 /* pp->active_link is valid iff any command is in flight */
2051 if (ap->qc_active && pp->active_link->sactive)
Tejun Heo12fad3f2006-05-15 21:03:55 +09002052 qc_active = readl(port_mmio + PORT_SCR_ACT);
2053 else
2054 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2055
Tejun Heo79f97da2008-04-07 22:47:20 +09002056 rc = ata_qc_complete_multiple(ap, qc_active);
Tejun Heob06ce3e2007-10-09 15:06:48 +09002057
Tejun Heo459ad682007-12-07 12:46:23 +09002058 /* while resetting, invalid completions are expected */
2059 if (unlikely(rc < 0 && !resetting)) {
Tejun Heo12fad3f2006-05-15 21:03:55 +09002060 ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09002061 ehi->action |= ATA_EH_RESET;
Tejun Heo12fad3f2006-05-15 21:03:55 +09002062 ata_port_freeze(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002063 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002064}
2065
David Howells7d12e782006-10-05 14:55:46 +01002066static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002067{
Jeff Garzikcca39742006-08-24 03:19:22 -04002068 struct ata_host *host = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002069 struct ahci_host_priv *hpriv;
2070 unsigned int i, handled = 0;
Jeff Garzikea6ba102005-08-30 05:18:18 -04002071 void __iomem *mmio;
Tejun Heod28f87a2008-07-05 13:10:50 +09002072 u32 irq_stat, irq_masked;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002073
2074 VPRINTK("ENTER\n");
2075
Jeff Garzikcca39742006-08-24 03:19:22 -04002076 hpriv = host->private_data;
Tejun Heo0d5ff562007-02-01 15:06:36 +09002077 mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002078
2079 /* sigh. 0xffffffff is a valid return from h/w */
2080 irq_stat = readl(mmio + HOST_IRQ_STAT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002081 if (!irq_stat)
2082 return IRQ_NONE;
2083
Tejun Heod28f87a2008-07-05 13:10:50 +09002084 irq_masked = irq_stat & hpriv->port_map;
2085
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002086 spin_lock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002087
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002088 for (i = 0; i < host->n_ports; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002089 struct ata_port *ap;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002090
Tejun Heod28f87a2008-07-05 13:10:50 +09002091 if (!(irq_masked & (1 << i)))
Jeff Garzik67846b32005-10-05 02:58:32 -04002092 continue;
2093
Jeff Garzikcca39742006-08-24 03:19:22 -04002094 ap = host->ports[i];
Jeff Garzik67846b32005-10-05 02:58:32 -04002095 if (ap) {
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002096 ahci_port_intr(ap);
Jeff Garzik67846b32005-10-05 02:58:32 -04002097 VPRINTK("port %u\n", i);
2098 } else {
2099 VPRINTK("port %u (no irq)\n", i);
Tejun Heo6971ed12006-03-11 12:47:54 +09002100 if (ata_ratelimit())
Jeff Garzikcca39742006-08-24 03:19:22 -04002101 dev_printk(KERN_WARNING, host->dev,
Jeff Garzika9524a72005-10-30 14:39:11 -05002102 "interrupt on disabled port %u\n", i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002103 }
Jeff Garzik67846b32005-10-05 02:58:32 -04002104
Linus Torvalds1da177e2005-04-16 15:20:36 -07002105 handled = 1;
2106 }
2107
Tejun Heod28f87a2008-07-05 13:10:50 +09002108 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2109 * it should be cleared after all the port events are cleared;
2110 * otherwise, it will raise a spurious interrupt after each
2111 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2112 * information.
2113 *
2114 * Also, use the unmasked value to clear interrupt as spurious
2115 * pending event on a dummy port might cause screaming IRQ.
2116 */
Tejun Heoea0c62f2008-06-28 01:49:02 +09002117 writel(irq_stat, mmio + HOST_IRQ_STAT);
2118
Jeff Garzikcca39742006-08-24 03:19:22 -04002119 spin_unlock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002120
2121 VPRINTK("EXIT\n");
2122
2123 return IRQ_RETVAL(handled);
2124}
2125
Tejun Heo9a3d9eb2006-01-23 13:09:36 +09002126static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002127{
2128 struct ata_port *ap = qc->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09002129 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7d50b602007-09-23 13:19:54 +09002130 struct ahci_port_priv *pp = ap->private_data;
2131
2132 /* Keep track of the currently active link. It will be used
2133 * in completion path to determine whether NCQ phase is in
2134 * progress.
2135 */
2136 pp->active_link = qc->dev->link;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002137
Tejun Heo12fad3f2006-05-15 21:03:55 +09002138 if (qc->tf.protocol == ATA_PROT_NCQ)
2139 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2140 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002141
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002142 ahci_sw_activity(qc->dev->link);
2143
Linus Torvalds1da177e2005-04-16 15:20:36 -07002144 return 0;
2145}
2146
Tejun Heo4c9bf4e2008-04-07 22:47:20 +09002147static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2148{
2149 struct ahci_port_priv *pp = qc->ap->private_data;
2150 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2151
2152 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2153 return true;
2154}
2155
Tejun Heo78cd52d2006-05-15 20:58:29 +09002156static void ahci_freeze(struct ata_port *ap)
2157{
Tejun Heo4447d352007-04-17 23:44:08 +09002158 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002159
2160 /* turn IRQ off */
2161 writel(0, port_mmio + PORT_IRQ_MASK);
2162}
2163
2164static void ahci_thaw(struct ata_port *ap)
2165{
Tejun Heo0d5ff562007-02-01 15:06:36 +09002166 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
Tejun Heo4447d352007-04-17 23:44:08 +09002167 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002168 u32 tmp;
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002169 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo78cd52d2006-05-15 20:58:29 +09002170
2171 /* clear IRQ */
2172 tmp = readl(port_mmio + PORT_IRQ_STAT);
2173 writel(tmp, port_mmio + PORT_IRQ_STAT);
Tejun Heoa7187282007-01-27 11:04:26 +09002174 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002175
Tejun Heo1c954a42007-10-09 15:01:37 +09002176 /* turn IRQ back on */
2177 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002178}
2179
2180static void ahci_error_handler(struct ata_port *ap)
2181{
Tejun Heob51e9e52006-06-29 01:29:30 +09002182 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
Tejun Heo78cd52d2006-05-15 20:58:29 +09002183 /* restart engine */
Tejun Heo4447d352007-04-17 23:44:08 +09002184 ahci_stop_engine(ap);
2185 ahci_start_engine(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002186 }
2187
Tejun Heoa1efdab2008-03-25 12:22:50 +09002188 sata_pmp_error_handler(ap);
Tejun Heoedc93052007-10-25 14:59:16 +09002189}
2190
Tejun Heo78cd52d2006-05-15 20:58:29 +09002191static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2192{
2193 struct ata_port *ap = qc->ap;
2194
Tejun Heod2e75df2007-07-16 14:29:39 +09002195 /* make DMA engine forget about the failed command */
2196 if (qc->flags & ATA_QCFLAG_FAILED)
2197 ahci_kick_engine(ap, 1);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002198}
2199
Tejun Heo7d50b602007-09-23 13:19:54 +09002200static void ahci_pmp_attach(struct ata_port *ap)
2201{
2202 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo1c954a42007-10-09 15:01:37 +09002203 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09002204 u32 cmd;
2205
2206 cmd = readl(port_mmio + PORT_CMD);
2207 cmd |= PORT_CMD_PMP;
2208 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo1c954a42007-10-09 15:01:37 +09002209
2210 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2211 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo7d50b602007-09-23 13:19:54 +09002212}
2213
2214static void ahci_pmp_detach(struct ata_port *ap)
2215{
2216 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo1c954a42007-10-09 15:01:37 +09002217 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09002218 u32 cmd;
2219
2220 cmd = readl(port_mmio + PORT_CMD);
2221 cmd &= ~PORT_CMD_PMP;
2222 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo1c954a42007-10-09 15:01:37 +09002223
2224 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2225 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo7d50b602007-09-23 13:19:54 +09002226}
2227
Alexey Dobriyan028a2592007-07-17 23:48:48 +04002228static int ahci_port_resume(struct ata_port *ap)
2229{
2230 ahci_power_up(ap);
2231 ahci_start_port(ap);
2232
Tejun Heo071f44b2008-04-07 22:47:22 +09002233 if (sata_pmp_attached(ap))
Tejun Heo7d50b602007-09-23 13:19:54 +09002234 ahci_pmp_attach(ap);
2235 else
2236 ahci_pmp_detach(ap);
2237
Alexey Dobriyan028a2592007-07-17 23:48:48 +04002238 return 0;
2239}
2240
Tejun Heo438ac6d2007-03-02 17:31:26 +09002241#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +09002242static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2243{
Tejun Heoc1332872006-07-26 15:59:26 +09002244 const char *emsg = NULL;
2245 int rc;
2246
Tejun Heo4447d352007-04-17 23:44:08 +09002247 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo8e16f942006-11-20 15:42:36 +09002248 if (rc == 0)
Tejun Heo4447d352007-04-17 23:44:08 +09002249 ahci_power_down(ap);
Tejun Heo8e16f942006-11-20 15:42:36 +09002250 else {
Tejun Heoc1332872006-07-26 15:59:26 +09002251 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002252 ahci_start_port(ap);
Tejun Heoc1332872006-07-26 15:59:26 +09002253 }
2254
2255 return rc;
2256}
2257
Tejun Heoc1332872006-07-26 15:59:26 +09002258static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2259{
Jeff Garzikcca39742006-08-24 03:19:22 -04002260 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09002261 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heoc1332872006-07-26 15:59:26 +09002262 u32 ctl;
2263
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +01002264 if (mesg.event & PM_EVENT_SLEEP) {
Tejun Heoc1332872006-07-26 15:59:26 +09002265 /* AHCI spec rev1.1 section 8.3.3:
2266 * Software must disable interrupts prior to requesting a
2267 * transition of the HBA to D3 state.
2268 */
2269 ctl = readl(mmio + HOST_CTL);
2270 ctl &= ~HOST_IRQ_EN;
2271 writel(ctl, mmio + HOST_CTL);
2272 readl(mmio + HOST_CTL); /* flush */
2273 }
2274
2275 return ata_pci_device_suspend(pdev, mesg);
2276}
2277
2278static int ahci_pci_device_resume(struct pci_dev *pdev)
2279{
Jeff Garzikcca39742006-08-24 03:19:22 -04002280 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heoc1332872006-07-26 15:59:26 +09002281 int rc;
2282
Tejun Heo553c4aa2006-12-26 19:39:50 +09002283 rc = ata_pci_device_do_resume(pdev);
2284 if (rc)
2285 return rc;
Tejun Heoc1332872006-07-26 15:59:26 +09002286
2287 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Tejun Heo4447d352007-04-17 23:44:08 +09002288 rc = ahci_reset_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002289 if (rc)
2290 return rc;
2291
Tejun Heo4447d352007-04-17 23:44:08 +09002292 ahci_init_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002293 }
2294
Jeff Garzikcca39742006-08-24 03:19:22 -04002295 ata_host_resume(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002296
2297 return 0;
2298}
Tejun Heo438ac6d2007-03-02 17:31:26 +09002299#endif
Tejun Heoc1332872006-07-26 15:59:26 +09002300
Tejun Heo254950c2006-07-26 15:59:25 +09002301static int ahci_port_start(struct ata_port *ap)
2302{
Jeff Garzikcca39742006-08-24 03:19:22 -04002303 struct device *dev = ap->host->dev;
Tejun Heo254950c2006-07-26 15:59:25 +09002304 struct ahci_port_priv *pp;
Tejun Heo254950c2006-07-26 15:59:25 +09002305 void *mem;
2306 dma_addr_t mem_dma;
Tejun Heo254950c2006-07-26 15:59:25 +09002307
Tejun Heo24dc5f32007-01-20 16:00:28 +09002308 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
Tejun Heo254950c2006-07-26 15:59:25 +09002309 if (!pp)
2310 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09002311
Tejun Heo24dc5f32007-01-20 16:00:28 +09002312 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2313 GFP_KERNEL);
2314 if (!mem)
Tejun Heo254950c2006-07-26 15:59:25 +09002315 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09002316 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2317
2318 /*
2319 * First item in chunk of DMA memory: 32-slot command table,
2320 * 32 bytes each in size
2321 */
2322 pp->cmd_slot = mem;
2323 pp->cmd_slot_dma = mem_dma;
2324
2325 mem += AHCI_CMD_SLOT_SZ;
2326 mem_dma += AHCI_CMD_SLOT_SZ;
2327
2328 /*
2329 * Second item: Received-FIS area
2330 */
2331 pp->rx_fis = mem;
2332 pp->rx_fis_dma = mem_dma;
2333
2334 mem += AHCI_RX_FIS_SZ;
2335 mem_dma += AHCI_RX_FIS_SZ;
2336
2337 /*
2338 * Third item: data area for storing a single command
2339 * and its scatter-gather table
2340 */
2341 pp->cmd_tbl = mem;
2342 pp->cmd_tbl_dma = mem_dma;
2343
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002344 /*
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002345 * Save off initial list of interrupts to be enabled.
2346 * This could be changed later
2347 */
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002348 pp->intr_mask = DEF_PORT_IRQ;
2349
Tejun Heo254950c2006-07-26 15:59:25 +09002350 ap->private_data = pp;
2351
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002352 /* engage engines, captain */
2353 return ahci_port_resume(ap);
Tejun Heo254950c2006-07-26 15:59:25 +09002354}
2355
2356static void ahci_port_stop(struct ata_port *ap)
2357{
Tejun Heo0be0aa92006-07-26 15:59:26 +09002358 const char *emsg = NULL;
2359 int rc;
Tejun Heo254950c2006-07-26 15:59:25 +09002360
Tejun Heo0be0aa92006-07-26 15:59:26 +09002361 /* de-initialize port */
Tejun Heo4447d352007-04-17 23:44:08 +09002362 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo0be0aa92006-07-26 15:59:26 +09002363 if (rc)
2364 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
Tejun Heo254950c2006-07-26 15:59:25 +09002365}
2366
Tejun Heo4447d352007-04-17 23:44:08 +09002367static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002368{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002369 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002370
Linus Torvalds1da177e2005-04-16 15:20:36 -07002371 if (using_dac &&
2372 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2373 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2374 if (rc) {
2375 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2376 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002377 dev_printk(KERN_ERR, &pdev->dev,
2378 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002379 return rc;
2380 }
2381 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002382 } else {
2383 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2384 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002385 dev_printk(KERN_ERR, &pdev->dev,
2386 "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002387 return rc;
2388 }
2389 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2390 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002391 dev_printk(KERN_ERR, &pdev->dev,
2392 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002393 return rc;
2394 }
2395 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002396 return 0;
2397}
2398
Tejun Heo4447d352007-04-17 23:44:08 +09002399static void ahci_print_info(struct ata_host *host)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002400{
Tejun Heo4447d352007-04-17 23:44:08 +09002401 struct ahci_host_priv *hpriv = host->private_data;
2402 struct pci_dev *pdev = to_pci_dev(host->dev);
2403 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002404 u32 vers, cap, impl, speed;
2405 const char *speed_s;
2406 u16 cc;
2407 const char *scc_s;
2408
2409 vers = readl(mmio + HOST_VERSION);
2410 cap = hpriv->cap;
2411 impl = hpriv->port_map;
2412
2413 speed = (cap >> 20) & 0xf;
2414 if (speed == 1)
2415 speed_s = "1.5";
2416 else if (speed == 2)
2417 speed_s = "3";
2418 else
2419 speed_s = "?";
2420
2421 pci_read_config_word(pdev, 0x0a, &cc);
Conke Huc9f89472007-01-09 05:32:51 -05002422 if (cc == PCI_CLASS_STORAGE_IDE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002423 scc_s = "IDE";
Conke Huc9f89472007-01-09 05:32:51 -05002424 else if (cc == PCI_CLASS_STORAGE_SATA)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002425 scc_s = "SATA";
Conke Huc9f89472007-01-09 05:32:51 -05002426 else if (cc == PCI_CLASS_STORAGE_RAID)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002427 scc_s = "RAID";
2428 else
2429 scc_s = "unknown";
2430
Jeff Garzika9524a72005-10-30 14:39:11 -05002431 dev_printk(KERN_INFO, &pdev->dev,
2432 "AHCI %02x%02x.%02x%02x "
Linus Torvalds1da177e2005-04-16 15:20:36 -07002433 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002434 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002435
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002436 (vers >> 24) & 0xff,
2437 (vers >> 16) & 0xff,
2438 (vers >> 8) & 0xff,
2439 vers & 0xff,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002440
2441 ((cap >> 8) & 0x1f) + 1,
2442 (cap & 0x1f) + 1,
2443 speed_s,
2444 impl,
2445 scc_s);
2446
Jeff Garzika9524a72005-10-30 14:39:11 -05002447 dev_printk(KERN_INFO, &pdev->dev,
2448 "flags: "
Tejun Heo203ef6c2007-07-16 14:29:40 +09002449 "%s%s%s%s%s%s%s"
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002450 "%s%s%s%s%s%s%s"
2451 "%s\n"
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002452 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002453
2454 cap & (1 << 31) ? "64bit " : "",
2455 cap & (1 << 30) ? "ncq " : "",
Tejun Heo203ef6c2007-07-16 14:29:40 +09002456 cap & (1 << 29) ? "sntf " : "",
Linus Torvalds1da177e2005-04-16 15:20:36 -07002457 cap & (1 << 28) ? "ilck " : "",
2458 cap & (1 << 27) ? "stag " : "",
2459 cap & (1 << 26) ? "pm " : "",
2460 cap & (1 << 25) ? "led " : "",
2461
2462 cap & (1 << 24) ? "clo " : "",
2463 cap & (1 << 19) ? "nz " : "",
2464 cap & (1 << 18) ? "only " : "",
2465 cap & (1 << 17) ? "pmp " : "",
2466 cap & (1 << 15) ? "pio " : "",
2467 cap & (1 << 14) ? "slum " : "",
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002468 cap & (1 << 13) ? "part " : "",
2469 cap & (1 << 6) ? "ems ": ""
Linus Torvalds1da177e2005-04-16 15:20:36 -07002470 );
2471}
2472
Tejun Heoedc93052007-10-25 14:59:16 +09002473/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2474 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2475 * support PMP and the 4726 either directly exports the device
2476 * attached to the first downstream port or acts as a hardware storage
2477 * controller and emulate a single ATA device (can be RAID 0/1 or some
2478 * other configuration).
2479 *
2480 * When there's no device attached to the first downstream port of the
2481 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2482 * configure the 4726. However, ATA emulation of the device is very
2483 * lame. It doesn't send signature D2H Reg FIS after the initial
2484 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2485 *
2486 * The following function works around the problem by always using
2487 * hardreset on the port and not depending on receiving signature FIS
2488 * afterward. If signature FIS isn't received soon, ATA class is
2489 * assumed without follow-up softreset.
2490 */
2491static void ahci_p5wdh_workaround(struct ata_host *host)
2492{
2493 static struct dmi_system_id sysids[] = {
2494 {
2495 .ident = "P5W DH Deluxe",
2496 .matches = {
2497 DMI_MATCH(DMI_SYS_VENDOR,
2498 "ASUSTEK COMPUTER INC"),
2499 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2500 },
2501 },
2502 { }
2503 };
2504 struct pci_dev *pdev = to_pci_dev(host->dev);
2505
2506 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2507 dmi_check_system(sysids)) {
2508 struct ata_port *ap = host->ports[1];
2509
2510 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2511 "Deluxe on-board SIMG4726 workaround\n");
2512
2513 ap->ops = &ahci_p5wdh_ops;
2514 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2515 }
2516}
2517
Tejun Heo24dc5f32007-01-20 16:00:28 +09002518static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002519{
2520 static int printed_version;
Tejun Heoe297d992008-06-10 00:13:04 +09002521 unsigned int board_id = ent->driver_data;
2522 struct ata_port_info pi = ahci_port_info[board_id];
Tejun Heo4447d352007-04-17 23:44:08 +09002523 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo24dc5f32007-01-20 16:00:28 +09002524 struct device *dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002525 struct ahci_host_priv *hpriv;
Tejun Heo4447d352007-04-17 23:44:08 +09002526 struct ata_host *host;
Tejun Heo837f5f82008-02-06 15:13:51 +09002527 int n_ports, i, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002528
2529 VPRINTK("ENTER\n");
2530
Tejun Heo12fad3f2006-05-15 21:03:55 +09002531 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2532
Linus Torvalds1da177e2005-04-16 15:20:36 -07002533 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05002534 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002535
Tejun Heo4447d352007-04-17 23:44:08 +09002536 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09002537 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002538 if (rc)
2539 return rc;
2540
Tejun Heodea55132008-03-11 19:52:31 +09002541 /* AHCI controllers often implement SFF compatible interface.
2542 * Grab all PCI BARs just in case.
2543 */
2544 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
Tejun Heo0d5ff562007-02-01 15:06:36 +09002545 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002546 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09002547 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002548 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002549
Tejun Heoc4f77922007-12-06 15:09:43 +09002550 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2551 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2552 u8 map;
2553
2554 /* ICH6s share the same PCI ID for both piix and ahci
2555 * modes. Enabling ahci mode while MAP indicates
2556 * combined mode is a bad idea. Yield to ata_piix.
2557 */
2558 pci_read_config_byte(pdev, ICH_MAP, &map);
2559 if (map & 0x3) {
2560 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2561 "combined mode, can't enable AHCI mode\n");
2562 return -ENODEV;
2563 }
2564 }
2565
Tejun Heo24dc5f32007-01-20 16:00:28 +09002566 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2567 if (!hpriv)
2568 return -ENOMEM;
Tejun Heo417a1a62007-09-23 13:19:55 +09002569 hpriv->flags |= (unsigned long)pi.private_data;
2570
Tejun Heoe297d992008-06-10 00:13:04 +09002571 /* MCP65 revision A1 and A2 can't do MSI */
2572 if (board_id == board_ahci_mcp65 &&
2573 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2574 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2575
Tejun Heo417a1a62007-09-23 13:19:55 +09002576 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2577 pci_intx(pdev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002578
Tejun Heo4447d352007-04-17 23:44:08 +09002579 /* save initial config */
Tejun Heo417a1a62007-09-23 13:19:55 +09002580 ahci_save_initial_config(pdev, hpriv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002581
Tejun Heo4447d352007-04-17 23:44:08 +09002582 /* prepare host */
Tejun Heo274c1fd2007-07-16 14:29:40 +09002583 if (hpriv->cap & HOST_CAP_NCQ)
Tejun Heo4447d352007-04-17 23:44:08 +09002584 pi.flags |= ATA_FLAG_NCQ;
2585
Tejun Heo7d50b602007-09-23 13:19:54 +09002586 if (hpriv->cap & HOST_CAP_PMP)
2587 pi.flags |= ATA_FLAG_PMP;
2588
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002589 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
2590 u8 messages;
2591 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
2592 u32 em_loc = readl(mmio + HOST_EM_LOC);
2593 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2594
2595 messages = (em_ctl & 0x000f0000) >> 16;
2596
2597 /* we only support LED message type right now */
2598 if ((messages & 0x01) && (ahci_em_messages == 1)) {
2599 /* store em_loc */
2600 hpriv->em_loc = ((em_loc >> 16) * 4);
2601 pi.flags |= ATA_FLAG_EM;
2602 if (!(em_ctl & EM_CTL_ALHD))
2603 pi.flags |= ATA_FLAG_SW_ACTIVITY;
2604 }
2605 }
2606
Tejun Heo837f5f82008-02-06 15:13:51 +09002607 /* CAP.NP sometimes indicate the index of the last enabled
2608 * port, at other times, that of the last possible port, so
2609 * determining the maximum port number requires looking at
2610 * both CAP.NP and port_map.
2611 */
2612 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2613
2614 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
Tejun Heo4447d352007-04-17 23:44:08 +09002615 if (!host)
2616 return -ENOMEM;
2617 host->iomap = pcim_iomap_table(pdev);
2618 host->private_data = hpriv;
2619
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002620 if (pi.flags & ATA_FLAG_EM)
2621 ahci_reset_em(host);
2622
Tejun Heo4447d352007-04-17 23:44:08 +09002623 for (i = 0; i < host->n_ports; i++) {
Jeff Garzikdab632e2007-05-28 08:33:01 -04002624 struct ata_port *ap = host->ports[i];
Tejun Heo4447d352007-04-17 23:44:08 +09002625
Tejun Heocbcdd872007-08-18 13:14:55 +09002626 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2627 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2628 0x100 + ap->port_no * 0x80, "port");
2629
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04002630 /* set initial link pm policy */
2631 ap->pm_policy = NOT_AVAILABLE;
2632
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002633 /* set enclosure management message type */
2634 if (ap->flags & ATA_FLAG_EM)
2635 ap->em_message_type = ahci_em_messages;
2636
2637
Jeff Garzikdab632e2007-05-28 08:33:01 -04002638 /* disabled/not-implemented port */
Tejun Heo350756f2008-04-07 22:47:21 +09002639 if (!(hpriv->port_map & (1 << i)))
Jeff Garzikdab632e2007-05-28 08:33:01 -04002640 ap->ops = &ata_dummy_port_ops;
Tejun Heo4447d352007-04-17 23:44:08 +09002641 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002642
Tejun Heoedc93052007-10-25 14:59:16 +09002643 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2644 ahci_p5wdh_workaround(host);
2645
Linus Torvalds1da177e2005-04-16 15:20:36 -07002646 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09002647 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002648 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002649 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002650
Tejun Heo4447d352007-04-17 23:44:08 +09002651 rc = ahci_reset_controller(host);
2652 if (rc)
2653 return rc;
Tejun Heo12fad3f2006-05-15 21:03:55 +09002654
Tejun Heo4447d352007-04-17 23:44:08 +09002655 ahci_init_controller(host);
2656 ahci_print_info(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002657
Tejun Heo4447d352007-04-17 23:44:08 +09002658 pci_set_master(pdev);
2659 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2660 &ahci_sht);
Jeff Garzik907f4672005-05-12 15:03:42 -04002661}
Linus Torvalds1da177e2005-04-16 15:20:36 -07002662
2663static int __init ahci_init(void)
2664{
Pavel Roskinb7887192006-08-10 18:13:18 +09002665 return pci_register_driver(&ahci_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002666}
2667
Linus Torvalds1da177e2005-04-16 15:20:36 -07002668static void __exit ahci_exit(void)
2669{
2670 pci_unregister_driver(&ahci_pci_driver);
2671}
2672
2673
2674MODULE_AUTHOR("Jeff Garzik");
2675MODULE_DESCRIPTION("AHCI SATA low-level driver");
2676MODULE_LICENSE("GPL");
2677MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04002678MODULE_VERSION(DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002679
2680module_init(ahci_init);
2681module_exit(ahci_exit);