Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: Dave Airlie |
| 24 | * Alex Deucher |
| 25 | */ |
| 26 | #include <drm/drmP.h> |
| 27 | #include <drm/drm_crtc_helper.h> |
| 28 | #include <drm/radeon_drm.h> |
Ben Skeggs | 68adac5 | 2010-04-28 11:46:42 +1000 | [diff] [blame] | 29 | #include <drm/drm_fixed.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 30 | #include "radeon.h" |
| 31 | #include "atom.h" |
| 32 | #include "atom-bits.h" |
| 33 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 34 | static void atombios_overscan_setup(struct drm_crtc *crtc, |
| 35 | struct drm_display_mode *mode, |
| 36 | struct drm_display_mode *adjusted_mode) |
| 37 | { |
| 38 | struct drm_device *dev = crtc->dev; |
| 39 | struct radeon_device *rdev = dev->dev_private; |
| 40 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 41 | SET_CRTC_OVERSCAN_PS_ALLOCATION args; |
| 42 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); |
| 43 | int a1, a2; |
| 44 | |
| 45 | memset(&args, 0, sizeof(args)); |
| 46 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 47 | args.ucCRTC = radeon_crtc->crtc_id; |
| 48 | |
| 49 | switch (radeon_crtc->rmx_type) { |
| 50 | case RMX_CENTER: |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 51 | args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); |
| 52 | args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); |
| 53 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); |
| 54 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 55 | break; |
| 56 | case RMX_ASPECT: |
| 57 | a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; |
| 58 | a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; |
| 59 | |
| 60 | if (a1 > a2) { |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 61 | args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); |
| 62 | args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 63 | } else if (a2 > a1) { |
Alex Deucher | 942b0e9 | 2011-03-14 23:18:00 -0400 | [diff] [blame] | 64 | args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); |
| 65 | args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 66 | } |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 67 | break; |
| 68 | case RMX_FULL: |
| 69 | default: |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 70 | args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); |
| 71 | args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); |
| 72 | args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); |
| 73 | args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 74 | break; |
| 75 | } |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 76 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | static void atombios_scaler_setup(struct drm_crtc *crtc) |
| 80 | { |
| 81 | struct drm_device *dev = crtc->dev; |
| 82 | struct radeon_device *rdev = dev->dev_private; |
| 83 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 84 | ENABLE_SCALER_PS_ALLOCATION args; |
| 85 | int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 86 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 87 | /* fixme - fill in enc_priv for atom dac */ |
| 88 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 89 | bool is_tv = false, is_cv = false; |
| 90 | struct drm_encoder *encoder; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 91 | |
| 92 | if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) |
| 93 | return; |
| 94 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 95 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 96 | /* find tv std */ |
| 97 | if (encoder->crtc == crtc) { |
| 98 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 99 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
| 100 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
| 101 | tv_std = tv_dac->tv_std; |
| 102 | is_tv = true; |
| 103 | } |
| 104 | } |
| 105 | } |
| 106 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 107 | memset(&args, 0, sizeof(args)); |
| 108 | |
| 109 | args.ucScaler = radeon_crtc->crtc_id; |
| 110 | |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 111 | if (is_tv) { |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 112 | switch (tv_std) { |
| 113 | case TV_STD_NTSC: |
| 114 | default: |
| 115 | args.ucTVStandard = ATOM_TV_NTSC; |
| 116 | break; |
| 117 | case TV_STD_PAL: |
| 118 | args.ucTVStandard = ATOM_TV_PAL; |
| 119 | break; |
| 120 | case TV_STD_PAL_M: |
| 121 | args.ucTVStandard = ATOM_TV_PALM; |
| 122 | break; |
| 123 | case TV_STD_PAL_60: |
| 124 | args.ucTVStandard = ATOM_TV_PAL60; |
| 125 | break; |
| 126 | case TV_STD_NTSC_J: |
| 127 | args.ucTVStandard = ATOM_TV_NTSCJ; |
| 128 | break; |
| 129 | case TV_STD_SCART_PAL: |
| 130 | args.ucTVStandard = ATOM_TV_PAL; /* ??? */ |
| 131 | break; |
| 132 | case TV_STD_SECAM: |
| 133 | args.ucTVStandard = ATOM_TV_SECAM; |
| 134 | break; |
| 135 | case TV_STD_PAL_CN: |
| 136 | args.ucTVStandard = ATOM_TV_PALCN; |
| 137 | break; |
| 138 | } |
| 139 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 140 | } else if (is_cv) { |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 141 | args.ucTVStandard = ATOM_TV_CV; |
| 142 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
| 143 | } else { |
| 144 | switch (radeon_crtc->rmx_type) { |
| 145 | case RMX_FULL: |
| 146 | args.ucEnable = ATOM_SCALER_EXPANSION; |
| 147 | break; |
| 148 | case RMX_CENTER: |
| 149 | args.ucEnable = ATOM_SCALER_CENTER; |
| 150 | break; |
| 151 | case RMX_ASPECT: |
| 152 | args.ucEnable = ATOM_SCALER_EXPANSION; |
| 153 | break; |
| 154 | default: |
| 155 | if (ASIC_IS_AVIVO(rdev)) |
| 156 | args.ucEnable = ATOM_SCALER_DISABLE; |
| 157 | else |
| 158 | args.ucEnable = ATOM_SCALER_CENTER; |
| 159 | break; |
| 160 | } |
| 161 | } |
| 162 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 163 | if ((is_tv || is_cv) |
| 164 | && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { |
| 165 | atom_rv515_force_tv_scaler(rdev, radeon_crtc); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 166 | } |
| 167 | } |
| 168 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 169 | static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) |
| 170 | { |
| 171 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 172 | struct drm_device *dev = crtc->dev; |
| 173 | struct radeon_device *rdev = dev->dev_private; |
| 174 | int index = |
| 175 | GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); |
| 176 | ENABLE_CRTC_PS_ALLOCATION args; |
| 177 | |
| 178 | memset(&args, 0, sizeof(args)); |
| 179 | |
| 180 | args.ucCRTC = radeon_crtc->crtc_id; |
| 181 | args.ucEnable = lock; |
| 182 | |
| 183 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 184 | } |
| 185 | |
| 186 | static void atombios_enable_crtc(struct drm_crtc *crtc, int state) |
| 187 | { |
| 188 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 189 | struct drm_device *dev = crtc->dev; |
| 190 | struct radeon_device *rdev = dev->dev_private; |
| 191 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); |
| 192 | ENABLE_CRTC_PS_ALLOCATION args; |
| 193 | |
| 194 | memset(&args, 0, sizeof(args)); |
| 195 | |
| 196 | args.ucCRTC = radeon_crtc->crtc_id; |
| 197 | args.ucEnable = state; |
| 198 | |
| 199 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 200 | } |
| 201 | |
| 202 | static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) |
| 203 | { |
| 204 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 205 | struct drm_device *dev = crtc->dev; |
| 206 | struct radeon_device *rdev = dev->dev_private; |
| 207 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); |
| 208 | ENABLE_CRTC_PS_ALLOCATION args; |
| 209 | |
| 210 | memset(&args, 0, sizeof(args)); |
| 211 | |
| 212 | args.ucCRTC = radeon_crtc->crtc_id; |
| 213 | args.ucEnable = state; |
| 214 | |
| 215 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 216 | } |
| 217 | |
| 218 | static void atombios_blank_crtc(struct drm_crtc *crtc, int state) |
| 219 | { |
| 220 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 221 | struct drm_device *dev = crtc->dev; |
| 222 | struct radeon_device *rdev = dev->dev_private; |
| 223 | int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); |
| 224 | BLANK_CRTC_PS_ALLOCATION args; |
| 225 | |
| 226 | memset(&args, 0, sizeof(args)); |
| 227 | |
| 228 | args.ucCRTC = radeon_crtc->crtc_id; |
| 229 | args.ucBlanking = state; |
| 230 | |
| 231 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 232 | } |
| 233 | |
Alex Deucher | fef9f91 | 2012-03-20 17:18:03 -0400 | [diff] [blame] | 234 | static void atombios_powergate_crtc(struct drm_crtc *crtc, int state) |
| 235 | { |
| 236 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 237 | struct drm_device *dev = crtc->dev; |
| 238 | struct radeon_device *rdev = dev->dev_private; |
| 239 | int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); |
| 240 | ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; |
| 241 | |
| 242 | memset(&args, 0, sizeof(args)); |
| 243 | |
| 244 | args.ucDispPipeId = radeon_crtc->crtc_id; |
| 245 | args.ucEnable = state; |
| 246 | |
| 247 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 248 | } |
| 249 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 250 | void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 251 | { |
| 252 | struct drm_device *dev = crtc->dev; |
| 253 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | 500b758 | 2009-12-02 11:46:52 -0500 | [diff] [blame] | 254 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 255 | |
| 256 | switch (mode) { |
| 257 | case DRM_MODE_DPMS_ON: |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 258 | radeon_crtc->enabled = true; |
| 259 | /* adjust pm to dpms changes BEFORE enabling crtcs */ |
| 260 | radeon_pm_compute_clocks(rdev); |
Alex Deucher | fef9f91 | 2012-03-20 17:18:03 -0400 | [diff] [blame] | 261 | /* disable crtc pair power gating before programming */ |
| 262 | if (ASIC_IS_DCE6(rdev)) |
| 263 | atombios_powergate_crtc(crtc, ATOM_DISABLE); |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 264 | atombios_enable_crtc(crtc, ATOM_ENABLE); |
Alex Deucher | 79f17c6 | 2012-03-20 17:18:02 -0400 | [diff] [blame] | 265 | if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 266 | atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); |
| 267 | atombios_blank_crtc(crtc, ATOM_DISABLE); |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 268 | drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); |
Alex Deucher | 500b758 | 2009-12-02 11:46:52 -0500 | [diff] [blame] | 269 | radeon_crtc_load_lut(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 270 | break; |
| 271 | case DRM_MODE_DPMS_STANDBY: |
| 272 | case DRM_MODE_DPMS_SUSPEND: |
| 273 | case DRM_MODE_DPMS_OFF: |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 274 | drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); |
Alex Deucher | a93f344 | 2010-12-20 11:22:29 -0500 | [diff] [blame] | 275 | if (radeon_crtc->enabled) |
| 276 | atombios_blank_crtc(crtc, ATOM_ENABLE); |
Alex Deucher | 79f17c6 | 2012-03-20 17:18:02 -0400 | [diff] [blame] | 277 | if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 278 | atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); |
| 279 | atombios_enable_crtc(crtc, ATOM_DISABLE); |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 280 | radeon_crtc->enabled = false; |
Alex Deucher | fef9f91 | 2012-03-20 17:18:03 -0400 | [diff] [blame] | 281 | /* power gating is per-pair */ |
| 282 | if (ASIC_IS_DCE6(rdev)) { |
| 283 | struct drm_crtc *other_crtc; |
| 284 | struct radeon_crtc *other_radeon_crtc; |
| 285 | list_for_each_entry(other_crtc, &rdev->ddev->mode_config.crtc_list, head) { |
| 286 | other_radeon_crtc = to_radeon_crtc(other_crtc); |
| 287 | if (((radeon_crtc->crtc_id == 0) && (other_radeon_crtc->crtc_id == 1)) || |
| 288 | ((radeon_crtc->crtc_id == 1) && (other_radeon_crtc->crtc_id == 0)) || |
| 289 | ((radeon_crtc->crtc_id == 2) && (other_radeon_crtc->crtc_id == 3)) || |
| 290 | ((radeon_crtc->crtc_id == 3) && (other_radeon_crtc->crtc_id == 2)) || |
| 291 | ((radeon_crtc->crtc_id == 4) && (other_radeon_crtc->crtc_id == 5)) || |
| 292 | ((radeon_crtc->crtc_id == 5) && (other_radeon_crtc->crtc_id == 4))) { |
| 293 | /* if both crtcs in the pair are off, enable power gating */ |
| 294 | if (other_radeon_crtc->enabled == false) |
| 295 | atombios_powergate_crtc(crtc, ATOM_ENABLE); |
| 296 | break; |
| 297 | } |
| 298 | } |
| 299 | } |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 300 | /* adjust pm to dpms changes AFTER disabling crtcs */ |
| 301 | radeon_pm_compute_clocks(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 302 | break; |
| 303 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 304 | } |
| 305 | |
| 306 | static void |
| 307 | atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 308 | struct drm_display_mode *mode) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 309 | { |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 310 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 311 | struct drm_device *dev = crtc->dev; |
| 312 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 313 | SET_CRTC_USING_DTD_TIMING_PARAMETERS args; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 314 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 315 | u16 misc = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 316 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 317 | memset(&args, 0, sizeof(args)); |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 318 | args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 319 | args.usH_Blanking_Time = |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 320 | cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); |
| 321 | args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 322 | args.usV_Blanking_Time = |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 323 | cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 324 | args.usH_SyncOffset = |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 325 | cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 326 | args.usH_SyncWidth = |
| 327 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); |
| 328 | args.usV_SyncOffset = |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 329 | cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 330 | args.usV_SyncWidth = |
| 331 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); |
Alex Deucher | 5b1714d | 2010-08-03 19:59:20 -0400 | [diff] [blame] | 332 | args.ucH_Border = radeon_crtc->h_border; |
| 333 | args.ucV_Border = radeon_crtc->v_border; |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 334 | |
| 335 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 336 | misc |= ATOM_VSYNC_POLARITY; |
| 337 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 338 | misc |= ATOM_HSYNC_POLARITY; |
| 339 | if (mode->flags & DRM_MODE_FLAG_CSYNC) |
| 340 | misc |= ATOM_COMPOSITESYNC; |
| 341 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 342 | misc |= ATOM_INTERLACE; |
| 343 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 344 | misc |= ATOM_DOUBLE_CLOCK_MODE; |
| 345 | |
| 346 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); |
| 347 | args.ucCRTC = radeon_crtc->crtc_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 348 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 349 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 350 | } |
| 351 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 352 | static void atombios_crtc_set_timing(struct drm_crtc *crtc, |
| 353 | struct drm_display_mode *mode) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 354 | { |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 355 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 356 | struct drm_device *dev = crtc->dev; |
| 357 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 358 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 359 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 360 | u16 misc = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 361 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 362 | memset(&args, 0, sizeof(args)); |
| 363 | args.usH_Total = cpu_to_le16(mode->crtc_htotal); |
| 364 | args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); |
| 365 | args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); |
| 366 | args.usH_SyncWidth = |
| 367 | cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); |
| 368 | args.usV_Total = cpu_to_le16(mode->crtc_vtotal); |
| 369 | args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); |
| 370 | args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); |
| 371 | args.usV_SyncWidth = |
| 372 | cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); |
| 373 | |
Alex Deucher | 54bfe49 | 2010-09-03 15:52:53 -0400 | [diff] [blame] | 374 | args.ucOverscanRight = radeon_crtc->h_border; |
| 375 | args.ucOverscanLeft = radeon_crtc->h_border; |
| 376 | args.ucOverscanBottom = radeon_crtc->v_border; |
| 377 | args.ucOverscanTop = radeon_crtc->v_border; |
| 378 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 379 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 380 | misc |= ATOM_VSYNC_POLARITY; |
| 381 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 382 | misc |= ATOM_HSYNC_POLARITY; |
| 383 | if (mode->flags & DRM_MODE_FLAG_CSYNC) |
| 384 | misc |= ATOM_COMPOSITESYNC; |
| 385 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 386 | misc |= ATOM_INTERLACE; |
| 387 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 388 | misc |= ATOM_DOUBLE_CLOCK_MODE; |
| 389 | |
| 390 | args.susModeMiscInfo.usAccess = cpu_to_le16(misc); |
| 391 | args.ucCRTC = radeon_crtc->crtc_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 392 | |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 393 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 394 | } |
| 395 | |
Alex Deucher | 3fa47d9 | 2012-01-20 14:56:39 -0500 | [diff] [blame] | 396 | static void atombios_disable_ss(struct radeon_device *rdev, int pll_id) |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 397 | { |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 398 | u32 ss_cntl; |
| 399 | |
| 400 | if (ASIC_IS_DCE4(rdev)) { |
Alex Deucher | 3fa47d9 | 2012-01-20 14:56:39 -0500 | [diff] [blame] | 401 | switch (pll_id) { |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 402 | case ATOM_PPLL1: |
| 403 | ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); |
| 404 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; |
| 405 | WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); |
| 406 | break; |
| 407 | case ATOM_PPLL2: |
| 408 | ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); |
| 409 | ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; |
| 410 | WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); |
| 411 | break; |
| 412 | case ATOM_DCPLL: |
| 413 | case ATOM_PPLL_INVALID: |
| 414 | return; |
| 415 | } |
| 416 | } else if (ASIC_IS_AVIVO(rdev)) { |
Alex Deucher | 3fa47d9 | 2012-01-20 14:56:39 -0500 | [diff] [blame] | 417 | switch (pll_id) { |
Alex Deucher | b792210 | 2010-03-06 10:57:30 -0500 | [diff] [blame] | 418 | case ATOM_PPLL1: |
| 419 | ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); |
| 420 | ss_cntl &= ~1; |
| 421 | WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); |
| 422 | break; |
| 423 | case ATOM_PPLL2: |
| 424 | ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); |
| 425 | ss_cntl &= ~1; |
| 426 | WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); |
| 427 | break; |
| 428 | case ATOM_DCPLL: |
| 429 | case ATOM_PPLL_INVALID: |
| 430 | return; |
| 431 | } |
| 432 | } |
| 433 | } |
| 434 | |
| 435 | |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 436 | union atom_enable_ss { |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 437 | ENABLE_LVDS_SS_PARAMETERS lvds_ss; |
| 438 | ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 439 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 440 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; |
Alex Deucher | a572eaa | 2011-01-06 21:19:16 -0500 | [diff] [blame] | 441 | ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 442 | }; |
| 443 | |
Alex Deucher | 3fa47d9 | 2012-01-20 14:56:39 -0500 | [diff] [blame] | 444 | static void atombios_crtc_program_ss(struct radeon_device *rdev, |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 445 | int enable, |
| 446 | int pll_id, |
| 447 | struct radeon_atom_ss *ss) |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 448 | { |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 449 | int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 450 | union atom_enable_ss args; |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 451 | |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 452 | memset(&args, 0, sizeof(args)); |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 453 | |
Alex Deucher | a572eaa | 2011-01-06 21:19:16 -0500 | [diff] [blame] | 454 | if (ASIC_IS_DCE5(rdev)) { |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 455 | args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame] | 456 | args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
Alex Deucher | a572eaa | 2011-01-06 21:19:16 -0500 | [diff] [blame] | 457 | switch (pll_id) { |
| 458 | case ATOM_PPLL1: |
| 459 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 460 | args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
| 461 | args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
Alex Deucher | a572eaa | 2011-01-06 21:19:16 -0500 | [diff] [blame] | 462 | break; |
| 463 | case ATOM_PPLL2: |
| 464 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 465 | args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
| 466 | args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
Alex Deucher | a572eaa | 2011-01-06 21:19:16 -0500 | [diff] [blame] | 467 | break; |
| 468 | case ATOM_DCPLL: |
| 469 | args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 470 | args.v3.usSpreadSpectrumAmount = cpu_to_le16(0); |
| 471 | args.v3.usSpreadSpectrumStep = cpu_to_le16(0); |
Alex Deucher | a572eaa | 2011-01-06 21:19:16 -0500 | [diff] [blame] | 472 | break; |
| 473 | case ATOM_PPLL_INVALID: |
| 474 | return; |
| 475 | } |
Alex Deucher | d0ae3e8 | 2011-05-23 14:06:20 -0400 | [diff] [blame] | 476 | args.v3.ucEnable = enable; |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame] | 477 | if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK)) |
| 478 | args.v3.ucEnable = ATOM_DISABLE; |
Alex Deucher | a572eaa | 2011-01-06 21:19:16 -0500 | [diff] [blame] | 479 | } else if (ASIC_IS_DCE4(rdev)) { |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 480 | args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame] | 481 | args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 482 | switch (pll_id) { |
| 483 | case ATOM_PPLL1: |
| 484 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 485 | args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
| 486 | args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 487 | break; |
| 488 | case ATOM_PPLL2: |
| 489 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 490 | args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); |
| 491 | args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 492 | break; |
| 493 | case ATOM_DCPLL: |
| 494 | args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 495 | args.v2.usSpreadSpectrumAmount = cpu_to_le16(0); |
| 496 | args.v2.usSpreadSpectrumStep = cpu_to_le16(0); |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 497 | break; |
| 498 | case ATOM_PPLL_INVALID: |
| 499 | return; |
| 500 | } |
| 501 | args.v2.ucEnable = enable; |
Alex Deucher | 09cc650 | 2011-10-12 18:44:33 -0400 | [diff] [blame] | 502 | if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev)) |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame] | 503 | args.v2.ucEnable = ATOM_DISABLE; |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 504 | } else if (ASIC_IS_DCE3(rdev)) { |
| 505 | args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame] | 506 | args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 507 | args.v1.ucSpreadSpectrumStep = ss->step; |
| 508 | args.v1.ucSpreadSpectrumDelay = ss->delay; |
| 509 | args.v1.ucSpreadSpectrumRange = ss->range; |
| 510 | args.v1.ucPpll = pll_id; |
| 511 | args.v1.ucEnable = enable; |
| 512 | } else if (ASIC_IS_AVIVO(rdev)) { |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame] | 513 | if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || |
| 514 | (ss->type & ATOM_EXTERNAL_SS_MASK)) { |
Alex Deucher | 3fa47d9 | 2012-01-20 14:56:39 -0500 | [diff] [blame] | 515 | atombios_disable_ss(rdev, pll_id); |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 516 | return; |
| 517 | } |
| 518 | args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame] | 519 | args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 520 | args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; |
| 521 | args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; |
| 522 | args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; |
| 523 | args.lvds_ss_2.ucEnable = enable; |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 524 | } else { |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame] | 525 | if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || |
| 526 | (ss->type & ATOM_EXTERNAL_SS_MASK)) { |
Alex Deucher | 3fa47d9 | 2012-01-20 14:56:39 -0500 | [diff] [blame] | 527 | atombios_disable_ss(rdev, pll_id); |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 528 | return; |
| 529 | } |
| 530 | args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame] | 531 | args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 532 | args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; |
| 533 | args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; |
| 534 | args.lvds_ss.ucEnable = enable; |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 535 | } |
Alex Deucher | 26b9fc3 | 2010-02-01 16:39:11 -0500 | [diff] [blame] | 536 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
Alex Deucher | ebbe1cb | 2009-10-16 11:15:25 -0400 | [diff] [blame] | 537 | } |
| 538 | |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 539 | union adjust_pixel_clock { |
| 540 | ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 541 | ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 542 | }; |
| 543 | |
| 544 | static u32 atombios_adjust_pll(struct drm_crtc *crtc, |
| 545 | struct drm_display_mode *mode, |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 546 | struct radeon_pll *pll, |
| 547 | bool ss_enabled, |
| 548 | struct radeon_atom_ss *ss) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 549 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 550 | struct drm_device *dev = crtc->dev; |
| 551 | struct radeon_device *rdev = dev->dev_private; |
| 552 | struct drm_encoder *encoder = NULL; |
| 553 | struct radeon_encoder *radeon_encoder = NULL; |
Alex Deucher | df271be | 2011-05-20 04:34:15 -0400 | [diff] [blame] | 554 | struct drm_connector *connector = NULL; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 555 | u32 adjusted_clock = mode->clock; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 556 | int encoder_mode = 0; |
Alex Deucher | fbee67a | 2010-08-16 12:44:47 -0400 | [diff] [blame] | 557 | u32 dp_clock = mode->clock; |
| 558 | int bpc = 8; |
Alex Deucher | 9aa5999 | 2012-01-20 15:03:30 -0500 | [diff] [blame] | 559 | bool is_duallink = false; |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 560 | |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 561 | /* reset the pll flags */ |
| 562 | pll->flags = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 563 | |
| 564 | if (ASIC_IS_AVIVO(rdev)) { |
Alex Deucher | eb1300b | 2009-07-13 11:09:56 -0400 | [diff] [blame] | 565 | if ((rdev->family == CHIP_RS600) || |
| 566 | (rdev->family == CHIP_RS690) || |
| 567 | (rdev->family == CHIP_RS740)) |
Alex Deucher | 2ff776c | 2010-06-08 19:44:36 -0400 | [diff] [blame] | 568 | pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 569 | RADEON_PLL_PREFER_CLOSEST_LOWER); |
Dave Airlie | 5480f72 | 2010-10-19 10:36:47 +1000 | [diff] [blame] | 570 | |
| 571 | if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ |
| 572 | pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
| 573 | else |
| 574 | pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
Alex Deucher | 9bb09fa | 2011-04-07 10:31:25 -0400 | [diff] [blame] | 575 | |
Alex Deucher | 5785e53 | 2011-04-19 15:24:59 -0400 | [diff] [blame] | 576 | if (rdev->family < CHIP_RV770) |
Alex Deucher | 9bb09fa | 2011-04-07 10:31:25 -0400 | [diff] [blame] | 577 | pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; |
Dave Airlie | 5480f72 | 2010-10-19 10:36:47 +1000 | [diff] [blame] | 578 | } else { |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 579 | pll->flags |= RADEON_PLL_LEGACY; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 580 | |
Dave Airlie | 5480f72 | 2010-10-19 10:36:47 +1000 | [diff] [blame] | 581 | if (mode->clock > 200000) /* range limits??? */ |
| 582 | pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
| 583 | else |
| 584 | pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
Dave Airlie | 5480f72 | 2010-10-19 10:36:47 +1000 | [diff] [blame] | 585 | } |
| 586 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 587 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 588 | if (encoder->crtc == crtc) { |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 589 | radeon_encoder = to_radeon_encoder(encoder); |
Alex Deucher | df271be | 2011-05-20 04:34:15 -0400 | [diff] [blame] | 590 | connector = radeon_get_connector_for_encoder(encoder); |
Dave Airlie | 06e4cd6 | 2011-12-20 11:44:30 +0000 | [diff] [blame] | 591 | if (connector && connector->display_info.bpc) |
Alex Deucher | df271be | 2011-05-20 04:34:15 -0400 | [diff] [blame] | 592 | bpc = connector->display_info.bpc; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 593 | encoder_mode = atombios_get_encoder_mode(encoder); |
Alex Deucher | 9aa5999 | 2012-01-20 15:03:30 -0500 | [diff] [blame] | 594 | is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); |
Alex Deucher | eac4dff | 2011-05-20 04:34:22 -0400 | [diff] [blame] | 595 | if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || |
Alex Deucher | 1d33e1f | 2011-10-31 08:58:47 -0400 | [diff] [blame] | 596 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { |
Alex Deucher | fbee67a | 2010-08-16 12:44:47 -0400 | [diff] [blame] | 597 | if (connector) { |
| 598 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 599 | struct radeon_connector_atom_dig *dig_connector = |
| 600 | radeon_connector->con_priv; |
| 601 | |
| 602 | dp_clock = dig_connector->dp_clock; |
| 603 | } |
| 604 | } |
Alex Deucher | 5b40ddf | 2011-02-14 11:43:11 -0500 | [diff] [blame] | 605 | |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 606 | /* use recommended ref_div for ss */ |
| 607 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 608 | if (ss_enabled) { |
| 609 | if (ss->refdiv) { |
| 610 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
| 611 | pll->reference_div = ss->refdiv; |
Alex Deucher | 5b40ddf | 2011-02-14 11:43:11 -0500 | [diff] [blame] | 612 | if (ASIC_IS_AVIVO(rdev)) |
| 613 | pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 614 | } |
| 615 | } |
| 616 | } |
Alex Deucher | 5b40ddf | 2011-02-14 11:43:11 -0500 | [diff] [blame] | 617 | |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 618 | if (ASIC_IS_AVIVO(rdev)) { |
| 619 | /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ |
| 620 | if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) |
| 621 | adjusted_clock = mode->clock * 2; |
Alex Deucher | 48dfaae | 2010-09-29 11:37:41 -0400 | [diff] [blame] | 622 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
Alex Deucher | a1a4b23 | 2010-04-09 15:31:56 -0400 | [diff] [blame] | 623 | pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; |
Alex Deucher | 5b40ddf | 2011-02-14 11:43:11 -0500 | [diff] [blame] | 624 | if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
| 625 | pll->flags |= RADEON_PLL_IS_LCD; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 626 | } else { |
| 627 | if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 628 | pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 629 | if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) |
Alex Deucher | fc10332 | 2010-01-19 17:16:10 -0500 | [diff] [blame] | 630 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 631 | } |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 632 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 633 | } |
| 634 | } |
| 635 | |
Alex Deucher | 2606c88 | 2009-10-08 13:36:21 -0400 | [diff] [blame] | 636 | /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock |
| 637 | * accordingly based on the encoder/transmitter to work around |
| 638 | * special hw requirements. |
| 639 | */ |
| 640 | if (ASIC_IS_DCE3(rdev)) { |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 641 | union adjust_pixel_clock args; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 642 | u8 frev, crev; |
| 643 | int index; |
Alex Deucher | 2606c88 | 2009-10-08 13:36:21 -0400 | [diff] [blame] | 644 | |
Alex Deucher | 2606c88 | 2009-10-08 13:36:21 -0400 | [diff] [blame] | 645 | index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 646 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
| 647 | &crev)) |
| 648 | return adjusted_clock; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 649 | |
| 650 | memset(&args, 0, sizeof(args)); |
| 651 | |
| 652 | switch (frev) { |
| 653 | case 1: |
| 654 | switch (crev) { |
| 655 | case 1: |
| 656 | case 2: |
| 657 | args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); |
| 658 | args.v1.ucTransmitterID = radeon_encoder->encoder_id; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 659 | args.v1.ucEncodeMode = encoder_mode; |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame] | 660 | if (ss_enabled && ss->percentage) |
Alex Deucher | fbee67a | 2010-08-16 12:44:47 -0400 | [diff] [blame] | 661 | args.v1.ucConfig |= |
| 662 | ADJUST_DISPLAY_CONFIG_SS_ENABLE; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 663 | |
| 664 | atom_execute_table(rdev->mode_info.atom_context, |
| 665 | index, (uint32_t *)&args); |
| 666 | adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; |
| 667 | break; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 668 | case 3: |
| 669 | args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); |
| 670 | args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; |
| 671 | args.v3.sInput.ucEncodeMode = encoder_mode; |
| 672 | args.v3.sInput.ucDispPllConfig = 0; |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame] | 673 | if (ss_enabled && ss->percentage) |
Alex Deucher | b526ce2 | 2011-01-20 23:35:58 +0000 | [diff] [blame] | 674 | args.v3.sInput.ucDispPllConfig |= |
| 675 | DISPPLL_CONFIG_SS_ENABLE; |
Alex Deucher | 996d5c5 | 2011-10-26 15:59:50 -0400 | [diff] [blame] | 676 | if (ENCODER_MODE_IS_DP(encoder_mode)) { |
Alex Deucher | b4f15f8 | 2011-10-25 11:34:51 -0400 | [diff] [blame] | 677 | args.v3.sInput.ucDispPllConfig |= |
| 678 | DISPPLL_CONFIG_COHERENT_MODE; |
| 679 | /* 16200 or 27000 */ |
| 680 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); |
| 681 | } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 682 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Alex Deucher | b4f15f8 | 2011-10-25 11:34:51 -0400 | [diff] [blame] | 683 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) |
| 684 | /* deep color support */ |
| 685 | args.v3.sInput.usPixelClock = |
| 686 | cpu_to_le16((mode->clock * bpc / 8) / 10); |
| 687 | if (dig->coherent_mode) |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 688 | args.v3.sInput.ucDispPllConfig |= |
| 689 | DISPPLL_CONFIG_COHERENT_MODE; |
Alex Deucher | 9aa5999 | 2012-01-20 15:03:30 -0500 | [diff] [blame] | 690 | if (is_duallink) |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 691 | args.v3.sInput.ucDispPllConfig |= |
Alex Deucher | b4f15f8 | 2011-10-25 11:34:51 -0400 | [diff] [blame] | 692 | DISPPLL_CONFIG_DUAL_LINK; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 693 | } |
Alex Deucher | 1d33e1f | 2011-10-31 08:58:47 -0400 | [diff] [blame] | 694 | if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != |
| 695 | ENCODER_OBJECT_ID_NONE) |
| 696 | args.v3.sInput.ucExtTransmitterID = |
| 697 | radeon_encoder_get_dp_bridge_encoder_id(encoder); |
| 698 | else |
Alex Deucher | cc9f67a | 2011-06-16 10:06:16 -0400 | [diff] [blame] | 699 | args.v3.sInput.ucExtTransmitterID = 0; |
| 700 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 701 | atom_execute_table(rdev->mode_info.atom_context, |
| 702 | index, (uint32_t *)&args); |
| 703 | adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; |
| 704 | if (args.v3.sOutput.ucRefDiv) { |
Alex Deucher | 9f4283f | 2011-02-16 21:17:04 -0500 | [diff] [blame] | 705 | pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 706 | pll->flags |= RADEON_PLL_USE_REF_DIV; |
| 707 | pll->reference_div = args.v3.sOutput.ucRefDiv; |
| 708 | } |
| 709 | if (args.v3.sOutput.ucPostDiv) { |
Alex Deucher | 9f4283f | 2011-02-16 21:17:04 -0500 | [diff] [blame] | 710 | pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 711 | pll->flags |= RADEON_PLL_USE_POST_DIV; |
| 712 | pll->post_div = args.v3.sOutput.ucPostDiv; |
| 713 | } |
| 714 | break; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 715 | default: |
| 716 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 717 | return adjusted_clock; |
| 718 | } |
| 719 | break; |
| 720 | default: |
| 721 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 722 | return adjusted_clock; |
| 723 | } |
Alex Deucher | d56ef9c | 2009-10-27 12:11:09 -0400 | [diff] [blame] | 724 | } |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 725 | return adjusted_clock; |
| 726 | } |
| 727 | |
| 728 | union set_pixel_clock { |
| 729 | SET_PIXEL_CLOCK_PS_ALLOCATION base; |
| 730 | PIXEL_CLOCK_PARAMETERS v1; |
| 731 | PIXEL_CLOCK_PARAMETERS_V2 v2; |
| 732 | PIXEL_CLOCK_PARAMETERS_V3 v3; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 733 | PIXEL_CLOCK_PARAMETERS_V5 v5; |
Alex Deucher | f82b3dd | 2011-01-06 21:19:15 -0500 | [diff] [blame] | 734 | PIXEL_CLOCK_PARAMETERS_V6 v6; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 735 | }; |
| 736 | |
Alex Deucher | f82b3dd | 2011-01-06 21:19:15 -0500 | [diff] [blame] | 737 | /* on DCE5, make sure the voltage is high enough to support the |
| 738 | * required disp clk. |
| 739 | */ |
Alex Deucher | f3f1f03 | 2012-03-20 17:18:04 -0400 | [diff] [blame] | 740 | static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, |
Alex Deucher | f82b3dd | 2011-01-06 21:19:15 -0500 | [diff] [blame] | 741 | u32 dispclk) |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 742 | { |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 743 | u8 frev, crev; |
| 744 | int index; |
| 745 | union set_pixel_clock args; |
| 746 | |
| 747 | memset(&args, 0, sizeof(args)); |
| 748 | |
| 749 | index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
Alex Deucher | a084e6e | 2010-03-18 01:04:01 -0400 | [diff] [blame] | 750 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
| 751 | &crev)) |
| 752 | return; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 753 | |
| 754 | switch (frev) { |
| 755 | case 1: |
| 756 | switch (crev) { |
| 757 | case 5: |
| 758 | /* if the default dcpll clock is specified, |
| 759 | * SetPixelClock provides the dividers |
| 760 | */ |
| 761 | args.v5.ucCRTC = ATOM_CRTC_INVALID; |
Cédric Cano | 4589433 | 2011-02-11 19:45:37 -0500 | [diff] [blame] | 762 | args.v5.usPixelClock = cpu_to_le16(dispclk); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 763 | args.v5.ucPpll = ATOM_DCPLL; |
| 764 | break; |
Alex Deucher | f82b3dd | 2011-01-06 21:19:15 -0500 | [diff] [blame] | 765 | case 6: |
| 766 | /* if the default dcpll clock is specified, |
| 767 | * SetPixelClock provides the dividers |
| 768 | */ |
Alex Deucher | 265aa6c | 2011-02-14 16:16:22 -0500 | [diff] [blame] | 769 | args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); |
Alex Deucher | 729b95e | 2012-03-20 17:18:31 -0400 | [diff] [blame] | 770 | if (ASIC_IS_DCE61(rdev)) |
| 771 | args.v6.ucPpll = ATOM_EXT_PLL1; |
| 772 | else if (ASIC_IS_DCE6(rdev)) |
Alex Deucher | f3f1f03 | 2012-03-20 17:18:04 -0400 | [diff] [blame] | 773 | args.v6.ucPpll = ATOM_PPLL0; |
| 774 | else |
| 775 | args.v6.ucPpll = ATOM_DCPLL; |
Alex Deucher | f82b3dd | 2011-01-06 21:19:15 -0500 | [diff] [blame] | 776 | break; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 777 | default: |
| 778 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 779 | return; |
| 780 | } |
| 781 | break; |
| 782 | default: |
| 783 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 784 | return; |
| 785 | } |
| 786 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 787 | } |
| 788 | |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 789 | static void atombios_crtc_program_pll(struct drm_crtc *crtc, |
Benjamin Herrenschmidt | f1bece7 | 2011-07-13 16:28:15 +1000 | [diff] [blame] | 790 | u32 crtc_id, |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 791 | int pll_id, |
| 792 | u32 encoder_mode, |
| 793 | u32 encoder_id, |
| 794 | u32 clock, |
| 795 | u32 ref_div, |
| 796 | u32 fb_div, |
| 797 | u32 frac_fb_div, |
Alex Deucher | df271be | 2011-05-20 04:34:15 -0400 | [diff] [blame] | 798 | u32 post_div, |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame] | 799 | int bpc, |
| 800 | bool ss_enabled, |
| 801 | struct radeon_atom_ss *ss) |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 802 | { |
| 803 | struct drm_device *dev = crtc->dev; |
| 804 | struct radeon_device *rdev = dev->dev_private; |
| 805 | u8 frev, crev; |
| 806 | int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
| 807 | union set_pixel_clock args; |
| 808 | |
| 809 | memset(&args, 0, sizeof(args)); |
| 810 | |
| 811 | if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
| 812 | &crev)) |
| 813 | return; |
| 814 | |
| 815 | switch (frev) { |
| 816 | case 1: |
| 817 | switch (crev) { |
| 818 | case 1: |
| 819 | if (clock == ATOM_DISABLE) |
| 820 | return; |
| 821 | args.v1.usPixelClock = cpu_to_le16(clock / 10); |
| 822 | args.v1.usRefDiv = cpu_to_le16(ref_div); |
| 823 | args.v1.usFbDiv = cpu_to_le16(fb_div); |
| 824 | args.v1.ucFracFbDiv = frac_fb_div; |
| 825 | args.v1.ucPostDiv = post_div; |
| 826 | args.v1.ucPpll = pll_id; |
| 827 | args.v1.ucCRTC = crtc_id; |
| 828 | args.v1.ucRefDivSrc = 1; |
| 829 | break; |
| 830 | case 2: |
| 831 | args.v2.usPixelClock = cpu_to_le16(clock / 10); |
| 832 | args.v2.usRefDiv = cpu_to_le16(ref_div); |
| 833 | args.v2.usFbDiv = cpu_to_le16(fb_div); |
| 834 | args.v2.ucFracFbDiv = frac_fb_div; |
| 835 | args.v2.ucPostDiv = post_div; |
| 836 | args.v2.ucPpll = pll_id; |
| 837 | args.v2.ucCRTC = crtc_id; |
| 838 | args.v2.ucRefDivSrc = 1; |
| 839 | break; |
| 840 | case 3: |
| 841 | args.v3.usPixelClock = cpu_to_le16(clock / 10); |
| 842 | args.v3.usRefDiv = cpu_to_le16(ref_div); |
| 843 | args.v3.usFbDiv = cpu_to_le16(fb_div); |
| 844 | args.v3.ucFracFbDiv = frac_fb_div; |
| 845 | args.v3.ucPostDiv = post_div; |
| 846 | args.v3.ucPpll = pll_id; |
| 847 | args.v3.ucMiscInfo = (pll_id << 2); |
Alex Deucher | 6f15c50 | 2011-05-20 12:36:12 -0400 | [diff] [blame] | 848 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
| 849 | args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 850 | args.v3.ucTransmitterId = encoder_id; |
| 851 | args.v3.ucEncoderMode = encoder_mode; |
| 852 | break; |
| 853 | case 5: |
| 854 | args.v5.ucCRTC = crtc_id; |
| 855 | args.v5.usPixelClock = cpu_to_le16(clock / 10); |
| 856 | args.v5.ucRefDiv = ref_div; |
| 857 | args.v5.usFbDiv = cpu_to_le16(fb_div); |
| 858 | args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); |
| 859 | args.v5.ucPostDiv = post_div; |
| 860 | args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame] | 861 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
| 862 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; |
Alex Deucher | df271be | 2011-05-20 04:34:15 -0400 | [diff] [blame] | 863 | switch (bpc) { |
| 864 | case 8: |
| 865 | default: |
| 866 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; |
| 867 | break; |
| 868 | case 10: |
| 869 | args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; |
| 870 | break; |
| 871 | } |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 872 | args.v5.ucTransmitterID = encoder_id; |
| 873 | args.v5.ucEncoderMode = encoder_mode; |
| 874 | args.v5.ucPpll = pll_id; |
| 875 | break; |
Alex Deucher | f82b3dd | 2011-01-06 21:19:15 -0500 | [diff] [blame] | 876 | case 6: |
Benjamin Herrenschmidt | f1bece7 | 2011-07-13 16:28:15 +1000 | [diff] [blame] | 877 | args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); |
Alex Deucher | f82b3dd | 2011-01-06 21:19:15 -0500 | [diff] [blame] | 878 | args.v6.ucRefDiv = ref_div; |
| 879 | args.v6.usFbDiv = cpu_to_le16(fb_div); |
| 880 | args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); |
| 881 | args.v6.ucPostDiv = post_div; |
| 882 | args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame] | 883 | if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) |
| 884 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; |
Alex Deucher | df271be | 2011-05-20 04:34:15 -0400 | [diff] [blame] | 885 | switch (bpc) { |
| 886 | case 8: |
| 887 | default: |
| 888 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; |
| 889 | break; |
| 890 | case 10: |
| 891 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP; |
| 892 | break; |
| 893 | case 12: |
| 894 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP; |
| 895 | break; |
| 896 | case 16: |
| 897 | args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; |
| 898 | break; |
| 899 | } |
Alex Deucher | f82b3dd | 2011-01-06 21:19:15 -0500 | [diff] [blame] | 900 | args.v6.ucTransmitterID = encoder_id; |
| 901 | args.v6.ucEncoderMode = encoder_mode; |
| 902 | args.v6.ucPpll = pll_id; |
| 903 | break; |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 904 | default: |
| 905 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 906 | return; |
| 907 | } |
| 908 | break; |
| 909 | default: |
| 910 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
| 911 | return; |
| 912 | } |
| 913 | |
| 914 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 915 | } |
| 916 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 917 | static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 918 | { |
| 919 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 920 | struct drm_device *dev = crtc->dev; |
| 921 | struct radeon_device *rdev = dev->dev_private; |
| 922 | struct drm_encoder *encoder = NULL; |
| 923 | struct radeon_encoder *radeon_encoder = NULL; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 924 | u32 pll_clock = mode->clock; |
| 925 | u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; |
| 926 | struct radeon_pll *pll; |
| 927 | u32 adjusted_clock; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 928 | int encoder_mode = 0; |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 929 | struct radeon_atom_ss ss; |
| 930 | bool ss_enabled = false; |
Alex Deucher | df271be | 2011-05-20 04:34:15 -0400 | [diff] [blame] | 931 | int bpc = 8; |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 932 | |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 933 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 934 | if (encoder->crtc == crtc) { |
| 935 | radeon_encoder = to_radeon_encoder(encoder); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 936 | encoder_mode = atombios_get_encoder_mode(encoder); |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 937 | break; |
| 938 | } |
| 939 | } |
| 940 | |
| 941 | if (!radeon_encoder) |
| 942 | return; |
| 943 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 944 | switch (radeon_crtc->pll_id) { |
| 945 | case ATOM_PPLL1: |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 946 | pll = &rdev->clock.p1pll; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 947 | break; |
| 948 | case ATOM_PPLL2: |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 949 | pll = &rdev->clock.p2pll; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 950 | break; |
| 951 | case ATOM_DCPLL: |
| 952 | case ATOM_PPLL_INVALID: |
Stefan Richter | 921d98b | 2010-05-26 10:27:44 +1000 | [diff] [blame] | 953 | default: |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 954 | pll = &rdev->clock.dcpll; |
| 955 | break; |
| 956 | } |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 957 | |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 958 | if (radeon_encoder->active_device & |
| 959 | (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) { |
| 960 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 961 | struct drm_connector *connector = |
| 962 | radeon_get_connector_for_encoder(encoder); |
| 963 | struct radeon_connector *radeon_connector = |
| 964 | to_radeon_connector(connector); |
| 965 | struct radeon_connector_atom_dig *dig_connector = |
| 966 | radeon_connector->con_priv; |
| 967 | int dp_clock; |
Alex Deucher | df271be | 2011-05-20 04:34:15 -0400 | [diff] [blame] | 968 | bpc = connector->display_info.bpc; |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 969 | |
| 970 | switch (encoder_mode) { |
Alex Deucher | 996d5c5 | 2011-10-26 15:59:50 -0400 | [diff] [blame] | 971 | case ATOM_ENCODER_MODE_DP_MST: |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 972 | case ATOM_ENCODER_MODE_DP: |
| 973 | /* DP/eDP */ |
| 974 | dp_clock = dig_connector->dp_clock / 10; |
Alex Deucher | 2307790 | 2011-05-20 12:36:11 -0400 | [diff] [blame] | 975 | if (ASIC_IS_DCE4(rdev)) |
| 976 | ss_enabled = |
| 977 | radeon_atombios_get_asic_ss_info(rdev, &ss, |
| 978 | ASIC_INTERNAL_SS_ON_DP, |
| 979 | dp_clock); |
| 980 | else { |
| 981 | if (dp_clock == 16200) { |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 982 | ss_enabled = |
| 983 | radeon_atombios_get_ppll_ss_info(rdev, &ss, |
Alex Deucher | 2307790 | 2011-05-20 12:36:11 -0400 | [diff] [blame] | 984 | ATOM_DP_SS_ID2); |
| 985 | if (!ss_enabled) |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 986 | ss_enabled = |
| 987 | radeon_atombios_get_ppll_ss_info(rdev, &ss, |
| 988 | ATOM_DP_SS_ID1); |
Alex Deucher | 2307790 | 2011-05-20 12:36:11 -0400 | [diff] [blame] | 989 | } else |
| 990 | ss_enabled = |
| 991 | radeon_atombios_get_ppll_ss_info(rdev, &ss, |
| 992 | ATOM_DP_SS_ID1); |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 993 | } |
| 994 | break; |
| 995 | case ATOM_ENCODER_MODE_LVDS: |
| 996 | if (ASIC_IS_DCE4(rdev)) |
| 997 | ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, |
| 998 | dig->lcd_ss_id, |
| 999 | mode->clock / 10); |
| 1000 | else |
| 1001 | ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss, |
| 1002 | dig->lcd_ss_id); |
| 1003 | break; |
| 1004 | case ATOM_ENCODER_MODE_DVI: |
| 1005 | if (ASIC_IS_DCE4(rdev)) |
| 1006 | ss_enabled = |
| 1007 | radeon_atombios_get_asic_ss_info(rdev, &ss, |
| 1008 | ASIC_INTERNAL_SS_ON_TMDS, |
| 1009 | mode->clock / 10); |
| 1010 | break; |
| 1011 | case ATOM_ENCODER_MODE_HDMI: |
| 1012 | if (ASIC_IS_DCE4(rdev)) |
| 1013 | ss_enabled = |
| 1014 | radeon_atombios_get_asic_ss_info(rdev, &ss, |
| 1015 | ASIC_INTERNAL_SS_ON_HDMI, |
| 1016 | mode->clock / 10); |
| 1017 | break; |
| 1018 | default: |
| 1019 | break; |
| 1020 | } |
| 1021 | } |
| 1022 | |
Alex Deucher | 4eaeca3 | 2010-01-19 17:32:27 -0500 | [diff] [blame] | 1023 | /* adjust pixel clock as needed */ |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1024 | adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss); |
Alex Deucher | 2606c88 | 2009-10-08 13:36:21 -0400 | [diff] [blame] | 1025 | |
Alex Deucher | 64146f8 | 2011-03-22 01:46:12 -0400 | [diff] [blame] | 1026 | if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) |
| 1027 | /* TV seems to prefer the legacy algo on some boards */ |
| 1028 | radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, |
| 1029 | &ref_div, &post_div); |
| 1030 | else if (ASIC_IS_AVIVO(rdev)) |
Alex Deucher | 619efb1 | 2011-01-31 16:48:53 -0500 | [diff] [blame] | 1031 | radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, |
| 1032 | &ref_div, &post_div); |
| 1033 | else |
| 1034 | radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, |
| 1035 | &ref_div, &post_div); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1036 | |
Alex Deucher | 3fa47d9 | 2012-01-20 14:56:39 -0500 | [diff] [blame] | 1037 | atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, &ss); |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1038 | |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 1039 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
| 1040 | encoder_mode, radeon_encoder->encoder_id, mode->clock, |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame] | 1041 | ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1042 | |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1043 | if (ss_enabled) { |
| 1044 | /* calculate ss amount and step size */ |
| 1045 | if (ASIC_IS_DCE4(rdev)) { |
| 1046 | u32 step_size; |
| 1047 | u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000; |
| 1048 | ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame] | 1049 | ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1050 | ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; |
| 1051 | if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) |
| 1052 | step_size = (4 * amount * ref_div * (ss.rate * 2048)) / |
| 1053 | (125 * 25 * pll->reference_freq / 100); |
| 1054 | else |
| 1055 | step_size = (2 * amount * ref_div * (ss.rate * 2048)) / |
| 1056 | (125 * 25 * pll->reference_freq / 100); |
| 1057 | ss.step = step_size; |
| 1058 | } |
| 1059 | |
Alex Deucher | 3fa47d9 | 2012-01-20 14:56:39 -0500 | [diff] [blame] | 1060 | atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, &ss); |
Alex Deucher | ba032a5 | 2010-10-04 17:13:01 -0400 | [diff] [blame] | 1061 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1062 | } |
| 1063 | |
Alex Deucher | c9417bd | 2011-02-06 14:23:26 -0500 | [diff] [blame] | 1064 | static int dce4_crtc_do_set_base(struct drm_crtc *crtc, |
| 1065 | struct drm_framebuffer *fb, |
| 1066 | int x, int y, int atomic) |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1067 | { |
| 1068 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1069 | struct drm_device *dev = crtc->dev; |
| 1070 | struct radeon_device *rdev = dev->dev_private; |
| 1071 | struct radeon_framebuffer *radeon_fb; |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1072 | struct drm_framebuffer *target_fb; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1073 | struct drm_gem_object *obj; |
| 1074 | struct radeon_bo *rbo; |
| 1075 | uint64_t fb_location; |
| 1076 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
Jerome Glisse | 285484e | 2011-12-16 17:03:42 -0500 | [diff] [blame] | 1077 | unsigned bankw, bankh, mtaspect, tile_split; |
Alex Deucher | fa6bee4 | 2011-01-25 11:55:50 -0500 | [diff] [blame] | 1078 | u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); |
Alex Deucher | adcfde5 | 2011-05-27 10:05:03 -0400 | [diff] [blame] | 1079 | u32 tmp, viewport_w, viewport_h; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1080 | int r; |
| 1081 | |
| 1082 | /* no fb bound */ |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1083 | if (!atomic && !crtc->fb) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 1084 | DRM_DEBUG_KMS("No FB bound\n"); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1085 | return 0; |
| 1086 | } |
| 1087 | |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1088 | if (atomic) { |
| 1089 | radeon_fb = to_radeon_framebuffer(fb); |
| 1090 | target_fb = fb; |
| 1091 | } |
| 1092 | else { |
| 1093 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
| 1094 | target_fb = crtc->fb; |
| 1095 | } |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1096 | |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1097 | /* If atomic, assume fb object is pinned & idle & fenced and |
| 1098 | * just update base pointers |
| 1099 | */ |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1100 | obj = radeon_fb->obj; |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 1101 | rbo = gem_to_radeon_bo(obj); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1102 | r = radeon_bo_reserve(rbo, false); |
| 1103 | if (unlikely(r != 0)) |
| 1104 | return r; |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1105 | |
| 1106 | if (atomic) |
| 1107 | fb_location = radeon_bo_gpu_offset(rbo); |
| 1108 | else { |
| 1109 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); |
| 1110 | if (unlikely(r != 0)) { |
| 1111 | radeon_bo_unreserve(rbo); |
| 1112 | return -EINVAL; |
| 1113 | } |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1114 | } |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1115 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1116 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
| 1117 | radeon_bo_unreserve(rbo); |
| 1118 | |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1119 | switch (target_fb->bits_per_pixel) { |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1120 | case 8: |
| 1121 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | |
| 1122 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); |
| 1123 | break; |
| 1124 | case 15: |
| 1125 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
| 1126 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); |
| 1127 | break; |
| 1128 | case 16: |
| 1129 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | |
| 1130 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); |
Alex Deucher | fa6bee4 | 2011-01-25 11:55:50 -0500 | [diff] [blame] | 1131 | #ifdef __BIG_ENDIAN |
| 1132 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); |
| 1133 | #endif |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1134 | break; |
| 1135 | case 24: |
| 1136 | case 32: |
| 1137 | fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | |
| 1138 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); |
Alex Deucher | fa6bee4 | 2011-01-25 11:55:50 -0500 | [diff] [blame] | 1139 | #ifdef __BIG_ENDIAN |
| 1140 | fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); |
| 1141 | #endif |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1142 | break; |
| 1143 | default: |
| 1144 | DRM_ERROR("Unsupported screen depth %d\n", |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1145 | target_fb->bits_per_pixel); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1146 | return -EINVAL; |
| 1147 | } |
| 1148 | |
Alex Deucher | 392e372 | 2011-11-28 14:49:27 -0500 | [diff] [blame] | 1149 | if (tiling_flags & RADEON_TILING_MACRO) { |
| 1150 | if (rdev->family >= CHIP_CAYMAN) |
| 1151 | tmp = rdev->config.cayman.tile_config; |
| 1152 | else |
| 1153 | tmp = rdev->config.evergreen.tile_config; |
| 1154 | |
| 1155 | switch ((tmp & 0xf0) >> 4) { |
| 1156 | case 0: /* 4 banks */ |
| 1157 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK); |
| 1158 | break; |
| 1159 | case 1: /* 8 banks */ |
| 1160 | default: |
| 1161 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK); |
| 1162 | break; |
| 1163 | case 2: /* 16 banks */ |
| 1164 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); |
| 1165 | break; |
| 1166 | } |
| 1167 | |
Alex Deucher | 97d6632 | 2010-05-20 12:12:48 -0400 | [diff] [blame] | 1168 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); |
Jerome Glisse | 285484e | 2011-12-16 17:03:42 -0500 | [diff] [blame] | 1169 | |
| 1170 | evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); |
| 1171 | fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); |
| 1172 | fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); |
| 1173 | fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); |
| 1174 | fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); |
Alex Deucher | 392e372 | 2011-11-28 14:49:27 -0500 | [diff] [blame] | 1175 | } else if (tiling_flags & RADEON_TILING_MICRO) |
Alex Deucher | 97d6632 | 2010-05-20 12:12:48 -0400 | [diff] [blame] | 1176 | fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); |
| 1177 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1178 | switch (radeon_crtc->crtc_id) { |
| 1179 | case 0: |
| 1180 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
| 1181 | break; |
| 1182 | case 1: |
| 1183 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
| 1184 | break; |
| 1185 | case 2: |
| 1186 | WREG32(EVERGREEN_D3VGA_CONTROL, 0); |
| 1187 | break; |
| 1188 | case 3: |
| 1189 | WREG32(EVERGREEN_D4VGA_CONTROL, 0); |
| 1190 | break; |
| 1191 | case 4: |
| 1192 | WREG32(EVERGREEN_D5VGA_CONTROL, 0); |
| 1193 | break; |
| 1194 | case 5: |
| 1195 | WREG32(EVERGREEN_D6VGA_CONTROL, 0); |
| 1196 | break; |
| 1197 | default: |
| 1198 | break; |
| 1199 | } |
| 1200 | |
| 1201 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
| 1202 | upper_32_bits(fb_location)); |
| 1203 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, |
| 1204 | upper_32_bits(fb_location)); |
| 1205 | WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
| 1206 | (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); |
| 1207 | WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
| 1208 | (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); |
| 1209 | WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
Alex Deucher | fa6bee4 | 2011-01-25 11:55:50 -0500 | [diff] [blame] | 1210 | WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1211 | |
| 1212 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
| 1213 | WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
| 1214 | WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); |
| 1215 | WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1216 | WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); |
| 1217 | WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1218 | |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 1219 | fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1220 | WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
| 1221 | WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
| 1222 | |
| 1223 | WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
Michel Dänzer | 1b61925 | 2012-02-01 12:09:55 +0100 | [diff] [blame] | 1224 | target_fb->height); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1225 | x &= ~3; |
| 1226 | y &= ~1; |
| 1227 | WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, |
| 1228 | (x << 16) | y); |
Alex Deucher | adcfde5 | 2011-05-27 10:05:03 -0400 | [diff] [blame] | 1229 | viewport_w = crtc->mode.hdisplay; |
| 1230 | viewport_h = (crtc->mode.vdisplay + 1) & ~1; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1231 | WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
Alex Deucher | adcfde5 | 2011-05-27 10:05:03 -0400 | [diff] [blame] | 1232 | (viewport_w << 16) | viewport_h); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1233 | |
Alex Deucher | fb9674b | 2011-04-02 09:15:50 -0400 | [diff] [blame] | 1234 | /* pageflip setup */ |
| 1235 | /* make sure flip is at vb rather than hb */ |
| 1236 | tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); |
| 1237 | tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; |
| 1238 | WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); |
| 1239 | |
| 1240 | /* set pageflip to happen anywhere in vblank interval */ |
| 1241 | WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); |
| 1242 | |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1243 | if (!atomic && fb && fb != crtc->fb) { |
| 1244 | radeon_fb = to_radeon_framebuffer(fb); |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 1245 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1246 | r = radeon_bo_reserve(rbo, false); |
| 1247 | if (unlikely(r != 0)) |
| 1248 | return r; |
| 1249 | radeon_bo_unpin(rbo); |
| 1250 | radeon_bo_unreserve(rbo); |
| 1251 | } |
| 1252 | |
| 1253 | /* Bytes per pixel may have changed */ |
| 1254 | radeon_bandwidth_update(rdev); |
| 1255 | |
| 1256 | return 0; |
| 1257 | } |
| 1258 | |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1259 | static int avivo_crtc_do_set_base(struct drm_crtc *crtc, |
| 1260 | struct drm_framebuffer *fb, |
| 1261 | int x, int y, int atomic) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1262 | { |
| 1263 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1264 | struct drm_device *dev = crtc->dev; |
| 1265 | struct radeon_device *rdev = dev->dev_private; |
| 1266 | struct radeon_framebuffer *radeon_fb; |
| 1267 | struct drm_gem_object *obj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1268 | struct radeon_bo *rbo; |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1269 | struct drm_framebuffer *target_fb; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1270 | uint64_t fb_location; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1271 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
Alex Deucher | fa6bee4 | 2011-01-25 11:55:50 -0500 | [diff] [blame] | 1272 | u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; |
Alex Deucher | adcfde5 | 2011-05-27 10:05:03 -0400 | [diff] [blame] | 1273 | u32 tmp, viewport_w, viewport_h; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1274 | int r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1275 | |
Jerome Glisse | 2de3b48 | 2009-11-17 14:08:55 -0800 | [diff] [blame] | 1276 | /* no fb bound */ |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1277 | if (!atomic && !crtc->fb) { |
Dave Airlie | d9fdaaf | 2010-08-02 10:42:55 +1000 | [diff] [blame] | 1278 | DRM_DEBUG_KMS("No FB bound\n"); |
Jerome Glisse | 2de3b48 | 2009-11-17 14:08:55 -0800 | [diff] [blame] | 1279 | return 0; |
| 1280 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1281 | |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1282 | if (atomic) { |
| 1283 | radeon_fb = to_radeon_framebuffer(fb); |
| 1284 | target_fb = fb; |
| 1285 | } |
| 1286 | else { |
| 1287 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
| 1288 | target_fb = crtc->fb; |
| 1289 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1290 | |
| 1291 | obj = radeon_fb->obj; |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 1292 | rbo = gem_to_radeon_bo(obj); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1293 | r = radeon_bo_reserve(rbo, false); |
| 1294 | if (unlikely(r != 0)) |
| 1295 | return r; |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1296 | |
| 1297 | /* If atomic, assume fb object is pinned & idle & fenced and |
| 1298 | * just update base pointers |
| 1299 | */ |
| 1300 | if (atomic) |
| 1301 | fb_location = radeon_bo_gpu_offset(rbo); |
| 1302 | else { |
| 1303 | r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); |
| 1304 | if (unlikely(r != 0)) { |
| 1305 | radeon_bo_unreserve(rbo); |
| 1306 | return -EINVAL; |
| 1307 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1308 | } |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1309 | radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); |
| 1310 | radeon_bo_unreserve(rbo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1311 | |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1312 | switch (target_fb->bits_per_pixel) { |
Dave Airlie | 41456df | 2009-09-16 10:15:21 +1000 | [diff] [blame] | 1313 | case 8: |
| 1314 | fb_format = |
| 1315 | AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | |
| 1316 | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; |
| 1317 | break; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1318 | case 15: |
| 1319 | fb_format = |
| 1320 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
| 1321 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; |
| 1322 | break; |
| 1323 | case 16: |
| 1324 | fb_format = |
| 1325 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
| 1326 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; |
Alex Deucher | fa6bee4 | 2011-01-25 11:55:50 -0500 | [diff] [blame] | 1327 | #ifdef __BIG_ENDIAN |
| 1328 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; |
| 1329 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1330 | break; |
| 1331 | case 24: |
| 1332 | case 32: |
| 1333 | fb_format = |
| 1334 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | |
| 1335 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; |
Alex Deucher | fa6bee4 | 2011-01-25 11:55:50 -0500 | [diff] [blame] | 1336 | #ifdef __BIG_ENDIAN |
| 1337 | fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; |
| 1338 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1339 | break; |
| 1340 | default: |
| 1341 | DRM_ERROR("Unsupported screen depth %d\n", |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1342 | target_fb->bits_per_pixel); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1343 | return -EINVAL; |
| 1344 | } |
| 1345 | |
Alex Deucher | 40c4ac1 | 2010-05-20 12:04:59 -0400 | [diff] [blame] | 1346 | if (rdev->family >= CHIP_R600) { |
| 1347 | if (tiling_flags & RADEON_TILING_MACRO) |
| 1348 | fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; |
| 1349 | else if (tiling_flags & RADEON_TILING_MICRO) |
| 1350 | fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; |
| 1351 | } else { |
| 1352 | if (tiling_flags & RADEON_TILING_MACRO) |
| 1353 | fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; |
Dave Airlie | cf2f05d | 2009-12-08 15:45:13 +1000 | [diff] [blame] | 1354 | |
Alex Deucher | 40c4ac1 | 2010-05-20 12:04:59 -0400 | [diff] [blame] | 1355 | if (tiling_flags & RADEON_TILING_MICRO) |
| 1356 | fb_format |= AVIVO_D1GRPH_TILED; |
| 1357 | } |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1358 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1359 | if (radeon_crtc->crtc_id == 0) |
| 1360 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
| 1361 | else |
| 1362 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
Alex Deucher | c290dad | 2009-10-22 16:12:34 -0400 | [diff] [blame] | 1363 | |
| 1364 | if (rdev->family >= CHIP_RV770) { |
| 1365 | if (radeon_crtc->crtc_id) { |
Alex Deucher | 9534787 | 2010-09-01 17:20:42 -0400 | [diff] [blame] | 1366 | WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
| 1367 | WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
Alex Deucher | c290dad | 2009-10-22 16:12:34 -0400 | [diff] [blame] | 1368 | } else { |
Alex Deucher | 9534787 | 2010-09-01 17:20:42 -0400 | [diff] [blame] | 1369 | WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
| 1370 | WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); |
Alex Deucher | c290dad | 2009-10-22 16:12:34 -0400 | [diff] [blame] | 1371 | } |
| 1372 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1373 | WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
| 1374 | (u32) fb_location); |
| 1375 | WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + |
| 1376 | radeon_crtc->crtc_offset, (u32) fb_location); |
| 1377 | WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
Alex Deucher | fa6bee4 | 2011-01-25 11:55:50 -0500 | [diff] [blame] | 1378 | if (rdev->family >= CHIP_R600) |
| 1379 | WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1380 | |
| 1381 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
| 1382 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
| 1383 | WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); |
| 1384 | WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1385 | WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); |
| 1386 | WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1387 | |
Ville Syrjälä | 01f2c77 | 2011-12-20 00:06:49 +0200 | [diff] [blame] | 1388 | fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1389 | WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
| 1390 | WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
| 1391 | |
| 1392 | WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
Michel Dänzer | 1b61925 | 2012-02-01 12:09:55 +0100 | [diff] [blame] | 1393 | target_fb->height); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1394 | x &= ~3; |
| 1395 | y &= ~1; |
| 1396 | WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, |
| 1397 | (x << 16) | y); |
Alex Deucher | adcfde5 | 2011-05-27 10:05:03 -0400 | [diff] [blame] | 1398 | viewport_w = crtc->mode.hdisplay; |
| 1399 | viewport_h = (crtc->mode.vdisplay + 1) & ~1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1400 | WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
Alex Deucher | adcfde5 | 2011-05-27 10:05:03 -0400 | [diff] [blame] | 1401 | (viewport_w << 16) | viewport_h); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1402 | |
Alex Deucher | fb9674b | 2011-04-02 09:15:50 -0400 | [diff] [blame] | 1403 | /* pageflip setup */ |
| 1404 | /* make sure flip is at vb rather than hb */ |
| 1405 | tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); |
| 1406 | tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; |
| 1407 | WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); |
| 1408 | |
| 1409 | /* set pageflip to happen anywhere in vblank interval */ |
| 1410 | WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); |
| 1411 | |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1412 | if (!atomic && fb && fb != crtc->fb) { |
| 1413 | radeon_fb = to_radeon_framebuffer(fb); |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 1414 | rbo = gem_to_radeon_bo(radeon_fb->obj); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1415 | r = radeon_bo_reserve(rbo, false); |
| 1416 | if (unlikely(r != 0)) |
| 1417 | return r; |
| 1418 | radeon_bo_unpin(rbo); |
| 1419 | radeon_bo_unreserve(rbo); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1420 | } |
Michel Dänzer | f30f37d | 2009-10-08 10:44:09 +0200 | [diff] [blame] | 1421 | |
| 1422 | /* Bytes per pixel may have changed */ |
| 1423 | radeon_bandwidth_update(rdev); |
| 1424 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1425 | return 0; |
| 1426 | } |
| 1427 | |
Alex Deucher | 54f088a | 2010-01-19 16:34:01 -0500 | [diff] [blame] | 1428 | int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
| 1429 | struct drm_framebuffer *old_fb) |
| 1430 | { |
| 1431 | struct drm_device *dev = crtc->dev; |
| 1432 | struct radeon_device *rdev = dev->dev_private; |
| 1433 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1434 | if (ASIC_IS_DCE4(rdev)) |
Alex Deucher | c9417bd | 2011-02-06 14:23:26 -0500 | [diff] [blame] | 1435 | return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1436 | else if (ASIC_IS_AVIVO(rdev)) |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1437 | return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); |
Alex Deucher | 54f088a | 2010-01-19 16:34:01 -0500 | [diff] [blame] | 1438 | else |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1439 | return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); |
| 1440 | } |
| 1441 | |
| 1442 | int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, |
| 1443 | struct drm_framebuffer *fb, |
Jason Wessel | 21c74a8 | 2010-10-13 14:09:44 -0500 | [diff] [blame] | 1444 | int x, int y, enum mode_set_atomic state) |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1445 | { |
| 1446 | struct drm_device *dev = crtc->dev; |
| 1447 | struct radeon_device *rdev = dev->dev_private; |
| 1448 | |
| 1449 | if (ASIC_IS_DCE4(rdev)) |
Alex Deucher | c9417bd | 2011-02-06 14:23:26 -0500 | [diff] [blame] | 1450 | return dce4_crtc_do_set_base(crtc, fb, x, y, 1); |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1451 | else if (ASIC_IS_AVIVO(rdev)) |
| 1452 | return avivo_crtc_do_set_base(crtc, fb, x, y, 1); |
| 1453 | else |
| 1454 | return radeon_crtc_do_set_base(crtc, fb, x, y, 1); |
Alex Deucher | 54f088a | 2010-01-19 16:34:01 -0500 | [diff] [blame] | 1455 | } |
| 1456 | |
Alex Deucher | 615e0cb | 2010-01-20 16:22:53 -0500 | [diff] [blame] | 1457 | /* properly set additional regs when using atombios */ |
| 1458 | static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) |
| 1459 | { |
| 1460 | struct drm_device *dev = crtc->dev; |
| 1461 | struct radeon_device *rdev = dev->dev_private; |
| 1462 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1463 | u32 disp_merge_cntl; |
| 1464 | |
| 1465 | switch (radeon_crtc->crtc_id) { |
| 1466 | case 0: |
| 1467 | disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); |
| 1468 | disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; |
| 1469 | WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); |
| 1470 | break; |
| 1471 | case 1: |
| 1472 | disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); |
| 1473 | disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; |
| 1474 | WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); |
| 1475 | WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); |
| 1476 | WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); |
| 1477 | break; |
| 1478 | } |
| 1479 | } |
| 1480 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1481 | static int radeon_atom_pick_pll(struct drm_crtc *crtc) |
| 1482 | { |
| 1483 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1484 | struct drm_device *dev = crtc->dev; |
| 1485 | struct radeon_device *rdev = dev->dev_private; |
| 1486 | struct drm_encoder *test_encoder; |
| 1487 | struct drm_crtc *test_crtc; |
| 1488 | uint32_t pll_in_use = 0; |
| 1489 | |
Alex Deucher | 24e1f79 | 2012-03-20 17:18:32 -0400 | [diff] [blame^] | 1490 | if (ASIC_IS_DCE61(rdev)) { |
| 1491 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { |
| 1492 | if (test_encoder->crtc && (test_encoder->crtc == crtc)) { |
| 1493 | struct radeon_encoder *test_radeon_encoder = |
| 1494 | to_radeon_encoder(test_encoder); |
| 1495 | struct radeon_encoder_atom_dig *dig = |
| 1496 | test_radeon_encoder->enc_priv; |
| 1497 | |
| 1498 | if ((test_radeon_encoder->encoder_id == |
| 1499 | ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && |
| 1500 | (dig->linkb == false)) /* UNIPHY A uses PPLL2 */ |
| 1501 | return ATOM_PPLL2; |
| 1502 | } |
| 1503 | } |
| 1504 | /* UNIPHY B/C/D/E/F */ |
| 1505 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
| 1506 | struct radeon_crtc *radeon_test_crtc; |
| 1507 | |
| 1508 | if (crtc == test_crtc) |
| 1509 | continue; |
| 1510 | |
| 1511 | radeon_test_crtc = to_radeon_crtc(test_crtc); |
| 1512 | if ((radeon_test_crtc->pll_id == ATOM_PPLL0) || |
| 1513 | (radeon_test_crtc->pll_id == ATOM_PPLL1)) |
| 1514 | pll_in_use |= (1 << radeon_test_crtc->pll_id); |
| 1515 | } |
| 1516 | if (!(pll_in_use & 4)) |
| 1517 | return ATOM_PPLL0; |
| 1518 | return ATOM_PPLL1; |
| 1519 | } else if (ASIC_IS_DCE4(rdev)) { |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1520 | list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { |
| 1521 | if (test_encoder->crtc && (test_encoder->crtc == crtc)) { |
Alex Deucher | 86a94de | 2011-05-20 04:34:17 -0400 | [diff] [blame] | 1522 | /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, |
| 1523 | * depending on the asic: |
| 1524 | * DCE4: PPLL or ext clock |
| 1525 | * DCE5: DCPLL or ext clock |
| 1526 | * |
| 1527 | * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip |
| 1528 | * PPLL/DCPLL programming and only program the DP DTO for the |
| 1529 | * crtc virtual pixel clock. |
| 1530 | */ |
Alex Deucher | 996d5c5 | 2011-10-26 15:59:50 -0400 | [diff] [blame] | 1531 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { |
Alex Deucher | 86a94de | 2011-05-20 04:34:17 -0400 | [diff] [blame] | 1532 | if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk) |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1533 | return ATOM_PPLL_INVALID; |
| 1534 | } |
| 1535 | } |
| 1536 | } |
| 1537 | |
| 1538 | /* otherwise, pick one of the plls */ |
| 1539 | list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { |
| 1540 | struct radeon_crtc *radeon_test_crtc; |
| 1541 | |
| 1542 | if (crtc == test_crtc) |
| 1543 | continue; |
| 1544 | |
| 1545 | radeon_test_crtc = to_radeon_crtc(test_crtc); |
| 1546 | if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) && |
| 1547 | (radeon_test_crtc->pll_id <= ATOM_PPLL2)) |
| 1548 | pll_in_use |= (1 << radeon_test_crtc->pll_id); |
| 1549 | } |
| 1550 | if (!(pll_in_use & 1)) |
| 1551 | return ATOM_PPLL1; |
| 1552 | return ATOM_PPLL2; |
| 1553 | } else |
| 1554 | return radeon_crtc->crtc_id; |
| 1555 | |
| 1556 | } |
| 1557 | |
Alex Deucher | f3f1f03 | 2012-03-20 17:18:04 -0400 | [diff] [blame] | 1558 | void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) |
Alex Deucher | 3fa47d9 | 2012-01-20 14:56:39 -0500 | [diff] [blame] | 1559 | { |
| 1560 | /* always set DCPLL */ |
Alex Deucher | f3f1f03 | 2012-03-20 17:18:04 -0400 | [diff] [blame] | 1561 | if (ASIC_IS_DCE6(rdev)) |
| 1562 | atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); |
| 1563 | else if (ASIC_IS_DCE4(rdev)) { |
Alex Deucher | 3fa47d9 | 2012-01-20 14:56:39 -0500 | [diff] [blame] | 1564 | struct radeon_atom_ss ss; |
| 1565 | bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, |
| 1566 | ASIC_INTERNAL_SS_ON_DCPLL, |
| 1567 | rdev->clock.default_dispclk); |
| 1568 | if (ss_enabled) |
| 1569 | atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, &ss); |
| 1570 | /* XXX: DCE5, make sure voltage, dispclk is high enough */ |
Alex Deucher | f3f1f03 | 2012-03-20 17:18:04 -0400 | [diff] [blame] | 1571 | atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); |
Alex Deucher | 3fa47d9 | 2012-01-20 14:56:39 -0500 | [diff] [blame] | 1572 | if (ss_enabled) |
| 1573 | atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, &ss); |
| 1574 | } |
| 1575 | |
| 1576 | } |
| 1577 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1578 | int atombios_crtc_mode_set(struct drm_crtc *crtc, |
| 1579 | struct drm_display_mode *mode, |
| 1580 | struct drm_display_mode *adjusted_mode, |
| 1581 | int x, int y, struct drm_framebuffer *old_fb) |
| 1582 | { |
| 1583 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1584 | struct drm_device *dev = crtc->dev; |
| 1585 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | 54bfe49 | 2010-09-03 15:52:53 -0400 | [diff] [blame] | 1586 | struct drm_encoder *encoder; |
| 1587 | bool is_tvcv = false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1588 | |
Alex Deucher | 54bfe49 | 2010-09-03 15:52:53 -0400 | [diff] [blame] | 1589 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 1590 | /* find tv std */ |
| 1591 | if (encoder->crtc == crtc) { |
| 1592 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 1593 | if (radeon_encoder->active_device & |
| 1594 | (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
| 1595 | is_tvcv = true; |
| 1596 | } |
| 1597 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1598 | |
| 1599 | atombios_crtc_set_pll(crtc, adjusted_mode); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1600 | |
Alex Deucher | 54bfe49 | 2010-09-03 15:52:53 -0400 | [diff] [blame] | 1601 | if (ASIC_IS_DCE4(rdev)) |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1602 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
Alex Deucher | 54bfe49 | 2010-09-03 15:52:53 -0400 | [diff] [blame] | 1603 | else if (ASIC_IS_AVIVO(rdev)) { |
| 1604 | if (is_tvcv) |
| 1605 | atombios_crtc_set_timing(crtc, adjusted_mode); |
| 1606 | else |
| 1607 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
| 1608 | } else { |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1609 | atombios_crtc_set_timing(crtc, adjusted_mode); |
Alex Deucher | 5a9bcac | 2009-10-08 15:09:31 -0400 | [diff] [blame] | 1610 | if (radeon_crtc->crtc_id == 0) |
| 1611 | atombios_set_crtc_dtd_timing(crtc, adjusted_mode); |
Alex Deucher | 615e0cb | 2010-01-20 16:22:53 -0500 | [diff] [blame] | 1612 | radeon_legacy_atom_fixup(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1613 | } |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1614 | atombios_crtc_set_base(crtc, x, y, old_fb); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1615 | atombios_overscan_setup(crtc, mode, adjusted_mode); |
| 1616 | atombios_scaler_setup(crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1617 | return 0; |
| 1618 | } |
| 1619 | |
| 1620 | static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, |
| 1621 | struct drm_display_mode *mode, |
| 1622 | struct drm_display_mode *adjusted_mode) |
| 1623 | { |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1624 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
| 1625 | return false; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1626 | return true; |
| 1627 | } |
| 1628 | |
| 1629 | static void atombios_crtc_prepare(struct drm_crtc *crtc) |
| 1630 | { |
Alex Deucher | 267364a | 2010-03-08 17:10:41 -0500 | [diff] [blame] | 1631 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
| 1632 | |
| 1633 | /* pick pll */ |
| 1634 | radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); |
| 1635 | |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 1636 | atombios_lock_crtc(crtc, ATOM_ENABLE); |
Alex Deucher | a348c84 | 2010-01-21 16:50:30 -0500 | [diff] [blame] | 1637 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1638 | } |
| 1639 | |
| 1640 | static void atombios_crtc_commit(struct drm_crtc *crtc) |
| 1641 | { |
| 1642 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
Alex Deucher | 37b4390 | 2010-02-09 12:04:43 -0500 | [diff] [blame] | 1643 | atombios_lock_crtc(crtc, ATOM_DISABLE); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1644 | } |
| 1645 | |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 1646 | static void atombios_crtc_disable(struct drm_crtc *crtc) |
| 1647 | { |
| 1648 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame] | 1649 | struct radeon_atom_ss ss; |
| 1650 | |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 1651 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
| 1652 | |
| 1653 | switch (radeon_crtc->pll_id) { |
| 1654 | case ATOM_PPLL1: |
| 1655 | case ATOM_PPLL2: |
| 1656 | /* disable the ppll */ |
| 1657 | atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |
Alex Deucher | 8e8e523 | 2011-05-20 04:34:16 -0400 | [diff] [blame] | 1658 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 1659 | break; |
| 1660 | default: |
| 1661 | break; |
| 1662 | } |
| 1663 | radeon_crtc->pll_id = -1; |
| 1664 | } |
| 1665 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1666 | static const struct drm_crtc_helper_funcs atombios_helper_funcs = { |
| 1667 | .dpms = atombios_crtc_dpms, |
| 1668 | .mode_fixup = atombios_crtc_mode_fixup, |
| 1669 | .mode_set = atombios_crtc_mode_set, |
| 1670 | .mode_set_base = atombios_crtc_set_base, |
Chris Ball | 4dd19b0 | 2010-09-26 06:47:23 -0500 | [diff] [blame] | 1671 | .mode_set_base_atomic = atombios_crtc_set_base_atomic, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1672 | .prepare = atombios_crtc_prepare, |
| 1673 | .commit = atombios_crtc_commit, |
Dave Airlie | 068143d | 2009-10-05 09:58:02 +1000 | [diff] [blame] | 1674 | .load_lut = radeon_crtc_load_lut, |
Alex Deucher | 37f9003 | 2010-06-11 17:58:38 -0400 | [diff] [blame] | 1675 | .disable = atombios_crtc_disable, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1676 | }; |
| 1677 | |
| 1678 | void radeon_atombios_init_crtc(struct drm_device *dev, |
| 1679 | struct radeon_crtc *radeon_crtc) |
| 1680 | { |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1681 | struct radeon_device *rdev = dev->dev_private; |
| 1682 | |
| 1683 | if (ASIC_IS_DCE4(rdev)) { |
| 1684 | switch (radeon_crtc->crtc_id) { |
| 1685 | case 0: |
| 1686 | default: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1687 | radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1688 | break; |
| 1689 | case 1: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1690 | radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1691 | break; |
| 1692 | case 2: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1693 | radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1694 | break; |
| 1695 | case 3: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1696 | radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1697 | break; |
| 1698 | case 4: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1699 | radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1700 | break; |
| 1701 | case 5: |
Alex Deucher | 12d7798 | 2010-02-09 17:18:48 -0500 | [diff] [blame] | 1702 | radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1703 | break; |
| 1704 | } |
| 1705 | } else { |
| 1706 | if (radeon_crtc->crtc_id == 1) |
| 1707 | radeon_crtc->crtc_offset = |
| 1708 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; |
| 1709 | else |
| 1710 | radeon_crtc->crtc_offset = 0; |
| 1711 | } |
| 1712 | radeon_crtc->pll_id = -1; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1713 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); |
| 1714 | } |