| Vitaly Wool | 78818e4 | 2006-05-16 11:54:37 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-pnx4008/clock.h |
| 3 | * |
| 4 | * Clock control driver for PNX4008 - internal header file |
| 5 | * |
| 6 | * Author: Vitaly Wool <source@mvista.com> |
| 7 | * |
| 8 | * 2006 (c) MontaVista Software, Inc. This file is licensed under |
| 9 | * the terms of the GNU General Public License version 2. This program |
| 10 | * is licensed "as is" without any warranty of any kind, whether express |
| 11 | * or implied. |
| 12 | */ |
| 13 | #ifndef __ARCH_ARM_PNX4008_CLOCK_H__ |
| 14 | #define __ARCH_ARM_PNX4008_CLOCK_H__ |
| 15 | |
| 16 | struct clk { |
| 17 | struct list_head node; |
| 18 | struct module *owner; |
| 19 | const char *name; |
| 20 | struct clk *parent; |
| 21 | struct clk *propagate_next; |
| 22 | u32 rate; |
| 23 | u32 user_rate; |
| 24 | s8 usecount; |
| 25 | u32 flags; |
| 26 | u32 scale_reg; |
| 27 | u8 enable_shift; |
| 28 | u32 enable_reg; |
| 29 | u8 enable_shift1; |
| 30 | u32 enable_reg1; |
| 31 | u32 parent_switch_reg; |
| 32 | u32(*round_rate) (struct clk *, u32); |
| 33 | int (*set_rate) (struct clk *, u32); |
| 34 | int (*set_parent) (struct clk * clk, struct clk * parent); |
| 35 | }; |
| 36 | |
| 37 | /* Flags */ |
| 38 | #define RATE_PROPAGATES (1<<0) |
| 39 | #define NEEDS_INITIALIZATION (1<<1) |
| 40 | #define PARENT_SET_RATE (1<<2) |
| 41 | #define FIXED_RATE (1<<3) |
| 42 | |
| 43 | #endif |