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Chaithrika U Sb67f4482009-06-05 06:28:40 -04001/*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
21#include <linux/delay.h>
22#include <linux/io.h>
23#include <linux/clk.h>
24
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/initval.h>
29#include <sound/soc.h>
30
31#include "davinci-pcm.h"
32#include "davinci-mcasp.h"
33
34/*
35 * McASP register definitions
36 */
37#define DAVINCI_MCASP_PID_REG 0x00
38#define DAVINCI_MCASP_PWREMUMGT_REG 0x04
39
40#define DAVINCI_MCASP_PFUNC_REG 0x10
41#define DAVINCI_MCASP_PDIR_REG 0x14
42#define DAVINCI_MCASP_PDOUT_REG 0x18
43#define DAVINCI_MCASP_PDSET_REG 0x1c
44
45#define DAVINCI_MCASP_PDCLR_REG 0x20
46
47#define DAVINCI_MCASP_TLGC_REG 0x30
48#define DAVINCI_MCASP_TLMR_REG 0x34
49
50#define DAVINCI_MCASP_GBLCTL_REG 0x44
51#define DAVINCI_MCASP_AMUTE_REG 0x48
52#define DAVINCI_MCASP_LBCTL_REG 0x4c
53
54#define DAVINCI_MCASP_TXDITCTL_REG 0x50
55
56#define DAVINCI_MCASP_GBLCTLR_REG 0x60
57#define DAVINCI_MCASP_RXMASK_REG 0x64
58#define DAVINCI_MCASP_RXFMT_REG 0x68
59#define DAVINCI_MCASP_RXFMCTL_REG 0x6c
60
61#define DAVINCI_MCASP_ACLKRCTL_REG 0x70
62#define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
63#define DAVINCI_MCASP_RXTDM_REG 0x78
64#define DAVINCI_MCASP_EVTCTLR_REG 0x7c
65
66#define DAVINCI_MCASP_RXSTAT_REG 0x80
67#define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
68#define DAVINCI_MCASP_RXCLKCHK_REG 0x88
69#define DAVINCI_MCASP_REVTCTL_REG 0x8c
70
71#define DAVINCI_MCASP_GBLCTLX_REG 0xa0
72#define DAVINCI_MCASP_TXMASK_REG 0xa4
73#define DAVINCI_MCASP_TXFMT_REG 0xa8
74#define DAVINCI_MCASP_TXFMCTL_REG 0xac
75
76#define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
77#define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
78#define DAVINCI_MCASP_TXTDM_REG 0xb8
79#define DAVINCI_MCASP_EVTCTLX_REG 0xbc
80
81#define DAVINCI_MCASP_TXSTAT_REG 0xc0
82#define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
83#define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
84#define DAVINCI_MCASP_XEVTCTL_REG 0xcc
85
86/* Left(even TDM Slot) Channel Status Register File */
87#define DAVINCI_MCASP_DITCSRA_REG 0x100
88/* Right(odd TDM slot) Channel Status Register File */
89#define DAVINCI_MCASP_DITCSRB_REG 0x118
90/* Left(even TDM slot) User Data Register File */
91#define DAVINCI_MCASP_DITUDRA_REG 0x130
92/* Right(odd TDM Slot) User Data Register File */
93#define DAVINCI_MCASP_DITUDRB_REG 0x148
94
95/* Serializer n Control Register */
96#define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
97#define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
98 (n << 2))
99
100/* Transmit Buffer for Serializer n */
101#define DAVINCI_MCASP_TXBUF_REG 0x200
102/* Receive Buffer for Serializer n */
103#define DAVINCI_MCASP_RXBUF_REG 0x280
104
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400105/* McASP FIFO Registers */
106#define DAVINCI_MCASP_WFIFOCTL (0x1010)
107#define DAVINCI_MCASP_WFIFOSTS (0x1014)
108#define DAVINCI_MCASP_RFIFOCTL (0x1018)
109#define DAVINCI_MCASP_RFIFOSTS (0x101C)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400110
111/*
112 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
113 * Register Bits
114 */
115#define MCASP_FREE BIT(0)
116#define MCASP_SOFT BIT(1)
117
118/*
119 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
120 */
121#define AXR(n) (1<<n)
122#define PFUNC_AMUTE BIT(25)
123#define ACLKX BIT(26)
124#define AHCLKX BIT(27)
125#define AFSX BIT(28)
126#define ACLKR BIT(29)
127#define AHCLKR BIT(30)
128#define AFSR BIT(31)
129
130/*
131 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
132 */
133#define AXR(n) (1<<n)
134#define PDIR_AMUTE BIT(25)
135#define ACLKX BIT(26)
136#define AHCLKX BIT(27)
137#define AFSX BIT(28)
138#define ACLKR BIT(29)
139#define AHCLKR BIT(30)
140#define AFSR BIT(31)
141
142/*
143 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
144 */
145#define DITEN BIT(0) /* Transmit DIT mode enable/disable */
146#define VA BIT(2)
147#define VB BIT(3)
148
149/*
150 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
151 */
152#define TXROT(val) (val)
153#define TXSEL BIT(3)
154#define TXSSZ(val) (val<<4)
155#define TXPBIT(val) (val<<8)
156#define TXPAD(val) (val<<13)
157#define TXORD BIT(15)
158#define FSXDLY(val) (val<<16)
159
160/*
161 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
162 */
163#define RXROT(val) (val)
164#define RXSEL BIT(3)
165#define RXSSZ(val) (val<<4)
166#define RXPBIT(val) (val<<8)
167#define RXPAD(val) (val<<13)
168#define RXORD BIT(15)
169#define FSRDLY(val) (val<<16)
170
171/*
172 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
173 */
174#define FSXPOL BIT(0)
175#define AFSXE BIT(1)
176#define FSXDUR BIT(4)
177#define FSXMOD(val) (val<<7)
178
179/*
180 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
181 */
182#define FSRPOL BIT(0)
183#define AFSRE BIT(1)
184#define FSRDUR BIT(4)
185#define FSRMOD(val) (val<<7)
186
187/*
188 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
189 */
190#define ACLKXDIV(val) (val)
191#define ACLKXE BIT(5)
192#define TX_ASYNC BIT(6)
193#define ACLKXPOL BIT(7)
194
195/*
196 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
197 */
198#define ACLKRDIV(val) (val)
199#define ACLKRE BIT(5)
200#define RX_ASYNC BIT(6)
201#define ACLKRPOL BIT(7)
202
203/*
204 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
205 * Register Bits
206 */
207#define AHCLKXDIV(val) (val)
208#define AHCLKXPOL BIT(14)
209#define AHCLKXE BIT(15)
210
211/*
212 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
213 * Register Bits
214 */
215#define AHCLKRDIV(val) (val)
216#define AHCLKRPOL BIT(14)
217#define AHCLKRE BIT(15)
218
219/*
220 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
221 */
222#define MODE(val) (val)
223#define DISMOD (val)(val<<2)
224#define TXSTATE BIT(4)
225#define RXSTATE BIT(5)
226
227/*
228 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
229 */
230#define LBEN BIT(0)
231#define LBORD BIT(1)
232#define LBGENMODE(val) (val<<2)
233
234/*
235 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
236 */
237#define TXTDMS(n) (1<<n)
238
239/*
240 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
241 */
242#define RXTDMS(n) (1<<n)
243
244/*
245 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
246 */
247#define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
248#define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
249#define RXSERCLR BIT(2) /* Receiver Serializer Clear */
250#define RXSMRST BIT(3) /* Receiver State Machine Reset */
251#define RXFSRST BIT(4) /* Frame Sync Generator Reset */
252#define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
253#define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
254#define TXSERCLR BIT(10) /* Transmit Serializer Clear */
255#define TXSMRST BIT(11) /* Transmitter State Machine Reset */
256#define TXFSRST BIT(12) /* Frame Sync Generator Reset */
257
258/*
259 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
260 */
261#define MUTENA(val) (val)
262#define MUTEINPOL BIT(2)
263#define MUTEINENA BIT(3)
264#define MUTEIN BIT(4)
265#define MUTER BIT(5)
266#define MUTEX BIT(6)
267#define MUTEFSR BIT(7)
268#define MUTEFSX BIT(8)
269#define MUTEBADCLKR BIT(9)
270#define MUTEBADCLKX BIT(10)
271#define MUTERXDMAERR BIT(11)
272#define MUTETXDMAERR BIT(12)
273
274/*
275 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
276 */
277#define RXDATADMADIS BIT(0)
278
279/*
280 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
281 */
282#define TXDATADMADIS BIT(0)
283
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400284/*
285 * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
286 */
287#define FIFO_ENABLE BIT(16)
288#define NUMEVT_MASK (0xFF << 8)
289#define NUMDMA_MASK (0xFF)
290
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400291#define DAVINCI_MCASP_NUM_SERIALIZER 16
292
293static inline void mcasp_set_bits(void __iomem *reg, u32 val)
294{
295 __raw_writel(__raw_readl(reg) | val, reg);
296}
297
298static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
299{
300 __raw_writel((__raw_readl(reg) & ~(val)), reg);
301}
302
303static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
304{
305 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
306}
307
308static inline void mcasp_set_reg(void __iomem *reg, u32 val)
309{
310 __raw_writel(val, reg);
311}
312
313static inline u32 mcasp_get_reg(void __iomem *reg)
314{
315 return (unsigned int)__raw_readl(reg);
316}
317
318static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
319{
320 int i = 0;
321
322 mcasp_set_bits(regs, val);
323
324 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
325 /* loop count is to avoid the lock-up */
326 for (i = 0; i < 1000; i++) {
327 if ((mcasp_get_reg(regs) & val) == val)
328 break;
329 }
330
331 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
332 printk(KERN_ERR "GBLCTL write error\n");
333}
334
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400335static void mcasp_start_rx(struct davinci_audio_dev *dev)
336{
337 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
338 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
339 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
340 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
341
342 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
343 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
344 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
345
346 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
347 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
348}
349
350static void mcasp_start_tx(struct davinci_audio_dev *dev)
351{
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400352 u8 offset = 0, i;
353 u32 cnt;
354
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400355 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
356 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
357 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
358 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
359
360 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
361 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
362 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400363 for (i = 0; i < dev->num_serializer; i++) {
364 if (dev->serial_dir[i] == TX_MODE) {
365 offset = i;
366 break;
367 }
368 }
369
370 /* wait for TX ready */
371 cnt = 0;
372 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
373 TXSTATE) && (cnt < 100000))
374 cnt++;
375
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400376 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
377}
378
379static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
380{
Chaithrika U S539d3d82009-09-23 10:12:08 -0400381 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
382 if (dev->txnumevt) /* enable FIFO */
383 mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
384 FIFO_ENABLE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400385 mcasp_start_tx(dev);
Chaithrika U S539d3d82009-09-23 10:12:08 -0400386 } else {
387 if (dev->rxnumevt) /* enable FIFO */
388 mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
389 FIFO_ENABLE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400390 mcasp_start_rx(dev);
Chaithrika U S539d3d82009-09-23 10:12:08 -0400391 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400392}
393
394static void mcasp_stop_rx(struct davinci_audio_dev *dev)
395{
396 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
397 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
398}
399
400static void mcasp_stop_tx(struct davinci_audio_dev *dev)
401{
402 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
403 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
404}
405
406static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
407{
Chaithrika U S539d3d82009-09-23 10:12:08 -0400408 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
409 if (dev->txnumevt) /* disable FIFO */
410 mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
411 FIFO_ENABLE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400412 mcasp_stop_tx(dev);
Chaithrika U S539d3d82009-09-23 10:12:08 -0400413 } else {
414 if (dev->rxnumevt) /* disable FIFO */
415 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
416 FIFO_ENABLE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400417 mcasp_stop_rx(dev);
Chaithrika U S539d3d82009-09-23 10:12:08 -0400418 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400419}
420
421static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
422 unsigned int fmt)
423{
424 struct davinci_audio_dev *dev = cpu_dai->private_data;
425 void __iomem *base = dev->base;
426
427 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
428 case SND_SOC_DAIFMT_CBS_CFS:
429 /* codec is clock and frame slave */
430 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
431 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
432
433 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
434 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
435
436 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x7 << 26));
437 break;
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400438 case SND_SOC_DAIFMT_CBM_CFS:
439 /* codec is clock master and frame slave */
440 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
441 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
442
443 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
444 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
445
446 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x2d << 26));
447 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400448 case SND_SOC_DAIFMT_CBM_CFM:
449 /* codec is clock and frame master */
450 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
451 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
452
453 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
454 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
455
456 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG, (0x3f << 26));
457 break;
458
459 default:
460 return -EINVAL;
461 }
462
463 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
464 case SND_SOC_DAIFMT_IB_NF:
465 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
466 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
467
468 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
469 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
470 break;
471
472 case SND_SOC_DAIFMT_NB_IF:
473 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
474 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
475
476 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
477 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
478 break;
479
480 case SND_SOC_DAIFMT_IB_IF:
481 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
482 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
483
484 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
485 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
486 break;
487
488 case SND_SOC_DAIFMT_NB_NF:
489 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
490 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
491
492 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
493 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
494 break;
495
496 default:
497 return -EINVAL;
498 }
499
500 return 0;
501}
502
503static int davinci_config_channel_size(struct davinci_audio_dev *dev,
504 int channel_size)
505{
506 u32 fmt = 0;
Chaithrika U S0c31cf32009-09-15 18:13:29 -0400507 u32 mask, rotate;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400508
509 switch (channel_size) {
510 case DAVINCI_AUDIO_WORD_8:
511 fmt = 0x03;
Chaithrika U S0c31cf32009-09-15 18:13:29 -0400512 rotate = 6;
513 mask = 0x000000ff;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400514 break;
515
516 case DAVINCI_AUDIO_WORD_12:
517 fmt = 0x05;
Chaithrika U S0c31cf32009-09-15 18:13:29 -0400518 rotate = 5;
519 mask = 0x00000fff;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400520 break;
521
522 case DAVINCI_AUDIO_WORD_16:
523 fmt = 0x07;
Chaithrika U S0c31cf32009-09-15 18:13:29 -0400524 rotate = 4;
525 mask = 0x0000ffff;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400526 break;
527
528 case DAVINCI_AUDIO_WORD_20:
529 fmt = 0x09;
Chaithrika U S0c31cf32009-09-15 18:13:29 -0400530 rotate = 3;
531 mask = 0x000fffff;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400532 break;
533
534 case DAVINCI_AUDIO_WORD_24:
535 fmt = 0x0B;
Chaithrika U S0c31cf32009-09-15 18:13:29 -0400536 rotate = 2;
537 mask = 0x00ffffff;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400538 break;
539
540 case DAVINCI_AUDIO_WORD_28:
541 fmt = 0x0D;
Chaithrika U S0c31cf32009-09-15 18:13:29 -0400542 rotate = 1;
543 mask = 0x0fffffff;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400544 break;
545
546 case DAVINCI_AUDIO_WORD_32:
547 fmt = 0x0F;
Chaithrika U S0c31cf32009-09-15 18:13:29 -0400548 rotate = 0;
549 mask = 0xffffffff;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400550 break;
551
552 default:
553 return -EINVAL;
554 }
555
556 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
557 RXSSZ(fmt), RXSSZ(0x0F));
558 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
559 TXSSZ(fmt), TXSSZ(0x0F));
Chaithrika U S0c31cf32009-09-15 18:13:29 -0400560 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXROT(rotate),
561 TXROT(7));
562 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXROT(rotate),
563 RXROT(7));
564 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
565 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, mask);
566
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400567 return 0;
568}
569
570static void davinci_hw_common_param(struct davinci_audio_dev *dev, int stream)
571{
572 int i;
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400573 u8 tx_ser = 0;
574 u8 rx_ser = 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400575
576 /* Default configuration */
577 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
578
579 /* All PINS as McASP */
580 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
581
582 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
583 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
584 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
585 TXDATADMADIS);
586 } else {
587 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
588 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
589 RXDATADMADIS);
590 }
591
592 for (i = 0; i < dev->num_serializer; i++) {
593 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
594 dev->serial_dir[i]);
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400595 if (dev->serial_dir[i] == TX_MODE) {
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400596 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
597 AXR(i));
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400598 tx_ser++;
599 } else if (dev->serial_dir[i] == RX_MODE) {
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400600 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
601 AXR(i));
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400602 rx_ser++;
603 }
604 }
605
606 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
607 if (dev->txnumevt * tx_ser > 64)
608 dev->txnumevt = 1;
609
610 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, tx_ser,
611 NUMDMA_MASK);
612 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
613 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
614 mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
615 }
616
617 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
618 if (dev->rxnumevt * rx_ser > 64)
619 dev->rxnumevt = 1;
620
621 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, rx_ser,
622 NUMDMA_MASK);
623 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
624 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
625 mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400626 }
627}
628
629static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
630{
631 int i, active_slots;
632 u32 mask = 0;
633
634 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
635 for (i = 0; i < active_slots; i++)
636 mask |= (1 << i);
637
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400638 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
639
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400640 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
641 /* bit stream is MSB first with no delay */
642 /* DSP_B mode */
643 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
644 AHCLKXE);
645 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
646 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
647
648 if ((dev->tdm_slots >= 2) || (dev->tdm_slots <= 32))
649 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
650 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
651 else
652 printk(KERN_ERR "playback tdm slot %d not supported\n",
653 dev->tdm_slots);
654
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400655 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
656 } else {
657 /* bit stream is MSB first with no delay */
658 /* DSP_B mode */
659 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
660 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
661 AHCLKRE);
662 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
663
664 if ((dev->tdm_slots >= 2) || (dev->tdm_slots <= 32))
665 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
666 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
667 else
668 printk(KERN_ERR "capture tdm slot %d not supported\n",
669 dev->tdm_slots);
670
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400671 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
672 }
673}
674
675/* S/PDIF */
676static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
677{
678 /* Set the PDIR for Serialiser as output */
679 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AFSX);
680
681 /* TXMASK for 24 bits */
682 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0x00FFFFFF);
683
684 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
685 and LSB first */
686 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
687 TXROT(6) | TXSSZ(15));
688
689 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
690 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
691 AFSXE | FSXMOD(0x180));
692
693 /* Set the TX tdm : for all the slots */
694 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
695
696 /* Set the TX clock controls : div = 1 and internal */
697 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
698 ACLKXE | TX_ASYNC);
699
700 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
701
702 /* Only 44100 and 48000 are valid, both have the same setting */
703 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
704
705 /* Enable the DIT */
706 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
707}
708
709static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
710 struct snd_pcm_hw_params *params,
711 struct snd_soc_dai *cpu_dai)
712{
713 struct davinci_audio_dev *dev = cpu_dai->private_data;
714 struct davinci_pcm_dma_params *dma_params =
Troy Kisky92e2a6f2009-09-11 14:29:03 -0700715 &dev->dma_params[substream->stream];
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400716 int word_length;
Chaithrika U S4fa9c1a2009-09-30 17:32:27 -0400717 u8 fifo_level;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400718
719 davinci_hw_common_param(dev, substream->stream);
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400720 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
Chaithrika U S4fa9c1a2009-09-30 17:32:27 -0400721 fifo_level = dev->txnumevt;
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400722 else
Chaithrika U S4fa9c1a2009-09-30 17:32:27 -0400723 fifo_level = dev->rxnumevt;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400724
725 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
726 davinci_hw_dit_param(dev);
727 else
728 davinci_hw_param(dev, substream->stream);
729
730 switch (params_format(params)) {
731 case SNDRV_PCM_FORMAT_S8:
732 dma_params->data_type = 1;
733 word_length = DAVINCI_AUDIO_WORD_8;
734 break;
735
736 case SNDRV_PCM_FORMAT_S16_LE:
737 dma_params->data_type = 2;
738 word_length = DAVINCI_AUDIO_WORD_16;
739 break;
740
741 case SNDRV_PCM_FORMAT_S32_LE:
742 dma_params->data_type = 4;
743 word_length = DAVINCI_AUDIO_WORD_32;
744 break;
745
746 default:
747 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
748 return -EINVAL;
749 }
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400750
Chaithrika U S4fa9c1a2009-09-30 17:32:27 -0400751 if (dev->version == MCASP_VERSION_2 && !fifo_level)
752 dma_params->acnt = 4;
753 else
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400754 dma_params->acnt = dma_params->data_type;
755
Chaithrika U S4fa9c1a2009-09-30 17:32:27 -0400756 dma_params->fifo_level = fifo_level;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400757 davinci_config_channel_size(dev, word_length);
758
759 return 0;
760}
761
762static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
763 int cmd, struct snd_soc_dai *cpu_dai)
764{
765 struct snd_soc_pcm_runtime *rtd = substream->private_data;
766 struct davinci_audio_dev *dev = rtd->dai->cpu_dai->private_data;
767 int ret = 0;
768
769 switch (cmd) {
770 case SNDRV_PCM_TRIGGER_START:
771 case SNDRV_PCM_TRIGGER_RESUME:
772 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
773 davinci_mcasp_start(dev, substream->stream);
774 break;
775
776 case SNDRV_PCM_TRIGGER_STOP:
777 case SNDRV_PCM_TRIGGER_SUSPEND:
778 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
779 davinci_mcasp_stop(dev, substream->stream);
780 break;
781
782 default:
783 ret = -EINVAL;
784 }
785
786 return ret;
787}
788
789static struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400790 .trigger = davinci_mcasp_trigger,
791 .hw_params = davinci_mcasp_hw_params,
792 .set_fmt = davinci_mcasp_set_dai_fmt,
793
794};
795
796struct snd_soc_dai davinci_mcasp_dai[] = {
797 {
798 .name = "davinci-i2s",
799 .id = 0,
800 .playback = {
801 .channels_min = 2,
802 .channels_max = 2,
803 .rates = DAVINCI_MCASP_RATES,
804 .formats = SNDRV_PCM_FMTBIT_S8 |
805 SNDRV_PCM_FMTBIT_S16_LE |
806 SNDRV_PCM_FMTBIT_S32_LE,
807 },
808 .capture = {
809 .channels_min = 2,
810 .channels_max = 2,
811 .rates = DAVINCI_MCASP_RATES,
812 .formats = SNDRV_PCM_FMTBIT_S8 |
813 SNDRV_PCM_FMTBIT_S16_LE |
814 SNDRV_PCM_FMTBIT_S32_LE,
815 },
816 .ops = &davinci_mcasp_dai_ops,
817
818 },
819 {
820 .name = "davinci-dit",
821 .id = 1,
822 .playback = {
823 .channels_min = 1,
824 .channels_max = 384,
825 .rates = DAVINCI_MCASP_RATES,
826 .formats = SNDRV_PCM_FMTBIT_S16_LE,
827 },
828 .ops = &davinci_mcasp_dai_ops,
829 },
830
831};
832EXPORT_SYMBOL_GPL(davinci_mcasp_dai);
833
834static int davinci_mcasp_probe(struct platform_device *pdev)
835{
836 struct davinci_pcm_dma_params *dma_data;
837 struct resource *mem, *ioarea, *res;
838 struct snd_platform_data *pdata;
839 struct davinci_audio_dev *dev;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400840 int ret = 0;
841
842 dev = kzalloc(sizeof(struct davinci_audio_dev), GFP_KERNEL);
843 if (!dev)
844 return -ENOMEM;
845
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400846 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
847 if (!mem) {
848 dev_err(&pdev->dev, "no mem resource?\n");
849 ret = -ENODEV;
850 goto err_release_data;
851 }
852
853 ioarea = request_mem_region(mem->start,
854 (mem->end - mem->start) + 1, pdev->name);
855 if (!ioarea) {
856 dev_err(&pdev->dev, "Audio region already claimed\n");
857 ret = -EBUSY;
858 goto err_release_data;
859 }
860
861 pdata = pdev->dev.platform_data;
Kevin Hilman3e46a442009-07-15 10:42:09 -0700862 dev->clk = clk_get(&pdev->dev, NULL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400863 if (IS_ERR(dev->clk)) {
864 ret = -ENODEV;
865 goto err_release_region;
866 }
867
868 clk_enable(dev->clk);
869
870 dev->base = (void __iomem *)IO_ADDRESS(mem->start);
871 dev->op_mode = pdata->op_mode;
872 dev->tdm_slots = pdata->tdm_slots;
873 dev->num_serializer = pdata->num_serializer;
874 dev->serial_dir = pdata->serial_dir;
875 dev->codec_fmt = pdata->codec_fmt;
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400876 dev->version = pdata->version;
877 dev->txnumevt = pdata->txnumevt;
878 dev->rxnumevt = pdata->rxnumevt;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400879
Troy Kisky92e2a6f2009-09-11 14:29:03 -0700880 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
881 dma_data->eventq_no = pdata->eventq_no;
882 dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400883 io_v2p(dev->base));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400884
885 /* first TX, then RX */
886 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
887 if (!res) {
888 dev_err(&pdev->dev, "no DMA resource\n");
889 goto err_release_region;
890 }
891
Troy Kisky92e2a6f2009-09-11 14:29:03 -0700892 dma_data->channel = res->start;
893
894 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
895 dma_data->eventq_no = pdata->eventq_no;
896 dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400897 io_v2p(dev->base));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400898
899 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
900 if (!res) {
901 dev_err(&pdev->dev, "no DMA resource\n");
902 goto err_release_region;
903 }
904
Troy Kisky92e2a6f2009-09-11 14:29:03 -0700905 dma_data->channel = res->start;
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400906 davinci_mcasp_dai[pdata->op_mode].private_data = dev;
Troy Kisky57512c62009-11-16 16:52:31 -0700907 davinci_mcasp_dai[pdata->op_mode].dma_data = dev->dma_params;
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400908 davinci_mcasp_dai[pdata->op_mode].dev = &pdev->dev;
909 ret = snd_soc_register_dai(&davinci_mcasp_dai[pdata->op_mode]);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400910
911 if (ret != 0)
912 goto err_release_region;
913 return 0;
914
915err_release_region:
916 release_mem_region(mem->start, (mem->end - mem->start) + 1);
917err_release_data:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400918 kfree(dev);
919
920 return ret;
921}
922
923static int davinci_mcasp_remove(struct platform_device *pdev)
924{
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400925 struct snd_platform_data *pdata = pdev->dev.platform_data;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400926 struct davinci_audio_dev *dev;
927 struct resource *mem;
928
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400929 snd_soc_unregister_dai(&davinci_mcasp_dai[pdata->op_mode]);
930 dev = davinci_mcasp_dai[pdata->op_mode].private_data;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400931 clk_disable(dev->clk);
932 clk_put(dev->clk);
933 dev->clk = NULL;
934
935 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
936 release_mem_region(mem->start, (mem->end - mem->start) + 1);
937
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400938 kfree(dev);
939
940 return 0;
941}
942
943static struct platform_driver davinci_mcasp_driver = {
944 .probe = davinci_mcasp_probe,
945 .remove = davinci_mcasp_remove,
946 .driver = {
947 .name = "davinci-mcasp",
948 .owner = THIS_MODULE,
949 },
950};
951
952static int __init davinci_mcasp_init(void)
953{
954 return platform_driver_register(&davinci_mcasp_driver);
955}
956module_init(davinci_mcasp_init);
957
958static void __exit davinci_mcasp_exit(void)
959{
960 platform_driver_unregister(&davinci_mcasp_driver);
961}
962module_exit(davinci_mcasp_exit);
963
964MODULE_AUTHOR("Steve Chen");
965MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
966MODULE_LICENSE("GPL");
967