blob: 3800fc791b2f788f69a2c19241f7cc54ebc392f6 [file] [log] [blame]
Ben Hutchings8ceee662008-04-27 12:55:59 +01001/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
Ben Hutchings906bb262009-11-29 15:16:19 +00003 * Copyright 2006-2009 Solarflare Communications Inc.
Ben Hutchings8ceee662008-04-27 12:55:59 +01004 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9/*
Ben Hutchingsb37b62f2009-10-23 08:33:42 +000010 * Driver for AMCC QT202x SFP+ and XFP adapters; see www.amcc.com for details
Ben Hutchings8ceee662008-04-27 12:55:59 +010011 */
12
13#include <linux/timer.h>
14#include <linux/delay.h>
15#include "efx.h"
Ben Hutchings8ceee662008-04-27 12:55:59 +010016#include "mdio_10g.h"
Ben Hutchings8ceee662008-04-27 12:55:59 +010017#include "phy.h"
Ben Hutchings744093c2009-11-29 15:12:08 +000018#include "nic.h"
Ben Hutchings8ceee662008-04-27 12:55:59 +010019
Ben Hutchingsb37b62f2009-10-23 08:33:42 +000020#define QT202X_REQUIRED_DEVS (MDIO_DEVS_PCS | \
21 MDIO_DEVS_PMAPMD | \
22 MDIO_DEVS_PHYXS)
Ben Hutchings8ceee662008-04-27 12:55:59 +010023
Ben Hutchingsb37b62f2009-10-23 08:33:42 +000024#define QT202X_LOOPBACKS ((1 << LOOPBACK_PCS) | \
25 (1 << LOOPBACK_PMAPMD) | \
Ben Hutchingse58f69f2009-11-29 15:08:41 +000026 (1 << LOOPBACK_PHYXS_WS))
Ben Hutchings3273c2e2008-05-07 13:36:19 +010027
Ben Hutchings8ceee662008-04-27 12:55:59 +010028/****************************************************************************/
29/* Quake-specific MDIO registers */
30#define MDIO_QUAKE_LED0_REG (0xD006)
31
Ben Hutchingsd2d2c372009-02-27 13:07:33 +000032/* QT2025C only */
33#define PCS_FW_HEARTBEAT_REG 0xd7ee
34#define PCS_FW_HEARTB_LBN 0
35#define PCS_FW_HEARTB_WIDTH 8
36#define PCS_UC8051_STATUS_REG 0xd7fd
37#define PCS_UC_STATUS_LBN 0
38#define PCS_UC_STATUS_WIDTH 8
39#define PCS_UC_STATUS_FW_SAVE 0x20
40#define PMA_PMD_FTX_CTRL2_REG 0xc309
41#define PMA_PMD_FTX_STATIC_LBN 13
42#define PMA_PMD_VEND1_REG 0xc001
43#define PMA_PMD_VEND1_LBTXD_LBN 15
44#define PCS_VEND1_REG 0xc000
45#define PCS_VEND1_LBTXD_LBN 5
46
Ben Hutchingsb37b62f2009-10-23 08:33:42 +000047void falcon_qt202x_set_led(struct efx_nic *p, int led, int mode)
Ben Hutchings8ceee662008-04-27 12:55:59 +010048{
49 int addr = MDIO_QUAKE_LED0_REG + led;
Ben Hutchings68e7f452009-04-29 08:05:08 +000050 efx_mdio_write(p, MDIO_MMD_PMAPMD, addr, mode);
Ben Hutchings8ceee662008-04-27 12:55:59 +010051}
52
Ben Hutchingsb37b62f2009-10-23 08:33:42 +000053struct qt202x_phy_data {
Ben Hutchingsf8b87c12008-09-01 12:48:17 +010054 enum efx_phy_mode phy_mode;
Ben Hutchings3273c2e2008-05-07 13:36:19 +010055};
56
Ben Hutchingsb37b62f2009-10-23 08:33:42 +000057#define QT2022C2_MAX_RESET_TIME 500
58#define QT2022C2_RESET_WAIT 10
Ben Hutchings8ceee662008-04-27 12:55:59 +010059
Ben Hutchingsd2d2c372009-02-27 13:07:33 +000060static int qt2025c_wait_reset(struct efx_nic *efx)
61{
62 unsigned long timeout = jiffies + 10 * HZ;
Ben Hutchingsd2d2c372009-02-27 13:07:33 +000063 int reg, old_counter = 0;
64
65 /* Wait for firmware heartbeat to start */
66 for (;;) {
67 int counter;
Ben Hutchings68e7f452009-04-29 08:05:08 +000068 reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG);
Ben Hutchingsd2d2c372009-02-27 13:07:33 +000069 if (reg < 0)
70 return reg;
71 counter = ((reg >> PCS_FW_HEARTB_LBN) &
72 ((1 << PCS_FW_HEARTB_WIDTH) - 1));
73 if (old_counter == 0)
74 old_counter = counter;
75 else if (counter != old_counter)
76 break;
77 if (time_after(jiffies, timeout))
78 return -ETIMEDOUT;
79 msleep(10);
80 }
81
82 /* Wait for firmware status to look good */
83 for (;;) {
Ben Hutchings68e7f452009-04-29 08:05:08 +000084 reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG);
Ben Hutchingsd2d2c372009-02-27 13:07:33 +000085 if (reg < 0)
86 return reg;
87 if ((reg &
88 ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >=
89 PCS_UC_STATUS_FW_SAVE)
90 break;
91 if (time_after(jiffies, timeout))
92 return -ETIMEDOUT;
93 msleep(100);
94 }
95
96 return 0;
97}
98
Ben Hutchingsb37b62f2009-10-23 08:33:42 +000099static int qt202x_reset_phy(struct efx_nic *efx)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100100{
101 int rc;
102
Ben Hutchingsd2d2c372009-02-27 13:07:33 +0000103 if (efx->phy_type == PHY_TYPE_QT2025C) {
Ben Hutchings5afaa752009-08-26 08:17:19 +0000104 /* Wait for the reset triggered by falcon_reset_hw()
105 * to complete */
Ben Hutchingsd2d2c372009-02-27 13:07:33 +0000106 rc = qt2025c_wait_reset(efx);
107 if (rc < 0)
108 goto fail;
Ben Hutchings5afaa752009-08-26 08:17:19 +0000109 } else {
110 /* Reset the PHYXS MMD. This is documented as doing
111 * a complete soft reset. */
112 rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS,
Ben Hutchingsb37b62f2009-10-23 08:33:42 +0000113 QT2022C2_MAX_RESET_TIME /
114 QT2022C2_RESET_WAIT,
115 QT2022C2_RESET_WAIT);
Ben Hutchings5afaa752009-08-26 08:17:19 +0000116 if (rc < 0)
117 goto fail;
Ben Hutchingsd2d2c372009-02-27 13:07:33 +0000118 }
119
Ben Hutchings8ceee662008-04-27 12:55:59 +0100120 /* Wait 250ms for the PHY to complete bootup */
121 msleep(250);
122
123 /* Check that all the MMDs we expect are present and responding. We
124 * expect faults on some if the link is down, but not on the PHY XS */
Ben Hutchingsb37b62f2009-10-23 08:33:42 +0000125 rc = efx_mdio_check_mmds(efx, QT202X_REQUIRED_DEVS, MDIO_DEVS_PHYXS);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100126 if (rc < 0)
127 goto fail;
128
Ben Hutchings44838a42009-11-25 16:09:41 +0000129 falcon_board(efx)->type->init_phy(efx);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100130
131 return rc;
132
133 fail:
Ben Hutchingsf794fd42009-02-27 13:06:58 +0000134 EFX_ERR(efx, "PHY reset timed out\n");
Ben Hutchings8ceee662008-04-27 12:55:59 +0100135 return rc;
136}
137
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000138static int qt202x_phy_probe(struct efx_nic *efx)
139{
140 efx->mdio.mmds = QT202X_REQUIRED_DEVS;
141 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
142 efx->loopback_modes = QT202X_LOOPBACKS | FALCON_XMAC_LOOPBACKS;
143 return 0;
144}
145
Ben Hutchingsb37b62f2009-10-23 08:33:42 +0000146static int qt202x_phy_init(struct efx_nic *efx)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100147{
Ben Hutchingsb37b62f2009-10-23 08:33:42 +0000148 struct qt202x_phy_data *phy_data;
Steve Hodgson47c3d192009-11-28 05:34:29 +0000149 u32 devid;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100150 int rc;
151
Steve Hodgson47c3d192009-11-28 05:34:29 +0000152 rc = qt202x_reset_phy(efx);
153 if (rc) {
154 EFX_ERR(efx, "PHY init failed\n");
155 return rc;
156 }
157
Ben Hutchingsb37b62f2009-10-23 08:33:42 +0000158 phy_data = kzalloc(sizeof(struct qt202x_phy_data), GFP_KERNEL);
Ben Hutchings9b7bfc42008-05-16 21:20:20 +0100159 if (!phy_data)
160 return -ENOMEM;
Ben Hutchingsd3208b52008-05-16 21:20:00 +0100161 efx->phy_data = phy_data;
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100162
Steve Hodgson47c3d192009-11-28 05:34:29 +0000163 devid = efx_mdio_read_id(efx, MDIO_MMD_PHYXS);
Ben Hutchings3f39a5e2009-02-27 13:07:15 +0000164 EFX_INFO(efx, "PHY ID reg %x (OUI %06x model %02x revision %x)\n",
Ben Hutchings68e7f452009-04-29 08:05:08 +0000165 devid, efx_mdio_id_oui(devid), efx_mdio_id_model(devid),
166 efx_mdio_id_rev(devid));
Ben Hutchings8ceee662008-04-27 12:55:59 +0100167
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100168 phy_data->phy_mode = efx->phy_mode;
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100169 return 0;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100170}
171
Ben Hutchingsb37b62f2009-10-23 08:33:42 +0000172static int qt202x_link_ok(struct efx_nic *efx)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100173{
Ben Hutchingsb37b62f2009-10-23 08:33:42 +0000174 return efx_mdio_links_ok(efx, QT202X_REQUIRED_DEVS);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100175}
176
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000177static bool qt202x_phy_poll(struct efx_nic *efx)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100178{
Steve Hodgsonfdaa9ae2009-11-28 05:34:05 +0000179 bool was_up = efx->link_state.up;
180
181 efx->link_state.up = qt202x_link_ok(efx);
182 efx->link_state.speed = 10000;
183 efx->link_state.fd = true;
184 efx->link_state.fc = efx->wanted_fc;
185
186 return efx->link_state.up != was_up;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100187}
188
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000189static int qt202x_phy_reconfigure(struct efx_nic *efx)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100190{
Ben Hutchingsb37b62f2009-10-23 08:33:42 +0000191 struct qt202x_phy_data *phy_data = efx->phy_data;
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100192
Ben Hutchingsd2d2c372009-02-27 13:07:33 +0000193 if (efx->phy_type == PHY_TYPE_QT2025C) {
194 /* There are several different register bits which can
195 * disable TX (and save power) on direct-attach cables
196 * or optical transceivers, varying somewhat between
197 * firmware versions. Only 'static mode' appears to
198 * cover everything. */
Ben Hutchings68e7f452009-04-29 08:05:08 +0000199 mdio_set_flag(
200 &efx->mdio, efx->mdio.prtad, MDIO_MMD_PMAPMD,
201 PMA_PMD_FTX_CTRL2_REG, 1 << PMA_PMD_FTX_STATIC_LBN,
Ben Hutchingsd2d2c372009-02-27 13:07:33 +0000202 efx->phy_mode & PHY_MODE_TX_DISABLED ||
203 efx->phy_mode & PHY_MODE_LOW_POWER ||
204 efx->loopback_mode == LOOPBACK_PCS ||
205 efx->loopback_mode == LOOPBACK_PMAPMD);
206 } else {
207 /* Reset the PHY when moving from tx off to tx on */
208 if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) &&
209 (phy_data->phy_mode & PHY_MODE_TX_DISABLED))
Ben Hutchingsb37b62f2009-10-23 08:33:42 +0000210 qt202x_reset_phy(efx);
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100211
Ben Hutchings68e7f452009-04-29 08:05:08 +0000212 efx_mdio_transmit_disable(efx);
Ben Hutchingsd2d2c372009-02-27 13:07:33 +0000213 }
214
Ben Hutchings68e7f452009-04-29 08:05:08 +0000215 efx_mdio_phy_reconfigure(efx);
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100216
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100217 phy_data->phy_mode = efx->phy_mode;
Ben Hutchingsd3245b22009-11-29 03:42:41 +0000218
219 return 0;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100220}
221
Ben Hutchingsb37b62f2009-10-23 08:33:42 +0000222static void qt202x_phy_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
Ben Hutchings68e7f452009-04-29 08:05:08 +0000223{
224 mdio45_ethtool_gset(&efx->mdio, ecmd);
225}
Ben Hutchings8ceee662008-04-27 12:55:59 +0100226
Ben Hutchingsb37b62f2009-10-23 08:33:42 +0000227static void qt202x_phy_fini(struct efx_nic *efx)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100228{
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100229 /* Free the context block */
230 kfree(efx->phy_data);
231 efx->phy_data = NULL;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100232}
233
Ben Hutchingsb37b62f2009-10-23 08:33:42 +0000234struct efx_phy_operations falcon_qt202x_phy_ops = {
Ben Hutchingsc1c4f452009-11-29 15:08:55 +0000235 .probe = qt202x_phy_probe,
Ben Hutchingsb37b62f2009-10-23 08:33:42 +0000236 .init = qt202x_phy_init,
237 .reconfigure = qt202x_phy_reconfigure,
238 .poll = qt202x_phy_poll,
239 .fini = qt202x_phy_fini,
Ben Hutchingsb37b62f2009-10-23 08:33:42 +0000240 .get_settings = qt202x_phy_get_settings,
Ben Hutchings68e7f452009-04-29 08:05:08 +0000241 .set_settings = efx_mdio_set_settings,
Ben Hutchings8ceee662008-04-27 12:55:59 +0100242};