blob: 122c786449a90d1c2f401232b127dfa9d26d10b5 [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
Sergei Shtylyov265b7212009-04-14 18:39:14 +040011 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc.
Jeff Garzik669a5db2006-08-29 18:12:40 -040012 *
13 * TODO
Sergei Shtylyovd44a65f2007-08-10 20:58:46 +040014 * Look into engine reset on timeout errors. Should not be required.
Jeff Garzik669a5db2006-08-29 18:12:40 -040015 */
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/pci.h>
20#include <linux/init.h>
21#include <linux/blkdev.h>
22#include <linux/delay.h>
23#include <scsi/scsi_host.h>
24#include <linux/libata.h>
25
26#define DRV_NAME "pata_hpt37x"
Sergei Shtylyov265b7212009-04-14 18:39:14 +040027#define DRV_VERSION "0.6.12"
Jeff Garzik669a5db2006-08-29 18:12:40 -040028
29struct hpt_clock {
30 u8 xfer_speed;
31 u32 timing;
32};
33
34struct hpt_chip {
35 const char *name;
36 unsigned int base;
37 struct hpt_clock const *clocks[4];
38};
39
40/* key for bus clock timings
41 * bit
42 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
43 * DMA. cycles = value + 1
44 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
45 * DMA. cycles = value + 1
46 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
47 * register access.
48 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
49 * register access.
50 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
51 * during task file register access.
52 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
53 * xfer.
54 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
55 * register access.
56 * 28 UDMA enable
57 * 29 DMA enable
58 * 30 PIO_MST enable. if set, the chip is in bus master mode during
59 * PIO.
60 * 31 FIFO enable.
61 */
62
Alan Coxfcc2f692007-03-08 23:28:52 +000063static struct hpt_clock hpt37x_timings_33[] = {
64 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
65 { XFER_UDMA_5, 0x12446231 },
66 { XFER_UDMA_4, 0x12446231 },
67 { XFER_UDMA_3, 0x126c6231 },
68 { XFER_UDMA_2, 0x12486231 },
69 { XFER_UDMA_1, 0x124c6233 },
70 { XFER_UDMA_0, 0x12506297 },
Jeff Garzik669a5db2006-08-29 18:12:40 -040071
Alan Coxfcc2f692007-03-08 23:28:52 +000072 { XFER_MW_DMA_2, 0x22406c31 },
73 { XFER_MW_DMA_1, 0x22406c33 },
74 { XFER_MW_DMA_0, 0x22406c97 },
Jeff Garzik669a5db2006-08-29 18:12:40 -040075
Alan Coxfcc2f692007-03-08 23:28:52 +000076 { XFER_PIO_4, 0x06414e31 },
77 { XFER_PIO_3, 0x06414e42 },
78 { XFER_PIO_2, 0x06414e53 },
79 { XFER_PIO_1, 0x06814e93 },
80 { XFER_PIO_0, 0x06814ea7 }
Jeff Garzik669a5db2006-08-29 18:12:40 -040081};
82
Alan Coxfcc2f692007-03-08 23:28:52 +000083static struct hpt_clock hpt37x_timings_50[] = {
84 { XFER_UDMA_6, 0x12848242 },
85 { XFER_UDMA_5, 0x12848242 },
86 { XFER_UDMA_4, 0x12ac8242 },
87 { XFER_UDMA_3, 0x128c8242 },
88 { XFER_UDMA_2, 0x120c8242 },
89 { XFER_UDMA_1, 0x12148254 },
90 { XFER_UDMA_0, 0x121882ea },
Jeff Garzik669a5db2006-08-29 18:12:40 -040091
Alan Coxfcc2f692007-03-08 23:28:52 +000092 { XFER_MW_DMA_2, 0x22808242 },
93 { XFER_MW_DMA_1, 0x22808254 },
94 { XFER_MW_DMA_0, 0x228082ea },
Jeff Garzik669a5db2006-08-29 18:12:40 -040095
Alan Coxfcc2f692007-03-08 23:28:52 +000096 { XFER_PIO_4, 0x0a81f442 },
97 { XFER_PIO_3, 0x0a81f443 },
98 { XFER_PIO_2, 0x0a81f454 },
99 { XFER_PIO_1, 0x0ac1f465 },
100 { XFER_PIO_0, 0x0ac1f48a }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400101};
102
Alan Coxfcc2f692007-03-08 23:28:52 +0000103static struct hpt_clock hpt37x_timings_66[] = {
104 { XFER_UDMA_6, 0x1c869c62 },
105 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
106 { XFER_UDMA_4, 0x1c8a9c62 },
107 { XFER_UDMA_3, 0x1c8e9c62 },
108 { XFER_UDMA_2, 0x1c929c62 },
109 { XFER_UDMA_1, 0x1c9a9c62 },
110 { XFER_UDMA_0, 0x1c829c62 },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400111
Alan Coxfcc2f692007-03-08 23:28:52 +0000112 { XFER_MW_DMA_2, 0x2c829c62 },
113 { XFER_MW_DMA_1, 0x2c829c66 },
114 { XFER_MW_DMA_0, 0x2c829d2e },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400115
Alan Coxfcc2f692007-03-08 23:28:52 +0000116 { XFER_PIO_4, 0x0c829c62 },
117 { XFER_PIO_3, 0x0c829c84 },
118 { XFER_PIO_2, 0x0c829ca6 },
119 { XFER_PIO_1, 0x0d029d26 },
120 { XFER_PIO_0, 0x0d029d5e }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400121};
122
Jeff Garzik669a5db2006-08-29 18:12:40 -0400123
124static const struct hpt_chip hpt370 = {
125 "HPT370",
126 48,
127 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000128 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400129 NULL,
130 NULL,
Alan Coxa4734462007-04-26 00:19:25 -0700131 NULL
Jeff Garzik669a5db2006-08-29 18:12:40 -0400132 }
133};
134
135static const struct hpt_chip hpt370a = {
136 "HPT370A",
137 48,
138 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000139 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400140 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000141 hpt37x_timings_50,
Alan Coxa4734462007-04-26 00:19:25 -0700142 NULL
Jeff Garzik669a5db2006-08-29 18:12:40 -0400143 }
144};
145
146static const struct hpt_chip hpt372 = {
147 "HPT372",
148 55,
149 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000150 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400151 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000152 hpt37x_timings_50,
153 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400154 }
155};
156
157static const struct hpt_chip hpt302 = {
158 "HPT302",
159 66,
160 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000161 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400162 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000163 hpt37x_timings_50,
164 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400165 }
166};
167
168static const struct hpt_chip hpt371 = {
169 "HPT371",
170 66,
171 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000172 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400173 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000174 hpt37x_timings_50,
175 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400176 }
177};
178
179static const struct hpt_chip hpt372a = {
180 "HPT372A",
181 66,
182 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000183 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400184 NULL,
Alan Coxfcc2f692007-03-08 23:28:52 +0000185 hpt37x_timings_50,
186 hpt37x_timings_66
Jeff Garzik669a5db2006-08-29 18:12:40 -0400187 }
188};
189
190static const struct hpt_chip hpt374 = {
191 "HPT374",
192 48,
193 {
Alan Coxfcc2f692007-03-08 23:28:52 +0000194 hpt37x_timings_33,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400195 NULL,
196 NULL,
197 NULL
198 }
199};
200
201/**
202 * hpt37x_find_mode - reset the hpt37x bus
203 * @ap: ATA port
204 * @speed: transfer mode
205 *
206 * Return the 32bit register programming information for this channel
207 * that matches the speed provided.
208 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400209
Jeff Garzik669a5db2006-08-29 18:12:40 -0400210static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
211{
212 struct hpt_clock *clocks = ap->host->private_data;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400213
Jeff Garzik669a5db2006-08-29 18:12:40 -0400214 while(clocks->xfer_speed) {
215 if (clocks->xfer_speed == speed)
216 return clocks->timing;
217 clocks++;
218 }
219 BUG();
220 return 0xffffffffU; /* silence compiler warning */
221}
222
223static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
224{
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900225 unsigned char model_num[ATA_ID_PROD_LEN + 1];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400226 int i = 0;
227
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900228 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
Jeff Garzik669a5db2006-08-29 18:12:40 -0400229
Tejun Heo8bfa79f2007-01-02 20:19:40 +0900230 while (list[i] != NULL) {
231 if (!strcmp(list[i], model_num)) {
Jeff Garzik85cd7252006-08-31 00:03:49 -0400232 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
Jeff Garzik669a5db2006-08-29 18:12:40 -0400233 modestr, list[i]);
234 return 1;
235 }
236 i++;
237 }
238 return 0;
239}
240
241static const char *bad_ata33[] = {
242 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
243 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
244 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
245 "Maxtor 90510D4",
246 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
247 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
248 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
249 NULL
250};
251
252static const char *bad_ata100_5[] = {
253 "IBM-DTLA-307075",
254 "IBM-DTLA-307060",
255 "IBM-DTLA-307045",
256 "IBM-DTLA-307030",
257 "IBM-DTLA-307020",
258 "IBM-DTLA-307015",
259 "IBM-DTLA-305040",
260 "IBM-DTLA-305030",
261 "IBM-DTLA-305020",
262 "IC35L010AVER07-0",
263 "IC35L020AVER07-0",
264 "IC35L030AVER07-0",
265 "IC35L040AVER07-0",
266 "IC35L060AVER07-0",
267 "WDC AC310200R",
268 NULL
269};
270
271/**
272 * hpt370_filter - mode selection filter
Jeff Garzik669a5db2006-08-29 18:12:40 -0400273 * @adev: ATA device
274 *
275 * Block UDMA on devices that cause trouble with this controller.
276 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400277
Alan Coxa76b62c2007-03-09 09:34:07 -0500278static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400279{
Alan6929da42007-01-05 16:37:01 -0800280 if (adev->class == ATA_DEV_ATA) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400281 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
282 mask &= ~ATA_MASK_UDMA;
283 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
Alan Cox6ddd6862008-02-26 13:35:54 -0800284 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400285 }
Tejun Heo9363c382008-04-07 22:47:16 +0900286 return ata_bmdma_mode_filter(adev, mask);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400287}
288
289/**
290 * hpt370a_filter - mode selection filter
Jeff Garzik669a5db2006-08-29 18:12:40 -0400291 * @adev: ATA device
292 *
293 * Block UDMA on devices that cause trouble with this controller.
294 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400295
Alan Coxa76b62c2007-03-09 09:34:07 -0500296static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400297{
Alan Cox73946f92007-11-05 22:53:38 +0000298 if (adev->class == ATA_DEV_ATA) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400299 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
Alan Cox6ddd6862008-02-26 13:35:54 -0800300 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400301 }
Tejun Heo9363c382008-04-07 22:47:16 +0900302 return ata_bmdma_mode_filter(adev, mask);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400303}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400304
Jeff Garzik669a5db2006-08-29 18:12:40 -0400305/**
306 * hpt37x_pre_reset - reset the hpt37x bus
Tejun Heocc0680a2007-08-06 18:36:23 +0900307 * @link: ATA link to reset
Tejun Heod4b2bab2007-02-02 16:50:52 +0900308 * @deadline: deadline jiffies for the operation
Jeff Garzik669a5db2006-08-29 18:12:40 -0400309 *
310 * Perform the initial reset handling for the 370/372 and 374 func 0
311 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400312
Tejun Heocc0680a2007-08-06 18:36:23 +0900313static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400314{
315 u8 scr2, ata66;
Tejun Heocc0680a2007-08-06 18:36:23 +0900316 struct ata_port *ap = link->ap;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400317 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Alan Coxb5bf24b2006-11-08 16:18:26 +0000318 static const struct pci_bits hpt37x_enable_bits[] = {
319 { 0x50, 1, 0x04, 0x04 },
320 { 0x54, 1, 0x04, 0x04 }
321 };
322 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
323 return -ENOENT;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500324
Jeff Garzik669a5db2006-08-29 18:12:40 -0400325 pci_read_config_byte(pdev, 0x5B, &scr2);
326 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
327 /* Cable register now active */
328 pci_read_config_byte(pdev, 0x5A, &ata66);
329 /* Restore state */
330 pci_write_config_byte(pdev, 0x5B, scr2);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400331
Alan Cox22d5c762007-11-19 14:39:13 +0000332 if (ata66 & (2 >> ap->port_no))
Jeff Garzik669a5db2006-08-29 18:12:40 -0400333 ap->cbl = ATA_CBL_PATA40;
334 else
335 ap->cbl = ATA_CBL_PATA80;
336
337 /* Reset the state machine */
Alan Coxfcc2f692007-03-08 23:28:52 +0000338 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400339 udelay(100);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400340
Tejun Heo9363c382008-04-07 22:47:16 +0900341 return ata_sff_prereset(link, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400342}
343
Tejun Heoa1efdab2008-03-25 12:22:50 +0900344static int hpt374_fn1_pre_reset(struct ata_link *link, unsigned long deadline)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400345{
Alan Coxb5bf24b2006-11-08 16:18:26 +0000346 static const struct pci_bits hpt37x_enable_bits[] = {
347 { 0x50, 1, 0x04, 0x04 },
348 { 0x54, 1, 0x04, 0x04 }
349 };
Alan Cox73946f92007-11-05 22:53:38 +0000350 u16 mcr3;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400351 u8 ata66;
Tejun Heocc0680a2007-08-06 18:36:23 +0900352 struct ata_port *ap = link->ap;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400353 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Alan Cox73946f92007-11-05 22:53:38 +0000354 unsigned int mcrbase = 0x50 + 4 * ap->port_no;
Alan Coxb5bf24b2006-11-08 16:18:26 +0000355
356 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
357 return -ENOENT;
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500358
Jeff Garzik669a5db2006-08-29 18:12:40 -0400359 /* Do the extra channel work */
Alan Cox73946f92007-11-05 22:53:38 +0000360 pci_read_config_word(pdev, mcrbase + 2, &mcr3);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400361 /* Set bit 15 of 0x52 to enable TCBLID as input
Jeff Garzik669a5db2006-08-29 18:12:40 -0400362 */
Alan Cox73946f92007-11-05 22:53:38 +0000363 pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400364 pci_read_config_byte(pdev, 0x5A, &ata66);
365 /* Reset TCBLID/FCBLID to output */
Alan Coxf941b162007-12-19 17:50:32 +0000366 pci_write_config_word(pdev, mcrbase + 2, mcr3);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400367
Alan Cox73946f92007-11-05 22:53:38 +0000368 if (ata66 & (2 >> ap->port_no))
Jeff Garzik669a5db2006-08-29 18:12:40 -0400369 ap->cbl = ATA_CBL_PATA40;
370 else
371 ap->cbl = ATA_CBL_PATA80;
372
373 /* Reset the state machine */
Alan Coxfcc2f692007-03-08 23:28:52 +0000374 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400375 udelay(100);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400376
Tejun Heo9363c382008-04-07 22:47:16 +0900377 return ata_sff_prereset(link, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400378}
379
380/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400381 * hpt370_set_piomode - PIO setup
382 * @ap: ATA interface
383 * @adev: device on the interface
384 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400385 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400386 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400387
Jeff Garzik669a5db2006-08-29 18:12:40 -0400388static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
389{
390 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
391 u32 addr1, addr2;
392 u32 reg;
393 u32 mode;
394 u8 fast;
395
396 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
397 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400398
Jeff Garzik669a5db2006-08-29 18:12:40 -0400399 /* Fast interrupt prediction disable, hold off interrupt disable */
400 pci_read_config_byte(pdev, addr2, &fast);
401 fast &= ~0x02;
402 fast |= 0x01;
403 pci_write_config_byte(pdev, addr2, fast);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400404
Jeff Garzik669a5db2006-08-29 18:12:40 -0400405 pci_read_config_dword(pdev, addr1, &reg);
406 mode = hpt37x_find_mode(ap, adev->pio_mode);
407 mode &= ~0x8000000; /* No FIFO in PIO */
408 mode &= ~0x30070000; /* Leave config bits alone */
409 reg &= 0x30070000; /* Strip timing bits */
410 pci_write_config_dword(pdev, addr1, reg | mode);
411}
412
413/**
414 * hpt370_set_dmamode - DMA timing setup
415 * @ap: ATA interface
416 * @adev: Device being configured
417 *
418 * Set up the channel for MWDMA or UDMA modes. Much the same as with
419 * PIO, load the mode number and then set MWDMA or UDMA flag.
420 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400421
Jeff Garzik669a5db2006-08-29 18:12:40 -0400422static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
423{
424 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
425 u32 addr1, addr2;
426 u32 reg;
427 u32 mode;
428 u8 fast;
429
430 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
431 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400432
Jeff Garzik669a5db2006-08-29 18:12:40 -0400433 /* Fast interrupt prediction disable, hold off interrupt disable */
434 pci_read_config_byte(pdev, addr2, &fast);
435 fast &= ~0x02;
436 fast |= 0x01;
437 pci_write_config_byte(pdev, addr2, fast);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400438
Jeff Garzik669a5db2006-08-29 18:12:40 -0400439 pci_read_config_dword(pdev, addr1, &reg);
440 mode = hpt37x_find_mode(ap, adev->dma_mode);
441 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
442 mode &= ~0xC0000000; /* Leave config bits alone */
443 reg &= 0xC0000000; /* Strip timing bits */
444 pci_write_config_dword(pdev, addr1, reg | mode);
445}
446
447/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400448 * hpt370_bmdma_end - DMA engine stop
449 * @qc: ATA command
450 *
451 * Work around the HPT370 DMA engine.
452 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400453
Jeff Garzik669a5db2006-08-29 18:12:40 -0400454static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
455{
456 struct ata_port *ap = qc->ap;
457 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Tejun Heo0d5ff562007-02-01 15:06:36 +0900458 u8 dma_stat = ioread8(ap->ioaddr.bmdma_addr + 2);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400459 u8 dma_cmd;
Tejun Heo0d5ff562007-02-01 15:06:36 +0900460 void __iomem *bmdma = ap->ioaddr.bmdma_addr;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400461
Jeff Garzik669a5db2006-08-29 18:12:40 -0400462 if (dma_stat & 0x01) {
463 udelay(20);
Tejun Heo0d5ff562007-02-01 15:06:36 +0900464 dma_stat = ioread8(bmdma + 2);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400465 }
466 if (dma_stat & 0x01) {
467 /* Clear the engine */
468 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
469 udelay(10);
470 /* Stop DMA */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900471 dma_cmd = ioread8(bmdma );
472 iowrite8(dma_cmd & 0xFE, bmdma);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400473 /* Clear Error */
Tejun Heo0d5ff562007-02-01 15:06:36 +0900474 dma_stat = ioread8(bmdma + 2);
475 iowrite8(dma_stat | 0x06 , bmdma + 2);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400476 /* Clear the engine */
477 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
478 udelay(10);
479 }
480 ata_bmdma_stop(qc);
481}
482
483/**
484 * hpt372_set_piomode - PIO setup
485 * @ap: ATA interface
486 * @adev: device on the interface
487 *
Jeff Garzik85cd7252006-08-31 00:03:49 -0400488 * Perform PIO mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400489 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400490
Jeff Garzik669a5db2006-08-29 18:12:40 -0400491static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
492{
493 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
494 u32 addr1, addr2;
495 u32 reg;
496 u32 mode;
497 u8 fast;
498
499 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
500 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400501
Jeff Garzik669a5db2006-08-29 18:12:40 -0400502 /* Fast interrupt prediction disable, hold off interrupt disable */
503 pci_read_config_byte(pdev, addr2, &fast);
504 fast &= ~0x07;
505 pci_write_config_byte(pdev, addr2, fast);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400506
Jeff Garzik669a5db2006-08-29 18:12:40 -0400507 pci_read_config_dword(pdev, addr1, &reg);
508 mode = hpt37x_find_mode(ap, adev->pio_mode);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400509
Jeff Garzik669a5db2006-08-29 18:12:40 -0400510 printk("Find mode for %d reports %X\n", adev->pio_mode, mode);
511 mode &= ~0x80000000; /* No FIFO in PIO */
512 mode &= ~0x30070000; /* Leave config bits alone */
513 reg &= 0x30070000; /* Strip timing bits */
514 pci_write_config_dword(pdev, addr1, reg | mode);
515}
516
517/**
518 * hpt372_set_dmamode - DMA timing setup
519 * @ap: ATA interface
520 * @adev: Device being configured
521 *
522 * Set up the channel for MWDMA or UDMA modes. Much the same as with
523 * PIO, load the mode number and then set MWDMA or UDMA flag.
524 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400525
Jeff Garzik669a5db2006-08-29 18:12:40 -0400526static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
527{
528 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
529 u32 addr1, addr2;
530 u32 reg;
531 u32 mode;
532 u8 fast;
533
534 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
535 addr2 = 0x51 + 4 * ap->port_no;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400536
Jeff Garzik669a5db2006-08-29 18:12:40 -0400537 /* Fast interrupt prediction disable, hold off interrupt disable */
538 pci_read_config_byte(pdev, addr2, &fast);
539 fast &= ~0x07;
540 pci_write_config_byte(pdev, addr2, fast);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400541
Jeff Garzik669a5db2006-08-29 18:12:40 -0400542 pci_read_config_dword(pdev, addr1, &reg);
543 mode = hpt37x_find_mode(ap, adev->dma_mode);
544 printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode);
545 mode &= ~0xC0000000; /* Leave config bits alone */
546 mode |= 0x80000000; /* FIFO in MWDMA or UDMA */
547 reg &= 0xC0000000; /* Strip timing bits */
548 pci_write_config_dword(pdev, addr1, reg | mode);
549}
550
551/**
552 * hpt37x_bmdma_end - DMA engine stop
553 * @qc: ATA command
554 *
555 * Clean up after the HPT372 and later DMA engine
556 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400557
Jeff Garzik669a5db2006-08-29 18:12:40 -0400558static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
559{
560 struct ata_port *ap = qc->ap;
561 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Alan6929da42007-01-05 16:37:01 -0800562 int mscreg = 0x50 + 4 * ap->port_no;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400563 u8 bwsr_stat, msc_stat;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400564
Jeff Garzik669a5db2006-08-29 18:12:40 -0400565 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
566 pci_read_config_byte(pdev, mscreg, &msc_stat);
567 if (bwsr_stat & (1 << ap->port_no))
568 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
569 ata_bmdma_stop(qc);
570}
571
572
573static struct scsi_host_template hpt37x_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900574 ATA_BMDMA_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400575};
576
577/*
578 * Configuration for HPT370
579 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400580
Jeff Garzik669a5db2006-08-29 18:12:40 -0400581static struct ata_port_operations hpt370_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900582 .inherits = &ata_bmdma_port_ops,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400583
Jeff Garzik669a5db2006-08-29 18:12:40 -0400584 .bmdma_stop = hpt370_bmdma_stop,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400585
Tejun Heo029cfd62008-03-25 12:22:49 +0900586 .mode_filter = hpt370_filter,
587 .set_piomode = hpt370_set_piomode,
588 .set_dmamode = hpt370_set_dmamode,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900589 .prereset = hpt37x_pre_reset,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400590};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400591
592/*
593 * Configuration for HPT370A. Close to 370 but less filters
594 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400595
Jeff Garzik669a5db2006-08-29 18:12:40 -0400596static struct ata_port_operations hpt370a_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900597 .inherits = &hpt370_port_ops,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400598 .mode_filter = hpt370a_filter,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400599};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400600
601/*
602 * Configuration for HPT372, HPT371, HPT302. Slightly different PIO
603 * and DMA mode setting functionality.
604 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400605
Jeff Garzik669a5db2006-08-29 18:12:40 -0400606static struct ata_port_operations hpt372_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900607 .inherits = &ata_bmdma_port_ops,
608
609 .bmdma_stop = hpt37x_bmdma_stop,
610
Jeff Garzik669a5db2006-08-29 18:12:40 -0400611 .set_piomode = hpt372_set_piomode,
612 .set_dmamode = hpt372_set_dmamode,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900613 .prereset = hpt37x_pre_reset,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400614};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400615
616/*
617 * Configuration for HPT374. Mode setting works like 372 and friends
Tejun Heoa1efdab2008-03-25 12:22:50 +0900618 * but we have a different cable detection procedure for function 1.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400619 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400620
Tejun Heoa1efdab2008-03-25 12:22:50 +0900621static struct ata_port_operations hpt374_fn1_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900622 .inherits = &hpt372_port_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900623 .prereset = hpt374_fn1_pre_reset,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400624};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400625
626/**
627 * htp37x_clock_slot - Turn timing to PC clock entry
628 * @freq: Reported frequency timing
629 * @base: Base timing
630 *
631 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
632 * and 3 for 66Mhz)
633 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400634
Jeff Garzik669a5db2006-08-29 18:12:40 -0400635static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
636{
637 unsigned int f = (base * freq) / 192; /* Mhz */
638 if (f < 40)
639 return 0; /* 33Mhz slot */
640 if (f < 45)
641 return 1; /* 40Mhz slot */
642 if (f < 55)
643 return 2; /* 50Mhz slot */
644 return 3; /* 60Mhz slot */
645}
646
647/**
648 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
Jeff Garzik85cd7252006-08-31 00:03:49 -0400649 * @dev: PCI device
Jeff Garzik669a5db2006-08-29 18:12:40 -0400650 *
651 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
652 * succeeds
653 */
654
655static int hpt37x_calibrate_dpll(struct pci_dev *dev)
656{
657 u8 reg5b;
658 u32 reg5c;
659 int tries;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400660
Jeff Garzik669a5db2006-08-29 18:12:40 -0400661 for(tries = 0; tries < 0x5000; tries++) {
662 udelay(50);
663 pci_read_config_byte(dev, 0x5b, &reg5b);
664 if (reg5b & 0x80) {
665 /* See if it stays set */
666 for(tries = 0; tries < 0x1000; tries ++) {
667 pci_read_config_byte(dev, 0x5b, &reg5b);
668 /* Failed ? */
669 if ((reg5b & 0x80) == 0)
670 return 0;
671 }
672 /* Turn off tuning, we have the DPLL set */
673 pci_read_config_dword(dev, 0x5c, &reg5c);
674 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
675 return 1;
676 }
677 }
678 /* Never went stable */
679 return 0;
680}
Alan Cox73946f92007-11-05 22:53:38 +0000681
682static u32 hpt374_read_freq(struct pci_dev *pdev)
683{
684 u32 freq;
685 unsigned long io_base = pci_resource_start(pdev, 4);
686 if (PCI_FUNC(pdev->devfn) & 1) {
Andrew Morton40f46f12007-12-13 16:01:38 -0800687 struct pci_dev *pdev_0;
688
689 pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
Alan Cox73946f92007-11-05 22:53:38 +0000690 /* Someone hot plugged the controller on us ? */
691 if (pdev_0 == NULL)
692 return 0;
693 io_base = pci_resource_start(pdev_0, 4);
694 freq = inl(io_base + 0x90);
695 pci_dev_put(pdev_0);
Andrew Morton40f46f12007-12-13 16:01:38 -0800696 } else
Alan Cox73946f92007-11-05 22:53:38 +0000697 freq = inl(io_base + 0x90);
698 return freq;
699}
700
Jeff Garzik669a5db2006-08-29 18:12:40 -0400701/**
702 * hpt37x_init_one - Initialise an HPT37X/302
703 * @dev: PCI device
704 * @id: Entry in match table
705 *
706 * Initialise an HPT37x device. There are some interesting complications
707 * here. Firstly the chip may report 366 and be one of several variants.
708 * Secondly all the timings depend on the clock for the chip which we must
709 * detect and look up
710 *
711 * This is the known chip mappings. It may be missing a couple of later
712 * releases.
713 *
714 * Chip version PCI Rev Notes
715 * HPT366 4 (HPT366) 0 Other driver
716 * HPT366 4 (HPT366) 1 Other driver
717 * HPT368 4 (HPT366) 2 Other driver
718 * HPT370 4 (HPT366) 3 UDMA100
719 * HPT370A 4 (HPT366) 4 UDMA100
720 * HPT372 4 (HPT366) 5 UDMA133 (1)
721 * HPT372N 4 (HPT366) 6 Other driver
722 * HPT372A 5 (HPT372) 1 UDMA133 (1)
723 * HPT372N 5 (HPT372) 2 Other driver
724 * HPT302 6 (HPT302) 1 UDMA133
725 * HPT302N 6 (HPT302) 2 Other driver
726 * HPT371 7 (HPT371) * UDMA133
727 * HPT374 8 (HPT374) * UDMA133 4 channel
728 * HPT372N 9 (HPT372N) * Other driver
729 *
730 * (1) UDMA133 support depends on the bus clock
731 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400732
Jeff Garzik669a5db2006-08-29 18:12:40 -0400733static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
734{
735 /* HPT370 - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200736 static const struct ata_port_info info_hpt370 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400737 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100738 .pio_mask = ATA_PIO4,
739 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400740 .udma_mask = ATA_UDMA5,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400741 .port_ops = &hpt370_port_ops
742 };
743 /* HPT370A - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200744 static const struct ata_port_info info_hpt370a = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400745 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100746 .pio_mask = ATA_PIO4,
747 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400748 .udma_mask = ATA_UDMA5,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400749 .port_ops = &hpt370a_port_ops
750 };
Alan Coxfcc2f692007-03-08 23:28:52 +0000751 /* HPT370 - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200752 static const struct ata_port_info info_hpt370_33 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400753 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100754 .pio_mask = ATA_PIO4,
755 .mwdma_mask = ATA_MWDMA2,
Alan Cox73946f92007-11-05 22:53:38 +0000756 .udma_mask = ATA_UDMA5,
Alan Coxfcc2f692007-03-08 23:28:52 +0000757 .port_ops = &hpt370_port_ops
758 };
759 /* HPT370A - UDMA100 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200760 static const struct ata_port_info info_hpt370a_33 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400761 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100762 .pio_mask = ATA_PIO4,
763 .mwdma_mask = ATA_MWDMA2,
Alan Cox73946f92007-11-05 22:53:38 +0000764 .udma_mask = ATA_UDMA5,
Alan Coxfcc2f692007-03-08 23:28:52 +0000765 .port_ops = &hpt370a_port_ops
766 };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400767 /* HPT371, 372 and friends - UDMA133 */
Tejun Heo1626aeb2007-05-04 12:43:58 +0200768 static const struct ata_port_info info_hpt372 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400769 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100770 .pio_mask = ATA_PIO4,
771 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400772 .udma_mask = ATA_UDMA6,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400773 .port_ops = &hpt372_port_ops
774 };
Tejun Heoa1efdab2008-03-25 12:22:50 +0900775 /* HPT374 - UDMA100, function 1 uses different prereset method */
776 static const struct ata_port_info info_hpt374_fn0 = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400777 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100778 .pio_mask = ATA_PIO4,
779 .mwdma_mask = ATA_MWDMA2,
Jeff Garzikbf6263a2007-07-09 12:16:50 -0400780 .udma_mask = ATA_UDMA5,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900781 .port_ops = &hpt372_port_ops
782 };
783 static const struct ata_port_info info_hpt374_fn1 = {
784 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100785 .pio_mask = ATA_PIO4,
786 .mwdma_mask = ATA_MWDMA2,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900787 .udma_mask = ATA_UDMA5,
788 .port_ops = &hpt374_fn1_port_ops
Jeff Garzik669a5db2006-08-29 18:12:40 -0400789 };
790
791 static const int MHz[4] = { 33, 40, 50, 66 };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200792 void *private_data = NULL;
Tejun Heo887125e2008-03-25 12:22:49 +0900793 const struct ata_port_info *ppi[] = { NULL, NULL };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400794
795 u8 irqmask;
796 u32 class_rev;
Alan Coxfcc2f692007-03-08 23:28:52 +0000797 u8 mcr1;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400798 u32 freq;
Alan Coxfcc2f692007-03-08 23:28:52 +0000799 int prefer_dpll = 1;
Jeff Garzika617c092007-05-21 20:14:23 -0400800
Alan Coxfcc2f692007-03-08 23:28:52 +0000801 unsigned long iobase = pci_resource_start(dev, 4);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400802
803 const struct hpt_chip *chip_table;
804 int clock_slot;
Tejun Heof08048e2008-03-25 12:22:47 +0900805 int rc;
806
807 rc = pcim_enable_device(dev);
808 if (rc)
809 return rc;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400810
811 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
812 class_rev &= 0xFF;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400813
Jeff Garzik669a5db2006-08-29 18:12:40 -0400814 if (dev->device == PCI_DEVICE_ID_TTI_HPT366) {
815 /* May be a later chip in disguise. Check */
816 /* Older chips are in the HPT366 driver. Ignore them */
817 if (class_rev < 3)
818 return -ENODEV;
819 /* N series chips have their own driver. Ignore */
820 if (class_rev == 6)
821 return -ENODEV;
822
Jeff Garzik85cd7252006-08-31 00:03:49 -0400823 switch(class_rev) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400824 case 3:
Tejun Heo887125e2008-03-25 12:22:49 +0900825 ppi[0] = &info_hpt370;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400826 chip_table = &hpt370;
Alan Coxfcc2f692007-03-08 23:28:52 +0000827 prefer_dpll = 0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400828 break;
829 case 4:
Tejun Heo887125e2008-03-25 12:22:49 +0900830 ppi[0] = &info_hpt370a;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400831 chip_table = &hpt370a;
Alan Coxfcc2f692007-03-08 23:28:52 +0000832 prefer_dpll = 0;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400833 break;
834 case 5:
Tejun Heo887125e2008-03-25 12:22:49 +0900835 ppi[0] = &info_hpt372;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400836 chip_table = &hpt372;
837 break;
838 default:
839 printk(KERN_ERR "pata_hpt37x: Unknown HPT366 subtype please report (%d).\n", class_rev);
840 return -ENODEV;
841 }
842 } else {
843 switch(dev->device) {
844 case PCI_DEVICE_ID_TTI_HPT372:
845 /* 372N if rev >= 2*/
846 if (class_rev >= 2)
847 return -ENODEV;
Tejun Heo887125e2008-03-25 12:22:49 +0900848 ppi[0] = &info_hpt372;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400849 chip_table = &hpt372a;
850 break;
851 case PCI_DEVICE_ID_TTI_HPT302:
852 /* 302N if rev > 1 */
853 if (class_rev > 1)
854 return -ENODEV;
Tejun Heo887125e2008-03-25 12:22:49 +0900855 ppi[0] = &info_hpt372;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400856 /* Check this */
857 chip_table = &hpt302;
858 break;
859 case PCI_DEVICE_ID_TTI_HPT371:
Alan Coxfcc2f692007-03-08 23:28:52 +0000860 if (class_rev > 1)
861 return -ENODEV;
Tejun Heo887125e2008-03-25 12:22:49 +0900862 ppi[0] = &info_hpt372;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400863 chip_table = &hpt371;
Alan Coxa4734462007-04-26 00:19:25 -0700864 /* Single channel device, master is not present
865 but the BIOS (or us for non x86) must mark it
Alan Coxfcc2f692007-03-08 23:28:52 +0000866 absent */
867 pci_read_config_byte(dev, 0x50, &mcr1);
868 mcr1 &= ~0x04;
869 pci_write_config_byte(dev, 0x50, mcr1);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400870 break;
871 case PCI_DEVICE_ID_TTI_HPT374:
872 chip_table = &hpt374;
Tejun Heoa1efdab2008-03-25 12:22:50 +0900873 if (!(PCI_FUNC(dev->devfn) & 1))
874 *ppi = &info_hpt374_fn0;
875 else
876 *ppi = &info_hpt374_fn1;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400877 break;
878 default:
879 printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device);
880 return -ENODEV;
881 }
882 }
883 /* Ok so this is a chip we support */
884
885 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
886 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
887 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
888 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
889
890 pci_read_config_byte(dev, 0x5A, &irqmask);
891 irqmask &= ~0x10;
892 pci_write_config_byte(dev, 0x5a, irqmask);
893
894 /*
895 * default to pci clock. make sure MA15/16 are set to output
896 * to prevent drives having problems with 40-pin cables. Needed
897 * for some drives such as IBM-DTLA which will not enter ready
898 * state on reset when PDIAG is a input.
899 */
900
Jeff Garzik85cd7252006-08-31 00:03:49 -0400901 pci_write_config_byte(dev, 0x5b, 0x23);
Jeff Garzika617c092007-05-21 20:14:23 -0400902
Alan Coxfcc2f692007-03-08 23:28:52 +0000903 /*
904 * HighPoint does this for HPT372A.
905 * NOTE: This register is only writeable via I/O space.
906 */
907 if (chip_table == &hpt372a)
908 outb(0x0e, iobase + 0x9c);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400909
Alan Coxfcc2f692007-03-08 23:28:52 +0000910 /* Some devices do not let this value be accessed via PCI space
Alan Cox73946f92007-11-05 22:53:38 +0000911 according to the old driver. In addition we must use the value
912 from FN 0 on the HPT374 */
Alan Coxfcc2f692007-03-08 23:28:52 +0000913
Alan Cox73946f92007-11-05 22:53:38 +0000914 if (chip_table == &hpt374) {
915 freq = hpt374_read_freq(dev);
916 if (freq == 0)
917 return -ENODEV;
918 } else
919 freq = inl(iobase + 0x90);
920
Jeff Garzik669a5db2006-08-29 18:12:40 -0400921 if ((freq >> 12) != 0xABCDE) {
922 int i;
923 u8 sr;
924 u32 total = 0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400925
Jeff Garzik669a5db2006-08-29 18:12:40 -0400926 printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n");
Jeff Garzik85cd7252006-08-31 00:03:49 -0400927
Jeff Garzik669a5db2006-08-29 18:12:40 -0400928 /* This is the process the HPT371 BIOS is reported to use */
929 for(i = 0; i < 128; i++) {
930 pci_read_config_byte(dev, 0x78, &sr);
Alan Coxfcc2f692007-03-08 23:28:52 +0000931 total += sr & 0x1FF;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400932 udelay(15);
933 }
934 freq = total / 128;
935 }
936 freq &= 0x1FF;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400937
Jeff Garzik669a5db2006-08-29 18:12:40 -0400938 /*
939 * Turn the frequency check into a band and then find a timing
940 * table to match it.
941 */
Jeff Garzika617c092007-05-21 20:14:23 -0400942
Jeff Garzik669a5db2006-08-29 18:12:40 -0400943 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
Alan Coxfcc2f692007-03-08 23:28:52 +0000944 if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400945 /*
946 * We need to try PLL mode instead
Alan Coxfcc2f692007-03-08 23:28:52 +0000947 *
948 * For non UDMA133 capable devices we should
949 * use a 50MHz DPLL by choice
Jeff Garzik669a5db2006-08-29 18:12:40 -0400950 */
Alan Coxfcc2f692007-03-08 23:28:52 +0000951 unsigned int f_low, f_high;
Alan Cox960c8a12007-05-25 20:48:55 +0100952 int dpll, adjust;
Jeff Garzika617c092007-05-21 20:14:23 -0400953
Alan Cox960c8a12007-05-25 20:48:55 +0100954 /* Compute DPLL */
Tejun Heo887125e2008-03-25 12:22:49 +0900955 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;
Jeff Garzika617c092007-05-21 20:14:23 -0400956
Alan Cox960c8a12007-05-25 20:48:55 +0100957 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
Alan Coxfcc2f692007-03-08 23:28:52 +0000958 f_high = f_low + 2;
Alan Cox960c8a12007-05-25 20:48:55 +0100959 if (clock_slot > 1)
960 f_high += 2;
Alan Coxfcc2f692007-03-08 23:28:52 +0000961
962 /* Select the DPLL clock. */
963 pci_write_config_byte(dev, 0x5b, 0x21);
Alan Cox64a81702007-07-24 15:17:48 +0100964 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400965
Jeff Garzik669a5db2006-08-29 18:12:40 -0400966 for(adjust = 0; adjust < 8; adjust++) {
967 if (hpt37x_calibrate_dpll(dev))
968 break;
969 /* See if it'll settle at a fractionally different clock */
Alan Cox64a81702007-07-24 15:17:48 +0100970 if (adjust & 1)
971 f_low -= adjust >> 1;
972 else
973 f_high += adjust >> 1;
974 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400975 }
976 if (adjust == 8) {
Sergei Shtylyov80b89872007-08-10 21:02:15 +0400977 printk(KERN_ERR "pata_hpt37x: DPLL did not stabilize!\n");
Jeff Garzik669a5db2006-08-29 18:12:40 -0400978 return -ENODEV;
979 }
Alan Cox960c8a12007-05-25 20:48:55 +0100980 if (dpll == 3)
Tejun Heo1626aeb2007-05-04 12:43:58 +0200981 private_data = (void *)hpt37x_timings_66;
Alan Coxfcc2f692007-03-08 23:28:52 +0000982 else
Tejun Heo1626aeb2007-05-04 12:43:58 +0200983 private_data = (void *)hpt37x_timings_50;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400984
Sergei Shtylyov80b89872007-08-10 21:02:15 +0400985 printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using %dMHz DPLL.\n",
986 MHz[clock_slot], MHz[dpll]);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400987 } else {
Tejun Heo1626aeb2007-05-04 12:43:58 +0200988 private_data = (void *)chip_table->clocks[clock_slot];
Jeff Garzik669a5db2006-08-29 18:12:40 -0400989 /*
Alan Coxa4734462007-04-26 00:19:25 -0700990 * Perform a final fixup. Note that we will have used the
991 * DPLL on the HPT372 which means we don't have to worry
992 * about lack of UDMA133 support on lower clocks
993 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400994
Tejun Heo887125e2008-03-25 12:22:49 +0900995 if (clock_slot < 2 && ppi[0] == &info_hpt370)
996 ppi[0] = &info_hpt370_33;
997 if (clock_slot < 2 && ppi[0] == &info_hpt370a)
998 ppi[0] = &info_hpt370a_33;
Sergei Shtylyov80b89872007-08-10 21:02:15 +0400999 printk(KERN_INFO "pata_hpt37x: %s using %dMHz bus clock.\n",
1000 chip_table->name, MHz[clock_slot]);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001001 }
Alan Coxfcc2f692007-03-08 23:28:52 +00001002
Jeff Garzik669a5db2006-08-29 18:12:40 -04001003 /* Now kick off ATA set up */
Tejun Heo9363c382008-04-07 22:47:16 +09001004 return ata_pci_sff_init_one(dev, ppi, &hpt37x_sht, private_data);
Jeff Garzik669a5db2006-08-29 18:12:40 -04001005}
1006
Jeff Garzik2d2744f2006-09-28 20:21:59 -04001007static const struct pci_device_id hpt37x[] = {
1008 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
1009 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
1010 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
1011 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
1012 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1013
1014 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -04001015};
1016
1017static struct pci_driver hpt37x_pci_driver = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -04001018 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -04001019 .id_table = hpt37x,
1020 .probe = hpt37x_init_one,
1021 .remove = ata_pci_remove_one
1022};
1023
1024static int __init hpt37x_init(void)
1025{
1026 return pci_register_driver(&hpt37x_pci_driver);
1027}
1028
Jeff Garzik669a5db2006-08-29 18:12:40 -04001029static void __exit hpt37x_exit(void)
1030{
1031 pci_unregister_driver(&hpt37x_pci_driver);
1032}
1033
Jeff Garzik669a5db2006-08-29 18:12:40 -04001034MODULE_AUTHOR("Alan Cox");
1035MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1036MODULE_LICENSE("GPL");
1037MODULE_DEVICE_TABLE(pci, hpt37x);
1038MODULE_VERSION(DRV_VERSION);
1039
1040module_init(hpt37x_init);
1041module_exit(hpt37x_exit);