Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. |
| 3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
| 4 | * Leo Duran <leo.duran@amd.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published |
| 8 | * by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 18 | */ |
| 19 | |
| 20 | #ifndef __AMD_IOMMU_TYPES_H__ |
| 21 | #define __AMD_IOMMU_TYPES_H__ |
| 22 | |
| 23 | #include <linux/types.h> |
| 24 | #include <linux/list.h> |
| 25 | #include <linux/spinlock.h> |
| 26 | |
| 27 | /* |
| 28 | * some size calculation constants |
| 29 | */ |
Joerg Roedel | 83f5aac | 2008-07-11 17:14:34 +0200 | [diff] [blame] | 30 | #define DEV_TABLE_ENTRY_SIZE 32 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 31 | #define ALIAS_TABLE_ENTRY_SIZE 2 |
| 32 | #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *)) |
| 33 | |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 34 | /* Length of the MMIO region for the AMD IOMMU */ |
| 35 | #define MMIO_REGION_LENGTH 0x4000 |
| 36 | |
| 37 | /* Capability offsets used by the driver */ |
| 38 | #define MMIO_CAP_HDR_OFFSET 0x00 |
| 39 | #define MMIO_RANGE_OFFSET 0x0c |
| 40 | |
| 41 | /* Masks, shifts and macros to parse the device range capability */ |
| 42 | #define MMIO_RANGE_LD_MASK 0xff000000 |
| 43 | #define MMIO_RANGE_FD_MASK 0x00ff0000 |
| 44 | #define MMIO_RANGE_BUS_MASK 0x0000ff00 |
| 45 | #define MMIO_RANGE_LD_SHIFT 24 |
| 46 | #define MMIO_RANGE_FD_SHIFT 16 |
| 47 | #define MMIO_RANGE_BUS_SHIFT 8 |
| 48 | #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT) |
| 49 | #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT) |
| 50 | #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT) |
| 51 | |
| 52 | /* Flag masks for the AMD IOMMU exclusion range */ |
| 53 | #define MMIO_EXCL_ENABLE_MASK 0x01ULL |
| 54 | #define MMIO_EXCL_ALLOW_MASK 0x02ULL |
| 55 | |
| 56 | /* Used offsets into the MMIO space */ |
| 57 | #define MMIO_DEV_TABLE_OFFSET 0x0000 |
| 58 | #define MMIO_CMD_BUF_OFFSET 0x0008 |
| 59 | #define MMIO_EVT_BUF_OFFSET 0x0010 |
| 60 | #define MMIO_CONTROL_OFFSET 0x0018 |
| 61 | #define MMIO_EXCL_BASE_OFFSET 0x0020 |
| 62 | #define MMIO_EXCL_LIMIT_OFFSET 0x0028 |
| 63 | #define MMIO_CMD_HEAD_OFFSET 0x2000 |
| 64 | #define MMIO_CMD_TAIL_OFFSET 0x2008 |
| 65 | #define MMIO_EVT_HEAD_OFFSET 0x2010 |
| 66 | #define MMIO_EVT_TAIL_OFFSET 0x2018 |
| 67 | #define MMIO_STATUS_OFFSET 0x2020 |
| 68 | |
Joerg Roedel | 519c31b | 2008-08-14 19:55:15 +0200 | [diff] [blame] | 69 | /* MMIO status bits */ |
| 70 | #define MMIO_STATUS_COM_WAIT_INT_MASK 0x04 |
| 71 | |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 72 | /* feature control bits */ |
| 73 | #define CONTROL_IOMMU_EN 0x00ULL |
| 74 | #define CONTROL_HT_TUN_EN 0x01ULL |
| 75 | #define CONTROL_EVT_LOG_EN 0x02ULL |
| 76 | #define CONTROL_EVT_INT_EN 0x03ULL |
| 77 | #define CONTROL_COMWAIT_EN 0x04ULL |
| 78 | #define CONTROL_PASSPW_EN 0x08ULL |
| 79 | #define CONTROL_RESPASSPW_EN 0x09ULL |
| 80 | #define CONTROL_COHERENT_EN 0x0aULL |
| 81 | #define CONTROL_ISOC_EN 0x0bULL |
| 82 | #define CONTROL_CMDBUF_EN 0x0cULL |
| 83 | #define CONTROL_PPFLOG_EN 0x0dULL |
| 84 | #define CONTROL_PPFINT_EN 0x0eULL |
| 85 | |
| 86 | /* command specific defines */ |
| 87 | #define CMD_COMPL_WAIT 0x01 |
| 88 | #define CMD_INV_DEV_ENTRY 0x02 |
| 89 | #define CMD_INV_IOMMU_PAGES 0x03 |
| 90 | |
| 91 | #define CMD_COMPL_WAIT_STORE_MASK 0x01 |
Joerg Roedel | 519c31b | 2008-08-14 19:55:15 +0200 | [diff] [blame] | 92 | #define CMD_COMPL_WAIT_INT_MASK 0x02 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 93 | #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01 |
| 94 | #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02 |
| 95 | |
Joerg Roedel | 999ba41 | 2008-07-03 19:35:08 +0200 | [diff] [blame] | 96 | #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL |
| 97 | |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 98 | /* macros and definitions for device table entries */ |
| 99 | #define DEV_ENTRY_VALID 0x00 |
| 100 | #define DEV_ENTRY_TRANSLATION 0x01 |
| 101 | #define DEV_ENTRY_IR 0x3d |
| 102 | #define DEV_ENTRY_IW 0x3e |
Joerg Roedel | 9f5f5fb | 2008-08-14 19:55:16 +0200 | [diff] [blame] | 103 | #define DEV_ENTRY_NO_PAGE_FAULT 0x62 |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 104 | #define DEV_ENTRY_EX 0x67 |
| 105 | #define DEV_ENTRY_SYSMGT1 0x68 |
| 106 | #define DEV_ENTRY_SYSMGT2 0x69 |
| 107 | #define DEV_ENTRY_INIT_PASS 0xb8 |
| 108 | #define DEV_ENTRY_EINT_PASS 0xb9 |
| 109 | #define DEV_ENTRY_NMI_PASS 0xba |
| 110 | #define DEV_ENTRY_LINT0_PASS 0xbe |
| 111 | #define DEV_ENTRY_LINT1_PASS 0xbf |
| 112 | |
| 113 | /* constants to configure the command buffer */ |
| 114 | #define CMD_BUFFER_SIZE 8192 |
| 115 | #define CMD_BUFFER_ENTRIES 512 |
| 116 | #define MMIO_CMD_SIZE_SHIFT 56 |
| 117 | #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT) |
| 118 | |
| 119 | #define PAGE_MODE_1_LEVEL 0x01 |
| 120 | #define PAGE_MODE_2_LEVEL 0x02 |
| 121 | #define PAGE_MODE_3_LEVEL 0x03 |
| 122 | |
| 123 | #define IOMMU_PDE_NL_0 0x000ULL |
| 124 | #define IOMMU_PDE_NL_1 0x200ULL |
| 125 | #define IOMMU_PDE_NL_2 0x400ULL |
| 126 | #define IOMMU_PDE_NL_3 0x600ULL |
| 127 | |
| 128 | #define IOMMU_PTE_L2_INDEX(address) (((address) >> 30) & 0x1ffULL) |
| 129 | #define IOMMU_PTE_L1_INDEX(address) (((address) >> 21) & 0x1ffULL) |
| 130 | #define IOMMU_PTE_L0_INDEX(address) (((address) >> 12) & 0x1ffULL) |
| 131 | |
| 132 | #define IOMMU_MAP_SIZE_L1 (1ULL << 21) |
| 133 | #define IOMMU_MAP_SIZE_L2 (1ULL << 30) |
| 134 | #define IOMMU_MAP_SIZE_L3 (1ULL << 39) |
| 135 | |
| 136 | #define IOMMU_PTE_P (1ULL << 0) |
| 137 | #define IOMMU_PTE_U (1ULL << 59) |
| 138 | #define IOMMU_PTE_FC (1ULL << 60) |
| 139 | #define IOMMU_PTE_IR (1ULL << 61) |
| 140 | #define IOMMU_PTE_IW (1ULL << 62) |
| 141 | |
| 142 | #define IOMMU_L1_PDE(address) \ |
| 143 | ((address) | IOMMU_PDE_NL_1 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW) |
| 144 | #define IOMMU_L2_PDE(address) \ |
| 145 | ((address) | IOMMU_PDE_NL_2 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW) |
| 146 | |
| 147 | #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) |
| 148 | #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P) |
| 149 | #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK)) |
| 150 | #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07) |
| 151 | |
| 152 | #define IOMMU_PROT_MASK 0x03 |
| 153 | #define IOMMU_PROT_IR 0x01 |
| 154 | #define IOMMU_PROT_IW 0x02 |
| 155 | |
| 156 | /* IOMMU capabilities */ |
| 157 | #define IOMMU_CAP_IOTLB 24 |
| 158 | #define IOMMU_CAP_NPCACHE 26 |
| 159 | |
| 160 | #define MAX_DOMAIN_ID 65536 |
| 161 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 162 | /* |
| 163 | * This structure contains generic data for IOMMU protection domains |
| 164 | * independent of their use. |
| 165 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 166 | struct protection_domain { |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 167 | spinlock_t lock; /* mostly used to lock the page table*/ |
| 168 | u16 id; /* the domain id written to the device table */ |
| 169 | int mode; /* paging mode (0-6 levels) */ |
| 170 | u64 *pt_root; /* page table root pointer */ |
| 171 | void *priv; /* private data */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 172 | }; |
| 173 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 174 | /* |
| 175 | * Data container for a dma_ops specific protection domain |
| 176 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 177 | struct dma_ops_domain { |
| 178 | struct list_head list; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 179 | |
| 180 | /* generic protection domain information */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 181 | struct protection_domain domain; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 182 | |
| 183 | /* size of the aperture for the mappings */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 184 | unsigned long aperture_size; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 185 | |
| 186 | /* address we start to search for free addresses */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 187 | unsigned long next_bit; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 188 | |
| 189 | /* address allocation bitmap */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 190 | unsigned long *bitmap; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 191 | |
| 192 | /* |
| 193 | * Array of PTE pages for the aperture. In this array we save all the |
| 194 | * leaf pages of the domain page table used for the aperture. This way |
| 195 | * we don't need to walk the page table to find a specific PTE. We can |
| 196 | * just calculate its address in constant time. |
| 197 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 198 | u64 **pte_pages; |
| 199 | }; |
| 200 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 201 | /* |
| 202 | * Structure where we save information about one hardware AMD IOMMU in the |
| 203 | * system. |
| 204 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 205 | struct amd_iommu { |
| 206 | struct list_head list; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 207 | |
| 208 | /* locks the accesses to the hardware */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 209 | spinlock_t lock; |
| 210 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 211 | /* device id of this IOMMU */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 212 | u16 devid; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 213 | /* |
| 214 | * Capability pointer. There could be more than one IOMMU per PCI |
| 215 | * device function if there are more than one AMD IOMMU capability |
| 216 | * pointers. |
| 217 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 218 | u16 cap_ptr; |
| 219 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 220 | /* physical address of MMIO space */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 221 | u64 mmio_phys; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 222 | /* virtual address of MMIO space */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 223 | u8 *mmio_base; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 224 | |
| 225 | /* capabilities of that IOMMU read from ACPI */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 226 | u32 cap; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 227 | |
| 228 | /* first device this IOMMU handles. read from PCI */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 229 | u16 first_device; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 230 | /* last device this IOMMU handles. read from PCI */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 231 | u16 last_device; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 232 | |
| 233 | /* start of exclusion range of that IOMMU */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 234 | u64 exclusion_start; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 235 | /* length of exclusion range of that IOMMU */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 236 | u64 exclusion_length; |
| 237 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 238 | /* command buffer virtual address */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 239 | u8 *cmd_buf; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 240 | /* size of command buffer */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 241 | u32 cmd_buf_size; |
| 242 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 243 | /* if one, we need to send a completion wait command */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 244 | int need_sync; |
| 245 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 246 | /* default dma_ops domain for that IOMMU */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 247 | struct dma_ops_domain *default_dom; |
| 248 | }; |
| 249 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 250 | /* |
| 251 | * List with all IOMMUs in the system. This list is not locked because it is |
| 252 | * only written and read at driver initialization or suspend time |
| 253 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 254 | extern struct list_head amd_iommu_list; |
| 255 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 256 | /* |
| 257 | * Structure defining one entry in the device table |
| 258 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 259 | struct dev_table_entry { |
| 260 | u32 data[8]; |
| 261 | }; |
| 262 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 263 | /* |
| 264 | * One entry for unity mappings parsed out of the ACPI table. |
| 265 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 266 | struct unity_map_entry { |
| 267 | struct list_head list; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 268 | |
| 269 | /* starting device id this entry is used for (including) */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 270 | u16 devid_start; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 271 | /* end device id this entry is used for (including) */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 272 | u16 devid_end; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 273 | |
| 274 | /* start address to unity map (including) */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 275 | u64 address_start; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 276 | /* end address to unity map (including) */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 277 | u64 address_end; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 278 | |
| 279 | /* required protection */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 280 | int prot; |
| 281 | }; |
| 282 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 283 | /* |
| 284 | * List of all unity mappings. It is not locked because as runtime it is only |
| 285 | * read. It is created at ACPI table parsing time. |
| 286 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 287 | extern struct list_head amd_iommu_unity_map; |
| 288 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 289 | /* |
| 290 | * Data structures for device handling |
| 291 | */ |
| 292 | |
| 293 | /* |
| 294 | * Device table used by hardware. Read and write accesses by software are |
| 295 | * locked with the amd_iommu_pd_table lock. |
| 296 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 297 | extern struct dev_table_entry *amd_iommu_dev_table; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 298 | |
| 299 | /* |
| 300 | * Alias table to find requestor ids to device ids. Not locked because only |
| 301 | * read on runtime. |
| 302 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 303 | extern u16 *amd_iommu_alias_table; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 304 | |
| 305 | /* |
| 306 | * Reverse lookup table to find the IOMMU which translates a specific device. |
| 307 | */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 308 | extern struct amd_iommu **amd_iommu_rlookup_table; |
| 309 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 310 | /* size of the dma_ops aperture as power of 2 */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 311 | extern unsigned amd_iommu_aperture_order; |
| 312 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 313 | /* largest PCI device id we expect translation requests for */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 314 | extern u16 amd_iommu_last_bdf; |
| 315 | |
| 316 | /* data structures for protection domain handling */ |
| 317 | extern struct protection_domain **amd_iommu_pd_table; |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 318 | |
| 319 | /* allocation bitmap for domain ids */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 320 | extern unsigned long *amd_iommu_pd_alloc_bitmap; |
| 321 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 322 | /* will be 1 if device isolation is enabled */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 323 | extern int amd_iommu_isolate; |
| 324 | |
Joerg Roedel | 5694703 | 2008-07-11 17:14:20 +0200 | [diff] [blame] | 325 | /* takes a PCI device id and prints it out in a readable form */ |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 326 | static inline void print_devid(u16 devid, int nl) |
| 327 | { |
| 328 | int bus = devid >> 8; |
| 329 | int dev = devid >> 3 & 0x1f; |
| 330 | int fn = devid & 0x07; |
| 331 | |
| 332 | printk("%02x:%02x.%x", bus, dev, fn); |
| 333 | if (nl) |
| 334 | printk("\n"); |
| 335 | } |
| 336 | |
Joerg Roedel | d591b0a | 2008-07-11 17:14:35 +0200 | [diff] [blame] | 337 | /* takes bus and device/function and returns the device id |
| 338 | * FIXME: should that be in generic PCI code? */ |
| 339 | static inline u16 calc_devid(u8 bus, u8 devfn) |
| 340 | { |
| 341 | return (((u16)bus) << 8) | devfn; |
| 342 | } |
| 343 | |
Joerg Roedel | 8d283c3 | 2008-06-26 21:27:38 +0200 | [diff] [blame] | 344 | #endif |