Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 1 | #ifndef __ASM_X86_MSR_H_ |
| 2 | #define __ASM_X86_MSR_H_ |
| 3 | |
| 4 | #include <asm/msr-index.h> |
| 5 | |
Mike Frysinger | d43a331 | 2008-01-15 16:44:38 +0100 | [diff] [blame] | 6 | #ifndef __ASSEMBLY__ |
| 7 | # include <linux/types.h> |
| 8 | #endif |
| 9 | |
Glauber de Oliveira Costa | 8f12dea | 2008-01-30 13:31:06 +0100 | [diff] [blame] | 10 | #ifdef __KERNEL__ |
| 11 | #ifndef __ASSEMBLY__ |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 12 | |
| 13 | #include <asm/asm.h> |
| 14 | #include <asm/errno.h> |
| 15 | |
Andrew Morton | 1e160cc | 2008-01-30 13:31:17 +0100 | [diff] [blame] | 16 | static inline unsigned long long native_read_tscp(unsigned int *aux) |
Glauber de Oliveira Costa | 8f12dea | 2008-01-30 13:31:06 +0100 | [diff] [blame] | 17 | { |
| 18 | unsigned long low, high; |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 19 | asm volatile(".byte 0x0f,0x01,0xf9" |
| 20 | : "=a" (low), "=d" (high), "=c" (*aux)); |
Max Asbock | 41aefdc | 2008-06-25 14:45:28 -0700 | [diff] [blame] | 21 | return low | ((u64)high << 32); |
Glauber de Oliveira Costa | 8f12dea | 2008-01-30 13:31:06 +0100 | [diff] [blame] | 22 | } |
| 23 | |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 24 | /* |
| 25 | * i386 calling convention returns 64-bit value in edx:eax, while |
| 26 | * x86_64 returns at rax. Also, the "A" constraint does not really |
| 27 | * mean rdx:rax in x86_64, so we need specialized behaviour for each |
| 28 | * architecture |
| 29 | */ |
| 30 | #ifdef CONFIG_X86_64 |
| 31 | #define DECLARE_ARGS(val, low, high) unsigned low, high |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 32 | #define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32)) |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 33 | #define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high) |
| 34 | #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) |
| 35 | #else |
| 36 | #define DECLARE_ARGS(val, low, high) unsigned long long val |
| 37 | #define EAX_EDX_VAL(val, low, high) (val) |
| 38 | #define EAX_EDX_ARGS(val, low, high) "A" (val) |
| 39 | #define EAX_EDX_RET(val, low, high) "=A" (val) |
Glauber de Oliveira Costa | 8f12dea | 2008-01-30 13:31:06 +0100 | [diff] [blame] | 40 | #endif |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 41 | |
| 42 | static inline unsigned long long native_read_msr(unsigned int msr) |
| 43 | { |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 44 | DECLARE_ARGS(val, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 45 | |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 46 | asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); |
| 47 | return EAX_EDX_VAL(val, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 48 | } |
| 49 | |
| 50 | static inline unsigned long long native_read_msr_safe(unsigned int msr, |
| 51 | int *err) |
| 52 | { |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 53 | DECLARE_ARGS(val, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 54 | |
H. Peter Anvin | 08970fc | 2008-08-25 22:39:15 -0700 | [diff] [blame] | 55 | asm volatile("2: rdmsr ; xor %[err],%[err]\n" |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 56 | "1:\n\t" |
| 57 | ".section .fixup,\"ax\"\n\t" |
H. Peter Anvin | 08970fc | 2008-08-25 22:39:15 -0700 | [diff] [blame] | 58 | "3: mov %[fault],%[err] ; jmp 1b\n\t" |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 59 | ".previous\n\t" |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 60 | _ASM_EXTABLE(2b, 3b) |
H. Peter Anvin | 08970fc | 2008-08-25 22:39:15 -0700 | [diff] [blame] | 61 | : [err] "=r" (*err), EAX_EDX_RET(val, low, high) |
| 62 | : "c" (msr), [fault] "i" (-EFAULT)); |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 63 | return EAX_EDX_VAL(val, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 64 | } |
| 65 | |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 66 | static inline void native_write_msr(unsigned int msr, |
| 67 | unsigned low, unsigned high) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 68 | { |
Jeremy Fitzhardinge | af2b1c6 | 2008-06-25 00:18:59 -0400 | [diff] [blame] | 69 | asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory"); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 70 | } |
| 71 | |
| 72 | static inline int native_write_msr_safe(unsigned int msr, |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 73 | unsigned low, unsigned high) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 74 | { |
| 75 | int err; |
H. Peter Anvin | 08970fc | 2008-08-25 22:39:15 -0700 | [diff] [blame] | 76 | asm volatile("2: wrmsr ; xor %[err],%[err]\n" |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 77 | "1:\n\t" |
| 78 | ".section .fixup,\"ax\"\n\t" |
H. Peter Anvin | 08970fc | 2008-08-25 22:39:15 -0700 | [diff] [blame] | 79 | "3: mov %[fault],%[err] ; jmp 1b\n\t" |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 80 | ".previous\n\t" |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 81 | _ASM_EXTABLE(2b, 3b) |
H. Peter Anvin | 08970fc | 2008-08-25 22:39:15 -0700 | [diff] [blame] | 82 | : [err] "=a" (err) |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 83 | : "c" (msr), "0" (low), "d" (high), |
H. Peter Anvin | 08970fc | 2008-08-25 22:39:15 -0700 | [diff] [blame] | 84 | [fault] "i" (-EFAULT) |
Jeremy Fitzhardinge | af2b1c6 | 2008-06-25 00:18:59 -0400 | [diff] [blame] | 85 | : "memory"); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 86 | return err; |
| 87 | } |
| 88 | |
Ingo Molnar | cdc7957 | 2008-01-30 13:32:39 +0100 | [diff] [blame] | 89 | extern unsigned long long native_read_tsc(void); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 90 | |
Ingo Molnar | 92767af | 2008-01-30 13:32:40 +0100 | [diff] [blame] | 91 | static __always_inline unsigned long long __native_read_tsc(void) |
| 92 | { |
| 93 | DECLARE_ARGS(val, low, high); |
| 94 | |
| 95 | rdtsc_barrier(); |
| 96 | asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); |
| 97 | rdtsc_barrier(); |
| 98 | |
| 99 | return EAX_EDX_VAL(val, low, high); |
| 100 | } |
| 101 | |
Glauber de Oliveira Costa | b8d1fae | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 102 | static inline unsigned long long native_read_pmc(int counter) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 103 | { |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 104 | DECLARE_ARGS(val, low, high); |
| 105 | |
| 106 | asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); |
| 107 | return EAX_EDX_VAL(val, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | #ifdef CONFIG_PARAVIRT |
| 111 | #include <asm/paravirt.h> |
Thomas Gleixner | 96a388d | 2007-10-11 11:20:03 +0200 | [diff] [blame] | 112 | #else |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 113 | #include <linux/errno.h> |
| 114 | /* |
| 115 | * Access to machine-specific registers (available on 586 and better only) |
| 116 | * Note: the rd* operations modify the parameters directly (without using |
| 117 | * pointer indirection), this allows gcc to optimize better |
| 118 | */ |
| 119 | |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 120 | #define rdmsr(msr, val1, val2) \ |
| 121 | do { \ |
| 122 | u64 __val = native_read_msr((msr)); \ |
| 123 | (val1) = (u32)__val; \ |
| 124 | (val2) = (u32)(__val >> 32); \ |
| 125 | } while (0) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 126 | |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 127 | static inline void wrmsr(unsigned msr, unsigned low, unsigned high) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 128 | { |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 129 | native_write_msr(msr, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 130 | } |
| 131 | |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 132 | #define rdmsrl(msr, val) \ |
| 133 | ((val) = native_read_msr((msr))) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 134 | |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 135 | #define wrmsrl(msr, val) \ |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 136 | native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32)) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 137 | |
| 138 | /* wrmsr with exception handling */ |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 139 | static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 140 | { |
Glauber de Oliveira Costa | c9dcda5 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 141 | return native_write_msr_safe(msr, low, high); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 142 | } |
| 143 | |
| 144 | /* rdmsr with exception handling */ |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 145 | #define rdmsr_safe(msr, p1, p2) \ |
| 146 | ({ \ |
| 147 | int __err; \ |
| 148 | u64 __val = native_read_msr_safe((msr), &__err); \ |
| 149 | (*p1) = (u32)__val; \ |
| 150 | (*p2) = (u32)(__val >> 32); \ |
| 151 | __err; \ |
| 152 | }) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 153 | |
Andi Kleen | 1de87bd | 2008-03-22 10:59:28 +0100 | [diff] [blame] | 154 | static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
| 155 | { |
| 156 | int err; |
| 157 | |
| 158 | *p = native_read_msr_safe(msr, &err); |
| 159 | return err; |
| 160 | } |
| 161 | |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 162 | #define rdtscl(low) \ |
| 163 | ((low) = (u32)native_read_tsc()) |
| 164 | |
| 165 | #define rdtscll(val) \ |
| 166 | ((val) = native_read_tsc()) |
| 167 | |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 168 | #define rdpmc(counter, low, high) \ |
| 169 | do { \ |
| 170 | u64 _l = native_read_pmc((counter)); \ |
| 171 | (low) = (u32)_l; \ |
| 172 | (high) = (u32)(_l >> 32); \ |
| 173 | } while (0) |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 174 | |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 175 | #define rdtscp(low, high, aux) \ |
| 176 | do { \ |
| 177 | unsigned long long _val = native_read_tscp(&(aux)); \ |
| 178 | (low) = (u32)_val; \ |
| 179 | (high) = (u32)(_val >> 32); \ |
| 180 | } while (0) |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 181 | |
| 182 | #define rdtscpll(val, aux) (val) = native_read_tscp(&(aux)) |
| 183 | |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 184 | #endif /* !CONFIG_PARAVIRT */ |
| 185 | |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 186 | |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 187 | #define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val), \ |
| 188 | (u32)((val) >> 32)) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 189 | |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 190 | #define write_tsc(val1, val2) wrmsr(0x10, (val1), (val2)) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 191 | |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 192 | #define write_rdtscp_aux(val) wrmsr(0xc0000103, (val), 0) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 193 | |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 194 | #ifdef CONFIG_SMP |
H. Peter Anvin | c6f3193 | 2008-08-25 17:27:21 -0700 | [diff] [blame] | 195 | int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
| 196 | int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 197 | int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
| 198 | int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); |
| 199 | #else /* CONFIG_SMP */ |
H. Peter Anvin | c6f3193 | 2008-08-25 17:27:21 -0700 | [diff] [blame] | 200 | static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 201 | { |
| 202 | rdmsr(msr_no, *l, *h); |
H. Peter Anvin | c6f3193 | 2008-08-25 17:27:21 -0700 | [diff] [blame] | 203 | return 0; |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 204 | } |
H. Peter Anvin | c6f3193 | 2008-08-25 17:27:21 -0700 | [diff] [blame] | 205 | static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 206 | { |
| 207 | wrmsr(msr_no, l, h); |
H. Peter Anvin | c6f3193 | 2008-08-25 17:27:21 -0700 | [diff] [blame] | 208 | return 0; |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 209 | } |
Joe Perches | abb0ade | 2008-03-23 01:02:51 -0700 | [diff] [blame] | 210 | static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, |
| 211 | u32 *l, u32 *h) |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 212 | { |
| 213 | return rdmsr_safe(msr_no, l, h); |
| 214 | } |
| 215 | static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) |
| 216 | { |
| 217 | return wrmsr_safe(msr_no, l, h); |
| 218 | } |
| 219 | #endif /* CONFIG_SMP */ |
Glauber de Oliveira Costa | 751de83 | 2008-01-30 13:31:03 +0100 | [diff] [blame] | 220 | #endif /* __ASSEMBLY__ */ |
Glauber de Oliveira Costa | c210d24 | 2008-01-30 13:31:07 +0100 | [diff] [blame] | 221 | #endif /* __KERNEL__ */ |
| 222 | |
Thomas Gleixner | be7baf8 | 2007-10-23 22:37:24 +0200 | [diff] [blame] | 223 | |
Thomas Gleixner | 96a388d | 2007-10-11 11:20:03 +0200 | [diff] [blame] | 224 | #endif |