Daniel Walker | da6df07 | 2010-04-23 16:04:20 -0700 | [diff] [blame] | 1 | /* include/linux/msm_mdp.h |
| 2 | * |
| 3 | * Copyright (C) 2007 Google Incorporated |
Pawan Kumar | ce25d14 | 2014-01-29 16:47:35 +0530 | [diff] [blame] | 4 | * Copyright (c) 2012-2014 The Linux Foundation. All rights reserved. |
Daniel Walker | da6df07 | 2010-04-23 16:04:20 -0700 | [diff] [blame] | 5 | * |
| 6 | * This software is licensed under the terms of the GNU General Public |
| 7 | * License version 2, as published by the Free Software Foundation, and |
| 8 | * may be copied, distributed, and modified under those terms. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | #ifndef _MSM_MDP_H_ |
| 16 | #define _MSM_MDP_H_ |
| 17 | |
| 18 | #include <linux/types.h> |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 19 | #include <linux/fb.h> |
Daniel Walker | da6df07 | 2010-04-23 16:04:20 -0700 | [diff] [blame] | 20 | |
| 21 | #define MSMFB_IOCTL_MAGIC 'm' |
| 22 | #define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) |
| 23 | #define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 24 | #define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) |
| 25 | #define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) |
| 26 | #define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) |
| 27 | #define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) |
Carl Vanderlip | ba093a2 | 2011-11-22 13:59:59 -0800 | [diff] [blame] | 28 | #define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 29 | /* new ioctls's for set/get ccs matrix */ |
| 30 | #define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) |
| 31 | #define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) |
| 32 | #define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \ |
| 33 | struct mdp_overlay) |
| 34 | #define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) |
Kuogee Hsieh | 586fd16 | 2012-02-14 15:24:16 -0800 | [diff] [blame] | 35 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 36 | #define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \ |
| 37 | struct msmfb_overlay_data) |
Kuogee Hsieh | 586fd16 | 2012-02-14 15:24:16 -0800 | [diff] [blame] | 38 | #define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY |
| 39 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 40 | #define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \ |
| 41 | struct mdp_page_protection) |
| 42 | #define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \ |
| 43 | struct mdp_page_protection) |
| 44 | #define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \ |
| 45 | struct mdp_overlay) |
| 46 | #define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) |
| 47 | #define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \ |
| 48 | struct msmfb_overlay_blt) |
| 49 | #define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) |
Carl Vanderlip | ba093a2 | 2011-11-22 13:59:59 -0800 | [diff] [blame] | 50 | #define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \ |
| 51 | struct mdp_histogram_start_req) |
| 52 | #define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) |
Carl Vanderlip | 0d6ef4a | 2013-05-30 11:48:48 -0700 | [diff] [blame] | 53 | #define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 54 | |
| 55 | #define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \ |
| 56 | struct msmfb_overlay_3d) |
| 57 | |
kuogee hsieh | 405dc30 | 2011-07-21 15:06:59 -0700 | [diff] [blame] | 58 | #define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \ |
| 59 | struct msmfb_mixer_info_req) |
Nagamalleswararao Ganji | 0737d65 | 2011-10-14 02:02:33 -0700 | [diff] [blame] | 60 | #define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \ |
| 61 | struct msmfb_overlay_data) |
Vinay Kalia | 27020d1 | 2011-10-14 17:50:29 -0700 | [diff] [blame] | 62 | #define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) |
Vinay Kalia | e1ba270 | 2011-12-21 16:24:52 -0800 | [diff] [blame] | 63 | #define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) |
| 64 | #define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) |
Vinay Kalia | 27020d1 | 2011-10-14 17:50:29 -0700 | [diff] [blame] | 65 | #define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \ |
| 66 | struct msmfb_data) |
| 67 | #define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \ |
| 68 | struct msmfb_data) |
| 69 | #define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) |
Pravin Tamkhane | 02a4068 | 2011-11-29 14:17:01 -0800 | [diff] [blame] | 70 | #define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) |
Padmanabhan Komanduru | f3b0c23 | 2012-07-27 20:46:06 +0530 | [diff] [blame] | 71 | #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) |
| 72 | #define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) |
Vishnuvardhan Prodduturi | feb2629 | 2013-02-06 18:23:35 +0530 | [diff] [blame] | 73 | #define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) |
Kalyan Thota | 9284a27 | 2012-11-02 20:55:30 +0530 | [diff] [blame] | 74 | #define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) |
Vishnuvardhan Prodduturi | feb2629 | 2013-02-06 18:23:35 +0530 | [diff] [blame] | 75 | #define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \ |
Ken Zhang | 4e83b93 | 2012-12-02 21:15:47 -0500 | [diff] [blame] | 76 | struct mdp_display_commit) |
Vishnuvardhan Prodduturi | feb2629 | 2013-02-06 18:23:35 +0530 | [diff] [blame] | 77 | #define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) |
Ken Zhang | 420dd20 | 2013-01-08 14:28:20 -0500 | [diff] [blame] | 78 | #define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) |
Deva Ramasubramanian | 166b098 | 2013-01-25 20:11:41 -0800 | [diff] [blame] | 79 | #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \ |
| 80 | unsigned int) |
Terence Hampson | 3e636aa | 2013-05-08 19:01:51 -0400 | [diff] [blame] | 81 | #define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) |
Adrian Salido-Moreno | 6b15509 | 2014-01-07 17:29:20 -0800 | [diff] [blame] | 82 | #define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, \ |
| 83 | struct mdp_overlay_list) |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 84 | #define FB_TYPE_3D_PANEL 0x10101010 |
| 85 | #define MDP_IMGTYPE2_START 0x10000 |
| 86 | #define MSMFB_DRIVER_VERSION 0xF9E8D701 |
Daniel Walker | da6df07 | 2010-04-23 16:04:20 -0700 | [diff] [blame] | 87 | |
Ujwal Patel | 999ee56 | 2013-12-05 13:35:51 -0800 | [diff] [blame] | 88 | /* HW Revisions for different MDSS targets */ |
| 89 | #define MDSS_GET_MAJOR(rev) ((rev) >> 28) |
| 90 | #define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) |
| 91 | #define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) |
| 92 | #define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) |
| 93 | |
| 94 | #define IS_MDSS_MAJOR_MINOR_SAME(rev1, rev2) \ |
| 95 | (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) |
| 96 | |
| 97 | #define MDSS_MDP_REV(major, minor, step) \ |
| 98 | ((((major) & 0x000F) << 28) | \ |
| 99 | (((minor) & 0x0FFF) << 16) | \ |
| 100 | ((step) & 0xFFFF)) |
| 101 | |
| 102 | #define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) /* 8974 v1.0 */ |
| 103 | #define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) /* 8x26 v1.0 */ |
| 104 | #define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) /* 8x26 v2.0, 8926 v1.0 */ |
| 105 | #define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) /* 8926 v2.0 */ |
| 106 | #define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */ |
| 107 | #define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */ |
| 108 | #define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */ |
| 109 | #define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) /* 8084 v1.1 */ |
| 110 | #define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */ |
| 111 | |
Daniel Walker | da6df07 | 2010-04-23 16:04:20 -0700 | [diff] [blame] | 112 | enum { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 113 | NOTIFY_UPDATE_START, |
| 114 | NOTIFY_UPDATE_STOP, |
Arpita Banerjee | a8b7fbf | 2013-06-11 19:24:20 -0700 | [diff] [blame] | 115 | NOTIFY_UPDATE_POWER_OFF, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 116 | }; |
| 117 | |
| 118 | enum { |
Carl Vanderlip | 0d6ef4a | 2013-05-30 11:48:48 -0700 | [diff] [blame] | 119 | NOTIFY_TYPE_NO_UPDATE, |
| 120 | NOTIFY_TYPE_SUSPEND, |
| 121 | NOTIFY_TYPE_UPDATE, |
Ping Li | aabff72 | 2014-03-17 10:06:47 -0700 | [diff] [blame] | 122 | NOTIFY_TYPE_BL_UPDATE, |
Carl Vanderlip | 0d6ef4a | 2013-05-30 11:48:48 -0700 | [diff] [blame] | 123 | }; |
| 124 | |
| 125 | enum { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 126 | MDP_RGB_565, /* RGB 565 planer */ |
| 127 | MDP_XRGB_8888, /* RGB 888 padded */ |
| 128 | MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */ |
Padmanabhan Komanduru | d9f38b0 | 2012-02-02 18:57:03 +0530 | [diff] [blame] | 129 | MDP_Y_CBCR_H2V2_ADRENO, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 130 | MDP_ARGB_8888, /* ARGB 888 */ |
| 131 | MDP_RGB_888, /* RGB 888 planer */ |
| 132 | MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */ |
| 133 | MDP_YCRYCB_H2V1, /* YCrYCb interleave */ |
Pawan Kumar | 42acdef | 2013-03-21 19:55:49 +0530 | [diff] [blame] | 134 | MDP_CBYCRY_H2V1, /* CbYCrY interleave */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 135 | MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ |
| 136 | MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ |
Adrian Salido-Moreno | e55fa12 | 2012-05-29 15:36:08 -0700 | [diff] [blame] | 137 | MDP_Y_CRCB_H1V2, |
| 138 | MDP_Y_CBCR_H1V2, |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 139 | MDP_RGBA_8888, /* ARGB 888 */ |
| 140 | MDP_BGRA_8888, /* ABGR 888 */ |
| 141 | MDP_RGBX_8888, /* RGBX 888 */ |
| 142 | MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */ |
| 143 | MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */ |
| 144 | MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */ |
Pradeep Jilagam | 9b4a6be | 2011-10-03 17:19:20 +0530 | [diff] [blame] | 145 | MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 146 | MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */ |
| 147 | MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */ |
| 148 | MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */ |
Adrian Salido-Moreno | 2b41048 | 2011-08-15 10:40:40 -0700 | [diff] [blame] | 149 | MDP_YCRCB_H1V1, /* YCrCb interleave */ |
| 150 | MDP_YCBCR_H1V1, /* YCbCr interleave */ |
Adrian Salido-Moreno | e55fa12 | 2012-05-29 15:36:08 -0700 | [diff] [blame] | 151 | MDP_BGR_565, /* BGR 565 planer */ |
Adrian Salido-Moreno | d559ef1 | 2012-07-12 20:16:14 -0700 | [diff] [blame] | 152 | MDP_BGR_888, /* BGR 888 */ |
Adrian Salido-Moreno | 330c0bf | 2012-08-22 14:15:33 -0700 | [diff] [blame] | 153 | MDP_Y_CBCR_H2V2_VENUS, |
Pawan Kumar | 7985438 | 2013-02-14 15:27:12 +0530 | [diff] [blame] | 154 | MDP_BGRX_8888, /* BGRX 8888 */ |
Shalabh Jain | bea586a | 2013-08-23 12:30:48 -0700 | [diff] [blame] | 155 | MDP_RGBA_8888_TILE, /* RGBA 8888 in tile format */ |
| 156 | MDP_ARGB_8888_TILE, /* ARGB 8888 in tile format */ |
| 157 | MDP_ABGR_8888_TILE, /* ABGR 8888 in tile format */ |
| 158 | MDP_BGRA_8888_TILE, /* BGRA 8888 in tile format */ |
| 159 | MDP_RGBX_8888_TILE, /* RGBX 8888 in tile format */ |
| 160 | MDP_XRGB_8888_TILE, /* XRGB 8888 in tile format */ |
| 161 | MDP_XBGR_8888_TILE, /* XBGR 8888 in tile format */ |
| 162 | MDP_BGRX_8888_TILE, /* BGRX 8888 in tile format */ |
Ramkumar Radhakrishnan | 97180fa | 2013-08-06 20:50:52 -0700 | [diff] [blame] | 163 | MDP_YCBYCR_H2V1, /* YCbYCr interleave */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 164 | MDP_IMGTYPE_LIMIT, |
kuogee hsieh | 1ce7e4c | 2012-01-13 14:05:54 -0800 | [diff] [blame] | 165 | MDP_RGB_BORDERFILL, /* border fill pipe */ |
Adrian Salido-Moreno | e55fa12 | 2012-05-29 15:36:08 -0700 | [diff] [blame] | 166 | MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 167 | MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */ |
Daniel Walker | da6df07 | 2010-04-23 16:04:20 -0700 | [diff] [blame] | 168 | }; |
| 169 | |
| 170 | enum { |
| 171 | PMEM_IMG, |
| 172 | FB_IMG, |
| 173 | }; |
| 174 | |
Liyuan Li | d973663 | 2011-11-11 13:47:59 -0800 | [diff] [blame] | 175 | enum { |
| 176 | HSIC_HUE = 0, |
| 177 | HSIC_SAT, |
| 178 | HSIC_INT, |
| 179 | HSIC_CON, |
| 180 | NUM_HSIC_PARAM, |
| 181 | }; |
| 182 | |
Adrian Salido-Moreno | 1857f06 | 2012-05-29 17:57:28 -0700 | [diff] [blame] | 183 | #define MDSS_MDP_ROT_ONLY 0x80 |
Adrian Salido-Moreno | e55fa12 | 2012-05-29 15:36:08 -0700 | [diff] [blame] | 184 | #define MDSS_MDP_RIGHT_MIXER 0x100 |
Adrian Salido-Moreno | 6afd780 | 2013-08-05 14:03:25 -0700 | [diff] [blame] | 185 | #define MDSS_MDP_DUAL_PIPE 0x200 |
Adrian Salido-Moreno | e55fa12 | 2012-05-29 15:36:08 -0700 | [diff] [blame] | 186 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 187 | /* mdp_blit_req flag values */ |
| 188 | #define MDP_ROT_NOP 0 |
| 189 | #define MDP_FLIP_LR 0x1 |
| 190 | #define MDP_FLIP_UD 0x2 |
| 191 | #define MDP_ROT_90 0x4 |
| 192 | #define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR) |
| 193 | #define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR) |
| 194 | #define MDP_DITHER 0x8 |
| 195 | #define MDP_BLUR 0x10 |
| 196 | #define MDP_BLEND_FG_PREMULT 0x20000 |
Padmanabhan Komanduru | dd10bf1 | 2012-10-17 20:27:33 +0530 | [diff] [blame] | 197 | #define MDP_IS_FG 0x40000 |
Mayank Chopra | 1d91e09 | 2013-12-19 10:46:04 +0530 | [diff] [blame] | 198 | #define MDP_SOLID_FILL 0x00000020 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 199 | #define MDP_DEINTERLACE 0x80000000 |
| 200 | #define MDP_SHARPENING 0x40000000 |
| 201 | #define MDP_NO_DMA_BARRIER_START 0x20000000 |
| 202 | #define MDP_NO_DMA_BARRIER_END 0x10000000 |
| 203 | #define MDP_NO_BLIT 0x08000000 |
| 204 | #define MDP_BLIT_WITH_DMA_BARRIERS 0x000 |
| 205 | #define MDP_BLIT_WITH_NO_DMA_BARRIERS \ |
| 206 | (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) |
| 207 | #define MDP_BLIT_SRC_GEM 0x04000000 |
| 208 | #define MDP_BLIT_DST_GEM 0x02000000 |
| 209 | #define MDP_BLIT_NON_CACHED 0x01000000 |
| 210 | #define MDP_OV_PIPE_SHARE 0x00800000 |
| 211 | #define MDP_DEINTERLACE_ODD 0x00400000 |
| 212 | #define MDP_OV_PLAY_NOWAIT 0x00200000 |
| 213 | #define MDP_SOURCE_ROTATED_90 0x00100000 |
Carl Vanderlip | dfe5751 | 2012-07-23 12:34:47 -0700 | [diff] [blame] | 214 | #define MDP_OVERLAY_PP_CFG_EN 0x00080000 |
Ajay Singh Parmar | 4c7ccb3 | 2012-02-21 12:56:04 +0530 | [diff] [blame] | 215 | #define MDP_BACKEND_COMPOSITION 0x00040000 |
Nagamalleswararao Ganji | 880f847 | 2011-12-14 03:52:28 -0800 | [diff] [blame] | 216 | #define MDP_BORDERFILL_SUPPORTED 0x00010000 |
| 217 | #define MDP_SECURE_OVERLAY_SESSION 0x00008000 |
Arun Kumar K.R | 9ce1fd6 | 2013-09-24 11:35:08 -0700 | [diff] [blame] | 218 | #define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 |
Adrian Salido-Moreno | 9a8485c | 2013-02-06 14:08:28 -0800 | [diff] [blame] | 219 | #define MDP_OV_PIPE_FORCE_DMA 0x00004000 |
Nagamalleswararao Ganji | 880f847 | 2011-12-14 03:52:28 -0800 | [diff] [blame] | 220 | #define MDP_MEMORY_ID_TYPE_FB 0x00001000 |
Sree Sesha Aravind Vadrevu | 3514313 | 2013-03-12 02:32:06 -0700 | [diff] [blame] | 221 | #define MDP_BWC_EN 0x00000400 |
Sree Sesha Aravind Vadrevu | 05d4d22 | 2013-04-01 14:31:28 -0700 | [diff] [blame] | 222 | #define MDP_DECIMATION_EN 0x00000800 |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 223 | #define MDP_TRANSP_NOP 0xffffffff |
| 224 | #define MDP_ALPHA_NOP 0xff |
| 225 | |
| 226 | #define MDP_FB_PAGE_PROTECTION_NONCACHED (0) |
| 227 | #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) |
| 228 | #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) |
| 229 | #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) |
| 230 | #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) |
| 231 | /* Sentinel: Don't use! */ |
| 232 | #define MDP_FB_PAGE_PROTECTION_INVALID (5) |
| 233 | /* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */ |
| 234 | #define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) |
Daniel Walker | da6df07 | 2010-04-23 16:04:20 -0700 | [diff] [blame] | 235 | |
| 236 | struct mdp_rect { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 237 | uint32_t x; |
| 238 | uint32_t y; |
| 239 | uint32_t w; |
| 240 | uint32_t h; |
Daniel Walker | da6df07 | 2010-04-23 16:04:20 -0700 | [diff] [blame] | 241 | }; |
| 242 | |
| 243 | struct mdp_img { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 244 | uint32_t width; |
| 245 | uint32_t height; |
| 246 | uint32_t format; |
| 247 | uint32_t offset; |
Daniel Walker | da6df07 | 2010-04-23 16:04:20 -0700 | [diff] [blame] | 248 | int memory_id; /* the file descriptor */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 249 | uint32_t priv; |
Daniel Walker | da6df07 | 2010-04-23 16:04:20 -0700 | [diff] [blame] | 250 | }; |
| 251 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 252 | /* |
| 253 | * {3x3} + {3} ccs matrix |
| 254 | */ |
| 255 | |
| 256 | #define MDP_CCS_RGB2YUV 0 |
| 257 | #define MDP_CCS_YUV2RGB 1 |
| 258 | |
| 259 | #define MDP_CCS_SIZE 9 |
| 260 | #define MDP_BV_SIZE 3 |
| 261 | |
| 262 | struct mdp_ccs { |
| 263 | int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */ |
| 264 | uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */ |
| 265 | uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */ |
| 266 | }; |
| 267 | |
Nagamalleswararao Ganji | 4b99172 | 2011-01-28 13:24:34 -0800 | [diff] [blame] | 268 | struct mdp_csc { |
| 269 | int id; |
| 270 | uint32_t csc_mv[9]; |
| 271 | uint32_t csc_pre_bv[3]; |
| 272 | uint32_t csc_post_bv[3]; |
| 273 | uint32_t csc_pre_lv[6]; |
| 274 | uint32_t csc_post_lv[6]; |
| 275 | }; |
| 276 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 277 | /* The version of the mdp_blit_req structure so that |
| 278 | * user applications can selectively decide which functionality |
| 279 | * to include |
| 280 | */ |
| 281 | |
| 282 | #define MDP_BLIT_REQ_VERSION 2 |
| 283 | |
Shivaraj Shetty | 1bbb383 | 2013-10-22 18:43:17 +0530 | [diff] [blame] | 284 | struct color { |
| 285 | uint32_t r; |
| 286 | uint32_t g; |
| 287 | uint32_t b; |
| 288 | uint32_t alpha; |
| 289 | }; |
| 290 | |
Daniel Walker | da6df07 | 2010-04-23 16:04:20 -0700 | [diff] [blame] | 291 | struct mdp_blit_req { |
| 292 | struct mdp_img src; |
| 293 | struct mdp_img dst; |
| 294 | struct mdp_rect src_rect; |
| 295 | struct mdp_rect dst_rect; |
Shivaraj Shetty | 1bbb383 | 2013-10-22 18:43:17 +0530 | [diff] [blame] | 296 | struct color const_color; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 297 | uint32_t alpha; |
| 298 | uint32_t transp_mask; |
| 299 | uint32_t flags; |
| 300 | int sharpening_strength; /* -127 <--> 127, default 64 */ |
Daniel Walker | da6df07 | 2010-04-23 16:04:20 -0700 | [diff] [blame] | 301 | }; |
| 302 | |
| 303 | struct mdp_blit_req_list { |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 304 | uint32_t count; |
Daniel Walker | da6df07 | 2010-04-23 16:04:20 -0700 | [diff] [blame] | 305 | struct mdp_blit_req req[]; |
| 306 | }; |
| 307 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 308 | #define MSMFB_DATA_VERSION 2 |
| 309 | |
| 310 | struct msmfb_data { |
| 311 | uint32_t offset; |
| 312 | int memory_id; |
| 313 | int id; |
| 314 | uint32_t flags; |
| 315 | uint32_t priv; |
Vinay Kalia | e1ba270 | 2011-12-21 16:24:52 -0800 | [diff] [blame] | 316 | uint32_t iova; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 317 | }; |
| 318 | |
| 319 | #define MSMFB_NEW_REQUEST -1 |
| 320 | |
| 321 | struct msmfb_overlay_data { |
| 322 | uint32_t id; |
| 323 | struct msmfb_data data; |
| 324 | uint32_t version_key; |
| 325 | struct msmfb_data plane1_data; |
| 326 | struct msmfb_data plane2_data; |
Adrian Salido-Moreno | 1857f06 | 2012-05-29 17:57:28 -0700 | [diff] [blame] | 327 | struct msmfb_data dst_data; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 328 | }; |
| 329 | |
| 330 | struct msmfb_img { |
| 331 | uint32_t width; |
| 332 | uint32_t height; |
| 333 | uint32_t format; |
| 334 | }; |
| 335 | |
Vinay Kalia | 27020d1 | 2011-10-14 17:50:29 -0700 | [diff] [blame] | 336 | #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 |
| 337 | struct msmfb_writeback_data { |
| 338 | struct msmfb_data buf_info; |
| 339 | struct msmfb_img img; |
| 340 | }; |
| 341 | |
Ken Zhang | 77ce019 | 2012-08-10 11:27:19 -0400 | [diff] [blame] | 342 | #define MDP_PP_OPS_ENABLE 0x1 |
Carl Vanderlip | dfe5751 | 2012-07-23 12:34:47 -0700 | [diff] [blame] | 343 | #define MDP_PP_OPS_READ 0x2 |
| 344 | #define MDP_PP_OPS_WRITE 0x4 |
Ken Zhang | 77ce019 | 2012-08-10 11:27:19 -0400 | [diff] [blame] | 345 | #define MDP_PP_OPS_DISABLE 0x8 |
Ken Zhang | 824758e | 2012-08-15 11:02:21 -0400 | [diff] [blame] | 346 | #define MDP_PP_IGC_FLAG_ROM0 0x10 |
| 347 | #define MDP_PP_IGC_FLAG_ROM1 0x20 |
Carl Vanderlip | dfe5751 | 2012-07-23 12:34:47 -0700 | [diff] [blame] | 348 | |
Benet Clark | 477baa0 | 2013-10-04 17:21:45 -0700 | [diff] [blame] | 349 | #define MDP_PP_PA_HUE_ENABLE 0x10 |
| 350 | #define MDP_PP_PA_SAT_ENABLE 0x20 |
| 351 | #define MDP_PP_PA_VAL_ENABLE 0x40 |
| 352 | #define MDP_PP_PA_CONT_ENABLE 0x80 |
| 353 | #define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 |
| 354 | #define MDP_PP_PA_SKIN_ENABLE 0x200 |
| 355 | #define MDP_PP_PA_SKY_ENABLE 0x400 |
| 356 | #define MDP_PP_PA_FOL_ENABLE 0x800 |
| 357 | #define MDP_PP_PA_HUE_MASK 0x1000 |
| 358 | #define MDP_PP_PA_SAT_MASK 0x2000 |
| 359 | #define MDP_PP_PA_VAL_MASK 0x4000 |
| 360 | #define MDP_PP_PA_CONT_MASK 0x8000 |
| 361 | #define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 |
| 362 | #define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 |
| 363 | #define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 |
| 364 | #define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 |
| 365 | #define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 |
| 366 | #define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 |
| 367 | #define MDP_PP_PA_MEM_PROTECT_EN 0x400000 |
| 368 | #define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 |
| 369 | |
Carl Vanderlip | bf16fdf6 | 2013-03-11 13:45:45 -0700 | [diff] [blame] | 370 | #define MDSS_PP_DSPP_CFG 0x000 |
| 371 | #define MDSS_PP_SSPP_CFG 0x100 |
| 372 | #define MDSS_PP_LM_CFG 0x200 |
| 373 | #define MDSS_PP_WB_CFG 0x300 |
Ping Li | 8231ae4 | 2013-01-09 20:39:25 -0500 | [diff] [blame] | 374 | |
Carl Vanderlip | bf16fdf6 | 2013-03-11 13:45:45 -0700 | [diff] [blame] | 375 | #define MDSS_PP_ARG_MASK 0x3C00 |
| 376 | #define MDSS_PP_ARG_NUM 4 |
Carl Vanderlip | 793aa58 | 2013-03-18 10:18:47 -0700 | [diff] [blame] | 377 | #define MDSS_PP_ARG_SHIFT 10 |
Carl Vanderlip | bf16fdf6 | 2013-03-11 13:45:45 -0700 | [diff] [blame] | 378 | #define MDSS_PP_LOCATION_MASK 0x0300 |
| 379 | #define MDSS_PP_LOGICAL_MASK 0x00FF |
Ping Li | 8231ae4 | 2013-01-09 20:39:25 -0500 | [diff] [blame] | 380 | |
Carl Vanderlip | bf16fdf6 | 2013-03-11 13:45:45 -0700 | [diff] [blame] | 381 | #define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) |
| 382 | #define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) |
Ping Li | 8231ae4 | 2013-01-09 20:39:25 -0500 | [diff] [blame] | 383 | #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) |
| 384 | #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) |
| 385 | |
| 386 | |
Carl Vanderlip | dfe5751 | 2012-07-23 12:34:47 -0700 | [diff] [blame] | 387 | struct mdp_qseed_cfg { |
| 388 | uint32_t table_num; |
| 389 | uint32_t ops; |
| 390 | uint32_t len; |
| 391 | uint32_t *data; |
| 392 | }; |
| 393 | |
Ping Li | 87cca83 | 2013-01-30 18:27:52 -0500 | [diff] [blame] | 394 | struct mdp_sharp_cfg { |
| 395 | uint32_t flags; |
| 396 | uint32_t strength; |
| 397 | uint32_t edge_thr; |
| 398 | uint32_t smooth_thr; |
| 399 | uint32_t noise_thr; |
| 400 | }; |
| 401 | |
Carl Vanderlip | dfe5751 | 2012-07-23 12:34:47 -0700 | [diff] [blame] | 402 | struct mdp_qseed_cfg_data { |
| 403 | uint32_t block; |
| 404 | struct mdp_qseed_cfg qseed_data; |
| 405 | }; |
| 406 | |
Carl Vanderlip | 94d9b78 | 2013-01-16 12:13:52 -0800 | [diff] [blame] | 407 | #define MDP_OVERLAY_PP_CSC_CFG 0x1 |
| 408 | #define MDP_OVERLAY_PP_QSEED_CFG 0x2 |
| 409 | #define MDP_OVERLAY_PP_PA_CFG 0x4 |
| 410 | #define MDP_OVERLAY_PP_IGC_CFG 0x8 |
Ping Li | 87cca83 | 2013-01-30 18:27:52 -0500 | [diff] [blame] | 411 | #define MDP_OVERLAY_PP_SHARP_CFG 0x10 |
Carl Vanderlip | bf16fdf6 | 2013-03-11 13:45:45 -0700 | [diff] [blame] | 412 | #define MDP_OVERLAY_PP_HIST_CFG 0x20 |
Carl Vanderlip | 5702713 | 2013-03-18 13:53:16 -0700 | [diff] [blame] | 413 | #define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 |
Benet Clark | 477baa0 | 2013-10-04 17:21:45 -0700 | [diff] [blame] | 414 | #define MDP_OVERLAY_PP_PA_V2_CFG 0x80 |
Carl Vanderlip | dfe5751 | 2012-07-23 12:34:47 -0700 | [diff] [blame] | 415 | |
| 416 | #define MDP_CSC_FLAG_ENABLE 0x1 |
| 417 | #define MDP_CSC_FLAG_YUV_IN 0x2 |
| 418 | #define MDP_CSC_FLAG_YUV_OUT 0x4 |
| 419 | |
| 420 | struct mdp_csc_cfg { |
| 421 | /* flags for enable CSC, toggling RGB,YUV input/output */ |
| 422 | uint32_t flags; |
| 423 | uint32_t csc_mv[9]; |
| 424 | uint32_t csc_pre_bv[3]; |
| 425 | uint32_t csc_post_bv[3]; |
| 426 | uint32_t csc_pre_lv[6]; |
| 427 | uint32_t csc_post_lv[6]; |
| 428 | }; |
| 429 | |
| 430 | struct mdp_csc_cfg_data { |
| 431 | uint32_t block; |
| 432 | struct mdp_csc_cfg csc_data; |
| 433 | }; |
| 434 | |
Ping Li | 5822924 | 2012-11-30 14:05:43 -0500 | [diff] [blame] | 435 | struct mdp_pa_cfg { |
| 436 | uint32_t flags; |
| 437 | uint32_t hue_adj; |
| 438 | uint32_t sat_adj; |
| 439 | uint32_t val_adj; |
| 440 | uint32_t cont_adj; |
| 441 | }; |
| 442 | |
Benet Clark | 477baa0 | 2013-10-04 17:21:45 -0700 | [diff] [blame] | 443 | struct mdp_pa_mem_col_cfg { |
| 444 | uint32_t color_adjust_p0; |
| 445 | uint32_t color_adjust_p1; |
| 446 | uint32_t hue_region; |
| 447 | uint32_t sat_region; |
| 448 | uint32_t val_region; |
| 449 | }; |
| 450 | |
Benet Clark | 93577da | 2013-11-19 17:17:01 -0800 | [diff] [blame] | 451 | #define MDP_SIX_ZONE_LUT_SIZE 384 |
Carl Vanderlip | 4ac3a13 | 2013-11-19 16:52:52 -0800 | [diff] [blame] | 452 | |
Benet Clark | 477baa0 | 2013-10-04 17:21:45 -0700 | [diff] [blame] | 453 | struct mdp_pa_v2_data { |
| 454 | /* Mask bits for PA features */ |
| 455 | uint32_t flags; |
| 456 | uint32_t global_hue_adj; |
| 457 | uint32_t global_sat_adj; |
| 458 | uint32_t global_val_adj; |
| 459 | uint32_t global_cont_adj; |
| 460 | struct mdp_pa_mem_col_cfg skin_cfg; |
| 461 | struct mdp_pa_mem_col_cfg sky_cfg; |
| 462 | struct mdp_pa_mem_col_cfg fol_cfg; |
Benet Clark | 6695511 | 2013-12-04 12:52:22 -0800 | [diff] [blame] | 463 | uint32_t six_zone_len; |
| 464 | uint32_t six_zone_thresh; |
| 465 | uint32_t *six_zone_curve_p0; |
| 466 | uint32_t *six_zone_curve_p1; |
Benet Clark | 477baa0 | 2013-10-04 17:21:45 -0700 | [diff] [blame] | 467 | }; |
| 468 | |
Carl Vanderlip | 94d9b78 | 2013-01-16 12:13:52 -0800 | [diff] [blame] | 469 | struct mdp_igc_lut_data { |
| 470 | uint32_t block; |
| 471 | uint32_t len, ops; |
| 472 | uint32_t *c0_c1_data; |
| 473 | uint32_t *c2_data; |
| 474 | }; |
| 475 | |
Carl Vanderlip | bf16fdf6 | 2013-03-11 13:45:45 -0700 | [diff] [blame] | 476 | struct mdp_histogram_cfg { |
| 477 | uint32_t ops; |
| 478 | uint32_t block; |
| 479 | uint8_t frame_cnt; |
| 480 | uint8_t bit_mask; |
| 481 | uint16_t num_bins; |
| 482 | }; |
| 483 | |
Carl Vanderlip | 5702713 | 2013-03-18 13:53:16 -0700 | [diff] [blame] | 484 | struct mdp_hist_lut_data { |
| 485 | uint32_t block; |
| 486 | uint32_t ops; |
| 487 | uint32_t len; |
| 488 | uint32_t *data; |
| 489 | }; |
| 490 | |
Carl Vanderlip | dfe5751 | 2012-07-23 12:34:47 -0700 | [diff] [blame] | 491 | struct mdp_overlay_pp_params { |
| 492 | uint32_t config_ops; |
| 493 | struct mdp_csc_cfg csc_cfg; |
| 494 | struct mdp_qseed_cfg qseed_cfg[2]; |
Ping Li | 5822924 | 2012-11-30 14:05:43 -0500 | [diff] [blame] | 495 | struct mdp_pa_cfg pa_cfg; |
Benet Clark | 477baa0 | 2013-10-04 17:21:45 -0700 | [diff] [blame] | 496 | struct mdp_pa_v2_data pa_v2_cfg; |
Carl Vanderlip | 94d9b78 | 2013-01-16 12:13:52 -0800 | [diff] [blame] | 497 | struct mdp_igc_lut_data igc_cfg; |
Ping Li | 87cca83 | 2013-01-30 18:27:52 -0500 | [diff] [blame] | 498 | struct mdp_sharp_cfg sharp_cfg; |
Carl Vanderlip | bf16fdf6 | 2013-03-11 13:45:45 -0700 | [diff] [blame] | 499 | struct mdp_histogram_cfg hist_cfg; |
Carl Vanderlip | 5702713 | 2013-03-18 13:53:16 -0700 | [diff] [blame] | 500 | struct mdp_hist_lut_data hist_lut_cfg; |
Carl Vanderlip | dfe5751 | 2012-07-23 12:34:47 -0700 | [diff] [blame] | 501 | }; |
| 502 | |
Mayank Chopra | 29c4ee5 | 2013-07-24 12:31:01 +0530 | [diff] [blame] | 503 | /** |
| 504 | * enum mdss_mdp_blend_op - Different blend operations set by userspace |
| 505 | * |
| 506 | * @BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. |
| 507 | * @BLEND_OP_OPAQUE: Apply a constant blend operation. The layer |
| 508 | * would appear opaque in case fg plane alpha is |
| 509 | * 0xff. |
| 510 | * @BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already has |
| 511 | * alpha pre-multiplication done. If fg plane alpha |
| 512 | * is less than 0xff, apply modulation as well. This |
| 513 | * operation is intended on layers having alpha |
| 514 | * channel. |
| 515 | * @BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not alpha |
| 516 | * pre-multiplied. Apply pre-multiplication. If fg |
| 517 | * plane alpha is less than 0xff, apply modulation as |
| 518 | * well. |
| 519 | * @BLEND_OP_MAX: Used to track maximum blend operation possible by |
| 520 | * mdp. |
| 521 | */ |
| 522 | enum mdss_mdp_blend_op { |
| 523 | BLEND_OP_NOT_DEFINED = 0, |
| 524 | BLEND_OP_OPAQUE, |
| 525 | BLEND_OP_PREMULTIPLIED, |
| 526 | BLEND_OP_COVERAGE, |
| 527 | BLEND_OP_MAX, |
| 528 | }; |
| 529 | |
Sree Sesha Aravind Vadrevu | 494961d | 2013-10-03 12:51:03 -0700 | [diff] [blame] | 530 | #define MAX_PLANES 4 |
| 531 | struct mdp_scale_data { |
| 532 | uint8_t enable_pxl_ext; |
| 533 | |
| 534 | int init_phase_x[MAX_PLANES]; |
| 535 | int phase_step_x[MAX_PLANES]; |
| 536 | int init_phase_y[MAX_PLANES]; |
| 537 | int phase_step_y[MAX_PLANES]; |
| 538 | |
| 539 | int num_ext_pxls_left[MAX_PLANES]; |
| 540 | int num_ext_pxls_right[MAX_PLANES]; |
| 541 | int num_ext_pxls_top[MAX_PLANES]; |
| 542 | int num_ext_pxls_btm[MAX_PLANES]; |
| 543 | |
| 544 | int left_ftch[MAX_PLANES]; |
| 545 | int left_rpt[MAX_PLANES]; |
| 546 | int right_ftch[MAX_PLANES]; |
| 547 | int right_rpt[MAX_PLANES]; |
| 548 | |
| 549 | int top_rpt[MAX_PLANES]; |
| 550 | int btm_rpt[MAX_PLANES]; |
| 551 | int top_ftch[MAX_PLANES]; |
| 552 | int btm_ftch[MAX_PLANES]; |
| 553 | |
| 554 | uint32_t roi_w[MAX_PLANES]; |
| 555 | }; |
| 556 | |
Adrian Salido-Moreno | f8da392 | 2013-07-03 15:19:25 -0700 | [diff] [blame] | 557 | /** |
Vineet Bajaj | 297ae49 | 2014-06-10 21:10:24 +0530 | [diff] [blame^] | 558 | * enum mdp_overlay_pipe_type - Different pipe type set by userspace |
| 559 | * |
| 560 | * @PIPE_TYPE_AUTO: Not specified, pipe will be selected according to flags. |
| 561 | * @PIPE_TYPE_VIG: VIG pipe. |
| 562 | * @PIPE_TYPE_RGB: RGB pipe. |
| 563 | * @PIPE_TYPE_DMA: DMA pipe. |
| 564 | * @PIPE_TYPE_MAX: Used to track maximum number of pipe type. |
| 565 | */ |
| 566 | enum mdp_overlay_pipe_type { |
| 567 | PIPE_TYPE_AUTO = 0, |
| 568 | PIPE_TYPE_VIG, |
| 569 | PIPE_TYPE_RGB, |
| 570 | PIPE_TYPE_DMA, |
| 571 | PIPE_TYPE_MAX, |
| 572 | }; |
| 573 | |
| 574 | /** |
Adrian Salido-Moreno | f8da392 | 2013-07-03 15:19:25 -0700 | [diff] [blame] | 575 | * struct mdp_overlay - overlay surface structure |
| 576 | * @src: Source image information (width, height, format). |
| 577 | * @src_rect: Source crop rectangle, portion of image that will be fetched. |
| 578 | * This should always be within boundaries of source image. |
| 579 | * @dst_rect: Destination rectangle, the position and size of image on screen. |
| 580 | * This should always be within panel boundaries. |
| 581 | * @z_order: Blending stage to occupy in display, if multiple layers are |
| 582 | * present, highest z_order usually means the top most visible |
| 583 | * layer. The range acceptable is from 0-3 to support blending |
| 584 | * up to 4 layers. |
| 585 | * @is_fg: This flag is used to disable blending of any layers with z_order |
| 586 | * less than this overlay. It means that any layers with z_order |
| 587 | * less than this layer will not be blended and will be replaced |
| 588 | * by the background border color. |
| 589 | * @alpha: Used to set plane opacity. The range can be from 0-255, where |
| 590 | * 0 means completely transparent and 255 means fully opaque. |
| 591 | * @transp_mask: Color used as color key for transparency. Any pixel in fetched |
| 592 | * image matching this color will be transparent when blending. |
| 593 | * The color should be in same format as the source image format. |
| 594 | * @flags: This is used to customize operation of overlay. See MDP flags |
| 595 | * for more information. |
Vineet Bajaj | 297ae49 | 2014-06-10 21:10:24 +0530 | [diff] [blame^] | 596 | * @pipe_type: Used to specify the type of overlay pipe. |
Adrian Salido-Moreno | f8da392 | 2013-07-03 15:19:25 -0700 | [diff] [blame] | 597 | * @user_data: DEPRECATED* Used to store user application specific information. |
Adrian Salido-Moreno | e21074d | 2013-07-03 15:41:33 -0700 | [diff] [blame] | 598 | * @bg_color: Solid color used to fill the overlay surface when no source |
| 599 | * buffer is provided. |
Adrian Salido-Moreno | f8da392 | 2013-07-03 15:19:25 -0700 | [diff] [blame] | 600 | * @horz_deci: Horizontal decimation value, this indicates the amount of pixels |
| 601 | * dropped for each pixel that is fetched from a line. The value |
| 602 | * given should be power of two of decimation amount. |
| 603 | * 0: no decimation |
| 604 | * 1: decimate by 2 (drop 1 pixel for each pixel fetched) |
| 605 | * 2: decimate by 4 (drop 3 pixels for each pixel fetched) |
| 606 | * 3: decimate by 8 (drop 7 pixels for each pixel fetched) |
| 607 | * 4: decimate by 16 (drop 15 pixels for each pixel fetched) |
| 608 | * @vert_deci: Vertical decimation value, this indicates the amount of lines |
| 609 | * dropped for each line that is fetched from overlay. The value |
| 610 | * given should be power of two of decimation amount. |
| 611 | * 0: no decimation |
| 612 | * 1: decimation by 2 (drop 1 line for each line fetched) |
| 613 | * 2: decimation by 4 (drop 3 lines for each line fetched) |
| 614 | * 3: decimation by 8 (drop 7 lines for each line fetched) |
| 615 | * 4: decimation by 16 (drop 15 lines for each line fetched) |
| 616 | * @overlay_pp_cfg: Overlay post processing configuration, for more information |
| 617 | * see struct mdp_overlay_pp_params. |
| 618 | */ |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 619 | struct mdp_overlay { |
| 620 | struct msmfb_img src; |
| 621 | struct mdp_rect src_rect; |
| 622 | struct mdp_rect dst_rect; |
| 623 | uint32_t z_order; /* stage number */ |
| 624 | uint32_t is_fg; /* control alpha & transp */ |
| 625 | uint32_t alpha; |
Mayank Chopra | 29c4ee5 | 2013-07-24 12:31:01 +0530 | [diff] [blame] | 626 | uint32_t blend_op; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 627 | uint32_t transp_mask; |
| 628 | uint32_t flags; |
Vineet Bajaj | 297ae49 | 2014-06-10 21:10:24 +0530 | [diff] [blame^] | 629 | uint32_t pipe_type; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 630 | uint32_t id; |
Adrian Salido-Moreno | e21074d | 2013-07-03 15:41:33 -0700 | [diff] [blame] | 631 | uint32_t user_data[6]; |
| 632 | uint32_t bg_color; |
Sree Sesha Aravind Vadrevu | 05d4d22 | 2013-04-01 14:31:28 -0700 | [diff] [blame] | 633 | uint8_t horz_deci; |
| 634 | uint8_t vert_deci; |
Carl Vanderlip | dfe5751 | 2012-07-23 12:34:47 -0700 | [diff] [blame] | 635 | struct mdp_overlay_pp_params overlay_pp_cfg; |
Sree Sesha Aravind Vadrevu | 494961d | 2013-10-03 12:51:03 -0700 | [diff] [blame] | 636 | struct mdp_scale_data scale; |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 637 | }; |
| 638 | |
| 639 | struct msmfb_overlay_3d { |
| 640 | uint32_t is_3d; |
| 641 | uint32_t width; |
| 642 | uint32_t height; |
| 643 | }; |
| 644 | |
| 645 | |
| 646 | struct msmfb_overlay_blt { |
| 647 | uint32_t enable; |
| 648 | uint32_t offset; |
| 649 | uint32_t width; |
| 650 | uint32_t height; |
| 651 | uint32_t bpp; |
| 652 | }; |
| 653 | |
| 654 | struct mdp_histogram { |
| 655 | uint32_t frame_cnt; |
| 656 | uint32_t bin_cnt; |
| 657 | uint32_t *r; |
| 658 | uint32_t *g; |
| 659 | uint32_t *b; |
| 660 | }; |
| 661 | |
Mayank Chopra | 0a8c476 | 2013-07-12 18:19:36 +0530 | [diff] [blame] | 662 | #define MISR_CRC_BATCH_SIZE 32 |
Sree Sesha Aravind Vadrevu | 7bacaaa | 2013-03-20 11:50:25 -0700 | [diff] [blame] | 663 | enum { |
Mayank Chopra | 0a8c476 | 2013-07-12 18:19:36 +0530 | [diff] [blame] | 664 | DISPLAY_MISR_EDP = 0, |
Sree Sesha Aravind Vadrevu | 7bacaaa | 2013-03-20 11:50:25 -0700 | [diff] [blame] | 665 | DISPLAY_MISR_DSI0, |
| 666 | DISPLAY_MISR_DSI1, |
| 667 | DISPLAY_MISR_HDMI, |
| 668 | DISPLAY_MISR_LCDC, |
Mayank Chopra | 0a8c476 | 2013-07-12 18:19:36 +0530 | [diff] [blame] | 669 | DISPLAY_MISR_MDP, |
Sree Sesha Aravind Vadrevu | 7bacaaa | 2013-03-20 11:50:25 -0700 | [diff] [blame] | 670 | DISPLAY_MISR_ATV, |
| 671 | DISPLAY_MISR_DSI_CMD, |
| 672 | DISPLAY_MISR_MAX |
| 673 | }; |
| 674 | |
| 675 | enum { |
Mayank Chopra | 0a8c476 | 2013-07-12 18:19:36 +0530 | [diff] [blame] | 676 | MISR_OP_NONE = 0, |
Sree Sesha Aravind Vadrevu | 7bacaaa | 2013-03-20 11:50:25 -0700 | [diff] [blame] | 677 | MISR_OP_SFM, |
| 678 | MISR_OP_MFM, |
| 679 | MISR_OP_BM, |
| 680 | MISR_OP_MAX |
| 681 | }; |
| 682 | |
| 683 | struct mdp_misr { |
| 684 | uint32_t block_id; |
| 685 | uint32_t frame_count; |
| 686 | uint32_t crc_op_mode; |
Mayank Chopra | 0a8c476 | 2013-07-12 18:19:36 +0530 | [diff] [blame] | 687 | uint32_t crc_value[MISR_CRC_BATCH_SIZE]; |
Sree Sesha Aravind Vadrevu | 7bacaaa | 2013-03-20 11:50:25 -0700 | [diff] [blame] | 688 | }; |
Pravin Tamkhane | 02a4068 | 2011-11-29 14:17:01 -0800 | [diff] [blame] | 689 | |
| 690 | /* |
| 691 | |
Ken Zhang | 6a43163 | 2012-08-08 16:46:22 -0400 | [diff] [blame] | 692 | mdp_block_type defines the identifiers for pipes in MDP 4.3 and up |
Pravin Tamkhane | 02a4068 | 2011-11-29 14:17:01 -0800 | [diff] [blame] | 693 | |
| 694 | MDP_BLOCK_RESERVED is provided for backward compatibility and is |
| 695 | deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used |
| 696 | instead. |
| 697 | |
Ken Zhang | 6a43163 | 2012-08-08 16:46:22 -0400 | [diff] [blame] | 698 | MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses, |
| 699 | same for others. |
| 700 | |
Pravin Tamkhane | 02a4068 | 2011-11-29 14:17:01 -0800 | [diff] [blame] | 701 | */ |
| 702 | |
| 703 | enum { |
| 704 | MDP_BLOCK_RESERVED = 0, |
| 705 | MDP_BLOCK_OVERLAY_0, |
| 706 | MDP_BLOCK_OVERLAY_1, |
| 707 | MDP_BLOCK_VG_1, |
| 708 | MDP_BLOCK_VG_2, |
| 709 | MDP_BLOCK_RGB_1, |
| 710 | MDP_BLOCK_RGB_2, |
| 711 | MDP_BLOCK_DMA_P, |
| 712 | MDP_BLOCK_DMA_S, |
| 713 | MDP_BLOCK_DMA_E, |
Pravin Tamkhane | b18c9e2 | 2012-04-13 18:29:34 -0700 | [diff] [blame] | 714 | MDP_BLOCK_OVERLAY_2, |
Carl Vanderlip | bf16fdf6 | 2013-03-11 13:45:45 -0700 | [diff] [blame] | 715 | MDP_LOGICAL_BLOCK_DISP_0 = 0x10, |
Ken Zhang | 6a43163 | 2012-08-08 16:46:22 -0400 | [diff] [blame] | 716 | MDP_LOGICAL_BLOCK_DISP_1, |
| 717 | MDP_LOGICAL_BLOCK_DISP_2, |
Pravin Tamkhane | 02a4068 | 2011-11-29 14:17:01 -0800 | [diff] [blame] | 718 | MDP_BLOCK_MAX, |
| 719 | }; |
| 720 | |
Carl Vanderlip | ba093a2 | 2011-11-22 13:59:59 -0800 | [diff] [blame] | 721 | /* |
| 722 | * mdp_histogram_start_req is used to provide the parameters for |
| 723 | * histogram start request |
| 724 | */ |
| 725 | |
| 726 | struct mdp_histogram_start_req { |
| 727 | uint32_t block; |
| 728 | uint8_t frame_cnt; |
| 729 | uint8_t bit_mask; |
Carl Vanderlip | 1631632 | 2012-10-08 16:47:34 -0700 | [diff] [blame] | 730 | uint16_t num_bins; |
Carl Vanderlip | ba093a2 | 2011-11-22 13:59:59 -0800 | [diff] [blame] | 731 | }; |
| 732 | |
| 733 | /* |
| 734 | * mdp_histogram_data is used to return the histogram data, once |
| 735 | * the histogram is done/stopped/cance |
| 736 | */ |
| 737 | |
| 738 | struct mdp_histogram_data { |
| 739 | uint32_t block; |
Ken Zhang | 0f523bd | 2012-08-23 11:14:03 -0400 | [diff] [blame] | 740 | uint32_t bin_cnt; |
Carl Vanderlip | ba093a2 | 2011-11-22 13:59:59 -0800 | [diff] [blame] | 741 | uint32_t *c0; |
| 742 | uint32_t *c1; |
| 743 | uint32_t *c2; |
Carl Vanderlip | 7b8b640 | 2012-03-01 10:58:03 -0800 | [diff] [blame] | 744 | uint32_t *extra_info; |
Carl Vanderlip | ba093a2 | 2011-11-22 13:59:59 -0800 | [diff] [blame] | 745 | }; |
| 746 | |
Pravin Tamkhane | 02a4068 | 2011-11-29 14:17:01 -0800 | [diff] [blame] | 747 | struct mdp_pcc_coeff { |
| 748 | uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; |
| 749 | }; |
| 750 | |
| 751 | struct mdp_pcc_cfg_data { |
| 752 | uint32_t block; |
| 753 | uint32_t ops; |
| 754 | struct mdp_pcc_coeff r, g, b; |
| 755 | }; |
| 756 | |
Ken Zhang | bf5fb4c | 2012-08-19 14:41:01 -0400 | [diff] [blame] | 757 | #define MDP_GAMUT_TABLE_NUM 8 |
| 758 | |
Pravin Tamkhane | 02a4068 | 2011-11-29 14:17:01 -0800 | [diff] [blame] | 759 | enum { |
| 760 | mdp_lut_igc, |
| 761 | mdp_lut_pgc, |
| 762 | mdp_lut_hist, |
| 763 | mdp_lut_max, |
| 764 | }; |
| 765 | |
Pravin Tamkhane | 02a4068 | 2011-11-29 14:17:01 -0800 | [diff] [blame] | 766 | struct mdp_ar_gc_lut_data { |
| 767 | uint32_t x_start; |
| 768 | uint32_t slope; |
| 769 | uint32_t offset; |
| 770 | }; |
| 771 | |
| 772 | struct mdp_pgc_lut_data { |
| 773 | uint32_t block; |
| 774 | uint32_t flags; |
| 775 | uint8_t num_r_stages; |
| 776 | uint8_t num_g_stages; |
| 777 | uint8_t num_b_stages; |
| 778 | struct mdp_ar_gc_lut_data *r_data; |
| 779 | struct mdp_ar_gc_lut_data *g_data; |
| 780 | struct mdp_ar_gc_lut_data *b_data; |
| 781 | }; |
| 782 | |
| 783 | |
Pravin Tamkhane | 02a4068 | 2011-11-29 14:17:01 -0800 | [diff] [blame] | 784 | struct mdp_lut_cfg_data { |
| 785 | uint32_t lut_type; |
| 786 | union { |
| 787 | struct mdp_igc_lut_data igc_lut_data; |
| 788 | struct mdp_pgc_lut_data pgc_lut_data; |
| 789 | struct mdp_hist_lut_data hist_lut_data; |
| 790 | } data; |
| 791 | }; |
| 792 | |
Carl Vanderlip | f0fd8e7 | 2012-05-03 15:08:20 -0700 | [diff] [blame] | 793 | struct mdp_bl_scale_data { |
| 794 | uint32_t min_lvl; |
| 795 | uint32_t scale; |
| 796 | }; |
Pravin Tamkhane | 67726da | 2012-04-13 11:59:11 -0700 | [diff] [blame] | 797 | |
Ken Zhang | 77ce019 | 2012-08-10 11:27:19 -0400 | [diff] [blame] | 798 | struct mdp_pa_cfg_data { |
| 799 | uint32_t block; |
Ping Li | 5822924 | 2012-11-30 14:05:43 -0500 | [diff] [blame] | 800 | struct mdp_pa_cfg pa_data; |
Ken Zhang | 77ce019 | 2012-08-10 11:27:19 -0400 | [diff] [blame] | 801 | }; |
| 802 | |
Benet Clark | 477baa0 | 2013-10-04 17:21:45 -0700 | [diff] [blame] | 803 | struct mdp_pa_v2_cfg_data { |
| 804 | uint32_t block; |
| 805 | struct mdp_pa_v2_data pa_v2_data; |
| 806 | }; |
| 807 | |
Ken Zhang | 7fb8577 | 2012-08-18 14:51:33 -0400 | [diff] [blame] | 808 | struct mdp_dither_cfg_data { |
| 809 | uint32_t block; |
| 810 | uint32_t flags; |
| 811 | uint32_t g_y_depth; |
| 812 | uint32_t r_cr_depth; |
| 813 | uint32_t b_cb_depth; |
| 814 | }; |
| 815 | |
Ken Zhang | bf5fb4c | 2012-08-19 14:41:01 -0400 | [diff] [blame] | 816 | struct mdp_gamut_cfg_data { |
| 817 | uint32_t block; |
| 818 | uint32_t flags; |
| 819 | uint32_t gamut_first; |
| 820 | uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; |
| 821 | uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM]; |
| 822 | uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM]; |
| 823 | uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM]; |
| 824 | }; |
| 825 | |
Carl Vanderlip | e8ed5ec | 2012-09-28 16:04:10 -0700 | [diff] [blame] | 826 | struct mdp_calib_config_data { |
| 827 | uint32_t ops; |
| 828 | uint32_t addr; |
| 829 | uint32_t data; |
| 830 | }; |
| 831 | |
Arpita Banerjee | 676eea2 | 2013-06-04 19:43:24 -0700 | [diff] [blame] | 832 | struct mdp_calib_config_buffer { |
| 833 | uint32_t ops; |
| 834 | uint32_t size; |
| 835 | uint32_t *buffer; |
| 836 | }; |
| 837 | |
Arpita Banerjee | a8b7fbf | 2013-06-11 19:24:20 -0700 | [diff] [blame] | 838 | struct mdp_calib_dcm_state { |
| 839 | uint32_t ops; |
| 840 | uint32_t dcm_state; |
| 841 | }; |
| 842 | |
| 843 | enum { |
| 844 | DCM_UNINIT, |
| 845 | DCM_UNBLANK, |
| 846 | DCM_ENTER, |
| 847 | DCM_EXIT, |
| 848 | DCM_BLANK, |
Dhaval Patel | 3909053 | 2013-12-04 12:11:32 -0800 | [diff] [blame] | 849 | DTM_ENTER, |
| 850 | DTM_EXIT, |
Arpita Banerjee | a8b7fbf | 2013-06-11 19:24:20 -0700 | [diff] [blame] | 851 | }; |
| 852 | |
Carl Vanderlip | 45e042b | 2013-12-11 13:27:00 -0800 | [diff] [blame] | 853 | #define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 |
| 854 | #define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 |
| 855 | #define MDSS_PP_SPLIT_MASK 0x30000000 |
| 856 | |
Carl Vanderlip | e5592b6 | 2013-05-16 21:00:03 -0700 | [diff] [blame] | 857 | #define MDSS_MAX_BL_BRIGHTNESS 255 |
Benet Clark | c5982d5 | 2013-11-08 16:05:58 -0800 | [diff] [blame] | 858 | #define AD_BL_LIN_LEN 256 |
Ping Li | d69888a | 2014-01-22 16:55:35 -0800 | [diff] [blame] | 859 | #define AD_BL_ATT_LUT_LEN 33 |
Carl Vanderlip | e5592b6 | 2013-05-16 21:00:03 -0700 | [diff] [blame] | 860 | |
Carl Vanderlip | 8b493b0 | 2013-03-22 13:40:02 -0700 | [diff] [blame] | 861 | #define MDSS_AD_MODE_AUTO_BL 0x0 |
| 862 | #define MDSS_AD_MODE_AUTO_STR 0x1 |
| 863 | #define MDSS_AD_MODE_TARG_STR 0x3 |
| 864 | #define MDSS_AD_MODE_MAN_STR 0x7 |
Carl Vanderlip | 819c509 | 2013-05-19 12:08:33 -0700 | [diff] [blame] | 865 | #define MDSS_AD_MODE_CALIB 0xF |
Carl Vanderlip | 8b493b0 | 2013-03-22 13:40:02 -0700 | [diff] [blame] | 866 | |
| 867 | #define MDP_PP_AD_INIT 0x10 |
| 868 | #define MDP_PP_AD_CFG 0x20 |
| 869 | |
| 870 | struct mdss_ad_init { |
| 871 | uint32_t asym_lut[33]; |
| 872 | uint32_t color_corr_lut[33]; |
| 873 | uint8_t i_control[2]; |
| 874 | uint16_t black_lvl; |
| 875 | uint16_t white_lvl; |
| 876 | uint8_t var; |
| 877 | uint8_t limit_ampl; |
| 878 | uint8_t i_dither; |
| 879 | uint8_t slope_max; |
| 880 | uint8_t slope_min; |
| 881 | uint8_t dither_ctl; |
| 882 | uint8_t format; |
| 883 | uint8_t auto_size; |
| 884 | uint16_t frame_w; |
| 885 | uint16_t frame_h; |
| 886 | uint8_t logo_v; |
| 887 | uint8_t logo_h; |
Ping Li | d69888a | 2014-01-22 16:55:35 -0800 | [diff] [blame] | 888 | uint32_t alpha; |
| 889 | uint32_t alpha_base; |
Carl Vanderlip | e5592b6 | 2013-05-16 21:00:03 -0700 | [diff] [blame] | 890 | uint32_t bl_lin_len; |
Ping Li | d69888a | 2014-01-22 16:55:35 -0800 | [diff] [blame] | 891 | uint32_t bl_att_len; |
Carl Vanderlip | e5592b6 | 2013-05-16 21:00:03 -0700 | [diff] [blame] | 892 | uint32_t *bl_lin; |
| 893 | uint32_t *bl_lin_inv; |
Ping Li | d69888a | 2014-01-22 16:55:35 -0800 | [diff] [blame] | 894 | uint32_t *bl_att_lut; |
Carl Vanderlip | 8b493b0 | 2013-03-22 13:40:02 -0700 | [diff] [blame] | 895 | }; |
| 896 | |
Carl Vanderlip | 5e81ced | 2013-05-23 20:02:14 -0700 | [diff] [blame] | 897 | #define MDSS_AD_BL_CTRL_MODE_EN 1 |
| 898 | #define MDSS_AD_BL_CTRL_MODE_DIS 0 |
Carl Vanderlip | 8b493b0 | 2013-03-22 13:40:02 -0700 | [diff] [blame] | 899 | struct mdss_ad_cfg { |
| 900 | uint32_t mode; |
| 901 | uint32_t al_calib_lut[33]; |
| 902 | uint16_t backlight_min; |
| 903 | uint16_t backlight_max; |
| 904 | uint16_t backlight_scale; |
| 905 | uint16_t amb_light_min; |
| 906 | uint16_t filter[2]; |
| 907 | uint16_t calib[4]; |
| 908 | uint8_t strength_limit; |
| 909 | uint8_t t_filter_recursion; |
Carl Vanderlip | 956360e | 2013-04-04 20:57:17 -0700 | [diff] [blame] | 910 | uint16_t stab_itr; |
Carl Vanderlip | 5e81ced | 2013-05-23 20:02:14 -0700 | [diff] [blame] | 911 | uint32_t bl_ctrl_mode; |
Carl Vanderlip | 8b493b0 | 2013-03-22 13:40:02 -0700 | [diff] [blame] | 912 | }; |
| 913 | |
| 914 | /* ops uses standard MDP_PP_* flags */ |
| 915 | struct mdss_ad_init_cfg { |
| 916 | uint32_t ops; |
| 917 | union { |
| 918 | struct mdss_ad_init init; |
| 919 | struct mdss_ad_cfg cfg; |
| 920 | } params; |
| 921 | }; |
| 922 | |
| 923 | /* mode uses MDSS_AD_MODE_* flags */ |
| 924 | struct mdss_ad_input { |
| 925 | uint32_t mode; |
| 926 | union { |
| 927 | uint32_t amb_light; |
| 928 | uint32_t strength; |
Carl Vanderlip | 819c509 | 2013-05-19 12:08:33 -0700 | [diff] [blame] | 929 | uint32_t calib_bl; |
Carl Vanderlip | 8b493b0 | 2013-03-22 13:40:02 -0700 | [diff] [blame] | 930 | } in; |
Carl Vanderlip | 16e7953 | 2013-04-02 11:12:16 -0700 | [diff] [blame] | 931 | uint32_t output; |
Carl Vanderlip | 8b493b0 | 2013-03-22 13:40:02 -0700 | [diff] [blame] | 932 | }; |
| 933 | |
Carl Vanderlip | a088b7c | 2013-05-17 13:52:53 -0700 | [diff] [blame] | 934 | #define MDSS_CALIB_MODE_BL 0x1 |
Carl Vanderlip | 95a07e1 | 2013-05-17 13:51:38 -0700 | [diff] [blame] | 935 | struct mdss_calib_cfg { |
| 936 | uint32_t ops; |
| 937 | uint32_t calib_mask; |
| 938 | }; |
| 939 | |
Pravin Tamkhane | 02a4068 | 2011-11-29 14:17:01 -0800 | [diff] [blame] | 940 | enum { |
| 941 | mdp_op_pcc_cfg, |
| 942 | mdp_op_csc_cfg, |
| 943 | mdp_op_lut_cfg, |
Pravin Tamkhane | 67726da | 2012-04-13 11:59:11 -0700 | [diff] [blame] | 944 | mdp_op_qseed_cfg, |
Carl Vanderlip | f0fd8e7 | 2012-05-03 15:08:20 -0700 | [diff] [blame] | 945 | mdp_bl_scale_cfg, |
Ken Zhang | 77ce019 | 2012-08-10 11:27:19 -0400 | [diff] [blame] | 946 | mdp_op_pa_cfg, |
Benet Clark | 477baa0 | 2013-10-04 17:21:45 -0700 | [diff] [blame] | 947 | mdp_op_pa_v2_cfg, |
Ken Zhang | 7fb8577 | 2012-08-18 14:51:33 -0400 | [diff] [blame] | 948 | mdp_op_dither_cfg, |
Ken Zhang | bf5fb4c | 2012-08-19 14:41:01 -0400 | [diff] [blame] | 949 | mdp_op_gamut_cfg, |
Carl Vanderlip | e8ed5ec | 2012-09-28 16:04:10 -0700 | [diff] [blame] | 950 | mdp_op_calib_cfg, |
Carl Vanderlip | 8b493b0 | 2013-03-22 13:40:02 -0700 | [diff] [blame] | 951 | mdp_op_ad_cfg, |
| 952 | mdp_op_ad_input, |
Carl Vanderlip | 95a07e1 | 2013-05-17 13:51:38 -0700 | [diff] [blame] | 953 | mdp_op_calib_mode, |
Arpita Banerjee | 676eea2 | 2013-06-04 19:43:24 -0700 | [diff] [blame] | 954 | mdp_op_calib_buffer, |
Arpita Banerjee | a8b7fbf | 2013-06-11 19:24:20 -0700 | [diff] [blame] | 955 | mdp_op_calib_dcm_state, |
Pravin Tamkhane | 02a4068 | 2011-11-29 14:17:01 -0800 | [diff] [blame] | 956 | mdp_op_max, |
| 957 | }; |
| 958 | |
Pawan Kumar | 9807ea1 | 2013-02-14 18:12:02 +0530 | [diff] [blame] | 959 | enum { |
| 960 | WB_FORMAT_NV12, |
| 961 | WB_FORMAT_RGB_565, |
| 962 | WB_FORMAT_RGB_888, |
| 963 | WB_FORMAT_xRGB_8888, |
| 964 | WB_FORMAT_ARGB_8888, |
Pawan Kumar | ee81193 | 2013-07-09 15:45:01 +0530 | [diff] [blame] | 965 | WB_FORMAT_BGRA_8888, |
| 966 | WB_FORMAT_BGRX_8888, |
Pawan Kumar | 9807ea1 | 2013-02-14 18:12:02 +0530 | [diff] [blame] | 967 | WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */ |
| 968 | }; |
| 969 | |
Pravin Tamkhane | 02a4068 | 2011-11-29 14:17:01 -0800 | [diff] [blame] | 970 | struct msmfb_mdp_pp { |
| 971 | uint32_t op; |
| 972 | union { |
| 973 | struct mdp_pcc_cfg_data pcc_cfg_data; |
| 974 | struct mdp_csc_cfg_data csc_cfg_data; |
| 975 | struct mdp_lut_cfg_data lut_cfg_data; |
Pravin Tamkhane | 67726da | 2012-04-13 11:59:11 -0700 | [diff] [blame] | 976 | struct mdp_qseed_cfg_data qseed_cfg_data; |
Carl Vanderlip | f0fd8e7 | 2012-05-03 15:08:20 -0700 | [diff] [blame] | 977 | struct mdp_bl_scale_data bl_scale_data; |
Ken Zhang | 77ce019 | 2012-08-10 11:27:19 -0400 | [diff] [blame] | 978 | struct mdp_pa_cfg_data pa_cfg_data; |
Benet Clark | 477baa0 | 2013-10-04 17:21:45 -0700 | [diff] [blame] | 979 | struct mdp_pa_v2_cfg_data pa_v2_cfg_data; |
Ken Zhang | 7fb8577 | 2012-08-18 14:51:33 -0400 | [diff] [blame] | 980 | struct mdp_dither_cfg_data dither_cfg_data; |
Ken Zhang | bf5fb4c | 2012-08-19 14:41:01 -0400 | [diff] [blame] | 981 | struct mdp_gamut_cfg_data gamut_cfg_data; |
Carl Vanderlip | e8ed5ec | 2012-09-28 16:04:10 -0700 | [diff] [blame] | 982 | struct mdp_calib_config_data calib_cfg; |
Carl Vanderlip | 8b493b0 | 2013-03-22 13:40:02 -0700 | [diff] [blame] | 983 | struct mdss_ad_init_cfg ad_init_cfg; |
Carl Vanderlip | 95a07e1 | 2013-05-17 13:51:38 -0700 | [diff] [blame] | 984 | struct mdss_calib_cfg mdss_calib_cfg; |
Carl Vanderlip | 8b493b0 | 2013-03-22 13:40:02 -0700 | [diff] [blame] | 985 | struct mdss_ad_input ad_input; |
Arpita Banerjee | 676eea2 | 2013-06-04 19:43:24 -0700 | [diff] [blame] | 986 | struct mdp_calib_config_buffer calib_buffer; |
Arpita Banerjee | a8b7fbf | 2013-06-11 19:24:20 -0700 | [diff] [blame] | 987 | struct mdp_calib_dcm_state calib_dcm; |
Pravin Tamkhane | 02a4068 | 2011-11-29 14:17:01 -0800 | [diff] [blame] | 988 | } data; |
| 989 | }; |
| 990 | |
Manoj Rao | a8e39d9 | 2013-02-16 08:47:21 -0800 | [diff] [blame] | 991 | #define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 |
Ken Zhang | 5cf85c0 | 2012-08-23 19:32:52 -0700 | [diff] [blame] | 992 | enum { |
| 993 | metadata_op_none, |
| 994 | metadata_op_base_blend, |
Ken Zhang | 420dd20 | 2013-01-08 14:28:20 -0500 | [diff] [blame] | 995 | metadata_op_frame_rate, |
Manoj Rao | a8e39d9 | 2013-02-16 08:47:21 -0800 | [diff] [blame] | 996 | metadata_op_vic, |
Pawan Kumar | 9807ea1 | 2013-02-14 18:12:02 +0530 | [diff] [blame] | 997 | metadata_op_wb_format, |
Tatenda Chipeperekwa | 5dc8c48 | 2013-10-25 17:44:37 -0700 | [diff] [blame] | 998 | metadata_op_wb_secure, |
Adrian Salido-Moreno | 9bf71f3 | 2013-03-05 19:23:44 -0800 | [diff] [blame] | 999 | metadata_op_get_caps, |
Sree Sesha Aravind Vadrevu | 7bacaaa | 2013-03-20 11:50:25 -0700 | [diff] [blame] | 1000 | metadata_op_crc, |
Ken Zhang | 5cf85c0 | 2012-08-23 19:32:52 -0700 | [diff] [blame] | 1001 | metadata_op_max |
| 1002 | }; |
Pravin Tamkhane | 02a4068 | 2011-11-29 14:17:01 -0800 | [diff] [blame] | 1003 | |
Ken Zhang | 5cf85c0 | 2012-08-23 19:32:52 -0700 | [diff] [blame] | 1004 | struct mdp_blend_cfg { |
| 1005 | uint32_t is_premultiplied; |
| 1006 | }; |
| 1007 | |
Pawan Kumar | 9807ea1 | 2013-02-14 18:12:02 +0530 | [diff] [blame] | 1008 | struct mdp_mixer_cfg { |
| 1009 | uint32_t writeback_format; |
| 1010 | uint32_t alpha; |
| 1011 | }; |
| 1012 | |
Adrian Salido-Moreno | 9bf71f3 | 2013-03-05 19:23:44 -0800 | [diff] [blame] | 1013 | struct mdss_hw_caps { |
| 1014 | uint32_t mdp_rev; |
| 1015 | uint8_t rgb_pipes; |
| 1016 | uint8_t vig_pipes; |
| 1017 | uint8_t dma_pipes; |
Mayank Chopra | fc77ef1 | 2013-11-20 19:31:14 +0530 | [diff] [blame] | 1018 | uint8_t max_smp_cnt; |
| 1019 | uint8_t smp_per_pipe; |
Sree Sesha Aravind Vadrevu | 10c4d77 | 2013-03-28 13:11:12 -0700 | [diff] [blame] | 1020 | uint32_t features; |
Adrian Salido-Moreno | 9bf71f3 | 2013-03-05 19:23:44 -0800 | [diff] [blame] | 1021 | }; |
| 1022 | |
Ken Zhang | 5cf85c0 | 2012-08-23 19:32:52 -0700 | [diff] [blame] | 1023 | struct msmfb_metadata { |
| 1024 | uint32_t op; |
| 1025 | uint32_t flags; |
| 1026 | union { |
Sree Sesha Aravind Vadrevu | 7bacaaa | 2013-03-20 11:50:25 -0700 | [diff] [blame] | 1027 | struct mdp_misr misr_request; |
Ken Zhang | 5cf85c0 | 2012-08-23 19:32:52 -0700 | [diff] [blame] | 1028 | struct mdp_blend_cfg blend_cfg; |
Pawan Kumar | 9807ea1 | 2013-02-14 18:12:02 +0530 | [diff] [blame] | 1029 | struct mdp_mixer_cfg mixer_cfg; |
Ken Zhang | 420dd20 | 2013-01-08 14:28:20 -0500 | [diff] [blame] | 1030 | uint32_t panel_frame_rate; |
Manoj Rao | a8e39d9 | 2013-02-16 08:47:21 -0800 | [diff] [blame] | 1031 | uint32_t video_info_code; |
Adrian Salido-Moreno | 9bf71f3 | 2013-03-05 19:23:44 -0800 | [diff] [blame] | 1032 | struct mdss_hw_caps caps; |
Tatenda Chipeperekwa | 5dc8c48 | 2013-10-25 17:44:37 -0700 | [diff] [blame] | 1033 | uint8_t secure_en; |
Ken Zhang | 5cf85c0 | 2012-08-23 19:32:52 -0700 | [diff] [blame] | 1034 | } data; |
| 1035 | }; |
Ken Zhang | 5295d80 | 2012-11-07 18:33:16 -0500 | [diff] [blame] | 1036 | |
Adrian Salido-Moreno | 1a74a49 | 2013-05-11 21:24:43 -0700 | [diff] [blame] | 1037 | #define MDP_MAX_FENCE_FD 32 |
Ken Zhang | 5295d80 | 2012-11-07 18:33:16 -0500 | [diff] [blame] | 1038 | #define MDP_BUF_SYNC_FLAG_WAIT 1 |
Adrian Salido-Moreno | 1017e94 | 2014-01-10 15:39:49 -0800 | [diff] [blame] | 1039 | #define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 |
Ken Zhang | 5295d80 | 2012-11-07 18:33:16 -0500 | [diff] [blame] | 1040 | |
| 1041 | struct mdp_buf_sync { |
| 1042 | uint32_t flags; |
| 1043 | uint32_t acq_fen_fd_cnt; |
Jayant Shekhar | f399699 | 2013-08-22 14:28:10 +0530 | [diff] [blame] | 1044 | uint32_t session_id; |
Ken Zhang | 5295d80 | 2012-11-07 18:33:16 -0500 | [diff] [blame] | 1045 | int *acq_fen_fd; |
| 1046 | int *rel_fen_fd; |
Adrian Salido-Moreno | 1017e94 | 2014-01-10 15:39:49 -0800 | [diff] [blame] | 1047 | int *retire_fen_fd; |
Ken Zhang | 5295d80 | 2012-11-07 18:33:16 -0500 | [diff] [blame] | 1048 | }; |
| 1049 | |
Terence Hampson | 3e636aa | 2013-05-08 19:01:51 -0400 | [diff] [blame] | 1050 | struct mdp_async_blit_req_list { |
| 1051 | struct mdp_buf_sync sync; |
| 1052 | uint32_t count; |
| 1053 | struct mdp_blit_req req[]; |
| 1054 | }; |
| 1055 | |
Ken Zhang | 4e83b93 | 2012-12-02 21:15:47 -0500 | [diff] [blame] | 1056 | #define MDP_DISPLAY_COMMIT_OVERLAY 1 |
| 1057 | |
| 1058 | struct mdp_display_commit { |
| 1059 | uint32_t flags; |
| 1060 | uint32_t wait_for_finish; |
| 1061 | struct fb_var_screeninfo var; |
Jeykumar Sankaran | b826f33 | 2013-09-07 00:58:43 -0700 | [diff] [blame] | 1062 | struct mdp_rect roi; |
Ken Zhang | 4e83b93 | 2012-12-02 21:15:47 -0500 | [diff] [blame] | 1063 | }; |
| 1064 | |
Adrian Salido-Moreno | 6b15509 | 2014-01-07 17:29:20 -0800 | [diff] [blame] | 1065 | /** |
| 1066 | * struct mdp_overlay_list - argument for ioctl MSMFB_OVERLAY_PREPARE |
| 1067 | * @num_overlays: Number of overlay layers as part of the frame. |
| 1068 | * @overlay_list: Pointer to a list of overlay structures identifying |
| 1069 | * the layers as part of the frame |
| 1070 | * @flags: Flags can be used to extend behavior. |
| 1071 | * @processed_overlays: Output parameter indicating how many pipes were |
| 1072 | * successful. If there are no errors this number should |
| 1073 | * match num_overlays. Otherwise it will indicate the last |
| 1074 | * successful index for overlay that couldn't be set. |
| 1075 | */ |
| 1076 | struct mdp_overlay_list { |
| 1077 | uint32_t num_overlays; |
| 1078 | struct mdp_overlay **overlay_list; |
| 1079 | uint32_t flags; |
| 1080 | uint32_t processed_overlays; |
| 1081 | }; |
| 1082 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1083 | struct mdp_page_protection { |
| 1084 | uint32_t page_protection; |
| 1085 | }; |
| 1086 | |
kuogee hsieh | 405dc30 | 2011-07-21 15:06:59 -0700 | [diff] [blame] | 1087 | |
| 1088 | struct mdp_mixer_info { |
| 1089 | int pndx; |
| 1090 | int pnum; |
| 1091 | int ptype; |
| 1092 | int mixer_num; |
| 1093 | int z_order; |
| 1094 | }; |
| 1095 | |
| 1096 | #define MAX_PIPE_PER_MIXER 4 |
| 1097 | |
| 1098 | struct msmfb_mixer_info_req { |
| 1099 | int mixer_num; |
| 1100 | int cnt; |
| 1101 | struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; |
| 1102 | }; |
| 1103 | |
Ravishangar Kalyanam | 6bc448a | 2012-03-14 11:31:52 -0700 | [diff] [blame] | 1104 | enum { |
| 1105 | DISPLAY_SUBSYSTEM_ID, |
| 1106 | ROTATOR_SUBSYSTEM_ID, |
| 1107 | }; |
kuogee hsieh | 405dc30 | 2011-07-21 15:06:59 -0700 | [diff] [blame] | 1108 | |
Adrian Salido-Moreno | 96d88d4 | 2012-12-20 13:01:39 -0800 | [diff] [blame] | 1109 | enum { |
| 1110 | MDP_IOMMU_DOMAIN_CP, |
| 1111 | MDP_IOMMU_DOMAIN_NS, |
| 1112 | }; |
| 1113 | |
Deva Ramasubramanian | 166b098 | 2013-01-25 20:11:41 -0800 | [diff] [blame] | 1114 | enum { |
| 1115 | MDP_WRITEBACK_MIRROR_OFF, |
| 1116 | MDP_WRITEBACK_MIRROR_ON, |
| 1117 | MDP_WRITEBACK_MIRROR_PAUSE, |
| 1118 | MDP_WRITEBACK_MIRROR_RESUME, |
| 1119 | }; |
| 1120 | |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1121 | #ifdef __KERNEL__ |
Adrian Salido-Moreno | 96d88d4 | 2012-12-20 13:01:39 -0800 | [diff] [blame] | 1122 | int msm_fb_get_iommu_domain(struct fb_info *info, int domain); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1123 | /* get the framebuffer physical address information */ |
Ravishangar Kalyanam | 6bc448a | 2012-03-14 11:31:52 -0700 | [diff] [blame] | 1124 | int get_fb_phys_info(unsigned long *start, unsigned long *len, int fb_num, |
| 1125 | int subsys_id); |
Vinay Kalia | 27020d1 | 2011-10-14 17:50:29 -0700 | [diff] [blame] | 1126 | struct fb_info *msm_fb_get_writeback_fb(void); |
| 1127 | int msm_fb_writeback_init(struct fb_info *info); |
Vinay Kalia | e1ba270 | 2011-12-21 16:24:52 -0800 | [diff] [blame] | 1128 | int msm_fb_writeback_start(struct fb_info *info); |
Vinay Kalia | 27020d1 | 2011-10-14 17:50:29 -0700 | [diff] [blame] | 1129 | int msm_fb_writeback_queue_buffer(struct fb_info *info, |
| 1130 | struct msmfb_data *data); |
| 1131 | int msm_fb_writeback_dequeue_buffer(struct fb_info *info, |
| 1132 | struct msmfb_data *data); |
Vinay Kalia | e1ba270 | 2011-12-21 16:24:52 -0800 | [diff] [blame] | 1133 | int msm_fb_writeback_stop(struct fb_info *info); |
Vinay Kalia | 27020d1 | 2011-10-14 17:50:29 -0700 | [diff] [blame] | 1134 | int msm_fb_writeback_terminate(struct fb_info *info); |
Adrian Salido-Moreno | 96d88d4 | 2012-12-20 13:01:39 -0800 | [diff] [blame] | 1135 | int msm_fb_writeback_set_secure(struct fb_info *info, int enable); |
Pawan Kumar | ce25d14 | 2014-01-29 16:47:35 +0530 | [diff] [blame] | 1136 | int msm_fb_writeback_iommu_ref(struct fb_info *info, int enable); |
Bryan Huntsman | 3f2bc4d | 2011-08-16 17:27:22 -0700 | [diff] [blame] | 1137 | #endif |
| 1138 | |
| 1139 | #endif /*_MSM_MDP_H_*/ |