Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 2 | * ata_piix.c - Intel PATA/SATA controllers |
| 3 | * |
| 4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
| 5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
| 6 | * on emails. |
| 7 | * |
| 8 | * |
| 9 | * Copyright 2003-2005 Red Hat Inc |
| 10 | * Copyright 2003-2005 Jeff Garzik |
| 11 | * |
| 12 | * |
| 13 | * Copyright header from piix.c: |
| 14 | * |
| 15 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer |
| 16 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> |
| 17 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> |
| 18 | * |
| 19 | * |
| 20 | * This program is free software; you can redistribute it and/or modify |
| 21 | * it under the terms of the GNU General Public License as published by |
| 22 | * the Free Software Foundation; either version 2, or (at your option) |
| 23 | * any later version. |
| 24 | * |
| 25 | * This program is distributed in the hope that it will be useful, |
| 26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 28 | * GNU General Public License for more details. |
| 29 | * |
| 30 | * You should have received a copy of the GNU General Public License |
| 31 | * along with this program; see the file COPYING. If not, write to |
| 32 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
| 33 | * |
| 34 | * |
| 35 | * libata documentation is available via 'make {ps|pdf}docs', |
| 36 | * as Documentation/DocBook/libata.* |
| 37 | * |
| 38 | * Hardware documentation available at http://developer.intel.com/ |
| 39 | * |
Alan Cox | d96212e | 2005-12-08 19:19:50 +0000 | [diff] [blame] | 40 | * Documentation |
| 41 | * Publically available from Intel web site. Errata documentation |
| 42 | * is also publically available. As an aide to anyone hacking on this |
| 43 | * driver the list of errata that are relevant is below.going back to |
| 44 | * PIIX4. Older device documentation is now a bit tricky to find. |
| 45 | * |
| 46 | * The chipsets all follow very much the same design. The orginal Triton |
| 47 | * series chipsets do _not_ support independant device timings, but this |
| 48 | * is fixed in Triton II. With the odd mobile exception the chips then |
| 49 | * change little except in gaining more modes until SATA arrives. This |
| 50 | * driver supports only the chips with independant timing (that is those |
| 51 | * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix |
| 52 | * for the early chip drivers. |
| 53 | * |
| 54 | * Errata of note: |
| 55 | * |
| 56 | * Unfixable |
| 57 | * PIIX4 errata #9 - Only on ultra obscure hw |
| 58 | * ICH3 errata #13 - Not observed to affect real hw |
| 59 | * by Intel |
| 60 | * |
| 61 | * Things we must deal with |
| 62 | * PIIX4 errata #10 - BM IDE hang with non UDMA |
| 63 | * (must stop/start dma to recover) |
| 64 | * 440MX errata #15 - As PIIX4 errata #10 |
| 65 | * PIIX4 errata #15 - Must not read control registers |
| 66 | * during a PIO transfer |
| 67 | * 440MX errata #13 - As PIIX4 errata #15 |
| 68 | * ICH2 errata #21 - DMA mode 0 doesn't work right |
| 69 | * ICH0/1 errata #55 - As ICH2 errata #21 |
| 70 | * ICH2 spec c #9 - Extra operations needed to handle |
| 71 | * drive hotswap [NOT YET SUPPORTED] |
| 72 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary |
| 73 | * and must be dword aligned |
| 74 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 |
| 75 | * |
| 76 | * Should have been BIOS fixed: |
| 77 | * 450NX: errata #19 - DMA hangs on old 450NX |
| 78 | * 450NX: errata #20 - DMA hangs on old 450NX |
| 79 | * 450NX: errata #25 - Corruption with DMA on old 450NX |
| 80 | * ICH3 errata #15 - IDE deadlock under high load |
| 81 | * (BIOS must set dev 31 fn 0 bit 23) |
| 82 | * ICH3 errata #18 - Don't use native mode |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | */ |
| 84 | |
| 85 | #include <linux/kernel.h> |
| 86 | #include <linux/module.h> |
| 87 | #include <linux/pci.h> |
| 88 | #include <linux/init.h> |
| 89 | #include <linux/blkdev.h> |
| 90 | #include <linux/delay.h> |
Jeff Garzik | 6248e64 | 2005-10-30 06:42:18 -0500 | [diff] [blame] | 91 | #include <linux/device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | #include <scsi/scsi_host.h> |
| 93 | #include <linux/libata.h> |
| 94 | |
| 95 | #define DRV_NAME "ata_piix" |
Jeff Garzik | 8676ce0 | 2006-06-26 20:41:33 -0400 | [diff] [blame] | 96 | #define DRV_VERSION "2.00" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 97 | |
| 98 | enum { |
| 99 | PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ |
| 100 | ICH5_PMR = 0x90, /* port mapping register */ |
| 101 | ICH5_PCS = 0x92, /* port control and status */ |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 102 | PIIX_SCC = 0x0A, /* sub-class code register */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | |
Tejun Heo | 219e621 | 2006-03-05 14:28:51 +0900 | [diff] [blame] | 104 | PIIX_FLAG_IGNORE_PCS = (1 << 25), /* ignore PCS present bits */ |
Tejun Heo | d435804 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 105 | PIIX_FLAG_SCR = (1 << 26), /* SCR available */ |
Tejun Heo | ff0fc14 | 2005-12-18 17:17:07 +0900 | [diff] [blame] | 106 | PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */ |
| 107 | PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 108 | |
| 109 | /* combined mode. if set, PATA is channel 0. |
| 110 | * if clear, PATA is channel 1. |
| 111 | */ |
Hannes Reinecke | 6a690df | 2005-06-28 17:30:38 -0700 | [diff] [blame] | 112 | PIIX_PORT_ENABLED = (1 << 0), |
| 113 | PIIX_PORT_PRESENT = (1 << 4), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 114 | |
| 115 | PIIX_80C_PRI = (1 << 5) | (1 << 4), |
| 116 | PIIX_80C_SEC = (1 << 7) | (1 << 6), |
| 117 | |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 118 | /* controller IDs */ |
| 119 | piix4_pata = 0, |
| 120 | ich5_pata = 1, |
| 121 | ich5_sata = 2, |
| 122 | esb_sata = 3, |
| 123 | ich6_sata = 4, |
| 124 | ich6_sata_ahci = 5, |
| 125 | ich6m_sata_ahci = 6, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 126 | ich8_sata_ahci = 7, |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 127 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 128 | /* constants for mapping table */ |
| 129 | P0 = 0, /* port 0 */ |
| 130 | P1 = 1, /* port 1 */ |
| 131 | P2 = 2, /* port 2 */ |
| 132 | P3 = 3, /* port 3 */ |
| 133 | IDE = -1, /* IDE */ |
| 134 | NA = -2, /* not avaliable */ |
| 135 | RV = -3, /* reserved */ |
| 136 | |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 137 | PIIX_AHCI_DEVICE = 6, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 138 | }; |
| 139 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 140 | struct piix_map_db { |
| 141 | const u32 mask; |
Jeff Garzik | 73291a1 | 2006-07-11 13:11:17 -0400 | [diff] [blame] | 142 | const u16 port_enable; |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 143 | const int present_shift; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 144 | const int map[][4]; |
| 145 | }; |
| 146 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 147 | struct piix_host_priv { |
| 148 | const int *map; |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 149 | const struct piix_map_db *map_db; |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 150 | }; |
| 151 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 152 | static int piix_init_one (struct pci_dev *pdev, |
| 153 | const struct pci_device_id *ent); |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 154 | static void piix_host_stop(struct ata_host_set *host_set); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 155 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev); |
| 156 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev); |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 157 | static void piix_pata_error_handler(struct ata_port *ap); |
| 158 | static void piix_sata_error_handler(struct ata_port *ap); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 159 | |
| 160 | static unsigned int in_module_init = 1; |
| 161 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 162 | static const struct pci_device_id piix_pci_tbl[] = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 163 | #ifdef ATA_ENABLE_PATA |
| 164 | { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata }, |
| 165 | { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata }, |
| 166 | { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata }, |
Thomas Glanzmann | b74ba22 | 2006-05-12 10:00:41 +0200 | [diff] [blame] | 167 | { 0x8086, 0x27df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 168 | #endif |
| 169 | |
| 170 | /* NOTE: The following PCI ids must be kept in sync with the |
| 171 | * list in drivers/pci/quirks.c. |
| 172 | */ |
| 173 | |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 174 | /* 82801EB (ICH5) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 175 | { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 176 | /* 82801EB (ICH5) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 177 | { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 178 | /* 6300ESB (ICH5 variant with broken PCS present bits) */ |
| 179 | { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata }, |
| 180 | /* 6300ESB pretending RAID */ |
| 181 | { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata }, |
| 182 | /* 82801FB/FW (ICH6/ICH6W) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 183 | { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 184 | /* 82801FR/FRW (ICH6R/ICH6RW) */ |
Jeff Garzik | 1c24a41 | 2005-11-14 18:20:23 -0500 | [diff] [blame] | 185 | { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 186 | /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */ |
| 187 | { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, |
| 188 | /* 82801GB/GR/GH (ICH7, identical to ICH6) */ |
Jeff Garzik | 1c24a41 | 2005-11-14 18:20:23 -0500 | [diff] [blame] | 189 | { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 190 | /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ |
| 191 | { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, |
| 192 | /* Enterprise Southbridge 2 (where's the datasheet?) */ |
Jeff Garzik | 1c24a41 | 2005-11-14 18:20:23 -0500 | [diff] [blame] | 193 | { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 194 | /* SATA Controller 1 IDE (ICH8, no datasheet yet) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 195 | { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 196 | /* SATA Controller 2 IDE (ICH8, ditto) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 197 | { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 198 | /* Mobile SATA Controller IDE (ICH8M, ditto) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 199 | { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 200 | |
| 201 | { } /* terminate list */ |
| 202 | }; |
| 203 | |
| 204 | static struct pci_driver piix_pci_driver = { |
| 205 | .name = DRV_NAME, |
| 206 | .id_table = piix_pci_tbl, |
| 207 | .probe = piix_init_one, |
| 208 | .remove = ata_pci_remove_one, |
Jens Axboe | 9b84754 | 2006-01-06 09:28:07 +0100 | [diff] [blame] | 209 | .suspend = ata_pci_device_suspend, |
| 210 | .resume = ata_pci_device_resume, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 211 | }; |
| 212 | |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 213 | static struct scsi_host_template piix_sht = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 214 | .module = THIS_MODULE, |
| 215 | .name = DRV_NAME, |
| 216 | .ioctl = ata_scsi_ioctl, |
| 217 | .queuecommand = ata_scsi_queuecmd, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 218 | .can_queue = ATA_DEF_QUEUE, |
| 219 | .this_id = ATA_SHT_THIS_ID, |
| 220 | .sg_tablesize = LIBATA_MAX_PRD, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 221 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 222 | .emulated = ATA_SHT_EMULATED, |
| 223 | .use_clustering = ATA_SHT_USE_CLUSTERING, |
| 224 | .proc_name = DRV_NAME, |
| 225 | .dma_boundary = ATA_DMA_BOUNDARY, |
| 226 | .slave_configure = ata_scsi_slave_config, |
Tejun Heo | ccf68c3 | 2006-05-31 18:28:09 +0900 | [diff] [blame] | 227 | .slave_destroy = ata_scsi_slave_destroy, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 228 | .bios_param = ata_std_bios_param, |
Jens Axboe | 9b84754 | 2006-01-06 09:28:07 +0100 | [diff] [blame] | 229 | .resume = ata_scsi_device_resume, |
| 230 | .suspend = ata_scsi_device_suspend, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 231 | }; |
| 232 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 233 | static const struct ata_port_operations piix_pata_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 234 | .port_disable = ata_port_disable, |
| 235 | .set_piomode = piix_set_piomode, |
| 236 | .set_dmamode = piix_set_dmamode, |
Albert Lee | 89bad58 | 2006-05-26 13:49:18 +0800 | [diff] [blame] | 237 | .mode_filter = ata_pci_default_filter, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 238 | |
| 239 | .tf_load = ata_tf_load, |
| 240 | .tf_read = ata_tf_read, |
| 241 | .check_status = ata_check_status, |
| 242 | .exec_command = ata_exec_command, |
| 243 | .dev_select = ata_std_dev_select, |
| 244 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | .bmdma_setup = ata_bmdma_setup, |
| 246 | .bmdma_start = ata_bmdma_start, |
| 247 | .bmdma_stop = ata_bmdma_stop, |
| 248 | .bmdma_status = ata_bmdma_status, |
| 249 | .qc_prep = ata_qc_prep, |
| 250 | .qc_issue = ata_qc_issue_prot, |
Albert Lee | 89bad58 | 2006-05-26 13:49:18 +0800 | [diff] [blame] | 251 | .data_xfer = ata_pio_data_xfer, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 252 | |
Tejun Heo | 3f037db | 2006-05-15 20:58:25 +0900 | [diff] [blame] | 253 | .freeze = ata_bmdma_freeze, |
| 254 | .thaw = ata_bmdma_thaw, |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 255 | .error_handler = piix_pata_error_handler, |
Tejun Heo | 3f037db | 2006-05-15 20:58:25 +0900 | [diff] [blame] | 256 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 257 | |
| 258 | .irq_handler = ata_interrupt, |
| 259 | .irq_clear = ata_bmdma_irq_clear, |
| 260 | |
| 261 | .port_start = ata_port_start, |
| 262 | .port_stop = ata_port_stop, |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 263 | .host_stop = piix_host_stop, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 264 | }; |
| 265 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 266 | static const struct ata_port_operations piix_sata_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 267 | .port_disable = ata_port_disable, |
| 268 | |
| 269 | .tf_load = ata_tf_load, |
| 270 | .tf_read = ata_tf_read, |
| 271 | .check_status = ata_check_status, |
| 272 | .exec_command = ata_exec_command, |
| 273 | .dev_select = ata_std_dev_select, |
| 274 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 275 | .bmdma_setup = ata_bmdma_setup, |
| 276 | .bmdma_start = ata_bmdma_start, |
| 277 | .bmdma_stop = ata_bmdma_stop, |
| 278 | .bmdma_status = ata_bmdma_status, |
| 279 | .qc_prep = ata_qc_prep, |
| 280 | .qc_issue = ata_qc_issue_prot, |
Albert Lee | 89bad58 | 2006-05-26 13:49:18 +0800 | [diff] [blame] | 281 | .data_xfer = ata_pio_data_xfer, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 282 | |
Tejun Heo | 3f037db | 2006-05-15 20:58:25 +0900 | [diff] [blame] | 283 | .freeze = ata_bmdma_freeze, |
| 284 | .thaw = ata_bmdma_thaw, |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 285 | .error_handler = piix_sata_error_handler, |
Tejun Heo | 3f037db | 2006-05-15 20:58:25 +0900 | [diff] [blame] | 286 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 287 | |
| 288 | .irq_handler = ata_interrupt, |
| 289 | .irq_clear = ata_bmdma_irq_clear, |
| 290 | |
| 291 | .port_start = ata_port_start, |
| 292 | .port_stop = ata_port_stop, |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 293 | .host_stop = piix_host_stop, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 294 | }; |
| 295 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 296 | static const struct piix_map_db ich5_map_db = { |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 297 | .mask = 0x7, |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 298 | .port_enable = 0x3, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 299 | .present_shift = 4, |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 300 | .map = { |
| 301 | /* PM PS SM SS MAP */ |
| 302 | { P0, NA, P1, NA }, /* 000b */ |
| 303 | { P1, NA, P0, NA }, /* 001b */ |
| 304 | { RV, RV, RV, RV }, |
| 305 | { RV, RV, RV, RV }, |
| 306 | { P0, P1, IDE, IDE }, /* 100b */ |
| 307 | { P1, P0, IDE, IDE }, /* 101b */ |
| 308 | { IDE, IDE, P0, P1 }, /* 110b */ |
| 309 | { IDE, IDE, P1, P0 }, /* 111b */ |
| 310 | }, |
| 311 | }; |
| 312 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 313 | static const struct piix_map_db ich6_map_db = { |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 314 | .mask = 0x3, |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 315 | .port_enable = 0xf, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 316 | .present_shift = 4, |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 317 | .map = { |
| 318 | /* PM PS SM SS MAP */ |
Tejun Heo | 79ea24e | 2006-03-31 20:01:50 +0900 | [diff] [blame] | 319 | { P0, P2, P1, P3 }, /* 00b */ |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 320 | { IDE, IDE, P1, P3 }, /* 01b */ |
| 321 | { P0, P2, IDE, IDE }, /* 10b */ |
| 322 | { RV, RV, RV, RV }, |
| 323 | }, |
| 324 | }; |
| 325 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 326 | static const struct piix_map_db ich6m_map_db = { |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 327 | .mask = 0x3, |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 328 | .port_enable = 0x5, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 329 | .present_shift = 4, |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 330 | .map = { |
| 331 | /* PM PS SM SS MAP */ |
Tejun Heo | 79ea24e | 2006-03-31 20:01:50 +0900 | [diff] [blame] | 332 | { P0, P2, RV, RV }, /* 00b */ |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 333 | { RV, RV, RV, RV }, |
| 334 | { P0, P2, IDE, IDE }, /* 10b */ |
| 335 | { RV, RV, RV, RV }, |
| 336 | }, |
| 337 | }; |
| 338 | |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 339 | static const struct piix_map_db ich8_map_db = { |
| 340 | .mask = 0x3, |
| 341 | .port_enable = 0x3, |
| 342 | .present_shift = 8, |
| 343 | .map = { |
| 344 | /* PM PS SM SS MAP */ |
Jeff Garzik | f5beec4 | 2006-07-11 15:28:12 -0400 | [diff] [blame] | 345 | { P0, NA, P1, NA }, /* 00b (hardwired) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 346 | { RV, RV, RV, RV }, |
| 347 | { RV, RV, RV, RV }, /* 10b (never) */ |
| 348 | { RV, RV, RV, RV }, |
| 349 | }, |
| 350 | }; |
| 351 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 352 | static const struct piix_map_db *piix_map_db_table[] = { |
| 353 | [ich5_sata] = &ich5_map_db, |
| 354 | [esb_sata] = &ich5_map_db, |
| 355 | [ich6_sata] = &ich6_map_db, |
| 356 | [ich6_sata_ahci] = &ich6_map_db, |
| 357 | [ich6m_sata_ahci] = &ich6m_map_db, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 358 | [ich8_sata_ahci] = &ich8_map_db, |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 359 | }; |
| 360 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 361 | static struct ata_port_info piix_port_info[] = { |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 362 | /* piix4_pata */ |
| 363 | { |
| 364 | .sht = &piix_sht, |
| 365 | .host_flags = ATA_FLAG_SLAVE_POSS, |
| 366 | .pio_mask = 0x1f, /* pio0-4 */ |
| 367 | #if 0 |
| 368 | .mwdma_mask = 0x06, /* mwdma1-2 */ |
| 369 | #else |
| 370 | .mwdma_mask = 0x00, /* mwdma broken */ |
| 371 | #endif |
| 372 | .udma_mask = ATA_UDMA_MASK_40C, |
| 373 | .port_ops = &piix_pata_ops, |
| 374 | }, |
| 375 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 376 | /* ich5_pata */ |
| 377 | { |
| 378 | .sht = &piix_sht, |
Tejun Heo | 573db6b | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 379 | .host_flags = ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 380 | .pio_mask = 0x1f, /* pio0-4 */ |
| 381 | #if 0 |
| 382 | .mwdma_mask = 0x06, /* mwdma1-2 */ |
| 383 | #else |
| 384 | .mwdma_mask = 0x00, /* mwdma broken */ |
| 385 | #endif |
| 386 | .udma_mask = 0x3f, /* udma0-5 */ |
| 387 | .port_ops = &piix_pata_ops, |
| 388 | }, |
| 389 | |
| 390 | /* ich5_sata */ |
| 391 | { |
| 392 | .sht = &piix_sht, |
Jeff Garzik | 73291a1 | 2006-07-11 13:11:17 -0400 | [diff] [blame] | 393 | .host_flags = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 394 | .pio_mask = 0x1f, /* pio0-4 */ |
| 395 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 396 | .udma_mask = 0x7f, /* udma0-6 */ |
| 397 | .port_ops = &piix_sata_ops, |
| 398 | }, |
| 399 | |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 400 | /* i6300esb_sata */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 401 | { |
| 402 | .sht = &piix_sht, |
Jeff Garzik | 73291a1 | 2006-07-11 13:11:17 -0400 | [diff] [blame] | 403 | .host_flags = ATA_FLAG_SATA | |
Tejun Heo | 219e621 | 2006-03-05 14:28:51 +0900 | [diff] [blame] | 404 | PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGNORE_PCS, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 405 | .pio_mask = 0x1f, /* pio0-4 */ |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 406 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 407 | .udma_mask = 0x7f, /* udma0-6 */ |
| 408 | .port_ops = &piix_sata_ops, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 409 | }, |
| 410 | |
| 411 | /* ich6_sata */ |
| 412 | { |
| 413 | .sht = &piix_sht, |
Jeff Garzik | 73291a1 | 2006-07-11 13:11:17 -0400 | [diff] [blame] | 414 | .host_flags = ATA_FLAG_SATA | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 415 | PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 416 | .pio_mask = 0x1f, /* pio0-4 */ |
| 417 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 418 | .udma_mask = 0x7f, /* udma0-6 */ |
| 419 | .port_ops = &piix_sata_ops, |
| 420 | }, |
| 421 | |
Jeff Garzik | 1c24a41 | 2005-11-14 18:20:23 -0500 | [diff] [blame] | 422 | /* ich6_sata_ahci */ |
Jason Gaston | c368ca4 | 2005-04-16 15:24:44 -0700 | [diff] [blame] | 423 | { |
| 424 | .sht = &piix_sht, |
Jeff Garzik | 73291a1 | 2006-07-11 13:11:17 -0400 | [diff] [blame] | 425 | .host_flags = ATA_FLAG_SATA | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 426 | PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR | |
| 427 | PIIX_FLAG_AHCI, |
Jason Gaston | c368ca4 | 2005-04-16 15:24:44 -0700 | [diff] [blame] | 428 | .pio_mask = 0x1f, /* pio0-4 */ |
| 429 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 430 | .udma_mask = 0x7f, /* udma0-6 */ |
| 431 | .port_ops = &piix_sata_ops, |
| 432 | }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 433 | |
| 434 | /* ich6m_sata_ahci */ |
| 435 | { |
| 436 | .sht = &piix_sht, |
Jeff Garzik | 73291a1 | 2006-07-11 13:11:17 -0400 | [diff] [blame] | 437 | .host_flags = ATA_FLAG_SATA | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 438 | PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR | |
| 439 | PIIX_FLAG_AHCI, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 440 | .pio_mask = 0x1f, /* pio0-4 */ |
| 441 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 442 | .udma_mask = 0x7f, /* udma0-6 */ |
| 443 | .port_ops = &piix_sata_ops, |
| 444 | }, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 445 | |
| 446 | /* ich8_sata_ahci */ |
| 447 | { |
| 448 | .sht = &piix_sht, |
Jeff Garzik | 73291a1 | 2006-07-11 13:11:17 -0400 | [diff] [blame] | 449 | .host_flags = ATA_FLAG_SATA | |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 450 | PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR | |
| 451 | PIIX_FLAG_AHCI, |
| 452 | .pio_mask = 0x1f, /* pio0-4 */ |
| 453 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 454 | .udma_mask = 0x7f, /* udma0-6 */ |
| 455 | .port_ops = &piix_sata_ops, |
| 456 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 457 | }; |
| 458 | |
| 459 | static struct pci_bits piix_enable_bits[] = { |
| 460 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ |
| 461 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ |
| 462 | }; |
| 463 | |
| 464 | MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); |
| 465 | MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); |
| 466 | MODULE_LICENSE("GPL"); |
| 467 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); |
| 468 | MODULE_VERSION(DRV_VERSION); |
| 469 | |
| 470 | /** |
| 471 | * piix_pata_cbl_detect - Probe host controller cable detect info |
| 472 | * @ap: Port for which cable detect info is desired |
| 473 | * |
| 474 | * Read 80c cable indicator from ATA PCI device's PCI config |
| 475 | * register. This register is normally set by firmware (BIOS). |
| 476 | * |
| 477 | * LOCKING: |
| 478 | * None (inherited from caller). |
| 479 | */ |
| 480 | static void piix_pata_cbl_detect(struct ata_port *ap) |
| 481 | { |
| 482 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); |
| 483 | u8 tmp, mask; |
| 484 | |
| 485 | /* no 80c support in host controller? */ |
| 486 | if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0) |
| 487 | goto cbl40; |
| 488 | |
| 489 | /* check BIOS cable detect results */ |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame^] | 490 | mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 491 | pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); |
| 492 | if ((tmp & mask) == 0) |
| 493 | goto cbl40; |
| 494 | |
| 495 | ap->cbl = ATA_CBL_PATA80; |
| 496 | return; |
| 497 | |
| 498 | cbl40: |
| 499 | ap->cbl = ATA_CBL_PATA40; |
| 500 | ap->udma_mask &= ATA_UDMA_MASK_40C; |
| 501 | } |
| 502 | |
| 503 | /** |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 504 | * piix_pata_prereset - prereset for PATA host controller |
Tejun Heo | 573db6b | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 505 | * @ap: Target port |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 506 | * |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 507 | * Prereset including cable detection. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 508 | * |
| 509 | * LOCKING: |
| 510 | * None (inherited from caller). |
| 511 | */ |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 512 | static int piix_pata_prereset(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 513 | { |
| 514 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); |
| 515 | |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame^] | 516 | if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) { |
Tejun Heo | f15a1da | 2006-05-15 20:57:56 +0900 | [diff] [blame] | 517 | ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n"); |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 518 | ap->eh_context.i.action &= ~ATA_EH_RESET_MASK; |
Tejun Heo | 573db6b | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 519 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 520 | } |
| 521 | |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 522 | piix_pata_cbl_detect(ap); |
| 523 | |
| 524 | return ata_std_prereset(ap); |
| 525 | } |
| 526 | |
| 527 | static void piix_pata_error_handler(struct ata_port *ap) |
| 528 | { |
| 529 | ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL, |
| 530 | ata_std_postreset); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 531 | } |
| 532 | |
| 533 | /** |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 534 | * piix_sata_prereset - prereset for SATA host controller |
| 535 | * @ap: Target port |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 536 | * |
Tejun Heo | d133eca | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 537 | * Reads and configures SATA PCI device's PCI config register |
| 538 | * Port Configuration and Status (PCS) to determine port and |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 539 | * device availability. Return -ENODEV to skip reset if no |
| 540 | * device is present. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 541 | * |
| 542 | * LOCKING: |
| 543 | * None (inherited from caller). |
| 544 | * |
| 545 | * RETURNS: |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 546 | * 0 if device is present, -ENODEV otherwise. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 547 | */ |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 548 | static int piix_sata_prereset(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 549 | { |
| 550 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 551 | struct piix_host_priv *hpriv = ap->host_set->private_data; |
| 552 | const unsigned int *map = hpriv->map; |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame^] | 553 | int base = 2 * ap->port_no; |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 554 | unsigned int present = 0; |
Tejun Heo | d133eca | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 555 | int port, i; |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 556 | u16 pcs; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 557 | |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 558 | pci_read_config_word(pdev, ICH5_PCS, &pcs); |
Tejun Heo | d133eca | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 559 | DPRINTK("ata%u: ENTER, pcs=0x%x base=%d\n", ap->id, pcs, base); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 560 | |
Tejun Heo | d133eca | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 561 | for (i = 0; i < 2; i++) { |
| 562 | port = map[base + i]; |
| 563 | if (port < 0) |
| 564 | continue; |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 565 | if ((ap->flags & PIIX_FLAG_IGNORE_PCS) || |
| 566 | (pcs & 1 << (hpriv->map_db->present_shift + port))) |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 567 | present = 1; |
Tejun Heo | d133eca | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 568 | } |
| 569 | |
Keith Owens | 85455dd | 2006-08-08 13:51:02 +1000 | [diff] [blame] | 570 | DPRINTK("ata%u: LEAVE, pcs=0x%x present=0x%x\n", |
| 571 | ap->id, pcs, present); |
Tejun Heo | d133eca | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 572 | |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 573 | if (!present) { |
Tejun Heo | f15a1da | 2006-05-15 20:57:56 +0900 | [diff] [blame] | 574 | ata_port_printk(ap, KERN_INFO, "SATA port has no device.\n"); |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 575 | ap->eh_context.i.action &= ~ATA_EH_RESET_MASK; |
Tejun Heo | ccbe6d5 | 2006-02-15 15:01:42 +0900 | [diff] [blame] | 576 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 577 | } |
| 578 | |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 579 | return ata_std_prereset(ap); |
| 580 | } |
| 581 | |
| 582 | static void piix_sata_error_handler(struct ata_port *ap) |
| 583 | { |
| 584 | ata_bmdma_drive_eh(ap, piix_sata_prereset, ata_std_softreset, NULL, |
| 585 | ata_std_postreset); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 586 | } |
| 587 | |
| 588 | /** |
| 589 | * piix_set_piomode - Initialize host controller PATA PIO timings |
| 590 | * @ap: Port whose timings we are configuring |
| 591 | * @adev: um |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 592 | * |
| 593 | * Set PIO mode for device, in host controller PCI config space. |
| 594 | * |
| 595 | * LOCKING: |
| 596 | * None (inherited from caller). |
| 597 | */ |
| 598 | |
| 599 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev) |
| 600 | { |
| 601 | unsigned int pio = adev->pio_mode - XFER_PIO_0; |
| 602 | struct pci_dev *dev = to_pci_dev(ap->host_set->dev); |
| 603 | unsigned int is_slave = (adev->devno != 0); |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame^] | 604 | unsigned int master_port= ap->port_no ? 0x42 : 0x40; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 605 | unsigned int slave_port = 0x44; |
| 606 | u16 master_data; |
| 607 | u8 slave_data; |
| 608 | |
| 609 | static const /* ISP RTC */ |
| 610 | u8 timings[][2] = { { 0, 0 }, |
| 611 | { 0, 0 }, |
| 612 | { 1, 0 }, |
| 613 | { 2, 1 }, |
| 614 | { 2, 3 }, }; |
| 615 | |
| 616 | pci_read_config_word(dev, master_port, &master_data); |
| 617 | if (is_slave) { |
| 618 | master_data |= 0x4000; |
| 619 | /* enable PPE, IE and TIME */ |
| 620 | master_data |= 0x0070; |
| 621 | pci_read_config_byte(dev, slave_port, &slave_data); |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame^] | 622 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 623 | slave_data |= |
| 624 | (timings[pio][0] << 2) | |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame^] | 625 | (timings[pio][1] << (ap->port_no ? 4 : 0)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 626 | } else { |
| 627 | master_data &= 0xccf8; |
| 628 | /* enable PPE, IE and TIME */ |
| 629 | master_data |= 0x0007; |
| 630 | master_data |= |
| 631 | (timings[pio][0] << 12) | |
| 632 | (timings[pio][1] << 8); |
| 633 | } |
| 634 | pci_write_config_word(dev, master_port, master_data); |
| 635 | if (is_slave) |
| 636 | pci_write_config_byte(dev, slave_port, slave_data); |
| 637 | } |
| 638 | |
| 639 | /** |
| 640 | * piix_set_dmamode - Initialize host controller PATA PIO timings |
| 641 | * @ap: Port whose timings we are configuring |
| 642 | * @adev: um |
| 643 | * @udma: udma mode, 0 - 6 |
| 644 | * |
| 645 | * Set UDMA mode for device, in host controller PCI config space. |
| 646 | * |
| 647 | * LOCKING: |
| 648 | * None (inherited from caller). |
| 649 | */ |
| 650 | |
| 651 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev) |
| 652 | { |
| 653 | unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */ |
| 654 | struct pci_dev *dev = to_pci_dev(ap->host_set->dev); |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame^] | 655 | u8 maslave = ap->port_no ? 0x42 : 0x40; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 656 | u8 speed = udma; |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame^] | 657 | unsigned int drive_dn = (ap->port_no ? 2 : 0) + adev->devno; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 658 | int a_speed = 3 << (drive_dn * 4); |
| 659 | int u_flag = 1 << drive_dn; |
| 660 | int v_flag = 0x01 << drive_dn; |
| 661 | int w_flag = 0x10 << drive_dn; |
| 662 | int u_speed = 0; |
| 663 | int sitre; |
| 664 | u16 reg4042, reg4a; |
| 665 | u8 reg48, reg54, reg55; |
| 666 | |
| 667 | pci_read_config_word(dev, maslave, ®4042); |
| 668 | DPRINTK("reg4042 = 0x%04x\n", reg4042); |
| 669 | sitre = (reg4042 & 0x4000) ? 1 : 0; |
| 670 | pci_read_config_byte(dev, 0x48, ®48); |
| 671 | pci_read_config_word(dev, 0x4a, ®4a); |
| 672 | pci_read_config_byte(dev, 0x54, ®54); |
| 673 | pci_read_config_byte(dev, 0x55, ®55); |
| 674 | |
| 675 | switch(speed) { |
| 676 | case XFER_UDMA_4: |
| 677 | case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break; |
| 678 | case XFER_UDMA_6: |
| 679 | case XFER_UDMA_5: |
| 680 | case XFER_UDMA_3: |
| 681 | case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break; |
| 682 | case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break; |
| 683 | case XFER_MW_DMA_2: |
| 684 | case XFER_MW_DMA_1: break; |
| 685 | default: |
| 686 | BUG(); |
| 687 | return; |
| 688 | } |
| 689 | |
| 690 | if (speed >= XFER_UDMA_0) { |
| 691 | if (!(reg48 & u_flag)) |
| 692 | pci_write_config_byte(dev, 0x48, reg48 | u_flag); |
| 693 | if (speed == XFER_UDMA_5) { |
| 694 | pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag); |
| 695 | } else { |
| 696 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); |
| 697 | } |
| 698 | if ((reg4a & a_speed) != u_speed) |
| 699 | pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed); |
| 700 | if (speed > XFER_UDMA_2) { |
| 701 | if (!(reg54 & v_flag)) |
| 702 | pci_write_config_byte(dev, 0x54, reg54 | v_flag); |
| 703 | } else |
| 704 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); |
| 705 | } else { |
| 706 | if (reg48 & u_flag) |
| 707 | pci_write_config_byte(dev, 0x48, reg48 & ~u_flag); |
| 708 | if (reg4a & a_speed) |
| 709 | pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); |
| 710 | if (reg54 & v_flag) |
| 711 | pci_write_config_byte(dev, 0x54, reg54 & ~v_flag); |
| 712 | if (reg55 & w_flag) |
| 713 | pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); |
| 714 | } |
| 715 | } |
| 716 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 717 | #define AHCI_PCI_BAR 5 |
| 718 | #define AHCI_GLOBAL_CTL 0x04 |
| 719 | #define AHCI_ENABLE (1 << 31) |
| 720 | static int piix_disable_ahci(struct pci_dev *pdev) |
| 721 | { |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 722 | void __iomem *mmio; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 723 | u32 tmp; |
| 724 | int rc = 0; |
| 725 | |
| 726 | /* BUG: pci_enable_device has not yet been called. This |
| 727 | * works because this device is usually set up by BIOS. |
| 728 | */ |
| 729 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 730 | if (!pci_resource_start(pdev, AHCI_PCI_BAR) || |
| 731 | !pci_resource_len(pdev, AHCI_PCI_BAR)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 732 | return 0; |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 733 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 734 | mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 735 | if (!mmio) |
| 736 | return -ENOMEM; |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 737 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 738 | tmp = readl(mmio + AHCI_GLOBAL_CTL); |
| 739 | if (tmp & AHCI_ENABLE) { |
| 740 | tmp &= ~AHCI_ENABLE; |
| 741 | writel(tmp, mmio + AHCI_GLOBAL_CTL); |
| 742 | |
| 743 | tmp = readl(mmio + AHCI_GLOBAL_CTL); |
| 744 | if (tmp & AHCI_ENABLE) |
| 745 | rc = -EIO; |
| 746 | } |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 747 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 748 | pci_iounmap(pdev, mmio); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 749 | return rc; |
| 750 | } |
| 751 | |
| 752 | /** |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 753 | * piix_check_450nx_errata - Check for problem 450NX setup |
Randy Dunlap | c893a3a | 2006-01-28 13:15:32 -0500 | [diff] [blame] | 754 | * @ata_dev: the PCI device to check |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 755 | * |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 756 | * Check for the present of 450NX errata #19 and errata #25. If |
| 757 | * they are found return an error code so we can turn off DMA |
| 758 | */ |
| 759 | |
| 760 | static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) |
| 761 | { |
| 762 | struct pci_dev *pdev = NULL; |
| 763 | u16 cfg; |
| 764 | u8 rev; |
| 765 | int no_piix_dma = 0; |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 766 | |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 767 | while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) |
| 768 | { |
| 769 | /* Look for 450NX PXB. Check for problem configurations |
| 770 | A PCI quirk checks bit 6 already */ |
| 771 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); |
| 772 | pci_read_config_word(pdev, 0x41, &cfg); |
| 773 | /* Only on the original revision: IDE DMA can hang */ |
Alan Cox | 31a34fe | 2006-05-22 22:58:14 +0100 | [diff] [blame] | 774 | if (rev == 0x00) |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 775 | no_piix_dma = 1; |
| 776 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ |
Alan Cox | 31a34fe | 2006-05-22 22:58:14 +0100 | [diff] [blame] | 777 | else if (cfg & (1<<14) && rev < 5) |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 778 | no_piix_dma = 2; |
| 779 | } |
Alan Cox | 31a34fe | 2006-05-22 22:58:14 +0100 | [diff] [blame] | 780 | if (no_piix_dma) |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 781 | dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); |
Alan Cox | 31a34fe | 2006-05-22 22:58:14 +0100 | [diff] [blame] | 782 | if (no_piix_dma == 2) |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 783 | dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); |
| 784 | return no_piix_dma; |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 785 | } |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 786 | |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 787 | static void __devinit piix_init_pcs(struct pci_dev *pdev, |
| 788 | const struct piix_map_db *map_db) |
| 789 | { |
| 790 | u16 pcs, new_pcs; |
| 791 | |
| 792 | pci_read_config_word(pdev, ICH5_PCS, &pcs); |
| 793 | |
| 794 | new_pcs = pcs | map_db->port_enable; |
| 795 | |
| 796 | if (new_pcs != pcs) { |
| 797 | DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); |
| 798 | pci_write_config_word(pdev, ICH5_PCS, new_pcs); |
| 799 | msleep(150); |
| 800 | } |
| 801 | } |
| 802 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 803 | static void __devinit piix_init_sata_map(struct pci_dev *pdev, |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 804 | struct ata_port_info *pinfo, |
| 805 | const struct piix_map_db *map_db) |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 806 | { |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 807 | struct piix_host_priv *hpriv = pinfo[0].private_data; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 808 | const unsigned int *map; |
| 809 | int i, invalid_map = 0; |
| 810 | u8 map_value; |
| 811 | |
| 812 | pci_read_config_byte(pdev, ICH5_PMR, &map_value); |
| 813 | |
| 814 | map = map_db->map[map_value & map_db->mask]; |
| 815 | |
| 816 | dev_printk(KERN_INFO, &pdev->dev, "MAP ["); |
| 817 | for (i = 0; i < 4; i++) { |
| 818 | switch (map[i]) { |
| 819 | case RV: |
| 820 | invalid_map = 1; |
| 821 | printk(" XX"); |
| 822 | break; |
| 823 | |
| 824 | case NA: |
| 825 | printk(" --"); |
| 826 | break; |
| 827 | |
| 828 | case IDE: |
| 829 | WARN_ON((i & 1) || map[i + 1] != IDE); |
| 830 | pinfo[i / 2] = piix_port_info[ich5_pata]; |
Tejun Heo | f814b75 | 2006-08-05 03:59:13 +0900 | [diff] [blame] | 831 | pinfo[i / 2].private_data = hpriv; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 832 | i++; |
| 833 | printk(" IDE IDE"); |
| 834 | break; |
| 835 | |
| 836 | default: |
| 837 | printk(" P%d", map[i]); |
| 838 | if (i & 1) |
| 839 | pinfo[i / 2].host_flags |= ATA_FLAG_SLAVE_POSS; |
| 840 | break; |
| 841 | } |
| 842 | } |
| 843 | printk(" ]\n"); |
| 844 | |
| 845 | if (invalid_map) |
| 846 | dev_printk(KERN_ERR, &pdev->dev, |
| 847 | "invalid MAP value %u\n", map_value); |
| 848 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 849 | hpriv->map = map; |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 850 | hpriv->map_db = map_db; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 851 | } |
| 852 | |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 853 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 854 | * piix_init_one - Register PIIX ATA PCI device with kernel services |
| 855 | * @pdev: PCI device to register |
| 856 | * @ent: Entry in piix_pci_tbl matching with @pdev |
| 857 | * |
| 858 | * Called from kernel PCI layer. We probe for combined mode (sigh), |
| 859 | * and then hand over control to libata, for it to do the rest. |
| 860 | * |
| 861 | * LOCKING: |
| 862 | * Inherited from PCI layer (may sleep). |
| 863 | * |
| 864 | * RETURNS: |
| 865 | * Zero on success, or -ERRNO value. |
| 866 | */ |
| 867 | |
| 868 | static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
| 869 | { |
| 870 | static int printed_version; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 871 | struct ata_port_info port_info[2]; |
| 872 | struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] }; |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 873 | struct piix_host_priv *hpriv; |
Tejun Heo | ff0fc14 | 2005-12-18 17:17:07 +0900 | [diff] [blame] | 874 | unsigned long host_flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 875 | |
| 876 | if (!printed_version++) |
Jeff Garzik | 6248e64 | 2005-10-30 06:42:18 -0500 | [diff] [blame] | 877 | dev_printk(KERN_DEBUG, &pdev->dev, |
| 878 | "version " DRV_VERSION "\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 879 | |
| 880 | /* no hotplugging support (FIXME) */ |
| 881 | if (!in_module_init) |
| 882 | return -ENODEV; |
| 883 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 884 | hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL); |
| 885 | if (!hpriv) |
| 886 | return -ENOMEM; |
| 887 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 888 | port_info[0] = piix_port_info[ent->driver_data]; |
| 889 | port_info[1] = piix_port_info[ent->driver_data]; |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 890 | port_info[0].private_data = hpriv; |
| 891 | port_info[1].private_data = hpriv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 892 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 893 | host_flags = port_info[0].host_flags; |
Tejun Heo | ff0fc14 | 2005-12-18 17:17:07 +0900 | [diff] [blame] | 894 | |
| 895 | if (host_flags & PIIX_FLAG_AHCI) { |
Jeff Garzik | 8a60a07 | 2005-07-31 13:13:24 -0400 | [diff] [blame] | 896 | u8 tmp; |
| 897 | pci_read_config_byte(pdev, PIIX_SCC, &tmp); |
| 898 | if (tmp == PIIX_AHCI_DEVICE) { |
| 899 | int rc = piix_disable_ahci(pdev); |
| 900 | if (rc) |
| 901 | return rc; |
| 902 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 903 | } |
| 904 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 905 | /* Initialize SATA map */ |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 906 | if (host_flags & ATA_FLAG_SATA) { |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 907 | piix_init_sata_map(pdev, port_info, |
| 908 | piix_map_db_table[ent->driver_data]); |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 909 | piix_init_pcs(pdev, piix_map_db_table[ent->driver_data]); |
| 910 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 911 | |
| 912 | /* On ICH5, some BIOSen disable the interrupt using the |
| 913 | * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. |
| 914 | * On ICH6, this bit has the same effect, but only when |
| 915 | * MSI is disabled (and it is disabled, as we don't use |
| 916 | * message-signalled interrupts currently). |
| 917 | */ |
Tejun Heo | ff0fc14 | 2005-12-18 17:17:07 +0900 | [diff] [blame] | 918 | if (host_flags & PIIX_FLAG_CHECKINTR) |
Brett M Russ | a04ce0f | 2005-08-15 15:23:41 -0400 | [diff] [blame] | 919 | pci_intx(pdev, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 920 | |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 921 | if (piix_check_450nx_errata(pdev)) { |
| 922 | /* This writes into the master table but it does not |
| 923 | really matter for this errata as we will apply it to |
| 924 | all the PIIX devices on the board */ |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 925 | port_info[0].mwdma_mask = 0; |
| 926 | port_info[0].udma_mask = 0; |
| 927 | port_info[1].mwdma_mask = 0; |
| 928 | port_info[1].udma_mask = 0; |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 929 | } |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 930 | return ata_pci_init_one(pdev, ppinfo, 2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 931 | } |
| 932 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 933 | static void piix_host_stop(struct ata_host_set *host_set) |
| 934 | { |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 935 | ata_host_stop(host_set); |
| 936 | } |
| 937 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 938 | static int __init piix_init(void) |
| 939 | { |
| 940 | int rc; |
| 941 | |
| 942 | DPRINTK("pci_module_init\n"); |
| 943 | rc = pci_module_init(&piix_pci_driver); |
| 944 | if (rc) |
| 945 | return rc; |
| 946 | |
| 947 | in_module_init = 0; |
| 948 | |
| 949 | DPRINTK("done\n"); |
| 950 | return 0; |
| 951 | } |
| 952 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 953 | static void __exit piix_exit(void) |
| 954 | { |
| 955 | pci_unregister_driver(&piix_pci_driver); |
| 956 | } |
| 957 | |
| 958 | module_init(piix_init); |
| 959 | module_exit(piix_exit); |
| 960 | |