Blame - drivers/gpu/drm/radeon/r600d.h - kernel/msm

2009-09-08 10:10:24 +1000

[diff] [blame]

/*

*

* Permission is hereby granted, free of charge, to any person obtaining a

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* copy of this software and associated documentation files (the "Software"),

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* to deal in the Software without restriction, including without limitation

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* the rights to use, copy, modify, merge, publish, distribute, sublicense,

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* and/or sell copies of the Software, and to permit persons to whom the

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* Software is furnished to do so, subject to the following conditions:

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*

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* The above copyright notice and this permission notice shall be included in

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* all copies or substantial portions of the Software.

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*

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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

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* OTHER DEALINGS IN THE SOFTWARE.

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*

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* Authors: Dave Airlie

* Alex Deucher

* Jerome Glisse

*/

#ifndef R600D_H

#define R600D_H

#define CP_PACKET2 0x80000000

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#define PACKET2_PAD_SHIFT 0

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#define PACKET2_PAD_MASK (0x3fffffff << 0)

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#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

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#define R6XX_MAX_SH_GPRS 256

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#define R6XX_MAX_TEMP_GPRS 16

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#define R6XX_MAX_SH_THREADS 256

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#define R6XX_MAX_SH_STACK_ENTRIES 4096

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#define R6XX_MAX_BACKENDS 8

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#define R6XX_MAX_BACKENDS_MASK 0xff

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#define R6XX_MAX_SIMDS 8

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#define R6XX_MAX_SIMDS_MASK 0xff

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#define R6XX_MAX_PIPES 8

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#define R6XX_MAX_PIPES_MASK 0xff

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/* PTE flags */

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#define PTE_VALID (1 << 0)

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#define PTE_SYSTEM (1 << 1)

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#define PTE_SNOOPED (1 << 2)

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#define PTE_READABLE (1 << 5)

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#define PTE_WRITEABLE (1 << 6)

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/* tiling bits */

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#define ARRAY_LINEAR_GENERAL 0x00000000

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#define ARRAY_LINEAR_ALIGNED 0x00000001

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#define ARRAY_1D_TILED_THIN1 0x00000002

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#define ARRAY_2D_TILED_THIN1 0x00000004

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/* Registers */

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#define ARB_POP 0x2418

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#define ENABLE_TC128 (1 << 30)

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#define ARB_GDEC_RD_CNTL 0x246C

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#define CC_GC_SHADER_PIPE_CONFIG 0x8950

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#define CC_RB_BACKEND_DISABLE 0x98F4

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#define BACKEND_DISABLE(x) ((x) << 16)

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#define CB_COLOR0_BASE 0x28040

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#define CB_COLOR1_BASE 0x28044

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#define CB_COLOR2_BASE 0x28048

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#define CB_COLOR3_BASE 0x2804C

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#define CB_COLOR4_BASE 0x28050

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#define CB_COLOR5_BASE 0x28054

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#define CB_COLOR6_BASE 0x28058

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#define CB_COLOR7_BASE 0x2805C

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#define CB_COLOR7_FRAG 0x280FC

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#define CB_COLOR0_SIZE 0x28060

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#define CB_COLOR0_VIEW 0x28080

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#define R_028080_CB_COLOR0_VIEW 0x028080

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#define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0)

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#define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF)

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#define C_028080_SLICE_START 0xFFFFF800

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#define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13)

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#define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF)

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#define C_028080_SLICE_MAX 0xFF001FFF

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#define R_028084_CB_COLOR1_VIEW 0x028084

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#define R_028088_CB_COLOR2_VIEW 0x028088

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#define R_02808C_CB_COLOR3_VIEW 0x02808C

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#define R_028090_CB_COLOR4_VIEW 0x028090

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#define R_028094_CB_COLOR5_VIEW 0x028094

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#define R_028098_CB_COLOR6_VIEW 0x028098

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#define R_02809C_CB_COLOR7_VIEW 0x02809C

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#define CB_COLOR0_INFO 0x280a0

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# define CB_FORMAT(x) ((x) << 2)

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# define CB_ARRAY_MODE(x) ((x) << 8)

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# define CB_SOURCE_FORMAT(x) ((x) << 27)

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# define CB_SF_EXPORT_FULL 0

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# define CB_SF_EXPORT_NORM 1

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#define CB_COLOR0_TILE 0x280c0

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#define CB_COLOR0_FRAG 0x280e0

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#define CB_COLOR0_MASK 0x28100

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#define SQ_ALU_CONST_CACHE_PS_0 0x28940

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#define SQ_ALU_CONST_CACHE_PS_1 0x28944

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#define SQ_ALU_CONST_CACHE_PS_2 0x28948

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#define SQ_ALU_CONST_CACHE_PS_3 0x2894c

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#define SQ_ALU_CONST_CACHE_PS_4 0x28950

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#define SQ_ALU_CONST_CACHE_PS_5 0x28954

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#define SQ_ALU_CONST_CACHE_PS_6 0x28958

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#define SQ_ALU_CONST_CACHE_PS_7 0x2895c

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#define SQ_ALU_CONST_CACHE_PS_8 0x28960

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#define SQ_ALU_CONST_CACHE_PS_9 0x28964

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#define SQ_ALU_CONST_CACHE_PS_10 0x28968

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#define SQ_ALU_CONST_CACHE_PS_11 0x2896c

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#define SQ_ALU_CONST_CACHE_PS_12 0x28970

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#define SQ_ALU_CONST_CACHE_PS_13 0x28974

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#define SQ_ALU_CONST_CACHE_PS_14 0x28978

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#define SQ_ALU_CONST_CACHE_PS_15 0x2897c

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#define SQ_ALU_CONST_CACHE_VS_0 0x28980

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#define SQ_ALU_CONST_CACHE_VS_1 0x28984

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#define SQ_ALU_CONST_CACHE_VS_2 0x28988

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#define SQ_ALU_CONST_CACHE_VS_3 0x2898c

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#define SQ_ALU_CONST_CACHE_VS_4 0x28990

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#define SQ_ALU_CONST_CACHE_VS_5 0x28994

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#define SQ_ALU_CONST_CACHE_VS_6 0x28998

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#define SQ_ALU_CONST_CACHE_VS_7 0x2899c

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#define SQ_ALU_CONST_CACHE_VS_8 0x289a0

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#define SQ_ALU_CONST_CACHE_VS_9 0x289a4

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#define SQ_ALU_CONST_CACHE_VS_10 0x289a8

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#define SQ_ALU_CONST_CACHE_VS_11 0x289ac

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#define SQ_ALU_CONST_CACHE_VS_12 0x289b0

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#define SQ_ALU_CONST_CACHE_VS_13 0x289b4

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#define SQ_ALU_CONST_CACHE_VS_14 0x289b8

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#define SQ_ALU_CONST_CACHE_VS_15 0x289bc

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#define SQ_ALU_CONST_CACHE_GS_0 0x289c0

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#define SQ_ALU_CONST_CACHE_GS_1 0x289c4

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#define SQ_ALU_CONST_CACHE_GS_2 0x289c8

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#define SQ_ALU_CONST_CACHE_GS_3 0x289cc

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#define SQ_ALU_CONST_CACHE_GS_4 0x289d0

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#define SQ_ALU_CONST_CACHE_GS_5 0x289d4

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#define SQ_ALU_CONST_CACHE_GS_6 0x289d8

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#define SQ_ALU_CONST_CACHE_GS_7 0x289dc

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#define SQ_ALU_CONST_CACHE_GS_8 0x289e0

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#define SQ_ALU_CONST_CACHE_GS_9 0x289e4

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#define SQ_ALU_CONST_CACHE_GS_10 0x289e8

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#define SQ_ALU_CONST_CACHE_GS_11 0x289ec

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#define SQ_ALU_CONST_CACHE_GS_12 0x289f0

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#define SQ_ALU_CONST_CACHE_GS_13 0x289f4

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#define SQ_ALU_CONST_CACHE_GS_14 0x289f8

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#define SQ_ALU_CONST_CACHE_GS_15 0x289fc

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#define CONFIG_MEMSIZE 0x5428

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#define CONFIG_CNTL 0x5424

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#define CP_STAT 0x8680

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#define CP_COHER_BASE 0x85F8

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#define CP_DEBUG 0xC1FC

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#define R_0086D8_CP_ME_CNTL 0x86D8

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#define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28)

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#define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF)

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#define CP_ME_RAM_DATA 0xC160

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#define CP_ME_RAM_RADDR 0xC158

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#define CP_ME_RAM_WADDR 0xC15C

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#define CP_MEQ_THRESHOLDS 0x8764

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#define MEQ_END(x) ((x) << 16)

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#define ROQ_END(x) ((x) << 24)

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#define CP_PERFMON_CNTL 0x87FC

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#define CP_PFP_UCODE_ADDR 0xC150

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#define CP_PFP_UCODE_DATA 0xC154

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#define CP_QUEUE_THRESHOLDS 0x8760

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#define ROQ_IB1_START(x) ((x) << 0)

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#define ROQ_IB2_START(x) ((x) << 8)

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#define CP_RB_BASE 0xC100

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#define CP_RB_CNTL 0xC104

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#define RB_BUFSZ(x) ((x) << 0)

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#define RB_BLKSZ(x) ((x) << 8)

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#define RB_NO_UPDATE (1 << 27)

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#define RB_RPTR_WR_ENA (1 << 31)

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#define BUF_SWAP_32BIT (2 << 16)

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#define CP_RB_RPTR 0x8700

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#define CP_RB_RPTR_ADDR 0xC10C

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#define RB_RPTR_SWAP(x) ((x) << 0)

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#define CP_RB_RPTR_ADDR_HI 0xC110

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#define CP_RB_RPTR_WR 0xC108

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#define CP_RB_WPTR 0xC114

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#define CP_RB_WPTR_ADDR 0xC118

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#define CP_RB_WPTR_ADDR_HI 0xC11C

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#define CP_RB_WPTR_DELAY 0x8704

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#define CP_ROQ_IB1_STAT 0x8784

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#define CP_ROQ_IB2_STAT 0x8788

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#define CP_SEM_WAIT_TIMER 0x85BC

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#define DB_DEBUG 0x9830

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#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)

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#define DB_DEPTH_BASE 0x2800C

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#define DB_HTILE_DATA_BASE 0x28014

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#define DB_HTILE_SURFACE 0x28D24

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#define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0)

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#define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1)

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#define C_028D24_HTILE_WIDTH 0xFFFFFFFE

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#define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1)

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#define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1)

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#define C_028D24_HTILE_HEIGHT 0xFFFFFFFD

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#define G_028D24_LINEAR(x) (((x) >> 2) & 0x1)

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#define DB_WATERMARKS 0x9838

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#define DEPTH_FREE(x) ((x) << 0)

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#define DEPTH_FLUSH(x) ((x) << 5)

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#define DEPTH_PENDING_FREE(x) ((x) << 15)

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#define DEPTH_CACHELINE_FREE(x) ((x) << 20)

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#define DCP_TILING_CONFIG 0x6CA0

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#define PIPE_TILING(x) ((x) << 1)

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#define BANK_TILING(x) ((x) << 4)

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#define GROUP_SIZE(x) ((x) << 6)

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#define ROW_TILING(x) ((x) << 8)

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#define BANK_SWAPS(x) ((x) << 11)

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#define SAMPLE_SPLIT(x) ((x) << 14)

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#define BACKEND_MAP(x) ((x) << 16)

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#define GB_TILING_CONFIG 0x98F0

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#define GC_USER_SHADER_PIPE_CONFIG 0x8954

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#define INACTIVE_QD_PIPES(x) ((x) << 8)

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#define INACTIVE_QD_PIPES_MASK 0x0000FF00

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#define INACTIVE_SIMDS(x) ((x) << 16)

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#define INACTIVE_SIMDS_MASK 0x00FF0000

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#define SQ_CONFIG 0x8c00

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# define VC_ENABLE (1 << 0)

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# define EXPORT_SRC_C (1 << 1)

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# define DX9_CONSTS (1 << 2)

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# define ALU_INST_PREFER_VECTOR (1 << 3)

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# define DX10_CLAMP (1 << 4)

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# define CLAUSE_SEQ_PRIO(x) ((x) << 8)

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# define PS_PRIO(x) ((x) << 24)

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# define VS_PRIO(x) ((x) << 26)

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# define GS_PRIO(x) ((x) << 28)

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# define ES_PRIO(x) ((x) << 30)

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#define SQ_GPR_RESOURCE_MGMT_1 0x8c04

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# define NUM_PS_GPRS(x) ((x) << 0)

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# define NUM_VS_GPRS(x) ((x) << 16)

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# define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)

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#define SQ_GPR_RESOURCE_MGMT_2 0x8c08

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# define NUM_GS_GPRS(x) ((x) << 0)

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# define NUM_ES_GPRS(x) ((x) << 16)

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#define SQ_THREAD_RESOURCE_MGMT 0x8c0c

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# define NUM_PS_THREADS(x) ((x) << 0)

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# define NUM_VS_THREADS(x) ((x) << 8)

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# define NUM_GS_THREADS(x) ((x) << 16)

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# define NUM_ES_THREADS(x) ((x) << 24)

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#define SQ_STACK_RESOURCE_MGMT_1 0x8c10

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# define NUM_PS_STACK_ENTRIES(x) ((x) << 0)

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# define NUM_VS_STACK_ENTRIES(x) ((x) << 16)

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#define SQ_STACK_RESOURCE_MGMT_2 0x8c14

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# define NUM_GS_STACK_ENTRIES(x) ((x) << 0)

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# define NUM_ES_STACK_ENTRIES(x) ((x) << 16)

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#define SQ_ESGS_RING_BASE 0x8c40

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#define SQ_GSVS_RING_BASE 0x8c48

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#define SQ_ESTMP_RING_BASE 0x8c50

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#define SQ_GSTMP_RING_BASE 0x8c58

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#define SQ_VSTMP_RING_BASE 0x8c60

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#define SQ_PSTMP_RING_BASE 0x8c68

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#define SQ_FBUF_RING_BASE 0x8c70

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#define SQ_REDUC_RING_BASE 0x8c78

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#define GRBM_CNTL 0x8000

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# define GRBM_READ_TIMEOUT(x) ((x) << 0)

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#define GRBM_STATUS 0x8010

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#define CMDFIFO_AVAIL_MASK 0x0000001F

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#define GUI_ACTIVE (1<<31)

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#define GRBM_STATUS2 0x8014

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#define GRBM_SOFT_RESET 0x8020

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#define SOFT_RESET_CP (1<<0)

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#define CG_THERMAL_STATUS 0x7F4

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#define ASIC_T(x) ((x) << 0)

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#define ASIC_T_MASK 0x1FF

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#define ASIC_T_SHIFT 0

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#define HDP_HOST_PATH_CNTL 0x2C00

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#define HDP_NONSURFACE_BASE 0x2C04

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#define HDP_NONSURFACE_INFO 0x2C08

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#define HDP_NONSURFACE_SIZE 0x2C0C

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#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0

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#define HDP_TILING_CONFIG 0x2F3C

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#define HDP_DEBUG1 0x2F34

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#define MC_VM_AGP_TOP 0x2184

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#define MC_VM_AGP_BOT 0x2188

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#define MC_VM_AGP_BASE 0x218C

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#define MC_VM_FB_LOCATION 0x2180

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#define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C

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#define ENABLE_L1_TLB (1 << 0)

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#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)

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#define ENABLE_L1_STRICT_ORDERING (1 << 2)

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#define SYSTEM_ACCESS_MODE_MASK 0x000000C0

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#define SYSTEM_ACCESS_MODE_SHIFT 6

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#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)

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#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)

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#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)

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#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)

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#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)

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#define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)

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#define ENABLE_SEMAPHORE_MODE (1 << 10)

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#define ENABLE_WAIT_L2_QUERY (1 << 11)

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#define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12)

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#define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000

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#define EFFECTIVE_L1_TLB_SIZE_SHIFT 12

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#define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15)

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#define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000

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#define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15

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#define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0

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#define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC

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#define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204

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#define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208

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#define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C

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#define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200

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#define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4

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#define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8

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#define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210

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#define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218

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#define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C

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#define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220

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#define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214

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#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190

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#define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF

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#define LOGICAL_PAGE_NUMBER_SHIFT 0

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#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194

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#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198

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#define PA_CL_ENHANCE 0x8A14

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#define CLIP_VTX_REORDER_ENA (1 << 0)

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#define NUM_CLIP_SEQ(x) ((x) << 1)

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#define PA_SC_AA_CONFIG 0x28C04

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#define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40

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#define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44

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#define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48

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#define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C

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#define S0_X(x) ((x) << 0)

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#define S0_Y(x) ((x) << 4)

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#define S1_X(x) ((x) << 8)

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#define S1_Y(x) ((x) << 12)

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#define S2_X(x) ((x) << 16)

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#define S2_Y(x) ((x) << 20)

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#define S3_X(x) ((x) << 24)

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#define S3_Y(x) ((x) << 28)

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#define S4_X(x) ((x) << 0)

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#define S4_Y(x) ((x) << 4)

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#define S5_X(x) ((x) << 8)

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#define S5_Y(x) ((x) << 12)

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#define S6_X(x) ((x) << 16)

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#define S6_Y(x) ((x) << 20)

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#define S7_X(x) ((x) << 24)

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#define S7_Y(x) ((x) << 28)

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#define PA_SC_CLIPRECT_RULE 0x2820c

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#define PA_SC_ENHANCE 0x8BF0

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#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)

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#define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)

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#define PA_SC_LINE_STIPPLE 0x28A0C

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#define PA_SC_LINE_STIPPLE_STATE 0x8B10

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#define PA_SC_MODE_CNTL 0x28A4C

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#define PA_SC_MULTI_CHIP_CNTL 0x8B20

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#define PA_SC_SCREEN_SCISSOR_TL 0x28030

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#define PA_SC_GENERIC_SCISSOR_TL 0x28240

367

#define PA_SC_WINDOW_SCISSOR_TL 0x28204

368

369

#define PCIE_PORT_INDEX 0x0038

370

#define PCIE_PORT_DATA 0x003C

371

Alex Deucher

5885b7a

2009-10-19 17:23:33 -0400

[diff] [blame]

372

#define CHMAP 0x2004

373

#define NOOFCHAN_SHIFT 12

374

#define NOOFCHAN_MASK 0x00003000

375

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

376

#define RAMCFG 0x2408

377

#define NOOFBANK_SHIFT 0

378

#define NOOFBANK_MASK 0x00000001

379

#define NOOFRANK_SHIFT 1

380

#define NOOFRANK_MASK 0x00000002

381

#define NOOFROWS_SHIFT 2

382

#define NOOFROWS_MASK 0x0000001C

383

#define NOOFCOLS_SHIFT 5

384

#define NOOFCOLS_MASK 0x00000060

385

#define CHANSIZE_SHIFT 7

386

#define CHANSIZE_MASK 0x00000080

387

#define BURSTLENGTH_SHIFT 8

388

#define BURSTLENGTH_MASK 0x00000100

389

#define CHANSIZE_OVERRIDE (1 << 10)

390

391

#define SCRATCH_REG0 0x8500

392

#define SCRATCH_REG1 0x8504

393

#define SCRATCH_REG2 0x8508

394

#define SCRATCH_REG3 0x850C

395

#define SCRATCH_REG4 0x8510

396

#define SCRATCH_REG5 0x8514

397

#define SCRATCH_REG6 0x8518

398

#define SCRATCH_REG7 0x851C

399

#define SCRATCH_UMSK 0x8540

400

#define SCRATCH_ADDR 0x8544

401

402

#define SPI_CONFIG_CNTL 0x9100

403

#define GPR_WRITE_PRIORITY(x) ((x) << 0)

404

#define DISABLE_INTERP_1 (1 << 5)

405

#define SPI_CONFIG_CNTL_1 0x913C

406

#define VTX_DONE_DELAY(x) ((x) << 0)

407

#define INTERP_ONE_PRIM_PER_ROW (1 << 4)

408

#define SPI_INPUT_Z 0x286D8

409

#define SPI_PS_IN_CONTROL_0 0x286CC

410

#define NUM_INTERP(x) ((x)<<0)

411

#define POSITION_ENA (1<<8)

412

#define POSITION_CENTROID (1<<9)

413

#define POSITION_ADDR(x) ((x)<<10)

414

#define PARAM_GEN(x) ((x)<<15)

415

#define PARAM_GEN_ADDR(x) ((x)<<19)

416

#define BARYC_SAMPLE_CNTL(x) ((x)<<26)

417

#define PERSP_GRADIENT_ENA (1<<28)

418

#define LINEAR_GRADIENT_ENA (1<<29)

419

#define POSITION_SAMPLE (1<<30)

420

#define BARYC_AT_SAMPLE_ENA (1<<31)

421

#define SPI_PS_IN_CONTROL_1 0x286D0

422

#define GEN_INDEX_PIX (1<<0)

423

#define GEN_INDEX_PIX_ADDR(x) ((x)<<1)

424

#define FRONT_FACE_ENA (1<<8)

425

#define FRONT_FACE_CHAN(x) ((x)<<9)

426

#define FRONT_FACE_ALL_BITS (1<<11)

427

#define FRONT_FACE_ADDR(x) ((x)<<12)

428

#define FOG_ADDR(x) ((x)<<17)

429

#define FIXED_PT_POSITION_ENA (1<<24)

430

#define FIXED_PT_POSITION_ADDR(x) ((x)<<25)

431

432

#define SQ_MS_FIFO_SIZES 0x8CF0

433

#define CACHE_FIFO_SIZE(x) ((x) << 0)

434

#define FETCH_FIFO_HIWATER(x) ((x) << 8)

435

#define DONE_FIFO_HIWATER(x) ((x) << 16)

436

#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)

437

#define SQ_PGM_START_ES 0x28880

438

#define SQ_PGM_START_FS 0x28894

439

#define SQ_PGM_START_GS 0x2886C

440

#define SQ_PGM_START_PS 0x28840

441

#define SQ_PGM_RESOURCES_PS 0x28850

442

#define SQ_PGM_EXPORTS_PS 0x28854

443

#define SQ_PGM_CF_OFFSET_PS 0x288cc

444

#define SQ_PGM_START_VS 0x28858

445

#define SQ_PGM_RESOURCES_VS 0x28868

446

#define SQ_PGM_CF_OFFSET_VS 0x288d0

Ilija Hadzic

3a38612

2011-10-12 23:29:37 -0400

[diff] [blame]

447

448

#define SQ_VTX_CONSTANT_WORD0_0 0x30000

449

#define SQ_VTX_CONSTANT_WORD1_0 0x30004

450

#define SQ_VTX_CONSTANT_WORD2_0 0x30008

451

# define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0)

452

# define SQ_VTXC_STRIDE(x) ((x) << 8)

453

# define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30)

454

# define SQ_ENDIAN_NONE 0

455

# define SQ_ENDIAN_8IN16 1

456

# define SQ_ENDIAN_8IN32 2

457

#define SQ_VTX_CONSTANT_WORD3_0 0x3000c

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

458

#define SQ_VTX_CONSTANT_WORD6_0 0x38018

459

#define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30)

460

#define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3)

461

#define SQ_TEX_VTX_INVALID_TEXTURE 0x0

462

#define SQ_TEX_VTX_INVALID_BUFFER 0x1

463

#define SQ_TEX_VTX_VALID_TEXTURE 0x2

464

#define SQ_TEX_VTX_VALID_BUFFER 0x3

465

466

467

#define SX_MISC 0x28350

Alex Deucher

a39533b

2009-11-09 16:41:21 -0500

[diff] [blame]

468

#define SX_MEMORY_EXPORT_BASE 0x9010

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

469

#define SX_DEBUG_1 0x9054

470

#define SMX_EVENT_RELEASE (1 << 0)

471

#define ENABLE_NEW_SMX_ADDRESS (1 << 16)

472

473

#define TA_CNTL_AUX 0x9508

474

#define DISABLE_CUBE_WRAP (1 << 0)

475

#define DISABLE_CUBE_ANISO (1 << 1)

476

#define SYNC_GRADIENT (1 << 24)

477

#define SYNC_WALKER (1 << 25)

478

#define SYNC_ALIGNER (1 << 26)

479

#define BILINEAR_PRECISION_6_BIT (0 << 31)

480

#define BILINEAR_PRECISION_8_BIT (1 << 31)

481

482

#define TC_CNTL 0x9608

483

#define TC_L2_SIZE(x) ((x)<<5)

484

#define L2_DISABLE_LATE_HIT (1<<9)

485

486

487

#define VGT_CACHE_INVALIDATION 0x88C4

488

#define CACHE_INVALIDATION(x) ((x)<<0)

#define VC_ONLY 0

#define TC_ONLY 1

#define VC_AND_TC 2

#define VGT_DMA_BASE 0x287E8

493

#define VGT_DMA_BASE_HI 0x287E4

494

#define VGT_ES_PER_GS 0x88CC

495

#define VGT_GS_PER_ES 0x88C8

496

#define VGT_GS_PER_VS 0x88E8

497

#define VGT_GS_VERTEX_REUSE 0x88D4

498

#define VGT_PRIMITIVE_TYPE 0x8958

499

#define VGT_NUM_INSTANCES 0x8974

500

#define VGT_OUT_DEALLOC_CNTL 0x28C5C

501

#define DEALLOC_DIST_MASK 0x0000007F

502

#define VGT_STRMOUT_BASE_OFFSET_0 0x28B10

503

#define VGT_STRMOUT_BASE_OFFSET_1 0x28B14

504

#define VGT_STRMOUT_BASE_OFFSET_2 0x28B18

505

#define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c

506

#define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44

507

#define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48

508

#define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c

509

#define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50

510

#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8

511

#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8

512

#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8

513

#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08

514

#define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC

515

#define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC

516

#define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC

517

#define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C

Marek Olšák

dd220a0

2012-01-27 12:17:59 -0500

[diff] [blame]

518

#define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0

519

#define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0

520

#define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0

521

#define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00

522

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

523

#define VGT_STRMOUT_EN 0x28AB0

524

#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58

525

#define VTX_REUSE_DEPTH_MASK 0x000000FF

526

#define VGT_EVENT_INITIATOR 0x28a90

Alex Deucher

d0f8a85

2010-09-04 05:04:34 -0400

[diff] [blame]

527

# define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0)

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

528

# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)

529

530

#define VM_CONTEXT0_CNTL 0x1410

531

#define ENABLE_CONTEXT (1 << 0)

532

#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)

533

#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)

534

#define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490

535

#define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0

536

#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574

537

#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594

538

#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4

539

#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554

540

#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470

541

#define REQUEST_TYPE(x) (((x) & 0xf) << 0)

542

#define RESPONSE_TYPE_MASK 0x000000F0

543

#define RESPONSE_TYPE_SHIFT 4

544

#define VM_L2_CNTL 0x1400

545

#define ENABLE_L2_CACHE (1 << 0)

546

#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)

547

#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)

548

#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13)

549

#define VM_L2_CNTL2 0x1404

550

#define INVALIDATE_ALL_L1_TLBS (1 << 0)

551

#define INVALIDATE_L2_CACHE (1 << 1)

552

#define VM_L2_CNTL3 0x1408

553

#define BANK_SELECT_0(x) (((x) & 0x1f) << 0)

554

#define BANK_SELECT_1(x) (((x) & 0x1f) << 5)

555

#define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10)

556

#define VM_L2_STATUS 0x140C

557

#define L2_BUSY (1 << 0)

558

559

#define WAIT_UNTIL 0x8040

560

#define WAIT_2D_IDLE_bit (1 << 14)

561

#define WAIT_3D_IDLE_bit (1 << 15)

562

#define WAIT_2D_IDLECLEAN_bit (1 << 16)

563

#define WAIT_3D_IDLECLEAN_bit (1 << 17)

564

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

565

#define IH_RB_CNTL 0x3e00

566

# define IH_RB_ENABLE (1 << 0)

567

# define IH_IB_SIZE(x) ((x) << 1) /* log2 */

568

# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)

569

# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)

570

# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */

571

# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)

572

# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)

573

#define IH_RB_BASE 0x3e04

574

#define IH_RB_RPTR 0x3e08

575

#define IH_RB_WPTR 0x3e0c

576

# define RB_OVERFLOW (1 << 0)

577

# define WPTR_OFFSET_MASK 0x3fffc

578

#define IH_RB_WPTR_ADDR_HI 0x3e10

579

#define IH_RB_WPTR_ADDR_LO 0x3e14

580

#define IH_CNTL 0x3e18

581

# define ENABLE_INTR (1 << 0)

Alex Deucher

fcb857a

2011-07-06 19:52:27 +0000

[diff] [blame]

582

# define IH_MC_SWAP(x) ((x) << 1)

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

583

# define IH_MC_SWAP_NONE 0

584

# define IH_MC_SWAP_16BIT 1

585

# define IH_MC_SWAP_32BIT 2

586

# define IH_MC_SWAP_64BIT 3

587

# define RPTR_REARM (1 << 4)

588

# define MC_WRREQ_CREDIT(x) ((x) << 15)

589

# define MC_WR_CLEAN_CNT(x) ((x) << 20)

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

590

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

591

#define RLC_CNTL 0x3f00

592

# define RLC_ENABLE (1 << 0)

593

#define RLC_HB_BASE 0x3f10

594

#define RLC_HB_CNTL 0x3f0c

595

#define RLC_HB_RPTR 0x3f20

596

#define RLC_HB_WPTR 0x3f1c

597

#define RLC_HB_WPTR_LSB_ADDR 0x3f14

598

#define RLC_HB_WPTR_MSB_ADDR 0x3f18

599

#define RLC_MC_CNTL 0x3f44

600

#define RLC_UCODE_CNTL 0x3f48

601

#define RLC_UCODE_ADDR 0x3f2c

602

#define RLC_UCODE_DATA 0x3f30

603

Alex Deucher

c420c74

2012-03-20 17:18:39 -0400

[diff] [blame]

604

/* new for TN */

605

#define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10

606

#define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20

607

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

608

#define SRBM_SOFT_RESET 0xe60

609

# define SOFT_RESET_RLC (1 << 13)

610

611

#define CP_INT_CNTL 0xc124

612

# define CNTX_BUSY_INT_ENABLE (1 << 19)

613

# define CNTX_EMPTY_INT_ENABLE (1 << 20)

614

# define SCRATCH_INT_ENABLE (1 << 25)

615

# define TIME_STAMP_INT_ENABLE (1 << 26)

616

# define IB2_INT_ENABLE (1 << 29)

617

# define IB1_INT_ENABLE (1 << 30)

618

# define RB_INT_ENABLE (1 << 31)

619

#define CP_INT_STATUS 0xc128

620

# define SCRATCH_INT_STAT (1 << 25)

621

# define TIME_STAMP_INT_STAT (1 << 26)

622

# define IB2_INT_STAT (1 << 29)

623

# define IB1_INT_STAT (1 << 30)

624

# define RB_INT_STAT (1 << 31)

625

626

#define GRBM_INT_CNTL 0x8060

627

# define RDERR_INT_ENABLE (1 << 0)

628

# define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1)

629

# define GUI_IDLE_INT_ENABLE (1 << 19)

630

631

#define INTERRUPT_CNTL 0x5468

632

# define IH_DUMMY_RD_OVERRIDE (1 << 0)

633

# define IH_DUMMY_RD_EN (1 << 1)

634

# define IH_REQ_NONSNOOP_EN (1 << 3)

635

# define GEN_IH_INT_EN (1 << 8)

636

#define INTERRUPT_CNTL2 0x546c

637

638

#define D1MODE_VBLANK_STATUS 0x6534

639

#define D2MODE_VBLANK_STATUS 0x6d34

640

# define DxMODE_VBLANK_OCCURRED (1 << 0)

641

# define DxMODE_VBLANK_ACK (1 << 4)

642

# define DxMODE_VBLANK_STAT (1 << 12)

643

# define DxMODE_VBLANK_INTERRUPT (1 << 16)

644

# define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17)

645

#define D1MODE_VLINE_STATUS 0x653c

646

#define D2MODE_VLINE_STATUS 0x6d3c

647

# define DxMODE_VLINE_OCCURRED (1 << 0)

648

# define DxMODE_VLINE_ACK (1 << 4)

649

# define DxMODE_VLINE_STAT (1 << 12)

650

# define DxMODE_VLINE_INTERRUPT (1 << 16)

651

# define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17)

652

#define DxMODE_INT_MASK 0x6540

653

# define D1MODE_VBLANK_INT_MASK (1 << 0)

654

# define D1MODE_VLINE_INT_MASK (1 << 4)

655

# define D2MODE_VBLANK_INT_MASK (1 << 8)

656

# define D2MODE_VLINE_INT_MASK (1 << 12)

657

#define DCE3_DISP_INTERRUPT_STATUS 0x7ddc

658

# define DC_HPD1_INTERRUPT (1 << 18)

659

# define DC_HPD2_INTERRUPT (1 << 19)

660

#define DISP_INTERRUPT_STATUS 0x7edc

661

# define LB_D1_VLINE_INTERRUPT (1 << 2)

662

# define LB_D2_VLINE_INTERRUPT (1 << 3)

663

# define LB_D1_VBLANK_INTERRUPT (1 << 4)

664

# define LB_D2_VBLANK_INTERRUPT (1 << 5)

665

# define DACA_AUTODETECT_INTERRUPT (1 << 16)

666

# define DACB_AUTODETECT_INTERRUPT (1 << 17)

667

# define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18)

668

# define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19)

669

# define DC_I2C_SW_DONE_INTERRUPT (1 << 20)

670

# define DC_I2C_HW_DONE_INTERRUPT (1 << 21)

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

671

#define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

672

#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8

673

# define DC_HPD4_INTERRUPT (1 << 14)

674

# define DC_HPD4_RX_INTERRUPT (1 << 15)

675

# define DC_HPD3_INTERRUPT (1 << 28)

676

# define DC_HPD1_RX_INTERRUPT (1 << 29)

677

# define DC_HPD2_RX_INTERRUPT (1 << 30)

678

#define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec

679

# define DC_HPD3_RX_INTERRUPT (1 << 0)

680

# define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1)

681

# define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2)

682

# define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3)

683

# define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4)

684

# define AUX1_SW_DONE_INTERRUPT (1 << 5)

685

# define AUX1_LS_DONE_INTERRUPT (1 << 6)

686

# define AUX2_SW_DONE_INTERRUPT (1 << 7)

687

# define AUX2_LS_DONE_INTERRUPT (1 << 8)

688

# define AUX3_SW_DONE_INTERRUPT (1 << 9)

689

# define AUX3_LS_DONE_INTERRUPT (1 << 10)

690

# define AUX4_SW_DONE_INTERRUPT (1 << 11)

691

# define AUX4_LS_DONE_INTERRUPT (1 << 12)

692

# define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13)

693

# define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14)

694

/* DCE 3.2 */

695

# define AUX5_SW_DONE_INTERRUPT (1 << 15)

696

# define AUX5_LS_DONE_INTERRUPT (1 << 16)

697

# define AUX6_SW_DONE_INTERRUPT (1 << 17)

698

# define AUX6_LS_DONE_INTERRUPT (1 << 18)

699

# define DC_HPD5_INTERRUPT (1 << 19)

700

# define DC_HPD5_RX_INTERRUPT (1 << 20)

701

# define DC_HPD6_INTERRUPT (1 << 21)

702

# define DC_HPD6_RX_INTERRUPT (1 << 22)

703

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

704

#define DACA_AUTO_DETECT_CONTROL 0x7828

705

#define DACB_AUTO_DETECT_CONTROL 0x7a28

706

#define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028

707

#define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128

708

# define DACx_AUTODETECT_MODE(x) ((x) << 0)

709

# define DACx_AUTODETECT_MODE_NONE 0

710

# define DACx_AUTODETECT_MODE_CONNECT 1

711

# define DACx_AUTODETECT_MODE_DISCONNECT 2

712

# define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8)

713

/* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */

714

# define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16)

715

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

716

#define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038

717

#define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138

718

#define DACA_AUTODETECT_INT_CONTROL 0x7838

719

#define DACB_AUTODETECT_INT_CONTROL 0x7a38

720

# define DACx_AUTODETECT_ACK (1 << 0)

721

# define DACx_AUTODETECT_INT_ENABLE (1 << 16)

722

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

723

#define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00

724

#define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10

725

#define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24

726

# define DC_HOT_PLUG_DETECTx_EN (1 << 0)

727

728

#define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04

729

#define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14

730

#define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28

731

# define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0)

732

# define DC_HOT_PLUG_DETECTx_SENSE (1 << 1)

733

734

/* DCE 3.0 */

735

#define DC_HPD1_INT_STATUS 0x7d00

736

#define DC_HPD2_INT_STATUS 0x7d0c

737

#define DC_HPD3_INT_STATUS 0x7d18

738

#define DC_HPD4_INT_STATUS 0x7d24

739

/* DCE 3.2 */

740

#define DC_HPD5_INT_STATUS 0x7dc0

741

#define DC_HPD6_INT_STATUS 0x7df4

742

# define DC_HPDx_INT_STATUS (1 << 0)

743

# define DC_HPDx_SENSE (1 << 1)

744

# define DC_HPDx_RX_INT_STATUS (1 << 8)

745

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

746

#define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08

747

#define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18

748

#define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c

749

# define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0)

750

# define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8)

751

# define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16)

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

752

/* DCE 3.0 */

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

753

#define DC_HPD1_INT_CONTROL 0x7d04

754

#define DC_HPD2_INT_CONTROL 0x7d10

755

#define DC_HPD3_INT_CONTROL 0x7d1c

756

#define DC_HPD4_INT_CONTROL 0x7d28

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

757

/* DCE 3.2 */

758

#define DC_HPD5_INT_CONTROL 0x7dc4

759

#define DC_HPD6_INT_CONTROL 0x7df8

Alex Deucher

2009-12-01 13:43:46 -0500

[diff] [blame]

760

# define DC_HPDx_INT_ACK (1 << 0)

761

# define DC_HPDx_INT_POLARITY (1 << 8)

762

# define DC_HPDx_INT_EN (1 << 16)

763

# define DC_HPDx_RX_INT_ACK (1 << 20)

764

# define DC_HPDx_RX_INT_EN (1 << 24)

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

765

Alex Deucher

2009-12-03 13:08:53 -0500

[diff] [blame]

766

/* DCE 3.0 */

767

#define DC_HPD1_CONTROL 0x7d08

768

#define DC_HPD2_CONTROL 0x7d14

769

#define DC_HPD3_CONTROL 0x7d20

770

#define DC_HPD4_CONTROL 0x7d2c

771

/* DCE 3.2 */

772

#define DC_HPD5_CONTROL 0x7dc8

773

#define DC_HPD6_CONTROL 0x7dfc

774

# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)

775

# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)

776

/* DCE 3.2 */

777

# define DC_HPDx_EN (1 << 28)

778

Alex Deucher

6f34be5

2010-11-21 10:59:01 -0500

[diff] [blame]

779

#define D1GRPH_INTERRUPT_STATUS 0x6158

780

#define D2GRPH_INTERRUPT_STATUS 0x6958

781

# define DxGRPH_PFLIP_INT_OCCURRED (1 << 0)

782

# define DxGRPH_PFLIP_INT_CLEAR (1 << 8)

783

#define D1GRPH_INTERRUPT_CONTROL 0x615c

784

#define D2GRPH_INTERRUPT_CONTROL 0x695c

785

# define DxGRPH_PFLIP_INT_MASK (1 << 0)

786

# define DxGRPH_PFLIP_INT_TYPE (1 << 8)

787

Alex Deucher

9e46a48

2011-01-06 18:49:35 -0500

[diff] [blame]

788

/* PCIE link stuff */

789

#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */

790

# define LC_POINT_7_PLUS_EN (1 << 6)

791

#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */

792

# define LC_LINK_WIDTH_SHIFT 0

793

# define LC_LINK_WIDTH_MASK 0x7

794

# define LC_LINK_WIDTH_X0 0

795

# define LC_LINK_WIDTH_X1 1

796

# define LC_LINK_WIDTH_X2 2

797

# define LC_LINK_WIDTH_X4 3

798

# define LC_LINK_WIDTH_X8 4

799

# define LC_LINK_WIDTH_X16 6

800

# define LC_LINK_WIDTH_RD_SHIFT 4

801

# define LC_LINK_WIDTH_RD_MASK 0x70

802

# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)

803

# define LC_RECONFIG_NOW (1 << 8)

804

# define LC_RENEGOTIATION_SUPPORT (1 << 9)

805

# define LC_RENEGOTIATE_EN (1 << 10)

806

# define LC_SHORT_RECONFIG_EN (1 << 11)

807

# define LC_UPCONFIGURE_SUPPORT (1 << 12)

808

# define LC_UPCONFIGURE_DIS (1 << 13)

809

#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */

810

# define LC_GEN2_EN_STRAP (1 << 0)

811

# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)

812

# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)

813

# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)

814

# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)

815

# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3

816

# define LC_CURRENT_DATA_RATE (1 << 11)

817

# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)

818

# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)

819

# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)

820

# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)

821

#define MM_CFGREGS_CNTL 0x544c

822

# define MM_WR_TO_CFG_EN (1 << 3)

823

#define LINK_CNTL2 0x88 /* F0 */

824

# define TARGET_LINK_SPEED_MASK (0xf << 0)

825

# define SELECTABLE_DEEMPHASIS (1 << 6)

826

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

/*

* PM4

*/

#define PACKET_TYPE0 0

831

#define PACKET_TYPE1 1

832

#define PACKET_TYPE2 2

833

#define PACKET_TYPE3 3

834

835

#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)

836

#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)

837

#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)

838

#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)

839

#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \

840

(((reg) >> 2) & 0xFFFF) | \

841

((n) & 0x3FFF) << 16)

842

#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \

843

(((op) & 0xFF) << 8) | \

844

((n) & 0x3FFF) << 16)

845

846

/* Packet 3 types */

847

#define PACKET3_NOP 0x10

848

#define PACKET3_INDIRECT_BUFFER_END 0x17

849

#define PACKET3_SET_PREDICATION 0x20

850

#define PACKET3_REG_RMW 0x21

851

#define PACKET3_COND_EXEC 0x22

852

#define PACKET3_PRED_EXEC 0x23

853

#define PACKET3_START_3D_CMDBUF 0x24

854

#define PACKET3_DRAW_INDEX_2 0x27

855

#define PACKET3_CONTEXT_CONTROL 0x28

856

#define PACKET3_DRAW_INDEX_IMMD_BE 0x29

857

#define PACKET3_INDEX_TYPE 0x2A

858

#define PACKET3_DRAW_INDEX 0x2B

859

#define PACKET3_DRAW_INDEX_AUTO 0x2D

860

#define PACKET3_DRAW_INDEX_IMMD 0x2E

861

#define PACKET3_NUM_INSTANCES 0x2F

862

#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34

863

#define PACKET3_INDIRECT_BUFFER_MP 0x38

864

#define PACKET3_MEM_SEMAPHORE 0x39

Christian König

0be7043

2012-03-07 11:28:57 +0100

[diff] [blame]

865

# define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12)

Christian König

15d3332

2011-09-15 19:02:22 +0200

[diff] [blame]

866

# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)

867

# define PACKET3_SEM_SEL_WAIT (0x7 << 29)

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

868

#define PACKET3_MPEG_INDEX 0x3A

Marek Olšák

dd220a0

2012-01-27 12:17:59 -0500

[diff] [blame]

869

#define PACKET3_COPY_DW 0x3B

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

870

#define PACKET3_WAIT_REG_MEM 0x3C

871

#define PACKET3_MEM_WRITE 0x3D

872

#define PACKET3_INDIRECT_BUFFER 0x32

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

873

#define PACKET3_SURFACE_SYNC 0x43

874

# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)

875

# define PACKET3_TC_ACTION_ENA (1 << 23)

876

# define PACKET3_VC_ACTION_ENA (1 << 24)

877

# define PACKET3_CB_ACTION_ENA (1 << 25)

878

# define PACKET3_DB_ACTION_ENA (1 << 26)

879

# define PACKET3_SH_ACTION_ENA (1 << 27)

880

# define PACKET3_SMX_ACTION_ENA (1 << 28)

881

#define PACKET3_ME_INITIALIZE 0x44

882

#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)

883

#define PACKET3_COND_WRITE 0x45

884

#define PACKET3_EVENT_WRITE 0x46

Alex Deucher

d0f8a85

2010-09-04 05:04:34 -0400

[diff] [blame]

885

#define EVENT_TYPE(x) ((x) << 0)

886

#define EVENT_INDEX(x) ((x) << 8)

887

/* 0 - any non-TS event

888

* 1 - ZPASS_DONE

889

* 2 - SAMPLE_PIPELINESTAT

890

* 3 - SAMPLE_STREAMOUTSTAT*

891

* 4 - *S_PARTIAL_FLUSH

892

* 5 - TS events

893

*/

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

894

#define PACKET3_EVENT_WRITE_EOP 0x47

Alex Deucher

d0f8a85

2010-09-04 05:04:34 -0400

[diff] [blame]

895

#define DATA_SEL(x) ((x) << 29)

896

/* 0 - discard

897

* 1 - send low 32bit data

898

* 2 - send 64bit data

899

* 3 - send 64bit counter value

900

*/

901

#define INT_SEL(x) ((x) << 24)

902

/* 0 - none

903

* 1 - interrupt only (DATA_SEL = 0)

904

* 2 - interrupt when data write is confirmed

905

*/

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

906

#define PACKET3_ONE_REG_WRITE 0x57

907

#define PACKET3_SET_CONFIG_REG 0x68

908

#define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000

909

#define PACKET3_SET_CONFIG_REG_END 0x0000ac00

910

#define PACKET3_SET_CONTEXT_REG 0x69

911

#define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000

912

#define PACKET3_SET_CONTEXT_REG_END 0x00029000

913

#define PACKET3_SET_ALU_CONST 0x6A

914

#define PACKET3_SET_ALU_CONST_OFFSET 0x00030000

915

#define PACKET3_SET_ALU_CONST_END 0x00032000

916

#define PACKET3_SET_BOOL_CONST 0x6B

917

#define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380

918

#define PACKET3_SET_BOOL_CONST_END 0x00040000

919

#define PACKET3_SET_LOOP_CONST 0x6C

920

#define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200

921

#define PACKET3_SET_LOOP_CONST_END 0x0003e380

922

#define PACKET3_SET_RESOURCE 0x6D

923

#define PACKET3_SET_RESOURCE_OFFSET 0x00038000

924

#define PACKET3_SET_RESOURCE_END 0x0003c000

925

#define PACKET3_SET_SAMPLER 0x6E

926

#define PACKET3_SET_SAMPLER_OFFSET 0x0003c000

927

#define PACKET3_SET_SAMPLER_END 0x0003cff0

928

#define PACKET3_SET_CTL_CONST 0x6F

929

#define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0

930

#define PACKET3_SET_CTL_CONST_END 0x0003e200

931

#define PACKET3_SURFACE_BASE_UPDATE 0x73

932

933

934

#define R_008020_GRBM_SOFT_RESET 0x8020

935

#define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0)

936

#define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1)

937

#define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2)

938

#define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3)

939

#define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5)

940

#define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6)

941

#define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7)

942

#define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8)

943

#define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9)

944

#define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10)

945

#define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11)

946

#define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12)

947

#define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13)

948

#define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14)

949

#define R_008010_GRBM_STATUS 0x8010

950

#define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0)

951

#define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6)

952

#define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7)

953

#define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8)

954

#define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10)

955

#define S_008010_VC_BUSY(x) (((x) & 1) << 11)

956

#define S_008010_DB03_CLEAN(x) (((x) & 1) << 12)

957

#define S_008010_CB03_CLEAN(x) (((x) & 1) << 13)

958

#define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16)

959

#define S_008010_VGT_BUSY(x) (((x) & 1) << 17)

960

#define S_008010_TA03_BUSY(x) (((x) & 1) << 18)

961

#define S_008010_TC_BUSY(x) (((x) & 1) << 19)

962

#define S_008010_SX_BUSY(x) (((x) & 1) << 20)

963

#define S_008010_SH_BUSY(x) (((x) & 1) << 21)

964

#define S_008010_SPI03_BUSY(x) (((x) & 1) << 22)

965

#define S_008010_SMX_BUSY(x) (((x) & 1) << 23)

966

#define S_008010_SC_BUSY(x) (((x) & 1) << 24)

967

#define S_008010_PA_BUSY(x) (((x) & 1) << 25)

968

#define S_008010_DB03_BUSY(x) (((x) & 1) << 26)

969

#define S_008010_CR_BUSY(x) (((x) & 1) << 27)

970

#define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28)

971

#define S_008010_CP_BUSY(x) (((x) & 1) << 29)

972

#define S_008010_CB03_BUSY(x) (((x) & 1) << 30)

973

#define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31)

974

#define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F)

975

#define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1)

976

#define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1)

977

#define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1)

978

#define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1)

979

#define G_008010_VC_BUSY(x) (((x) >> 11) & 1)

980

#define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1)

981

#define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1)

982

#define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1)

983

#define G_008010_VGT_BUSY(x) (((x) >> 17) & 1)

984

#define G_008010_TA03_BUSY(x) (((x) >> 18) & 1)

985

#define G_008010_TC_BUSY(x) (((x) >> 19) & 1)

986

#define G_008010_SX_BUSY(x) (((x) >> 20) & 1)

987

#define G_008010_SH_BUSY(x) (((x) >> 21) & 1)

988

#define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1)

989

#define G_008010_SMX_BUSY(x) (((x) >> 23) & 1)

990

#define G_008010_SC_BUSY(x) (((x) >> 24) & 1)

991

#define G_008010_PA_BUSY(x) (((x) >> 25) & 1)

992

#define G_008010_DB03_BUSY(x) (((x) >> 26) & 1)

993

#define G_008010_CR_BUSY(x) (((x) >> 27) & 1)

994

#define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1)

995

#define G_008010_CP_BUSY(x) (((x) >> 29) & 1)

996

#define G_008010_CB03_BUSY(x) (((x) >> 30) & 1)

997

#define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1)

998

#define R_008014_GRBM_STATUS2 0x8014

999

#define S_008014_CR_CLEAN(x) (((x) & 1) << 0)

1000

#define S_008014_SMX_CLEAN(x) (((x) & 1) << 1)

1001

#define S_008014_SPI0_BUSY(x) (((x) & 1) << 8)

1002

#define S_008014_SPI1_BUSY(x) (((x) & 1) << 9)

1003

#define S_008014_SPI2_BUSY(x) (((x) & 1) << 10)

1004

#define S_008014_SPI3_BUSY(x) (((x) & 1) << 11)

1005

#define S_008014_TA0_BUSY(x) (((x) & 1) << 12)

1006

#define S_008014_TA1_BUSY(x) (((x) & 1) << 13)

1007

#define S_008014_TA2_BUSY(x) (((x) & 1) << 14)

1008

#define S_008014_TA3_BUSY(x) (((x) & 1) << 15)

1009

#define S_008014_DB0_BUSY(x) (((x) & 1) << 16)

1010

#define S_008014_DB1_BUSY(x) (((x) & 1) << 17)

1011

#define S_008014_DB2_BUSY(x) (((x) & 1) << 18)

1012

#define S_008014_DB3_BUSY(x) (((x) & 1) << 19)

1013

#define S_008014_CB0_BUSY(x) (((x) & 1) << 20)

1014

#define S_008014_CB1_BUSY(x) (((x) & 1) << 21)

1015

#define S_008014_CB2_BUSY(x) (((x) & 1) << 22)

1016

#define S_008014_CB3_BUSY(x) (((x) & 1) << 23)

1017

#define G_008014_CR_CLEAN(x) (((x) >> 0) & 1)

1018

#define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1)

1019

#define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1)

1020

#define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1)

1021

#define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1)

1022

#define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1)

1023

#define G_008014_TA0_BUSY(x) (((x) >> 12) & 1)

1024

#define G_008014_TA1_BUSY(x) (((x) >> 13) & 1)

1025

#define G_008014_TA2_BUSY(x) (((x) >> 14) & 1)

1026

#define G_008014_TA3_BUSY(x) (((x) >> 15) & 1)

1027

#define G_008014_DB0_BUSY(x) (((x) >> 16) & 1)

1028

#define G_008014_DB1_BUSY(x) (((x) >> 17) & 1)

1029

#define G_008014_DB2_BUSY(x) (((x) >> 18) & 1)

1030

#define G_008014_DB3_BUSY(x) (((x) >> 19) & 1)

1031

#define G_008014_CB0_BUSY(x) (((x) >> 20) & 1)

1032

#define G_008014_CB1_BUSY(x) (((x) >> 21) & 1)

1033

#define G_008014_CB2_BUSY(x) (((x) >> 22) & 1)

1034

#define G_008014_CB3_BUSY(x) (((x) >> 23) & 1)

1035

#define R_000E50_SRBM_STATUS 0x0E50

1036

#define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1)

1037

#define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1)

1038

#define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1)

1039

#define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1)

1040

#define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1)

1041

#define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1)

1042

#define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1)

1043

#define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1)

1044

#define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1)

1045

#define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1)

1046

#define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1)

1047

#define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1)

1048

#define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1)

Jerome Glisse

1a029b7

2009-10-06 19:04:30 +0200

[diff] [blame]

1049

#define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1)

Jerome Glisse

2009-09-08 10:10:24 +1000

[diff] [blame]

1050

#define R_000E60_SRBM_SOFT_RESET 0x0E60

1051

#define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1)

1052

#define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2)

1053

#define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3)

1054

#define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4)

1055

#define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5)

1056

#define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8)

1057

#define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9)

1058

#define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10)

1059

#define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11)

1060

#define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13)

1061

#define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14)

1062

#define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15)

1063

#define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16)

1064

#define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17)

1065

Dave Airlie

23956df

2009-11-23 12:01:09 +1000

[diff] [blame]

1066

#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480

Jerome Glisse

c8c15ff

2010-01-18 13:01:36 +0100

[diff] [blame]

1067

Jerome Glisse

2010-02-10 22:30:05 +0000

[diff] [blame]

1068

#define R_028C04_PA_SC_AA_CONFIG 0x028C04

1069

#define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0)

1070

#define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3)

1071

#define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC

1072

#define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4)

1073

#define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1)

1074

#define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF

1075

#define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13)

1076

#define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF)

1077

#define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF

Jerome Glisse

c8c15ff

2010-01-18 13:01:36 +0100

[diff] [blame]

1078

#define R_0280E0_CB_COLOR0_FRAG 0x0280E0

1079

#define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)

1080

#define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)

1081

#define C_0280E0_BASE_256B 0x00000000

1082

#define R_0280E4_CB_COLOR1_FRAG 0x0280E4

1083

#define R_0280E8_CB_COLOR2_FRAG 0x0280E8

1084

#define R_0280EC_CB_COLOR3_FRAG 0x0280EC

1085

#define R_0280F0_CB_COLOR4_FRAG 0x0280F0

1086

#define R_0280F4_CB_COLOR5_FRAG 0x0280F4

1087

#define R_0280F8_CB_COLOR6_FRAG 0x0280F8

1088

#define R_0280FC_CB_COLOR7_FRAG 0x0280FC

1089

#define R_0280C0_CB_COLOR0_TILE 0x0280C0

1090

#define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)

1091

#define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)

1092

#define C_0280C0_BASE_256B 0x00000000

1093

#define R_0280C4_CB_COLOR1_TILE 0x0280C4

1094

#define R_0280C8_CB_COLOR2_TILE 0x0280C8

1095

#define R_0280CC_CB_COLOR3_TILE 0x0280CC

1096

#define R_0280D0_CB_COLOR4_TILE 0x0280D0

1097

#define R_0280D4_CB_COLOR5_TILE 0x0280D4

1098

#define R_0280D8_CB_COLOR6_TILE 0x0280D8

1099

#define R_0280DC_CB_COLOR7_TILE 0x0280DC

Jerome Glisse

2010-02-10 22:30:05 +0000

[diff] [blame]

1100

#define R_0280A0_CB_COLOR0_INFO 0x0280A0

1101

#define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0)

1102

#define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3)

1103

#define C_0280A0_ENDIAN 0xFFFFFFFC

1104

#define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2)

1105

#define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F)

1106

#define C_0280A0_FORMAT 0xFFFFFF03

1107

#define V_0280A0_COLOR_INVALID 0x00000000

1108

#define V_0280A0_COLOR_8 0x00000001

1109

#define V_0280A0_COLOR_4_4 0x00000002

1110

#define V_0280A0_COLOR_3_3_2 0x00000003

1111

#define V_0280A0_COLOR_16 0x00000005

1112

#define V_0280A0_COLOR_16_FLOAT 0x00000006

1113

#define V_0280A0_COLOR_8_8 0x00000007

1114

#define V_0280A0_COLOR_5_6_5 0x00000008

1115

#define V_0280A0_COLOR_6_5_5 0x00000009

1116

#define V_0280A0_COLOR_1_5_5_5 0x0000000A

1117

#define V_0280A0_COLOR_4_4_4_4 0x0000000B

1118

#define V_0280A0_COLOR_5_5_5_1 0x0000000C

1119

#define V_0280A0_COLOR_32 0x0000000D

1120

#define V_0280A0_COLOR_32_FLOAT 0x0000000E

1121

#define V_0280A0_COLOR_16_16 0x0000000F

1122

#define V_0280A0_COLOR_16_16_FLOAT 0x00000010

1123

#define V_0280A0_COLOR_8_24 0x00000011

1124

#define V_0280A0_COLOR_8_24_FLOAT 0x00000012

1125

#define V_0280A0_COLOR_24_8 0x00000013

1126

#define V_0280A0_COLOR_24_8_FLOAT 0x00000014

1127

#define V_0280A0_COLOR_10_11_11 0x00000015

1128

#define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016

1129

#define V_0280A0_COLOR_11_11_10 0x00000017

1130

#define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018

1131

#define V_0280A0_COLOR_2_10_10_10 0x00000019

1132

#define V_0280A0_COLOR_8_8_8_8 0x0000001A

1133

#define V_0280A0_COLOR_10_10_10_2 0x0000001B

1134

#define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C

1135

#define V_0280A0_COLOR_32_32 0x0000001D

1136

#define V_0280A0_COLOR_32_32_FLOAT 0x0000001E

1137

#define V_0280A0_COLOR_16_16_16_16 0x0000001F

1138

#define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020

1139

#define V_0280A0_COLOR_32_32_32_32 0x00000022

1140

#define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023

1141

#define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8)

1142

#define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF)

1143

#define C_0280A0_ARRAY_MODE 0xFFFFF0FF

1144

#define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000

1145

#define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001

1146

#define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002

1147

#define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004

1148

#define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12)

1149

#define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7)

1150

#define C_0280A0_NUMBER_TYPE 0xFFFF8FFF

1151

#define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15)

1152

#define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1)

1153

#define C_0280A0_READ_SIZE 0xFFFF7FFF

1154

#define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16)

1155

#define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3)

1156

#define C_0280A0_COMP_SWAP 0xFFFCFFFF

1157

#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18)

1158

#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3)

1159

#define C_0280A0_TILE_MODE 0xFFF3FFFF

1160

#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20)

1161

#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1)

1162

#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF

1163

#define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21)

1164

#define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1)

1165

#define C_0280A0_CLEAR_COLOR 0xFFDFFFFF

1166

#define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22)

1167

#define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1)

1168

#define C_0280A0_BLEND_BYPASS 0xFFBFFFFF

1169

#define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23)

1170

#define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1)

1171

#define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF

1172

#define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24)

1173

#define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1)

1174

#define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF

1175

#define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25)

1176

#define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1)

1177

#define C_0280A0_ROUND_MODE 0xFDFFFFFF

1178

#define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26)

1179

#define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1)

1180

#define C_0280A0_TILE_COMPACT 0xFBFFFFFF

1181

#define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27)

1182

#define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1)

1183

#define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF

1184

#define R_0280A4_CB_COLOR1_INFO 0x0280A4

1185

#define R_0280A8_CB_COLOR2_INFO 0x0280A8

1186

#define R_0280AC_CB_COLOR3_INFO 0x0280AC

1187

#define R_0280B0_CB_COLOR4_INFO 0x0280B0

1188

#define R_0280B4_CB_COLOR5_INFO 0x0280B4

1189

#define R_0280B8_CB_COLOR6_INFO 0x0280B8

1190

#define R_0280BC_CB_COLOR7_INFO 0x0280BC

1191

#define R_028060_CB_COLOR0_SIZE 0x028060

1192

#define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)

1193

#define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)

1194

#define C_028060_PITCH_TILE_MAX 0xFFFFFC00

1195

#define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)

1196

#define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)

1197

#define C_028060_SLICE_TILE_MAX 0xC00003FF

1198

#define R_028064_CB_COLOR1_SIZE 0x028064

1199

#define R_028068_CB_COLOR2_SIZE 0x028068

1200

#define R_02806C_CB_COLOR3_SIZE 0x02806C

1201

#define R_028070_CB_COLOR4_SIZE 0x028070

1202

#define R_028074_CB_COLOR5_SIZE 0x028074

1203

#define R_028078_CB_COLOR6_SIZE 0x028078

1204

#define R_02807C_CB_COLOR7_SIZE 0x02807C

1205

#define R_028238_CB_TARGET_MASK 0x028238

1206

#define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0)

1207

#define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF)

1208

#define C_028238_TARGET0_ENABLE 0xFFFFFFF0

1209

#define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4)

1210

#define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF)

1211

#define C_028238_TARGET1_ENABLE 0xFFFFFF0F

1212

#define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8)

1213

#define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF)

1214

#define C_028238_TARGET2_ENABLE 0xFFFFF0FF

1215

#define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12)

1216

#define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF)

1217

#define C_028238_TARGET3_ENABLE 0xFFFF0FFF

1218

#define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16)

1219

#define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF)

1220

#define C_028238_TARGET4_ENABLE 0xFFF0FFFF

1221

#define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20)

1222

#define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF)

1223

#define C_028238_TARGET5_ENABLE 0xFF0FFFFF

1224

#define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24)

1225

#define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF)

1226

#define C_028238_TARGET6_ENABLE 0xF0FFFFFF

1227

#define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28)

1228

#define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF)

1229

#define C_028238_TARGET7_ENABLE 0x0FFFFFFF

1230

#define R_02823C_CB_SHADER_MASK 0x02823C

1231

#define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0)

1232

#define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF)

1233

#define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0

1234

#define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4)

1235

#define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF)

1236

#define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F

1237

#define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8)

1238

#define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF)

1239

#define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF

1240

#define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12)

1241

#define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF)

1242

#define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF

1243

#define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16)

1244

#define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF)

1245

#define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF

1246

#define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20)

1247

#define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF)

1248

#define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF

1249

#define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24)

1250

#define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF)

1251

#define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF

1252

#define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28)

1253

#define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF)

1254

#define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF

1255

#define R_028AB0_VGT_STRMOUT_EN 0x028AB0

1256

#define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0)

1257

#define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1)

1258

#define C_028AB0_STREAMOUT 0xFFFFFFFE

1259

#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20

1260

#define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0)

1261

#define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1)

1262

#define C_028B20_BUFFER_0_EN 0xFFFFFFFE

1263

#define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1)

1264

#define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1)

1265

#define C_028B20_BUFFER_1_EN 0xFFFFFFFD

1266

#define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2)

1267

#define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1)

1268

#define C_028B20_BUFFER_2_EN 0xFFFFFFFB

1269

#define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3)

1270

#define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1)

1271

#define C_028B20_BUFFER_3_EN 0xFFFFFFF7

1272

#define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1273

#define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1274

#define C_028B20_SIZE 0x00000000

1275

#define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000

1276

#define S_038000_DIM(x) (((x) & 0x7) << 0)

1277

#define G_038000_DIM(x) (((x) >> 0) & 0x7)

1278

#define C_038000_DIM 0xFFFFFFF8

1279

#define V_038000_SQ_TEX_DIM_1D 0x00000000

1280

#define V_038000_SQ_TEX_DIM_2D 0x00000001

1281

#define V_038000_SQ_TEX_DIM_3D 0x00000002

1282

#define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003

1283

#define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004

1284

#define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005

1285

#define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006

1286

#define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007

1287

#define S_038000_TILE_MODE(x) (((x) & 0xF) << 3)

1288

#define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF)

1289

#define C_038000_TILE_MODE 0xFFFFFF87

Alex Deucher

7f81337

2010-05-20 12:43:52 -0400

[diff] [blame]

1290

#define V_038000_ARRAY_LINEAR_GENERAL 0x00000000

1291

#define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001

1292

#define V_038000_ARRAY_1D_TILED_THIN1 0x00000002

1293

#define V_038000_ARRAY_2D_TILED_THIN1 0x00000004

Jerome Glisse

2010-02-10 22:30:05 +0000

[diff] [blame]

1294

#define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7)

1295

#define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1)

1296

#define C_038000_TILE_TYPE 0xFFFFFF7F

1297

#define S_038000_PITCH(x) (((x) & 0x7FF) << 8)

1298

#define G_038000_PITCH(x) (((x) >> 8) & 0x7FF)

1299

#define C_038000_PITCH 0xFFF800FF

1300

#define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19)

1301

#define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF)

1302

#define C_038000_TEX_WIDTH 0x0007FFFF

1303

#define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004

1304

#define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0)

1305

#define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF)

1306

#define C_038004_TEX_HEIGHT 0xFFFFE000

1307

#define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13)

1308

#define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF)

1309

#define C_038004_TEX_DEPTH 0xFC001FFF

1310

#define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26)

1311

#define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F)

1312

#define C_038004_DATA_FORMAT 0x03FFFFFF

1313

#define V_038004_COLOR_INVALID 0x00000000

1314

#define V_038004_COLOR_8 0x00000001

1315

#define V_038004_COLOR_4_4 0x00000002

1316

#define V_038004_COLOR_3_3_2 0x00000003

1317

#define V_038004_COLOR_16 0x00000005

1318

#define V_038004_COLOR_16_FLOAT 0x00000006

1319

#define V_038004_COLOR_8_8 0x00000007

1320

#define V_038004_COLOR_5_6_5 0x00000008

1321

#define V_038004_COLOR_6_5_5 0x00000009

1322

#define V_038004_COLOR_1_5_5_5 0x0000000A

1323

#define V_038004_COLOR_4_4_4_4 0x0000000B

1324

#define V_038004_COLOR_5_5_5_1 0x0000000C

1325

#define V_038004_COLOR_32 0x0000000D

1326

#define V_038004_COLOR_32_FLOAT 0x0000000E

1327

#define V_038004_COLOR_16_16 0x0000000F

1328

#define V_038004_COLOR_16_16_FLOAT 0x00000010

1329

#define V_038004_COLOR_8_24 0x00000011

1330

#define V_038004_COLOR_8_24_FLOAT 0x00000012

1331

#define V_038004_COLOR_24_8 0x00000013

1332

#define V_038004_COLOR_24_8_FLOAT 0x00000014

1333

#define V_038004_COLOR_10_11_11 0x00000015

1334

#define V_038004_COLOR_10_11_11_FLOAT 0x00000016

1335

#define V_038004_COLOR_11_11_10 0x00000017

1336

#define V_038004_COLOR_11_11_10_FLOAT 0x00000018

1337

#define V_038004_COLOR_2_10_10_10 0x00000019

1338

#define V_038004_COLOR_8_8_8_8 0x0000001A

1339

#define V_038004_COLOR_10_10_10_2 0x0000001B

1340

#define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C

1341

#define V_038004_COLOR_32_32 0x0000001D

1342

#define V_038004_COLOR_32_32_FLOAT 0x0000001E

1343

#define V_038004_COLOR_16_16_16_16 0x0000001F

1344

#define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020

1345

#define V_038004_COLOR_32_32_32_32 0x00000022

1346

#define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023

1347

#define V_038004_FMT_1 0x00000025

1348

#define V_038004_FMT_GB_GR 0x00000027

1349

#define V_038004_FMT_BG_RG 0x00000028

1350

#define V_038004_FMT_32_AS_8 0x00000029

1351

#define V_038004_FMT_32_AS_8_8 0x0000002A

1352

#define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B

1353

#define V_038004_FMT_8_8_8 0x0000002C

1354

#define V_038004_FMT_16_16_16 0x0000002D

1355

#define V_038004_FMT_16_16_16_FLOAT 0x0000002E

1356

#define V_038004_FMT_32_32_32 0x0000002F

1357

#define V_038004_FMT_32_32_32_FLOAT 0x00000030

Dave Airlie

60b212f

2011-02-18 05:51:58 +0000

[diff] [blame]

1358

#define V_038004_FMT_BC1 0x00000031

1359

#define V_038004_FMT_BC2 0x00000032

1360

#define V_038004_FMT_BC3 0x00000033

1361

#define V_038004_FMT_BC4 0x00000034

1362

#define V_038004_FMT_BC5 0x00000035

Marek Olšák

fe6f0bd

2011-05-07 01:09:57 +0200

[diff] [blame]

1363

#define V_038004_FMT_BC6 0x00000036

1364

#define V_038004_FMT_BC7 0x00000037

1365

#define V_038004_FMT_32_AS_32_32_32_32 0x00000038

Jerome Glisse

2010-02-10 22:30:05 +0000

[diff] [blame]

1366

#define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010

1367

#define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0)

1368

#define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3)

1369

#define C_038010_FORMAT_COMP_X 0xFFFFFFFC

1370

#define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2)

1371

#define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3)

1372

#define C_038010_FORMAT_COMP_Y 0xFFFFFFF3

1373

#define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4)

1374

#define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3)

1375

#define C_038010_FORMAT_COMP_Z 0xFFFFFFCF

1376

#define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6)

1377

#define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3)

1378

#define C_038010_FORMAT_COMP_W 0xFFFFFF3F

1379

#define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8)

1380

#define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3)

1381

#define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF

1382

#define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10)

1383

#define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1)

1384

#define C_038010_SRF_MODE_ALL 0xFFFFFBFF

1385

#define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11)

1386

#define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1)

1387

#define C_038010_FORCE_DEGAMMA 0xFFFFF7FF

1388

#define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12)

1389

#define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3)

1390

#define C_038010_ENDIAN_SWAP 0xFFFFCFFF

1391

#define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14)

1392

#define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3)

1393

#define C_038010_REQUEST_SIZE 0xFFFF3FFF

1394

#define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16)

1395

#define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7)

1396

#define C_038010_DST_SEL_X 0xFFF8FFFF

1397

#define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19)

1398

#define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7)

1399

#define C_038010_DST_SEL_Y 0xFFC7FFFF

1400

#define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22)

1401

#define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7)

1402

#define C_038010_DST_SEL_Z 0xFE3FFFFF

1403

#define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25)

1404

#define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7)

1405

#define C_038010_DST_SEL_W 0xF1FFFFFF

Ilija Hadzic

3a38612

2011-10-12 23:29:37 -0400

[diff] [blame]

# define SQ_SEL_X 0

# define SQ_SEL_Y 1

# define SQ_SEL_Z 2

# define SQ_SEL_W 3

# define SQ_SEL_0 4

# define SQ_SEL_1 5

Jerome Glisse

2010-02-10 22:30:05 +0000

[diff] [blame]

1412

#define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28)

1413

#define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF)

1414

#define C_038010_BASE_LEVEL 0x0FFFFFFF

1415

#define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014

1416

#define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0)

1417

#define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF)

1418

#define C_038014_LAST_LEVEL 0xFFFFFFF0

1419

#define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4)

1420

#define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF)

1421

#define C_038014_BASE_ARRAY 0xFFFE000F

1422

#define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17)

1423

#define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF)

1424

#define C_038014_LAST_ARRAY 0xC001FFFF

1425

#define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8

1426

#define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1427

#define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1428

#define C_0288A8_ITEMSIZE 0xFFFF8000

1429

#define R_008C44_SQ_ESGS_RING_SIZE 0x008C44

1430

#define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1431

#define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1432

#define C_008C44_MEM_SIZE 0x00000000

1433

#define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0

1434

#define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1435

#define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1436

#define C_0288B0_ITEMSIZE 0xFFFF8000

1437

#define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54

1438

#define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1439

#define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1440

#define C_008C54_MEM_SIZE 0x00000000

1441

#define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0

1442

#define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1443

#define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1444

#define C_0288C0_ITEMSIZE 0xFFFF8000

1445

#define R_008C74_SQ_FBUF_RING_SIZE 0x008C74

1446

#define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1447

#define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1448

#define C_008C74_MEM_SIZE 0x00000000

1449

#define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4

1450

#define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1451

#define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1452

#define C_0288B4_ITEMSIZE 0xFFFF8000

1453

#define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C

1454

#define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1455

#define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1456

#define C_008C5C_MEM_SIZE 0x00000000

1457

#define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC

1458

#define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1459

#define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1460

#define C_0288AC_ITEMSIZE 0xFFFF8000

1461

#define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C

1462

#define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1463

#define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1464

#define C_008C4C_MEM_SIZE 0x00000000

1465

#define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC

1466

#define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1467

#define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1468

#define C_0288BC_ITEMSIZE 0xFFFF8000

1469

#define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C

1470

#define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1471

#define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1472

#define C_008C6C_MEM_SIZE 0x00000000

1473

#define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4

1474

#define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1475

#define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1476

#define C_0288C4_ITEMSIZE 0xFFFF8000

1477

#define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C

1478

#define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1479

#define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1480

#define C_008C7C_MEM_SIZE 0x00000000

1481

#define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8

1482

#define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1483

#define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1484

#define C_0288B8_ITEMSIZE 0xFFFF8000

1485

#define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64

1486

#define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0)

1487

#define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF)

1488

#define C_008C64_MEM_SIZE 0x00000000

1489

#define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8

1490

#define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0)

1491

#define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF)

1492

#define C_0288C8_ITEMSIZE 0xFFFF8000

1493

#define R_028010_DB_DEPTH_INFO 0x028010

1494

#define S_028010_FORMAT(x) (((x) & 0x7) << 0)

1495

#define G_028010_FORMAT(x) (((x) >> 0) & 0x7)

1496

#define C_028010_FORMAT 0xFFFFFFF8

1497

#define V_028010_DEPTH_INVALID 0x00000000

1498

#define V_028010_DEPTH_16 0x00000001

1499

#define V_028010_DEPTH_X8_24 0x00000002

1500

#define V_028010_DEPTH_8_24 0x00000003

1501

#define V_028010_DEPTH_X8_24_FLOAT 0x00000004

1502

#define V_028010_DEPTH_8_24_FLOAT 0x00000005

1503

#define V_028010_DEPTH_32_FLOAT 0x00000006

1504

#define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007

1505

#define S_028010_READ_SIZE(x) (((x) & 0x1) << 3)

1506

#define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1)

1507

#define C_028010_READ_SIZE 0xFFFFFFF7

1508

#define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15)

1509

#define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF)

1510

#define C_028010_ARRAY_MODE 0xFFF87FFF

Alex Deucher

7f81337

2010-05-20 12:43:52 -0400

[diff] [blame]

1511

#define V_028010_ARRAY_1D_TILED_THIN1 0x00000002

1512

#define V_028010_ARRAY_2D_TILED_THIN1 0x00000004

Jerome Glisse

2010-02-10 22:30:05 +0000

[diff] [blame]

1513

#define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25)

1514

#define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1)

1515

#define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF

1516

#define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26)

1517

#define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1)

1518

#define C_028010_TILE_COMPACT 0xFBFFFFFF

1519

#define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)

1520

#define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)

1521

#define C_028010_ZRANGE_PRECISION 0x7FFFFFFF

1522

#define R_028000_DB_DEPTH_SIZE 0x028000

1523

#define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0)

1524

#define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF)

1525

#define C_028000_PITCH_TILE_MAX 0xFFFFFC00

1526

#define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10)

1527

#define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF)

1528

#define C_028000_SLICE_TILE_MAX 0xC00003FF

1529

#define R_028004_DB_DEPTH_VIEW 0x028004

1530

#define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0)

1531

#define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF)

1532

#define C_028004_SLICE_START 0xFFFFF800

1533

#define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13)

1534

#define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF)

1535

#define C_028004_SLICE_MAX 0xFF001FFF

1536

#define R_028800_DB_DEPTH_CONTROL 0x028800

1537

#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)

1538

#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)

1539

#define C_028800_STENCIL_ENABLE 0xFFFFFFFE

1540

#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)

1541

#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)

1542

#define C_028800_Z_ENABLE 0xFFFFFFFD

1543

#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)

1544

#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)

1545

#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB

1546

#define S_028800_ZFUNC(x) (((x) & 0x7) << 4)

1547

#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7)

1548

#define C_028800_ZFUNC 0xFFFFFF8F

1549

#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)

1550

#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)

1551

#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F

1552

#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8)

1553

#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7)

1554

#define C_028800_STENCILFUNC 0xFFFFF8FF

1555

#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11)

1556

#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7)

1557

#define C_028800_STENCILFAIL 0xFFFFC7FF

1558

#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14)

1559

#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7)

1560

#define C_028800_STENCILZPASS 0xFFFE3FFF

1561

#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17)

1562

#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7)

1563

#define C_028800_STENCILZFAIL 0xFFF1FFFF

1564

#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20)

1565

#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7)

1566

#define C_028800_STENCILFUNC_BF 0xFF8FFFFF

1567

#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23)

1568

#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7)

1569

#define C_028800_STENCILFAIL_BF 0xFC7FFFFF

1570

#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26)

1571

#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7)

1572

#define C_028800_STENCILZPASS_BF 0xE3FFFFFF

1573

#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29)

1574

#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7)

1575

#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF

Jerome Glisse

c8c15ff

2010-01-18 13:01:36 +0100

[diff] [blame]

1576

Jerome Glisse