blob: af8f0af8c9020e90e8f17dcf15b3bb3ac9f87207 [file] [log] [blame]
Manu Gautam5143b252012-01-05 19:25:23 -08001/* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/ctype.h>
17#include <linux/bitops.h>
18#include <linux/io.h>
19#include <linux/spinlock.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22
23#include <asm/clkdev.h>
24#include <asm/mach-types.h>
25
26#include <mach/msm_iomap.h>
27#include <mach/clk.h>
28#include <mach/rpm-regulator.h>
Stephen Boyd94625ef2011-07-12 17:06:01 -070029#include <mach/socinfo.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070030
31#include "clock-local.h"
32#include "clock-rpm.h"
33#include "clock-voter.h"
34#include "clock-dss-8960.h"
35#include "devices.h"
36
37#define REG(off) (MSM_CLK_CTL_BASE + (off))
38#define REG_MM(off) (MSM_MMSS_CLK_CTL_BASE + (off))
39#define REG_LPA(off) (MSM_LPASS_CLK_CTL_BASE + (off))
Matt Wagantall8b38f942011-08-02 18:23:18 -070040#define REG_GCC(off) (MSM_APCS_GCC_BASE + (off))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070041
42/* Peripheral clock registers. */
Stephen Boyda52d7e32011-11-10 11:59:00 -080043#define ADM0_PBUS_CLK_CTL_REG REG(0x2208)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070044#define CE1_HCLK_CTL_REG REG(0x2720)
45#define CE1_CORE_CLK_CTL_REG REG(0x2724)
Tianyi Gou05e01102012-02-08 22:15:49 -080046#define PRNG_CLK_NS_REG REG(0x2E80)
Tianyi Gou41515e22011-09-01 19:37:43 -070047#define CE3_HCLK_CTL_REG REG(0x36C4)
48#define CE3_CORE_CLK_CTL_REG REG(0x36CC)
49#define CE3_CLK_SRC_NS_REG REG(0x36C0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070050#define DMA_BAM_HCLK_CTL REG(0x25C0)
Tianyi Gou41515e22011-09-01 19:37:43 -070051#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070052#define CLK_HALT_CFPB_STATEA_REG REG(0x2FCC)
53#define CLK_HALT_CFPB_STATEB_REG REG(0x2FD0)
54#define CLK_HALT_CFPB_STATEC_REG REG(0x2FD4)
55#define CLK_HALT_DFAB_STATE_REG REG(0x2FC8)
Tianyi Gou41515e22011-09-01 19:37:43 -070056/* 8064 name CLK_HALT_GSS_KPSS_MISC_STATE_REG */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070057#define CLK_HALT_MSS_SMPSS_MISC_STATE_REG REG(0x2FDC)
58#define CLK_HALT_SFPB_MISC_STATE_REG REG(0x2FD8)
Stephen Boyd973e4ba2011-07-12 17:06:01 -070059#define CLK_HALT_AFAB_SFAB_STATEB_REG REG(0x2FC4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070060#define CLK_TEST_REG REG(0x2FA0)
Matt Wagantall7625a4c2011-11-01 16:17:53 -070061#define GPn_MD_REG(n) REG(0x2D00+(0x20*(n)))
62#define GPn_NS_REG(n) REG(0x2D24+(0x20*(n)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070063#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
64#define GSBIn_QUP_APPS_MD_REG(n) REG(0x29C8+(0x20*((n)-1)))
65#define GSBIn_QUP_APPS_NS_REG(n) REG(0x29CC+(0x20*((n)-1)))
66#define GSBIn_RESET_REG(n) REG(0x29DC+(0x20*((n)-1)))
67#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1)))
68#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070069#define PDM_CLK_NS_REG REG(0x2CC0)
Tianyi Gou41515e22011-09-01 19:37:43 -070070/* 8064 name BB_PLL_ENA_APCS_REG */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070071#define BB_PLL_ENA_SC0_REG REG(0x34C0)
Tianyi Gou59608a72012-01-31 22:19:30 -080072#define BB_PLL_ENA_RPM_REG REG(0x34A0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070073#define BB_PLL0_STATUS_REG REG(0x30D8)
74#define BB_PLL5_STATUS_REG REG(0x30F8)
75#define BB_PLL6_STATUS_REG REG(0x3118)
76#define BB_PLL7_STATUS_REG REG(0x3138)
77#define BB_PLL8_L_VAL_REG REG(0x3144)
78#define BB_PLL8_M_VAL_REG REG(0x3148)
79#define BB_PLL8_MODE_REG REG(0x3140)
80#define BB_PLL8_N_VAL_REG REG(0x314C)
81#define BB_PLL8_STATUS_REG REG(0x3158)
82#define BB_PLL8_CONFIG_REG REG(0x3154)
83#define BB_PLL8_TEST_CTL_REG REG(0x3150)
Stephen Boyd94625ef2011-07-12 17:06:01 -070084#define BB_MMCC_PLL2_MODE_REG REG(0x3160)
85#define BB_MMCC_PLL2_TEST_CTL_REG REG(0x3170)
Tianyi Gou41515e22011-09-01 19:37:43 -070086#define BB_PLL14_MODE_REG REG(0x31C0)
87#define BB_PLL14_L_VAL_REG REG(0x31C4)
88#define BB_PLL14_M_VAL_REG REG(0x31C8)
89#define BB_PLL14_N_VAL_REG REG(0x31CC)
90#define BB_PLL14_TEST_CTL_REG REG(0x31D0)
91#define BB_PLL14_CONFIG_REG REG(0x31D4)
Stephen Boyd94625ef2011-07-12 17:06:01 -070092#define BB_PLL14_STATUS_REG REG(0x31D8)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070093#define PLLTEST_PAD_CFG_REG REG(0x2FA4)
94#define PMEM_ACLK_CTL_REG REG(0x25A0)
95#define RINGOSC_NS_REG REG(0x2DC0)
96#define RINGOSC_STATUS_REG REG(0x2DCC)
97#define RINGOSC_TCXO_CTL_REG REG(0x2DC4)
Stephen Boyda52d7e32011-11-10 11:59:00 -080098#define RPM_MSG_RAM_HCLK_CTL_REG REG(0x27E0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070099#define SC0_U_CLK_BRANCH_ENA_VOTE_REG REG(0x3080)
100#define SDCn_APPS_CLK_MD_REG(n) REG(0x2828+(0x20*((n)-1)))
101#define SDCn_APPS_CLK_NS_REG(n) REG(0x282C+(0x20*((n)-1)))
102#define SDCn_HCLK_CTL_REG(n) REG(0x2820+(0x20*((n)-1)))
103#define SDCn_RESET_REG(n) REG(0x2830+(0x20*((n)-1)))
104#define SLIMBUS_XO_SRC_CLK_CTL_REG REG(0x2628)
105#define TSIF_HCLK_CTL_REG REG(0x2700)
106#define TSIF_REF_CLK_MD_REG REG(0x270C)
107#define TSIF_REF_CLK_NS_REG REG(0x2710)
108#define TSSC_CLK_CTL_REG REG(0x2CA0)
Tianyi Gou41515e22011-09-01 19:37:43 -0700109#define SATA_CLK_SRC_NS_REG REG(0x2C08)
110#define SATA_RXOOB_CLK_CTL_REG REG(0x2C0C)
111#define SATA_PMALIVE_CLK_CTL_REG REG(0x2C10)
112#define SATA_PHY_REF_CLK_CTL_REG REG(0x2C14)
113#define SATA_PHY_CFG_CLK_CTL_REG REG(0x2C40)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700114#define USB_FSn_HCLK_CTL_REG(n) REG(0x2960+(0x20*((n)-1)))
115#define USB_FSn_RESET_REG(n) REG(0x2974+(0x20*((n)-1)))
116#define USB_FSn_SYSTEM_CLK_CTL_REG(n) REG(0x296C+(0x20*((n)-1)))
117#define USB_FSn_XCVR_FS_CLK_MD_REG(n) REG(0x2964+(0x20*((n)-1)))
118#define USB_FSn_XCVR_FS_CLK_NS_REG(n) REG(0x2968+(0x20*((n)-1)))
119#define USB_HS1_HCLK_CTL_REG REG(0x2900)
Tianyi Gou41515e22011-09-01 19:37:43 -0700120#define USB_HS1_HCLK_FS_REG REG(0x2904)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700121#define USB_HS1_RESET_REG REG(0x2910)
122#define USB_HS1_XCVR_FS_CLK_MD_REG REG(0x2908)
123#define USB_HS1_XCVR_FS_CLK_NS_REG REG(0x290C)
Tianyi Gou41515e22011-09-01 19:37:43 -0700124#define USB_HS3_HCLK_CTL_REG REG(0x3700)
125#define USB_HS3_HCLK_FS_REG REG(0x3704)
126#define USB_HS3_RESET_REG REG(0x3710)
127#define USB_HS3_XCVR_FS_CLK_MD_REG REG(0X3708)
128#define USB_HS3_XCVR_FS_CLK_NS_REG REG(0X370C)
129#define USB_HS4_HCLK_CTL_REG REG(0x3720)
130#define USB_HS4_HCLK_FS_REG REG(0x3724)
131#define USB_HS4_RESET_REG REG(0x3730)
132#define USB_HS4_XCVR_FS_CLK_MD_REG REG(0X3728)
133#define USB_HS4_XCVR_FS_CLK_NS_REG REG(0X372C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700134#define USB_HSIC_HCLK_CTL_REG REG(0x2920)
135#define USB_HSIC_HSIC_CLK_CTL_REG REG(0x2B44)
136#define USB_HSIC_HSIC_CLK_SRC_CTL_REG REG(0x2B40)
137#define USB_HSIC_HSIO_CAL_CLK_CTL_REG REG(0x2B48)
138#define USB_HSIC_RESET_REG REG(0x2934)
139#define USB_HSIC_SYSTEM_CLK_CTL_REG REG(0x292C)
140#define USB_HSIC_XCVR_FS_CLK_MD_REG REG(0x2924)
141#define USB_HSIC_XCVR_FS_CLK_NS_REG REG(0x2928)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700142#define USB_PHY0_RESET_REG REG(0x2E20)
Tianyi Gou41515e22011-09-01 19:37:43 -0700143#define PCIE_ALT_REF_CLK_NS_REG REG(0x3860)
144#define PCIE_HCLK_CTL_REG REG(0x22CC)
145#define GPLL1_MODE_REG REG(0x3160)
146#define GPLL1_L_VAL_REG REG(0x3164)
147#define GPLL1_M_VAL_REG REG(0x3168)
148#define GPLL1_N_VAL_REG REG(0x316C)
149#define GPLL1_CONFIG_REG REG(0x3174)
150#define GPLL1_STATUS_REG REG(0x3178)
151#define PXO_SRC_CLK_CTL_REG REG(0x2EA0)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700152
153/* Multimedia clock registers. */
154#define AHB_EN_REG REG_MM(0x0008)
155#define AHB_EN2_REG REG_MM(0x0038)
Tianyi Gou41515e22011-09-01 19:37:43 -0700156#define AHB_EN3_REG REG_MM(0x0248)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700157#define AHB_NS_REG REG_MM(0x0004)
158#define AXI_NS_REG REG_MM(0x0014)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700159#define CAMCLK0_NS_REG REG_MM(0x0148)
160#define CAMCLK0_CC_REG REG_MM(0x0140)
161#define CAMCLK0_MD_REG REG_MM(0x0144)
162#define CAMCLK1_NS_REG REG_MM(0x015C)
163#define CAMCLK1_CC_REG REG_MM(0x0154)
164#define CAMCLK1_MD_REG REG_MM(0x0158)
165#define CAMCLK2_NS_REG REG_MM(0x0228)
166#define CAMCLK2_CC_REG REG_MM(0x0220)
167#define CAMCLK2_MD_REG REG_MM(0x0224)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700168#define CSI0_NS_REG REG_MM(0x0048)
169#define CSI0_CC_REG REG_MM(0x0040)
170#define CSI0_MD_REG REG_MM(0x0044)
171#define CSI1_NS_REG REG_MM(0x0010)
172#define CSI1_CC_REG REG_MM(0x0024)
173#define CSI1_MD_REG REG_MM(0x0028)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700174#define CSI2_NS_REG REG_MM(0x0234)
175#define CSI2_CC_REG REG_MM(0x022C)
176#define CSI2_MD_REG REG_MM(0x0230)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700177#define CSIPHYTIMER_CC_REG REG_MM(0x0160)
178#define CSIPHYTIMER_MD_REG REG_MM(0x0164)
179#define CSIPHYTIMER_NS_REG REG_MM(0x0168)
180#define DSI1_BYTE_NS_REG REG_MM(0x00B0)
181#define DSI1_BYTE_CC_REG REG_MM(0x0090)
182#define DSI2_BYTE_NS_REG REG_MM(0x00BC)
183#define DSI2_BYTE_CC_REG REG_MM(0x00B4)
184#define DSI1_ESC_NS_REG REG_MM(0x011C)
185#define DSI1_ESC_CC_REG REG_MM(0x00CC)
186#define DSI2_ESC_NS_REG REG_MM(0x0150)
187#define DSI2_ESC_CC_REG REG_MM(0x013C)
188#define DSI_PIXEL_CC_REG REG_MM(0x0130)
189#define DSI2_PIXEL_CC_REG REG_MM(0x0094)
190#define DBG_BUS_VEC_A_REG REG_MM(0x01C8)
191#define DBG_BUS_VEC_B_REG REG_MM(0x01CC)
192#define DBG_BUS_VEC_C_REG REG_MM(0x01D0)
193#define DBG_BUS_VEC_D_REG REG_MM(0x01D4)
194#define DBG_BUS_VEC_E_REG REG_MM(0x01D8)
195#define DBG_BUS_VEC_F_REG REG_MM(0x01DC)
196#define DBG_BUS_VEC_G_REG REG_MM(0x01E0)
197#define DBG_BUS_VEC_H_REG REG_MM(0x01E4)
198#define DBG_BUS_VEC_I_REG REG_MM(0x01E8)
Tianyi Gou41515e22011-09-01 19:37:43 -0700199#define DBG_BUS_VEC_J_REG REG_MM(0x0240)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700200#define DBG_CFG_REG_HS_REG REG_MM(0x01B4)
201#define DBG_CFG_REG_LS_REG REG_MM(0x01B8)
202#define GFX2D0_CC_REG REG_MM(0x0060)
203#define GFX2D0_MD0_REG REG_MM(0x0064)
204#define GFX2D0_MD1_REG REG_MM(0x0068)
205#define GFX2D0_NS_REG REG_MM(0x0070)
206#define GFX2D1_CC_REG REG_MM(0x0074)
207#define GFX2D1_MD0_REG REG_MM(0x0078)
208#define GFX2D1_MD1_REG REG_MM(0x006C)
209#define GFX2D1_NS_REG REG_MM(0x007C)
210#define GFX3D_CC_REG REG_MM(0x0080)
211#define GFX3D_MD0_REG REG_MM(0x0084)
212#define GFX3D_MD1_REG REG_MM(0x0088)
213#define GFX3D_NS_REG REG_MM(0x008C)
214#define IJPEG_CC_REG REG_MM(0x0098)
215#define IJPEG_MD_REG REG_MM(0x009C)
216#define IJPEG_NS_REG REG_MM(0x00A0)
217#define JPEGD_CC_REG REG_MM(0x00A4)
218#define JPEGD_NS_REG REG_MM(0x00AC)
Tianyi Gou41515e22011-09-01 19:37:43 -0700219#define VCAP_CC_REG REG_MM(0x0178)
220#define VCAP_NS_REG REG_MM(0x021C)
221#define VCAP_MD0_REG REG_MM(0x01EC)
222#define VCAP_MD1_REG REG_MM(0x0218)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700223#define MAXI_EN_REG REG_MM(0x0018)
224#define MAXI_EN2_REG REG_MM(0x0020)
225#define MAXI_EN3_REG REG_MM(0x002C)
226#define MAXI_EN4_REG REG_MM(0x0114)
Tianyi Gou41515e22011-09-01 19:37:43 -0700227#define MAXI_EN5_REG REG_MM(0x0244)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700228#define MDP_CC_REG REG_MM(0x00C0)
229#define MDP_LUT_CC_REG REG_MM(0x016C)
230#define MDP_MD0_REG REG_MM(0x00C4)
231#define MDP_MD1_REG REG_MM(0x00C8)
232#define MDP_NS_REG REG_MM(0x00D0)
233#define MISC_CC_REG REG_MM(0x0058)
234#define MISC_CC2_REG REG_MM(0x005C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700235#define MISC_CC3_REG REG_MM(0x0238)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700236#define MM_PLL1_MODE_REG REG_MM(0x031C)
Tianyi Gou41515e22011-09-01 19:37:43 -0700237#define MM_PLL1_L_VAL_REG REG_MM(0x0320)
238#define MM_PLL1_M_VAL_REG REG_MM(0x0324)
239#define MM_PLL1_N_VAL_REG REG_MM(0x0328)
240#define MM_PLL1_CONFIG_REG REG_MM(0x032C)
241#define MM_PLL1_TEST_CTL_REG REG_MM(0x0330)
242#define MM_PLL1_STATUS_REG REG_MM(0x0334)
243#define MM_PLL3_MODE_REG REG_MM(0x0338)
Tianyi Gou621f8742011-09-01 21:45:01 -0700244#define MM_PLL3_L_VAL_REG REG_MM(0x033C)
245#define MM_PLL3_M_VAL_REG REG_MM(0x0340)
246#define MM_PLL3_N_VAL_REG REG_MM(0x0344)
247#define MM_PLL3_CONFIG_REG REG_MM(0x0348)
248#define MM_PLL3_TEST_CTL_REG REG_MM(0x034C)
249#define MM_PLL3_STATUS_REG REG_MM(0x0350)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700250#define ROT_CC_REG REG_MM(0x00E0)
251#define ROT_NS_REG REG_MM(0x00E8)
252#define SAXI_EN_REG REG_MM(0x0030)
253#define SW_RESET_AHB_REG REG_MM(0x020C)
254#define SW_RESET_AHB2_REG REG_MM(0x0200)
255#define SW_RESET_ALL_REG REG_MM(0x0204)
256#define SW_RESET_AXI_REG REG_MM(0x0208)
257#define SW_RESET_CORE_REG REG_MM(0x0210)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700258#define SW_RESET_CORE2_REG REG_MM(0x0214)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700259#define TV_CC_REG REG_MM(0x00EC)
260#define TV_CC2_REG REG_MM(0x0124)
261#define TV_MD_REG REG_MM(0x00F0)
262#define TV_NS_REG REG_MM(0x00F4)
263#define VCODEC_CC_REG REG_MM(0x00F8)
264#define VCODEC_MD0_REG REG_MM(0x00FC)
265#define VCODEC_MD1_REG REG_MM(0x0128)
266#define VCODEC_NS_REG REG_MM(0x0100)
267#define VFE_CC_REG REG_MM(0x0104)
268#define VFE_MD_REG REG_MM(0x0108)
269#define VFE_NS_REG REG_MM(0x010C)
Stephen Boyd94625ef2011-07-12 17:06:01 -0700270#define VFE_CC2_REG REG_MM(0x023C)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700271#define VPE_CC_REG REG_MM(0x0110)
272#define VPE_NS_REG REG_MM(0x0118)
273
274/* Low-power Audio clock registers. */
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700275#define LCC_CLK_HS_DEBUG_CFG_REG REG_LPA(0x00A4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700276#define LCC_CLK_LS_DEBUG_CFG_REG REG_LPA(0x00A8)
277#define LCC_CODEC_I2S_MIC_MD_REG REG_LPA(0x0064)
278#define LCC_CODEC_I2S_MIC_NS_REG REG_LPA(0x0060)
279#define LCC_CODEC_I2S_MIC_STATUS_REG REG_LPA(0x0068)
280#define LCC_CODEC_I2S_SPKR_MD_REG REG_LPA(0x0070)
281#define LCC_CODEC_I2S_SPKR_NS_REG REG_LPA(0x006C)
282#define LCC_CODEC_I2S_SPKR_STATUS_REG REG_LPA(0x0074)
283#define LCC_MI2S_MD_REG REG_LPA(0x004C)
284#define LCC_MI2S_NS_REG REG_LPA(0x0048)
285#define LCC_MI2S_STATUS_REG REG_LPA(0x0050)
286#define LCC_PCM_MD_REG REG_LPA(0x0058)
287#define LCC_PCM_NS_REG REG_LPA(0x0054)
288#define LCC_PCM_STATUS_REG REG_LPA(0x005C)
Tianyi Gouc29c3242011-10-12 21:02:15 -0700289#define LCC_PLL0_MODE_REG REG_LPA(0x0000)
290#define LCC_PLL0_L_VAL_REG REG_LPA(0x0004)
291#define LCC_PLL0_M_VAL_REG REG_LPA(0x0008)
292#define LCC_PLL0_N_VAL_REG REG_LPA(0x000C)
293#define LCC_PLL0_CONFIG_REG REG_LPA(0x0014)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700294#define LCC_PLL0_STATUS_REG REG_LPA(0x0018)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700295#define LCC_SPARE_I2S_MIC_MD_REG REG_LPA(0x007C)
296#define LCC_SPARE_I2S_MIC_NS_REG REG_LPA(0x0078)
297#define LCC_SPARE_I2S_MIC_STATUS_REG REG_LPA(0x0080)
298#define LCC_SPARE_I2S_SPKR_MD_REG REG_LPA(0x0088)
299#define LCC_SPARE_I2S_SPKR_NS_REG REG_LPA(0x0084)
300#define LCC_SPARE_I2S_SPKR_STATUS_REG REG_LPA(0x008C)
301#define LCC_SLIMBUS_NS_REG REG_LPA(0x00CC)
302#define LCC_SLIMBUS_MD_REG REG_LPA(0x00D0)
303#define LCC_SLIMBUS_STATUS_REG REG_LPA(0x00D4)
304#define LCC_AHBEX_BRANCH_CTL_REG REG_LPA(0x00E4)
Tianyi Gouc29c3242011-10-12 21:02:15 -0700305#define LCC_PRI_PLL_CLK_CTL_REG REG_LPA(0x00C4)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700306
Matt Wagantall8b38f942011-08-02 18:23:18 -0700307#define GCC_APCS_CLK_DIAG REG_GCC(0x001C)
308
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700309/* MUX source input identifiers. */
310#define pxo_to_bb_mux 0
Matt Wagantall7625a4c2011-11-01 16:17:53 -0700311#define cxo_to_bb_mux 5
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700312#define pll0_to_bb_mux 2
313#define pll8_to_bb_mux 3
314#define pll6_to_bb_mux 4
315#define gnd_to_bb_mux 5
Stephen Boyd94625ef2011-07-12 17:06:01 -0700316#define pll3_to_bb_mux 6
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700317#define pxo_to_mm_mux 0
318#define pll1_to_mm_mux 1
Tianyi Gou41515e22011-09-01 19:37:43 -0700319#define pll2_to_mm_mux 1 /* or MMCC_PLL1 */
320#define pll8_to_mm_mux 2 /* or GCC_PERF */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700321#define pll0_to_mm_mux 3
Tianyi Gou41515e22011-09-01 19:37:43 -0700322#define pll15_to_mm_mux 3 /* or MM_PLL3 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700323#define gnd_to_mm_mux 4
Stephen Boyd7a776cd2011-10-20 12:46:04 -0700324#define pll3_to_mm_mux 3 /* or MMCC_PLL2 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700325#define hdmi_pll_to_mm_mux 3
326#define cxo_to_xo_mux 0
327#define pxo_to_xo_mux 1
328#define gnd_to_xo_mux 3
329#define pxo_to_lpa_mux 0
330#define cxo_to_lpa_mux 1
331#define pll4_to_lpa_mux 2
332#define gnd_to_lpa_mux 6
Tianyi Gou41515e22011-09-01 19:37:43 -0700333#define pxo_to_pcie_mux 0
334#define pll3_to_pcie_mux 1
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700335
336/* Test Vector Macros */
337#define TEST_TYPE_PER_LS 1
338#define TEST_TYPE_PER_HS 2
339#define TEST_TYPE_MM_LS 3
340#define TEST_TYPE_MM_HS 4
341#define TEST_TYPE_LPA 5
Matt Wagantall8b38f942011-08-02 18:23:18 -0700342#define TEST_TYPE_CPUL2 6
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700343#define TEST_TYPE_LPA_HS 7
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700344#define TEST_TYPE_SHIFT 24
345#define TEST_CLK_SEL_MASK BM(23, 0)
346#define TEST_VECTOR(s, t) (((t) << TEST_TYPE_SHIFT) | BVAL(23, 0, (s)))
347#define TEST_PER_LS(s) TEST_VECTOR((s), TEST_TYPE_PER_LS)
348#define TEST_PER_HS(s) TEST_VECTOR((s), TEST_TYPE_PER_HS)
349#define TEST_MM_LS(s) TEST_VECTOR((s), TEST_TYPE_MM_LS)
350#define TEST_MM_HS(s) TEST_VECTOR((s), TEST_TYPE_MM_HS)
351#define TEST_LPA(s) TEST_VECTOR((s), TEST_TYPE_LPA)
Stephen Boyd3939c8d2011-08-29 17:36:22 -0700352#define TEST_LPA_HS(s) TEST_VECTOR((s), TEST_TYPE_LPA_HS)
Matt Wagantall8b38f942011-08-02 18:23:18 -0700353#define TEST_CPUL2(s) TEST_VECTOR((s), TEST_TYPE_CPUL2)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700354
355#define MN_MODE_DUAL_EDGE 0x2
356
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700357struct pll_rate {
358 const uint32_t l_val;
359 const uint32_t m_val;
360 const uint32_t n_val;
361 const uint32_t vco;
362 const uint32_t post_div;
363 const uint32_t i_bits;
364};
365#define PLL_RATE(l, m, n, v, d, i) { l, m, n, v, (d>>1), i }
366
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700367enum vdd_dig_levels {
368 VDD_DIG_NONE,
369 VDD_DIG_LOW,
370 VDD_DIG_NOMINAL,
371 VDD_DIG_HIGH
372};
373
Saravana Kannan298ec392012-02-08 19:21:47 -0800374static int set_vdd_dig_8960(struct clk_vdd_class *vdd_class, int level)
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700375{
376 static const int vdd_uv[] = {
377 [VDD_DIG_NONE] = 0,
378 [VDD_DIG_LOW] = 945000,
379 [VDD_DIG_NOMINAL] = 1050000,
380 [VDD_DIG_HIGH] = 1150000
381 };
Saravana Kannan298ec392012-02-08 19:21:47 -0800382 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S3, RPM_VREG_VOTER3,
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700383 vdd_uv[level], 1150000, 1);
384}
385
Saravana Kannan298ec392012-02-08 19:21:47 -0800386static DEFINE_VDD_CLASS(vdd_dig, set_vdd_dig_8960);
387
388static int set_vdd_dig_8930(struct clk_vdd_class *vdd_class, int level)
389{
Saravana Kannanebaa3ac2012-02-08 19:55:44 -0800390 static const int vdd_corner[] = {
391 [VDD_DIG_NONE] = RPM_VREG_CORNER_NONE,
392 [VDD_DIG_LOW] = RPM_VREG_CORNER_LOW,
393 [VDD_DIG_NOMINAL] = RPM_VREG_CORNER_NOMINAL,
394 [VDD_DIG_HIGH] = RPM_VREG_CORNER_HIGH,
Saravana Kannan298ec392012-02-08 19:21:47 -0800395 };
Saravana Kannanebaa3ac2012-02-08 19:55:44 -0800396 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8038_VDD_DIG_CORNER,
397 RPM_VREG_VOTER3,
398 vdd_corner[level],
399 RPM_VREG_CORNER_HIGH, 1);
Saravana Kannan298ec392012-02-08 19:21:47 -0800400}
Matt Wagantalle18bbc82011-10-06 10:07:28 -0700401
402#define VDD_DIG_FMAX_MAP1(l1, f1) \
403 .vdd_class = &vdd_dig, \
404 .fmax[VDD_DIG_##l1] = (f1)
405#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
406 .vdd_class = &vdd_dig, \
407 .fmax[VDD_DIG_##l1] = (f1), \
408 .fmax[VDD_DIG_##l2] = (f2)
409#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
410 .vdd_class = &vdd_dig, \
411 .fmax[VDD_DIG_##l1] = (f1), \
412 .fmax[VDD_DIG_##l2] = (f2), \
413 .fmax[VDD_DIG_##l3] = (f3)
414
Tianyi Goue1faaf22012-01-24 16:07:19 -0800415enum vdd_sr2_pll_levels {
416 VDD_SR2_PLL_OFF,
417 VDD_SR2_PLL_ON
Matt Wagantallc57577d2011-10-06 17:06:53 -0700418};
419
Saravana Kannan298ec392012-02-08 19:21:47 -0800420static int set_vdd_sr2_pll_8960(struct clk_vdd_class *vdd_class, int level)
Matt Wagantallc57577d2011-10-06 17:06:53 -0700421{
Tianyi Goubf3d0b12012-01-23 14:37:28 -0800422 int rc = 0;
Saravana Kannan298ec392012-02-08 19:21:47 -0800423
424 if (level == VDD_SR2_PLL_OFF) {
425 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
426 RPM_VREG_VOTER3, 0, 0, 1);
427 if (rc)
428 return rc;
429 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
430 RPM_VREG_VOTER3, 0, 0, 1);
431 if (rc)
432 rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
433 RPM_VREG_VOTER3, 1800000, 1800000, 1);
Tianyi Goue1faaf22012-01-24 16:07:19 -0800434 } else {
Saravana Kannan298ec392012-02-08 19:21:47 -0800435 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
436 RPM_VREG_VOTER3, 2100000, 2100000, 1);
437 if (rc)
438 return rc;
439 rc = rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_L23,
440 RPM_VREG_VOTER3, 1800000, 1800000, 1);
441 if (rc)
442 rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_S8,
Tianyi Goubf3d0b12012-01-23 14:37:28 -0800443 RPM_VREG_VOTER3, 0, 0, 1);
Matt Wagantallc57577d2011-10-06 17:06:53 -0700444 }
445
446 return rc;
447}
448
Saravana Kannan298ec392012-02-08 19:21:47 -0800449static DEFINE_VDD_CLASS(vdd_sr2_pll, set_vdd_sr2_pll_8960);
450
451static int sr2_lreg_uv[] = {
452 [VDD_SR2_PLL_OFF] = 0,
453 [VDD_SR2_PLL_ON] = 1800000,
454};
455
456static int set_vdd_sr2_pll_8064(struct clk_vdd_class *vdd_class, int level)
457{
458 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8921_LVS7, RPM_VREG_VOTER3,
459 sr2_lreg_uv[level], sr2_lreg_uv[level], 1);
460}
461
462static int set_vdd_sr2_pll_8930(struct clk_vdd_class *vdd_class, int level)
463{
464 return rpm_vreg_set_voltage(RPM_VREG_ID_PM8038_L23, RPM_VREG_VOTER3,
465 sr2_lreg_uv[level], sr2_lreg_uv[level], 1);
466}
Matt Wagantallc57577d2011-10-06 17:06:53 -0700467
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700468/*
469 * Clock Descriptions
470 */
471
Stephen Boyd72a80352012-01-26 15:57:38 -0800472DEFINE_CLK_RPM_BRANCH(pxo_clk, pxo_a_clk, PXO, 27000000);
473DEFINE_CLK_RPM_BRANCH(cxo_clk, cxo_a_clk, CXO, 19200000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700474
475static struct pll_clk pll2_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700476 .mode_reg = MM_PLL1_MODE_REG,
477 .parent = &pxo_clk.c,
478 .c = {
479 .dbg_name = "pll2_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800480 .rate = 800000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700481 .ops = &clk_ops_pll,
482 CLK_INIT(pll2_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800483 .warned = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700484 },
485};
486
Stephen Boyd94625ef2011-07-12 17:06:01 -0700487static struct pll_clk pll3_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -0700488 .mode_reg = BB_MMCC_PLL2_MODE_REG,
489 .parent = &pxo_clk.c,
490 .c = {
491 .dbg_name = "pll3_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800492 .rate = 1200000000,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700493 .ops = &clk_ops_pll,
Tianyi Goue1faaf22012-01-24 16:07:19 -0800494 .vdd_class = &vdd_sr2_pll,
495 .fmax[VDD_SR2_PLL_ON] = ULONG_MAX,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700496 CLK_INIT(pll3_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800497 .warned = true,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700498 },
499};
500
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700501static struct pll_vote_clk pll4_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700502 .en_reg = BB_PLL_ENA_SC0_REG,
503 .en_mask = BIT(4),
504 .status_reg = LCC_PLL0_STATUS_REG,
505 .parent = &pxo_clk.c,
506 .c = {
507 .dbg_name = "pll4_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800508 .rate = 393216000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700509 .ops = &clk_ops_pll_vote,
510 CLK_INIT(pll4_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800511 .warned = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700512 },
513};
514
515static struct pll_vote_clk pll8_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700516 .en_reg = BB_PLL_ENA_SC0_REG,
517 .en_mask = BIT(8),
518 .status_reg = BB_PLL8_STATUS_REG,
519 .parent = &pxo_clk.c,
520 .c = {
521 .dbg_name = "pll8_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800522 .rate = 384000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700523 .ops = &clk_ops_pll_vote,
524 CLK_INIT(pll8_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800525 .warned = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700526 },
527};
528
Stephen Boyd94625ef2011-07-12 17:06:01 -0700529static struct pll_vote_clk pll14_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -0700530 .en_reg = BB_PLL_ENA_SC0_REG,
531 .en_mask = BIT(14),
532 .status_reg = BB_PLL14_STATUS_REG,
533 .parent = &pxo_clk.c,
534 .c = {
535 .dbg_name = "pll14_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800536 .rate = 480000000,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700537 .ops = &clk_ops_pll_vote,
538 CLK_INIT(pll14_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800539 .warned = true,
Stephen Boyd94625ef2011-07-12 17:06:01 -0700540 },
541};
542
Tianyi Gou41515e22011-09-01 19:37:43 -0700543static struct pll_clk pll15_clk = {
Tianyi Gou41515e22011-09-01 19:37:43 -0700544 .mode_reg = MM_PLL3_MODE_REG,
545 .parent = &pxo_clk.c,
546 .c = {
547 .dbg_name = "pll15_clk",
Tianyi Gou7949ecb2012-02-14 14:25:32 -0800548 .rate = 975000000,
Tianyi Gou41515e22011-09-01 19:37:43 -0700549 .ops = &clk_ops_pll,
550 CLK_INIT(pll15_clk.c),
Stephen Boyd3bbf3462012-01-12 00:19:23 -0800551 .warned = true,
Tianyi Gou41515e22011-09-01 19:37:43 -0700552 },
553};
554
Matt Wagantall84f43fd2011-08-16 23:28:38 -0700555static struct clk_ops clk_ops_rcg_8960 = {
Matt Wagantall0625ea02011-07-13 18:51:56 -0700556 .enable = rcg_clk_enable,
557 .disable = rcg_clk_disable,
Stephen Boyda52d7e32011-11-10 11:59:00 -0800558 .enable_hwcg = rcg_clk_enable_hwcg,
559 .disable_hwcg = rcg_clk_disable_hwcg,
560 .in_hwcg_mode = rcg_clk_in_hwcg_mode,
Matt Wagantall41af0772011-09-17 12:21:39 -0700561 .auto_off = rcg_clk_disable,
Matt Wagantall53d968f2011-07-19 13:22:53 -0700562 .handoff = rcg_clk_handoff,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700563 .set_rate = rcg_clk_set_rate,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700564 .list_rate = rcg_clk_list_rate,
565 .is_enabled = rcg_clk_is_enabled,
566 .round_rate = rcg_clk_round_rate,
Stephen Boyd7bf28142011-12-07 00:30:52 -0800567 .reset = rcg_clk_reset,
Matt Wagantall0625ea02011-07-13 18:51:56 -0700568 .get_parent = rcg_clk_get_parent,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800569 .set_flags = rcg_clk_set_flags,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700570};
571
572static struct clk_ops clk_ops_branch = {
573 .enable = branch_clk_enable,
574 .disable = branch_clk_disable,
Stephen Boyda52d7e32011-11-10 11:59:00 -0800575 .enable_hwcg = branch_clk_enable_hwcg,
576 .disable_hwcg = branch_clk_disable_hwcg,
577 .in_hwcg_mode = branch_clk_in_hwcg_mode,
Matt Wagantall41af0772011-09-17 12:21:39 -0700578 .auto_off = branch_clk_disable,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700579 .is_enabled = branch_clk_is_enabled,
580 .reset = branch_clk_reset,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700581 .get_parent = branch_clk_get_parent,
Stephen Boyda52d7e32011-11-10 11:59:00 -0800582 .handoff = branch_clk_handoff,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800583 .set_flags = branch_clk_set_flags,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700584};
585
586static struct clk_ops clk_ops_reset = {
587 .reset = branch_clk_reset,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700588};
589
590/* AXI Interfaces */
591static struct branch_clk gmem_axi_clk = {
592 .b = {
593 .ctl_reg = MAXI_EN_REG,
594 .en_mask = BIT(24),
595 .halt_reg = DBG_BUS_VEC_E_REG,
596 .halt_bit = 6,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800597 .retain_reg = MAXI_EN2_REG,
598 .retain_mask = BIT(21),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700599 },
600 .c = {
601 .dbg_name = "gmem_axi_clk",
602 .ops = &clk_ops_branch,
603 CLK_INIT(gmem_axi_clk.c),
604 },
605};
606
607static struct branch_clk ijpeg_axi_clk = {
608 .b = {
609 .ctl_reg = MAXI_EN_REG,
610 .en_mask = BIT(21),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800611 .hwcg_reg = MAXI_EN_REG,
612 .hwcg_mask = BIT(11),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700613 .reset_reg = SW_RESET_AXI_REG,
614 .reset_mask = BIT(14),
615 .halt_reg = DBG_BUS_VEC_E_REG,
616 .halt_bit = 4,
617 },
618 .c = {
619 .dbg_name = "ijpeg_axi_clk",
620 .ops = &clk_ops_branch,
621 CLK_INIT(ijpeg_axi_clk.c),
622 },
623};
624
625static struct branch_clk imem_axi_clk = {
626 .b = {
627 .ctl_reg = MAXI_EN_REG,
628 .en_mask = BIT(22),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800629 .hwcg_reg = MAXI_EN_REG,
630 .hwcg_mask = BIT(15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700631 .reset_reg = SW_RESET_CORE_REG,
632 .reset_mask = BIT(10),
633 .halt_reg = DBG_BUS_VEC_E_REG,
634 .halt_bit = 7,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800635 .retain_reg = MAXI_EN2_REG,
636 .retain_mask = BIT(10),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700637 },
638 .c = {
639 .dbg_name = "imem_axi_clk",
640 .ops = &clk_ops_branch,
641 CLK_INIT(imem_axi_clk.c),
642 },
643};
644
645static struct branch_clk jpegd_axi_clk = {
646 .b = {
647 .ctl_reg = MAXI_EN_REG,
648 .en_mask = BIT(25),
649 .halt_reg = DBG_BUS_VEC_E_REG,
650 .halt_bit = 5,
651 },
652 .c = {
653 .dbg_name = "jpegd_axi_clk",
654 .ops = &clk_ops_branch,
655 CLK_INIT(jpegd_axi_clk.c),
656 },
657};
658
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700659static struct branch_clk vcodec_axi_b_clk = {
660 .b = {
661 .ctl_reg = MAXI_EN4_REG,
662 .en_mask = BIT(23),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800663 .hwcg_reg = MAXI_EN4_REG,
664 .hwcg_mask = BIT(22),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700665 .halt_reg = DBG_BUS_VEC_I_REG,
666 .halt_bit = 25,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800667 .retain_reg = MAXI_EN4_REG,
668 .retain_mask = BIT(21),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700669 },
670 .c = {
671 .dbg_name = "vcodec_axi_b_clk",
672 .ops = &clk_ops_branch,
673 CLK_INIT(vcodec_axi_b_clk.c),
674 },
675};
676
Matt Wagantall91f42702011-07-14 12:01:15 -0700677static struct branch_clk vcodec_axi_a_clk = {
678 .b = {
679 .ctl_reg = MAXI_EN4_REG,
680 .en_mask = BIT(25),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800681 .hwcg_reg = MAXI_EN4_REG,
682 .hwcg_mask = BIT(24),
Matt Wagantall91f42702011-07-14 12:01:15 -0700683 .halt_reg = DBG_BUS_VEC_I_REG,
684 .halt_bit = 26,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800685 .retain_reg = MAXI_EN4_REG,
686 .retain_mask = BIT(10),
Matt Wagantall91f42702011-07-14 12:01:15 -0700687 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700688 .c = {
689 .dbg_name = "vcodec_axi_a_clk",
690 .ops = &clk_ops_branch,
691 CLK_INIT(vcodec_axi_a_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700692 .depends = &vcodec_axi_b_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700693 },
694};
695
696static struct branch_clk vcodec_axi_clk = {
697 .b = {
698 .ctl_reg = MAXI_EN_REG,
699 .en_mask = BIT(19),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800700 .hwcg_reg = MAXI_EN_REG,
701 .hwcg_mask = BIT(13),
Matt Wagantall91f42702011-07-14 12:01:15 -0700702 .reset_reg = SW_RESET_AXI_REG,
Gopikrishnaiah Anandan83b6e852012-01-05 17:47:02 -0800703 .reset_mask = BIT(4)|BIT(5)|BIT(7),
Matt Wagantall91f42702011-07-14 12:01:15 -0700704 .halt_reg = DBG_BUS_VEC_E_REG,
705 .halt_bit = 3,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800706 .retain_reg = MAXI_EN2_REG,
707 .retain_mask = BIT(28),
Matt Wagantall91f42702011-07-14 12:01:15 -0700708 },
Matt Wagantall91f42702011-07-14 12:01:15 -0700709 .c = {
710 .dbg_name = "vcodec_axi_clk",
711 .ops = &clk_ops_branch,
712 CLK_INIT(vcodec_axi_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -0700713 .depends = &vcodec_axi_a_clk.c,
Matt Wagantall91f42702011-07-14 12:01:15 -0700714 },
715};
716
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700717static struct branch_clk vfe_axi_clk = {
718 .b = {
719 .ctl_reg = MAXI_EN_REG,
720 .en_mask = BIT(18),
721 .reset_reg = SW_RESET_AXI_REG,
722 .reset_mask = BIT(9),
723 .halt_reg = DBG_BUS_VEC_E_REG,
724 .halt_bit = 0,
725 },
726 .c = {
727 .dbg_name = "vfe_axi_clk",
728 .ops = &clk_ops_branch,
729 CLK_INIT(vfe_axi_clk.c),
730 },
731};
732
733static struct branch_clk mdp_axi_clk = {
734 .b = {
735 .ctl_reg = MAXI_EN_REG,
736 .en_mask = BIT(23),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800737 .hwcg_reg = MAXI_EN_REG,
738 .hwcg_mask = BIT(16),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700739 .reset_reg = SW_RESET_AXI_REG,
740 .reset_mask = BIT(13),
741 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700742 .halt_bit = 8,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800743 .retain_reg = MAXI_EN_REG,
744 .retain_mask = BIT(0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700745 },
746 .c = {
747 .dbg_name = "mdp_axi_clk",
748 .ops = &clk_ops_branch,
749 CLK_INIT(mdp_axi_clk.c),
750 },
751};
752
753static struct branch_clk rot_axi_clk = {
754 .b = {
755 .ctl_reg = MAXI_EN2_REG,
756 .en_mask = BIT(24),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800757 .hwcg_reg = MAXI_EN2_REG,
758 .hwcg_mask = BIT(25),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700759 .reset_reg = SW_RESET_AXI_REG,
760 .reset_mask = BIT(6),
761 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700762 .halt_bit = 2,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800763 .retain_reg = MAXI_EN3_REG,
764 .retain_mask = BIT(10),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700765 },
766 .c = {
767 .dbg_name = "rot_axi_clk",
768 .ops = &clk_ops_branch,
769 CLK_INIT(rot_axi_clk.c),
770 },
771};
772
773static struct branch_clk vpe_axi_clk = {
774 .b = {
775 .ctl_reg = MAXI_EN2_REG,
776 .en_mask = BIT(26),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800777 .hwcg_reg = MAXI_EN2_REG,
778 .hwcg_mask = BIT(27),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700779 .reset_reg = SW_RESET_AXI_REG,
780 .reset_mask = BIT(15),
781 .halt_reg = DBG_BUS_VEC_E_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700782 .halt_bit = 1,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -0800783 .retain_reg = MAXI_EN3_REG,
784 .retain_mask = BIT(21),
785
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700786 },
787 .c = {
788 .dbg_name = "vpe_axi_clk",
789 .ops = &clk_ops_branch,
790 CLK_INIT(vpe_axi_clk.c),
791 },
792};
793
Tianyi Gou41515e22011-09-01 19:37:43 -0700794static struct branch_clk vcap_axi_clk = {
795 .b = {
796 .ctl_reg = MAXI_EN5_REG,
797 .en_mask = BIT(12),
798 .reset_reg = SW_RESET_AXI_REG,
799 .reset_mask = BIT(16),
800 .halt_reg = DBG_BUS_VEC_J_REG,
801 .halt_bit = 20,
802 },
803 .c = {
804 .dbg_name = "vcap_axi_clk",
805 .ops = &clk_ops_branch,
806 CLK_INIT(vcap_axi_clk.c),
807 },
808};
809
Tianyi Goue3d4f542012-03-15 17:06:45 -0700810/* gfx3d_axi_clk is set as a dependency of gmem_axi_clk at runtime */
811static struct branch_clk gfx3d_axi_clk_8064 = {
Tianyi Gou621f8742011-09-01 21:45:01 -0700812 .b = {
813 .ctl_reg = MAXI_EN5_REG,
814 .en_mask = BIT(25),
815 .reset_reg = SW_RESET_AXI_REG,
816 .reset_mask = BIT(17),
817 .halt_reg = DBG_BUS_VEC_J_REG,
818 .halt_bit = 30,
819 },
820 .c = {
821 .dbg_name = "gfx3d_axi_clk",
822 .ops = &clk_ops_branch,
Tianyi Goue3d4f542012-03-15 17:06:45 -0700823 CLK_INIT(gfx3d_axi_clk_8064.c),
824 },
825};
826
827static struct branch_clk gfx3d_axi_clk_8930 = {
828 .b = {
829 .ctl_reg = MAXI_EN5_REG,
830 .en_mask = BIT(12),
831 .reset_reg = SW_RESET_AXI_REG,
832 .reset_mask = BIT(16),
833 .halt_reg = DBG_BUS_VEC_J_REG,
834 .halt_bit = 12,
835 },
836 .c = {
837 .dbg_name = "gfx3d_axi_clk",
838 .ops = &clk_ops_branch,
839 CLK_INIT(gfx3d_axi_clk_8930.c),
Tianyi Gou621f8742011-09-01 21:45:01 -0700840 },
841};
842
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700843/* AHB Interfaces */
844static struct branch_clk amp_p_clk = {
845 .b = {
846 .ctl_reg = AHB_EN_REG,
847 .en_mask = BIT(24),
848 .halt_reg = DBG_BUS_VEC_F_REG,
849 .halt_bit = 18,
850 },
851 .c = {
852 .dbg_name = "amp_p_clk",
853 .ops = &clk_ops_branch,
854 CLK_INIT(amp_p_clk.c),
855 },
856};
857
Matt Wagantallc23eee92011-08-16 23:06:52 -0700858static struct branch_clk csi_p_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700859 .b = {
860 .ctl_reg = AHB_EN_REG,
861 .en_mask = BIT(7),
862 .reset_reg = SW_RESET_AHB_REG,
863 .reset_mask = BIT(17),
864 .halt_reg = DBG_BUS_VEC_F_REG,
865 .halt_bit = 16,
866 },
867 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -0700868 .dbg_name = "csi_p_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700869 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -0700870 CLK_INIT(csi_p_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700871 },
872};
873
874static struct branch_clk dsi1_m_p_clk = {
875 .b = {
876 .ctl_reg = AHB_EN_REG,
877 .en_mask = BIT(9),
878 .reset_reg = SW_RESET_AHB_REG,
879 .reset_mask = BIT(6),
880 .halt_reg = DBG_BUS_VEC_F_REG,
881 .halt_bit = 19,
882 },
883 .c = {
884 .dbg_name = "dsi1_m_p_clk",
885 .ops = &clk_ops_branch,
886 CLK_INIT(dsi1_m_p_clk.c),
887 },
888};
889
890static struct branch_clk dsi1_s_p_clk = {
891 .b = {
892 .ctl_reg = AHB_EN_REG,
893 .en_mask = BIT(18),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800894 .hwcg_reg = AHB_EN2_REG,
895 .hwcg_mask = BIT(20),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700896 .reset_reg = SW_RESET_AHB_REG,
897 .reset_mask = BIT(5),
898 .halt_reg = DBG_BUS_VEC_F_REG,
899 .halt_bit = 21,
900 },
901 .c = {
902 .dbg_name = "dsi1_s_p_clk",
903 .ops = &clk_ops_branch,
904 CLK_INIT(dsi1_s_p_clk.c),
905 },
906};
907
908static struct branch_clk dsi2_m_p_clk = {
909 .b = {
910 .ctl_reg = AHB_EN_REG,
911 .en_mask = BIT(17),
912 .reset_reg = SW_RESET_AHB2_REG,
913 .reset_mask = BIT(1),
914 .halt_reg = DBG_BUS_VEC_E_REG,
915 .halt_bit = 18,
916 },
917 .c = {
918 .dbg_name = "dsi2_m_p_clk",
919 .ops = &clk_ops_branch,
920 CLK_INIT(dsi2_m_p_clk.c),
921 },
922};
923
924static struct branch_clk dsi2_s_p_clk = {
925 .b = {
926 .ctl_reg = AHB_EN_REG,
927 .en_mask = BIT(22),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800928 .hwcg_reg = AHB_EN2_REG,
929 .hwcg_mask = BIT(15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700930 .reset_reg = SW_RESET_AHB2_REG,
931 .reset_mask = BIT(0),
932 .halt_reg = DBG_BUS_VEC_F_REG,
933 .halt_bit = 20,
934 },
935 .c = {
936 .dbg_name = "dsi2_s_p_clk",
937 .ops = &clk_ops_branch,
938 CLK_INIT(dsi2_s_p_clk.c),
939 },
940};
941
942static struct branch_clk gfx2d0_p_clk = {
943 .b = {
944 .ctl_reg = AHB_EN_REG,
945 .en_mask = BIT(19),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800946 .hwcg_reg = AHB_EN2_REG,
947 .hwcg_mask = BIT(28),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700948 .reset_reg = SW_RESET_AHB_REG,
949 .reset_mask = BIT(12),
950 .halt_reg = DBG_BUS_VEC_F_REG,
951 .halt_bit = 2,
952 },
953 .c = {
954 .dbg_name = "gfx2d0_p_clk",
955 .ops = &clk_ops_branch,
956 CLK_INIT(gfx2d0_p_clk.c),
957 },
958};
959
960static struct branch_clk gfx2d1_p_clk = {
961 .b = {
962 .ctl_reg = AHB_EN_REG,
963 .en_mask = BIT(2),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800964 .hwcg_reg = AHB_EN2_REG,
965 .hwcg_mask = BIT(29),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700966 .reset_reg = SW_RESET_AHB_REG,
967 .reset_mask = BIT(11),
968 .halt_reg = DBG_BUS_VEC_F_REG,
969 .halt_bit = 3,
970 },
971 .c = {
972 .dbg_name = "gfx2d1_p_clk",
973 .ops = &clk_ops_branch,
974 CLK_INIT(gfx2d1_p_clk.c),
975 },
976};
977
978static struct branch_clk gfx3d_p_clk = {
979 .b = {
980 .ctl_reg = AHB_EN_REG,
981 .en_mask = BIT(3),
Stephen Boyda52d7e32011-11-10 11:59:00 -0800982 .hwcg_reg = AHB_EN2_REG,
983 .hwcg_mask = BIT(27),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700984 .reset_reg = SW_RESET_AHB_REG,
985 .reset_mask = BIT(10),
986 .halt_reg = DBG_BUS_VEC_F_REG,
987 .halt_bit = 4,
988 },
989 .c = {
990 .dbg_name = "gfx3d_p_clk",
991 .ops = &clk_ops_branch,
992 CLK_INIT(gfx3d_p_clk.c),
993 },
994};
995
996static struct branch_clk hdmi_m_p_clk = {
997 .b = {
998 .ctl_reg = AHB_EN_REG,
999 .en_mask = BIT(14),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001000 .hwcg_reg = AHB_EN2_REG,
1001 .hwcg_mask = BIT(21),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001002 .reset_reg = SW_RESET_AHB_REG,
1003 .reset_mask = BIT(9),
1004 .halt_reg = DBG_BUS_VEC_F_REG,
1005 .halt_bit = 5,
1006 },
1007 .c = {
1008 .dbg_name = "hdmi_m_p_clk",
1009 .ops = &clk_ops_branch,
1010 CLK_INIT(hdmi_m_p_clk.c),
1011 },
1012};
1013
1014static struct branch_clk hdmi_s_p_clk = {
1015 .b = {
1016 .ctl_reg = AHB_EN_REG,
1017 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001018 .hwcg_reg = AHB_EN2_REG,
1019 .hwcg_mask = BIT(22),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001020 .reset_reg = SW_RESET_AHB_REG,
1021 .reset_mask = BIT(9),
1022 .halt_reg = DBG_BUS_VEC_F_REG,
1023 .halt_bit = 6,
1024 },
1025 .c = {
1026 .dbg_name = "hdmi_s_p_clk",
1027 .ops = &clk_ops_branch,
1028 CLK_INIT(hdmi_s_p_clk.c),
1029 },
1030};
1031
1032static struct branch_clk ijpeg_p_clk = {
1033 .b = {
1034 .ctl_reg = AHB_EN_REG,
1035 .en_mask = BIT(5),
1036 .reset_reg = SW_RESET_AHB_REG,
1037 .reset_mask = BIT(7),
1038 .halt_reg = DBG_BUS_VEC_F_REG,
1039 .halt_bit = 9,
1040 },
1041 .c = {
1042 .dbg_name = "ijpeg_p_clk",
1043 .ops = &clk_ops_branch,
1044 CLK_INIT(ijpeg_p_clk.c),
1045 },
1046};
1047
1048static struct branch_clk imem_p_clk = {
1049 .b = {
1050 .ctl_reg = AHB_EN_REG,
1051 .en_mask = BIT(6),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001052 .hwcg_reg = AHB_EN2_REG,
1053 .hwcg_mask = BIT(12),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001054 .reset_reg = SW_RESET_AHB_REG,
1055 .reset_mask = BIT(8),
1056 .halt_reg = DBG_BUS_VEC_F_REG,
1057 .halt_bit = 10,
1058 },
1059 .c = {
1060 .dbg_name = "imem_p_clk",
1061 .ops = &clk_ops_branch,
1062 CLK_INIT(imem_p_clk.c),
1063 },
1064};
1065
1066static struct branch_clk jpegd_p_clk = {
1067 .b = {
1068 .ctl_reg = AHB_EN_REG,
1069 .en_mask = BIT(21),
1070 .reset_reg = SW_RESET_AHB_REG,
1071 .reset_mask = BIT(4),
1072 .halt_reg = DBG_BUS_VEC_F_REG,
1073 .halt_bit = 7,
1074 },
1075 .c = {
1076 .dbg_name = "jpegd_p_clk",
1077 .ops = &clk_ops_branch,
1078 CLK_INIT(jpegd_p_clk.c),
1079 },
1080};
1081
1082static struct branch_clk mdp_p_clk = {
1083 .b = {
1084 .ctl_reg = AHB_EN_REG,
1085 .en_mask = BIT(10),
1086 .reset_reg = SW_RESET_AHB_REG,
1087 .reset_mask = BIT(3),
1088 .halt_reg = DBG_BUS_VEC_F_REG,
1089 .halt_bit = 11,
1090 },
1091 .c = {
1092 .dbg_name = "mdp_p_clk",
1093 .ops = &clk_ops_branch,
1094 CLK_INIT(mdp_p_clk.c),
1095 },
1096};
1097
1098static struct branch_clk rot_p_clk = {
1099 .b = {
1100 .ctl_reg = AHB_EN_REG,
1101 .en_mask = BIT(12),
1102 .reset_reg = SW_RESET_AHB_REG,
1103 .reset_mask = BIT(2),
1104 .halt_reg = DBG_BUS_VEC_F_REG,
1105 .halt_bit = 13,
1106 },
1107 .c = {
1108 .dbg_name = "rot_p_clk",
1109 .ops = &clk_ops_branch,
1110 CLK_INIT(rot_p_clk.c),
1111 },
1112};
1113
1114static struct branch_clk smmu_p_clk = {
1115 .b = {
1116 .ctl_reg = AHB_EN_REG,
1117 .en_mask = BIT(15),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001118 .hwcg_reg = AHB_EN_REG,
1119 .hwcg_mask = BIT(26),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001120 .halt_reg = DBG_BUS_VEC_F_REG,
1121 .halt_bit = 22,
1122 },
1123 .c = {
1124 .dbg_name = "smmu_p_clk",
1125 .ops = &clk_ops_branch,
1126 CLK_INIT(smmu_p_clk.c),
1127 },
1128};
1129
1130static struct branch_clk tv_enc_p_clk = {
1131 .b = {
1132 .ctl_reg = AHB_EN_REG,
1133 .en_mask = BIT(25),
1134 .reset_reg = SW_RESET_AHB_REG,
1135 .reset_mask = BIT(15),
1136 .halt_reg = DBG_BUS_VEC_F_REG,
1137 .halt_bit = 23,
1138 },
1139 .c = {
1140 .dbg_name = "tv_enc_p_clk",
1141 .ops = &clk_ops_branch,
1142 CLK_INIT(tv_enc_p_clk.c),
1143 },
1144};
1145
1146static struct branch_clk vcodec_p_clk = {
1147 .b = {
1148 .ctl_reg = AHB_EN_REG,
1149 .en_mask = BIT(11),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001150 .hwcg_reg = AHB_EN2_REG,
1151 .hwcg_mask = BIT(26),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001152 .reset_reg = SW_RESET_AHB_REG,
1153 .reset_mask = BIT(1),
1154 .halt_reg = DBG_BUS_VEC_F_REG,
1155 .halt_bit = 12,
1156 },
1157 .c = {
1158 .dbg_name = "vcodec_p_clk",
1159 .ops = &clk_ops_branch,
1160 CLK_INIT(vcodec_p_clk.c),
1161 },
1162};
1163
1164static struct branch_clk vfe_p_clk = {
1165 .b = {
1166 .ctl_reg = AHB_EN_REG,
1167 .en_mask = BIT(13),
1168 .reset_reg = SW_RESET_AHB_REG,
1169 .reset_mask = BIT(0),
1170 .halt_reg = DBG_BUS_VEC_F_REG,
1171 .halt_bit = 14,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08001172 .retain_reg = AHB_EN2_REG,
1173 .retain_mask = BIT(0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001174 },
1175 .c = {
1176 .dbg_name = "vfe_p_clk",
1177 .ops = &clk_ops_branch,
1178 CLK_INIT(vfe_p_clk.c),
1179 },
1180};
1181
1182static struct branch_clk vpe_p_clk = {
1183 .b = {
1184 .ctl_reg = AHB_EN_REG,
1185 .en_mask = BIT(16),
1186 .reset_reg = SW_RESET_AHB_REG,
1187 .reset_mask = BIT(14),
1188 .halt_reg = DBG_BUS_VEC_F_REG,
1189 .halt_bit = 15,
1190 },
1191 .c = {
1192 .dbg_name = "vpe_p_clk",
1193 .ops = &clk_ops_branch,
1194 CLK_INIT(vpe_p_clk.c),
1195 },
1196};
1197
Tianyi Gou41515e22011-09-01 19:37:43 -07001198static struct branch_clk vcap_p_clk = {
1199 .b = {
1200 .ctl_reg = AHB_EN3_REG,
1201 .en_mask = BIT(1),
1202 .reset_reg = SW_RESET_AHB2_REG,
1203 .reset_mask = BIT(2),
1204 .halt_reg = DBG_BUS_VEC_J_REG,
1205 .halt_bit = 23,
1206 },
1207 .c = {
1208 .dbg_name = "vcap_p_clk",
1209 .ops = &clk_ops_branch,
1210 CLK_INIT(vcap_p_clk.c),
1211 },
1212};
1213
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001214/*
1215 * Peripheral Clocks
1216 */
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001217#define CLK_GP(i, n, h_r, h_b) \
1218 struct rcg_clk i##_clk = { \
1219 .b = { \
1220 .ctl_reg = GPn_NS_REG(n), \
1221 .en_mask = BIT(9), \
1222 .halt_reg = h_r, \
1223 .halt_bit = h_b, \
1224 }, \
1225 .ns_reg = GPn_NS_REG(n), \
1226 .md_reg = GPn_MD_REG(n), \
1227 .root_en_mask = BIT(11), \
1228 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001229 .mnd_en_mask = BIT(8), \
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001230 .set_rate = set_rate_mnd, \
1231 .freq_tbl = clk_tbl_gp, \
1232 .current_freq = &rcg_dummy_freq, \
1233 .c = { \
1234 .dbg_name = #i "_clk", \
1235 .ops = &clk_ops_rcg_8960, \
1236 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), \
1237 CLK_INIT(i##_clk.c), \
1238 }, \
1239 }
1240#define F_GP(f, s, d, m, n) \
1241 { \
1242 .freq_hz = f, \
1243 .src_clk = &s##_clk.c, \
1244 .md_val = MD8(16, m, 0, n), \
1245 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Matt Wagantall7625a4c2011-11-01 16:17:53 -07001246 }
1247static struct clk_freq_tbl clk_tbl_gp[] = {
1248 F_GP( 0, gnd, 1, 0, 0),
1249 F_GP( 9600000, cxo, 2, 0, 0),
1250 F_GP( 13500000, pxo, 2, 0, 0),
1251 F_GP( 19200000, cxo, 1, 0, 0),
1252 F_GP( 27000000, pxo, 1, 0, 0),
1253 F_GP( 64000000, pll8, 2, 1, 3),
1254 F_GP( 76800000, pll8, 1, 1, 5),
1255 F_GP( 96000000, pll8, 4, 0, 0),
1256 F_GP(128000000, pll8, 3, 0, 0),
1257 F_GP(192000000, pll8, 2, 0, 0),
1258 F_GP(384000000, pll8, 1, 0, 0),
1259 F_END
1260};
1261
1262static CLK_GP(gp0, 0, CLK_HALT_SFPB_MISC_STATE_REG, 7);
1263static CLK_GP(gp1, 1, CLK_HALT_SFPB_MISC_STATE_REG, 6);
1264static CLK_GP(gp2, 2, CLK_HALT_SFPB_MISC_STATE_REG, 5);
1265
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001266#define CLK_GSBI_UART(i, n, h_r, h_b) \
1267 struct rcg_clk i##_clk = { \
1268 .b = { \
1269 .ctl_reg = GSBIn_UART_APPS_NS_REG(n), \
1270 .en_mask = BIT(9), \
1271 .reset_reg = GSBIn_RESET_REG(n), \
1272 .reset_mask = BIT(0), \
1273 .halt_reg = h_r, \
1274 .halt_bit = h_b, \
1275 }, \
1276 .ns_reg = GSBIn_UART_APPS_NS_REG(n), \
1277 .md_reg = GSBIn_UART_APPS_MD_REG(n), \
1278 .root_en_mask = BIT(11), \
1279 .ns_mask = (BM(31, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001280 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001281 .set_rate = set_rate_mnd, \
1282 .freq_tbl = clk_tbl_gsbi_uart, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001283 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001284 .c = { \
1285 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001286 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001287 VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001288 CLK_INIT(i##_clk.c), \
1289 }, \
1290 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001291#define F_GSBI_UART(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001292 { \
1293 .freq_hz = f, \
1294 .src_clk = &s##_clk.c, \
1295 .md_val = MD16(m, n), \
1296 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001297 }
1298static struct clk_freq_tbl clk_tbl_gsbi_uart[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001299 F_GSBI_UART( 0, gnd, 1, 0, 0),
Matt Wagantall9a561f72012-01-19 16:13:12 -08001300 F_GSBI_UART( 1843200, pll8, 2, 6, 625),
1301 F_GSBI_UART( 3686400, pll8, 2, 12, 625),
1302 F_GSBI_UART( 7372800, pll8, 2, 24, 625),
1303 F_GSBI_UART(14745600, pll8, 2, 48, 625),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001304 F_GSBI_UART(16000000, pll8, 4, 1, 6),
1305 F_GSBI_UART(24000000, pll8, 4, 1, 4),
1306 F_GSBI_UART(32000000, pll8, 4, 1, 3),
1307 F_GSBI_UART(40000000, pll8, 1, 5, 48),
1308 F_GSBI_UART(46400000, pll8, 1, 29, 240),
1309 F_GSBI_UART(48000000, pll8, 4, 1, 2),
1310 F_GSBI_UART(51200000, pll8, 1, 2, 15),
1311 F_GSBI_UART(56000000, pll8, 1, 7, 48),
1312 F_GSBI_UART(58982400, pll8, 1, 96, 625),
1313 F_GSBI_UART(64000000, pll8, 2, 1, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001314 F_END
1315};
1316
1317static CLK_GSBI_UART(gsbi1_uart, 1, CLK_HALT_CFPB_STATEA_REG, 10);
1318static CLK_GSBI_UART(gsbi2_uart, 2, CLK_HALT_CFPB_STATEA_REG, 6);
1319static CLK_GSBI_UART(gsbi3_uart, 3, CLK_HALT_CFPB_STATEA_REG, 2);
1320static CLK_GSBI_UART(gsbi4_uart, 4, CLK_HALT_CFPB_STATEB_REG, 26);
1321static CLK_GSBI_UART(gsbi5_uart, 5, CLK_HALT_CFPB_STATEB_REG, 22);
1322static CLK_GSBI_UART(gsbi6_uart, 6, CLK_HALT_CFPB_STATEB_REG, 18);
1323static CLK_GSBI_UART(gsbi7_uart, 7, CLK_HALT_CFPB_STATEB_REG, 14);
1324static CLK_GSBI_UART(gsbi8_uart, 8, CLK_HALT_CFPB_STATEB_REG, 10);
1325static CLK_GSBI_UART(gsbi9_uart, 9, CLK_HALT_CFPB_STATEB_REG, 6);
1326static CLK_GSBI_UART(gsbi10_uart, 10, CLK_HALT_CFPB_STATEB_REG, 2);
1327static CLK_GSBI_UART(gsbi11_uart, 11, CLK_HALT_CFPB_STATEC_REG, 17);
1328static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13);
1329
1330#define CLK_GSBI_QUP(i, n, h_r, h_b) \
1331 struct rcg_clk i##_clk = { \
1332 .b = { \
1333 .ctl_reg = GSBIn_QUP_APPS_NS_REG(n), \
1334 .en_mask = BIT(9), \
1335 .reset_reg = GSBIn_RESET_REG(n), \
1336 .reset_mask = BIT(0), \
1337 .halt_reg = h_r, \
1338 .halt_bit = h_b, \
1339 }, \
1340 .ns_reg = GSBIn_QUP_APPS_NS_REG(n), \
1341 .md_reg = GSBIn_QUP_APPS_MD_REG(n), \
1342 .root_en_mask = BIT(11), \
1343 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001344 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001345 .set_rate = set_rate_mnd, \
1346 .freq_tbl = clk_tbl_gsbi_qup, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001347 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001348 .c = { \
1349 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001350 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001351 VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001352 CLK_INIT(i##_clk.c), \
1353 }, \
1354 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001355#define F_GSBI_QUP(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001356 { \
1357 .freq_hz = f, \
1358 .src_clk = &s##_clk.c, \
1359 .md_val = MD8(16, m, 0, n), \
1360 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001361 }
1362static struct clk_freq_tbl clk_tbl_gsbi_qup[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001363 F_GSBI_QUP( 0, gnd, 1, 0, 0),
1364 F_GSBI_QUP( 1100000, pxo, 1, 2, 49),
1365 F_GSBI_QUP( 5400000, pxo, 1, 1, 5),
1366 F_GSBI_QUP(10800000, pxo, 1, 2, 5),
1367 F_GSBI_QUP(15060000, pll8, 1, 2, 51),
1368 F_GSBI_QUP(24000000, pll8, 4, 1, 4),
1369 F_GSBI_QUP(25600000, pll8, 1, 1, 15),
1370 F_GSBI_QUP(27000000, pxo, 1, 0, 0),
1371 F_GSBI_QUP(48000000, pll8, 4, 1, 2),
1372 F_GSBI_QUP(51200000, pll8, 1, 2, 15),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001373 F_END
1374};
1375
1376static CLK_GSBI_QUP(gsbi1_qup, 1, CLK_HALT_CFPB_STATEA_REG, 9);
1377static CLK_GSBI_QUP(gsbi2_qup, 2, CLK_HALT_CFPB_STATEA_REG, 4);
1378static CLK_GSBI_QUP(gsbi3_qup, 3, CLK_HALT_CFPB_STATEA_REG, 0);
1379static CLK_GSBI_QUP(gsbi4_qup, 4, CLK_HALT_CFPB_STATEB_REG, 24);
1380static CLK_GSBI_QUP(gsbi5_qup, 5, CLK_HALT_CFPB_STATEB_REG, 20);
1381static CLK_GSBI_QUP(gsbi6_qup, 6, CLK_HALT_CFPB_STATEB_REG, 16);
1382static CLK_GSBI_QUP(gsbi7_qup, 7, CLK_HALT_CFPB_STATEB_REG, 12);
1383static CLK_GSBI_QUP(gsbi8_qup, 8, CLK_HALT_CFPB_STATEB_REG, 8);
1384static CLK_GSBI_QUP(gsbi9_qup, 9, CLK_HALT_CFPB_STATEB_REG, 4);
1385static CLK_GSBI_QUP(gsbi10_qup, 10, CLK_HALT_CFPB_STATEB_REG, 0);
1386static CLK_GSBI_QUP(gsbi11_qup, 11, CLK_HALT_CFPB_STATEC_REG, 15);
1387static CLK_GSBI_QUP(gsbi12_qup, 12, CLK_HALT_CFPB_STATEC_REG, 11);
1388
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001389#define F_PDM(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001390 { \
1391 .freq_hz = f, \
1392 .src_clk = &s##_clk.c, \
1393 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001394 }
1395static struct clk_freq_tbl clk_tbl_pdm[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001396 F_PDM( 0, gnd, 1),
1397 F_PDM(27000000, pxo, 1),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001398 F_END
1399};
1400
1401static struct rcg_clk pdm_clk = {
1402 .b = {
1403 .ctl_reg = PDM_CLK_NS_REG,
1404 .en_mask = BIT(9),
1405 .reset_reg = PDM_CLK_NS_REG,
1406 .reset_mask = BIT(12),
1407 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1408 .halt_bit = 3,
1409 },
1410 .ns_reg = PDM_CLK_NS_REG,
1411 .root_en_mask = BIT(11),
1412 .ns_mask = BM(1, 0),
1413 .set_rate = set_rate_nop,
1414 .freq_tbl = clk_tbl_pdm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001415 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001416 .c = {
1417 .dbg_name = "pdm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001418 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001419 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001420 CLK_INIT(pdm_clk.c),
1421 },
1422};
1423
1424static struct branch_clk pmem_clk = {
1425 .b = {
1426 .ctl_reg = PMEM_ACLK_CTL_REG,
1427 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001428 .hwcg_reg = PMEM_ACLK_CTL_REG,
1429 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001430 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1431 .halt_bit = 20,
1432 },
1433 .c = {
1434 .dbg_name = "pmem_clk",
1435 .ops = &clk_ops_branch,
1436 CLK_INIT(pmem_clk.c),
1437 },
1438};
1439
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001440#define F_PRNG(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001441 { \
1442 .freq_hz = f, \
1443 .src_clk = &s##_clk.c, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001444 }
1445static struct clk_freq_tbl clk_tbl_prng[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001446 F_PRNG(64000000, pll8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001447 F_END
1448};
1449
1450static struct rcg_clk prng_clk = {
1451 .b = {
1452 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
1453 .en_mask = BIT(10),
1454 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
1455 .halt_check = HALT_VOTED,
1456 .halt_bit = 10,
1457 },
1458 .set_rate = set_rate_nop,
1459 .freq_tbl = clk_tbl_prng,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001460 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001461 .c = {
1462 .dbg_name = "prng_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001463 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001464 VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001465 CLK_INIT(prng_clk.c),
1466 },
1467};
1468
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001469#define CLK_SDC(name, n, h_b, fmax_low, fmax_nom) \
Stephen Boyda78a7402011-08-02 11:23:39 -07001470 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001471 .b = { \
1472 .ctl_reg = SDCn_APPS_CLK_NS_REG(n), \
1473 .en_mask = BIT(9), \
1474 .reset_reg = SDCn_RESET_REG(n), \
1475 .reset_mask = BIT(0), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001476 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001477 .halt_bit = h_b, \
1478 }, \
1479 .ns_reg = SDCn_APPS_CLK_NS_REG(n), \
1480 .md_reg = SDCn_APPS_CLK_MD_REG(n), \
1481 .root_en_mask = BIT(11), \
1482 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001483 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001484 .set_rate = set_rate_mnd, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001485 .freq_tbl = clk_tbl_sdc, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001486 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001487 .c = { \
Stephen Boyda78a7402011-08-02 11:23:39 -07001488 .dbg_name = #name, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001489 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001490 VDD_DIG_FMAX_MAP2(LOW, fmax_low, NOMINAL, fmax_nom), \
Stephen Boyda78a7402011-08-02 11:23:39 -07001491 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001492 }, \
1493 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001494#define F_SDC(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001495 { \
1496 .freq_hz = f, \
1497 .src_clk = &s##_clk.c, \
1498 .md_val = MD8(16, m, 0, n), \
1499 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001500 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001501static struct clk_freq_tbl clk_tbl_sdc[] = {
1502 F_SDC( 0, gnd, 1, 0, 0),
1503 F_SDC( 144000, pxo, 3, 2, 125),
1504 F_SDC( 400000, pll8, 4, 1, 240),
1505 F_SDC( 16000000, pll8, 4, 1, 6),
1506 F_SDC( 17070000, pll8, 1, 2, 45),
1507 F_SDC( 20210000, pll8, 1, 1, 19),
1508 F_SDC( 24000000, pll8, 4, 1, 4),
1509 F_SDC( 48000000, pll8, 4, 1, 2),
1510 F_SDC( 64000000, pll8, 3, 1, 2),
1511 F_SDC( 96000000, pll8, 4, 0, 0),
Subhash Jadavanibd238ba2011-11-24 15:12:39 +05301512 F_SDC(192000000, pll8, 2, 0, 0),
Stephen Boyda78a7402011-08-02 11:23:39 -07001513 F_END
1514};
1515
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001516static CLK_SDC(sdc1_clk, 1, 6, 52000000, 104000000);
1517static CLK_SDC(sdc2_clk, 2, 5, 52000000, 104000000);
1518static CLK_SDC(sdc3_clk, 3, 4, 104000000, 208000000);
1519static CLK_SDC(sdc4_clk, 4, 3, 33000000, 67000000);
1520static CLK_SDC(sdc5_clk, 5, 2, 33000000, 67000000);
Stephen Boyda78a7402011-08-02 11:23:39 -07001521
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001522#define F_TSIF_REF(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001523 { \
1524 .freq_hz = f, \
1525 .src_clk = &s##_clk.c, \
1526 .md_val = MD16(m, n), \
1527 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001528 }
1529static struct clk_freq_tbl clk_tbl_tsif_ref[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001530 F_TSIF_REF( 0, gnd, 1, 0, 0),
1531 F_TSIF_REF(105000, pxo, 1, 1, 256),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001532 F_END
1533};
1534
1535static struct rcg_clk tsif_ref_clk = {
1536 .b = {
1537 .ctl_reg = TSIF_REF_CLK_NS_REG,
1538 .en_mask = BIT(9),
1539 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1540 .halt_bit = 5,
1541 },
1542 .ns_reg = TSIF_REF_CLK_NS_REG,
1543 .md_reg = TSIF_REF_CLK_MD_REG,
1544 .root_en_mask = BIT(11),
1545 .ns_mask = (BM(31, 16) | BM(6, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08001546 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001547 .set_rate = set_rate_mnd,
1548 .freq_tbl = clk_tbl_tsif_ref,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001549 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001550 .c = {
1551 .dbg_name = "tsif_ref_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001552 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001553 VDD_DIG_FMAX_MAP2(LOW, 27000000, NOMINAL, 54000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001554 CLK_INIT(tsif_ref_clk.c),
1555 },
1556};
1557
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001558#define F_TSSC(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001559 { \
1560 .freq_hz = f, \
1561 .src_clk = &s##_clk.c, \
1562 .ns_val = NS_SRC_SEL(1, 0, s##_to_xo_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001563 }
1564static struct clk_freq_tbl clk_tbl_tssc[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001565 F_TSSC( 0, gnd),
1566 F_TSSC(27000000, pxo),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001567 F_END
1568};
1569
1570static struct rcg_clk tssc_clk = {
1571 .b = {
1572 .ctl_reg = TSSC_CLK_CTL_REG,
1573 .en_mask = BIT(4),
1574 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1575 .halt_bit = 4,
1576 },
1577 .ns_reg = TSSC_CLK_CTL_REG,
1578 .ns_mask = BM(1, 0),
1579 .set_rate = set_rate_nop,
1580 .freq_tbl = clk_tbl_tssc,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001581 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001582 .c = {
1583 .dbg_name = "tssc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001584 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001585 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001586 CLK_INIT(tssc_clk.c),
1587 },
1588};
1589
Tianyi Gou41515e22011-09-01 19:37:43 -07001590#define CLK_USB_HS(name, n, h_b) \
1591 static struct rcg_clk name = { \
1592 .b = { \
1593 .ctl_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \
1594 .en_mask = BIT(9), \
1595 .reset_reg = USB_HS##n##_RESET_REG, \
1596 .reset_mask = BIT(0), \
1597 .halt_reg = CLK_HALT_DFAB_STATE_REG, \
1598 .halt_bit = h_b, \
1599 }, \
1600 .ns_reg = USB_HS##n##_XCVR_FS_CLK_NS_REG, \
1601 .md_reg = USB_HS##n##_XCVR_FS_CLK_MD_REG, \
1602 .root_en_mask = BIT(11), \
1603 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001604 .mnd_en_mask = BIT(8), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001605 .set_rate = set_rate_mnd, \
1606 .freq_tbl = clk_tbl_usb, \
1607 .current_freq = &rcg_dummy_freq, \
1608 .c = { \
1609 .dbg_name = #name, \
1610 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001611 VDD_DIG_FMAX_MAP1(NOMINAL, 64000000), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001612 CLK_INIT(name.c), \
1613 }, \
1614}
1615
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001616#define F_USB(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001617 { \
1618 .freq_hz = f, \
1619 .src_clk = &s##_clk.c, \
1620 .md_val = MD8(16, m, 0, n), \
1621 .ns_val = NS(23, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001622 }
1623static struct clk_freq_tbl clk_tbl_usb[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001624 F_USB( 0, gnd, 1, 0, 0),
1625 F_USB(60000000, pll8, 1, 5, 32),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001626 F_END
1627};
1628
Tianyi Gou41515e22011-09-01 19:37:43 -07001629CLK_USB_HS(usb_hs1_xcvr_clk, 1, 0);
1630CLK_USB_HS(usb_hs3_xcvr_clk, 3, 30);
1631CLK_USB_HS(usb_hs4_xcvr_clk, 4, 2);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001632
Stephen Boyd94625ef2011-07-12 17:06:01 -07001633static struct clk_freq_tbl clk_tbl_usb_hsic[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001634 F_USB( 0, gnd, 1, 0, 0),
1635 F_USB(60000000, pll8, 1, 5, 32),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001636 F_END
1637};
1638
1639static struct rcg_clk usb_hsic_xcvr_fs_clk = {
1640 .b = {
1641 .ctl_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1642 .en_mask = BIT(9),
1643 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1644 .halt_bit = 26,
1645 },
1646 .ns_reg = USB_HSIC_XCVR_FS_CLK_NS_REG,
1647 .md_reg = USB_HSIC_XCVR_FS_CLK_MD_REG,
1648 .root_en_mask = BIT(11),
1649 .ns_mask = (BM(23, 16) | BM(6, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08001650 .mnd_en_mask = BIT(8),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001651 .set_rate = set_rate_mnd,
1652 .freq_tbl = clk_tbl_usb_hsic,
1653 .current_freq = &rcg_dummy_freq,
1654 .c = {
1655 .dbg_name = "usb_hsic_xcvr_fs_clk",
1656 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001657 VDD_DIG_FMAX_MAP1(LOW, 60000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001658 CLK_INIT(usb_hsic_xcvr_fs_clk.c),
1659 },
1660};
1661
1662static struct branch_clk usb_hsic_system_clk = {
1663 .b = {
1664 .ctl_reg = USB_HSIC_SYSTEM_CLK_CTL_REG,
1665 .en_mask = BIT(4),
1666 .reset_reg = USB_HSIC_RESET_REG,
1667 .reset_mask = BIT(0),
1668 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1669 .halt_bit = 24,
1670 },
1671 .parent = &usb_hsic_xcvr_fs_clk.c,
1672 .c = {
1673 .dbg_name = "usb_hsic_system_clk",
1674 .ops = &clk_ops_branch,
1675 CLK_INIT(usb_hsic_system_clk.c),
1676 },
1677};
1678
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001679#define F_USB_HSIC(f, s) \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001680 { \
1681 .freq_hz = f, \
1682 .src_clk = &s##_clk.c, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001683 }
1684static struct clk_freq_tbl clk_tbl_usb2_hsic[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001685 F_USB_HSIC(480000000, pll14),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001686 F_END
1687};
1688
1689static struct rcg_clk usb_hsic_hsic_src_clk = {
1690 .b = {
1691 .ctl_reg = USB_HSIC_HSIC_CLK_SRC_CTL_REG,
1692 .halt_check = NOCHECK,
1693 },
1694 .root_en_mask = BIT(0),
1695 .set_rate = set_rate_nop,
1696 .freq_tbl = clk_tbl_usb2_hsic,
1697 .current_freq = &rcg_dummy_freq,
1698 .c = {
1699 .dbg_name = "usb_hsic_hsic_src_clk",
1700 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001701 VDD_DIG_FMAX_MAP1(LOW, 480000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001702 CLK_INIT(usb_hsic_hsic_src_clk.c),
1703 },
1704};
1705
1706static struct branch_clk usb_hsic_hsic_clk = {
1707 .b = {
1708 .ctl_reg = USB_HSIC_HSIC_CLK_CTL_REG,
1709 .en_mask = BIT(0),
1710 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1711 .halt_bit = 19,
1712 },
1713 .parent = &usb_hsic_hsic_src_clk.c,
1714 .c = {
1715 .dbg_name = "usb_hsic_hsic_clk",
1716 .ops = &clk_ops_branch,
1717 CLK_INIT(usb_hsic_hsic_clk.c),
1718 },
1719};
1720
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001721#define F_USB_HSIO_CAL(f, s) \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001722 { \
1723 .freq_hz = f, \
1724 .src_clk = &s##_clk.c, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07001725 }
1726static struct clk_freq_tbl clk_tbl_usb_hsio_cal[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001727 F_USB_HSIO_CAL(9000000, pxo),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001728 F_END
1729};
1730
1731static struct rcg_clk usb_hsic_hsio_cal_clk = {
1732 .b = {
1733 .ctl_reg = USB_HSIC_HSIO_CAL_CLK_CTL_REG,
1734 .en_mask = BIT(0),
1735 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1736 .halt_bit = 23,
1737 },
1738 .set_rate = set_rate_nop,
1739 .freq_tbl = clk_tbl_usb_hsio_cal,
1740 .current_freq = &rcg_dummy_freq,
1741 .c = {
1742 .dbg_name = "usb_hsic_hsio_cal_clk",
Stephen Boyda0e82ec2011-09-19 12:18:45 -07001743 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001744 VDD_DIG_FMAX_MAP1(LOW, 10000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07001745 CLK_INIT(usb_hsic_hsio_cal_clk.c),
1746 },
1747};
1748
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001749static struct branch_clk usb_phy0_clk = {
1750 .b = {
1751 .reset_reg = USB_PHY0_RESET_REG,
1752 .reset_mask = BIT(0),
1753 },
1754 .c = {
1755 .dbg_name = "usb_phy0_clk",
1756 .ops = &clk_ops_reset,
1757 CLK_INIT(usb_phy0_clk.c),
1758 },
1759};
1760
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001761#define CLK_USB_FS(i, n, fmax_nom) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001762 struct rcg_clk i##_clk = { \
1763 .ns_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1764 .b = { \
1765 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(n), \
1766 .halt_check = NOCHECK, \
1767 }, \
1768 .md_reg = USB_FSn_XCVR_FS_CLK_MD_REG(n), \
1769 .root_en_mask = BIT(11), \
1770 .ns_mask = (BM(23, 16) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08001771 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001772 .set_rate = set_rate_mnd, \
1773 .freq_tbl = clk_tbl_usb, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001774 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001775 .c = { \
1776 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07001777 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001778 VDD_DIG_FMAX_MAP1(NOMINAL, fmax_nom), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001779 CLK_INIT(i##_clk.c), \
1780 }, \
1781 }
1782
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001783static CLK_USB_FS(usb_fs1_src, 1, 64000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001784static struct branch_clk usb_fs1_xcvr_clk = {
1785 .b = {
1786 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(1),
1787 .en_mask = BIT(9),
1788 .reset_reg = USB_FSn_RESET_REG(1),
1789 .reset_mask = BIT(1),
1790 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1791 .halt_bit = 15,
1792 },
1793 .parent = &usb_fs1_src_clk.c,
1794 .c = {
1795 .dbg_name = "usb_fs1_xcvr_clk",
1796 .ops = &clk_ops_branch,
1797 CLK_INIT(usb_fs1_xcvr_clk.c),
1798 },
1799};
1800
1801static struct branch_clk usb_fs1_sys_clk = {
1802 .b = {
1803 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(1),
1804 .en_mask = BIT(4),
1805 .reset_reg = USB_FSn_RESET_REG(1),
1806 .reset_mask = BIT(0),
1807 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1808 .halt_bit = 16,
1809 },
1810 .parent = &usb_fs1_src_clk.c,
1811 .c = {
1812 .dbg_name = "usb_fs1_sys_clk",
1813 .ops = &clk_ops_branch,
1814 CLK_INIT(usb_fs1_sys_clk.c),
1815 },
1816};
1817
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001818static CLK_USB_FS(usb_fs2_src, 2, 60000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001819static struct branch_clk usb_fs2_xcvr_clk = {
1820 .b = {
1821 .ctl_reg = USB_FSn_XCVR_FS_CLK_NS_REG(2),
1822 .en_mask = BIT(9),
1823 .reset_reg = USB_FSn_RESET_REG(2),
1824 .reset_mask = BIT(1),
1825 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1826 .halt_bit = 12,
1827 },
1828 .parent = &usb_fs2_src_clk.c,
1829 .c = {
1830 .dbg_name = "usb_fs2_xcvr_clk",
1831 .ops = &clk_ops_branch,
1832 CLK_INIT(usb_fs2_xcvr_clk.c),
1833 },
1834};
1835
1836static struct branch_clk usb_fs2_sys_clk = {
1837 .b = {
1838 .ctl_reg = USB_FSn_SYSTEM_CLK_CTL_REG(2),
1839 .en_mask = BIT(4),
1840 .reset_reg = USB_FSn_RESET_REG(2),
1841 .reset_mask = BIT(0),
1842 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
1843 .halt_bit = 13,
1844 },
1845 .parent = &usb_fs2_src_clk.c,
1846 .c = {
1847 .dbg_name = "usb_fs2_sys_clk",
1848 .ops = &clk_ops_branch,
1849 CLK_INIT(usb_fs2_sys_clk.c),
1850 },
1851};
1852
1853/* Fast Peripheral Bus Clocks */
1854static struct branch_clk ce1_core_clk = {
1855 .b = {
1856 .ctl_reg = CE1_CORE_CLK_CTL_REG,
1857 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001858 .hwcg_reg = CE1_CORE_CLK_CTL_REG,
1859 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001860 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1861 .halt_bit = 27,
1862 },
1863 .c = {
1864 .dbg_name = "ce1_core_clk",
1865 .ops = &clk_ops_branch,
1866 CLK_INIT(ce1_core_clk.c),
1867 },
1868};
Tianyi Gou41515e22011-09-01 19:37:43 -07001869
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001870static struct branch_clk ce1_p_clk = {
1871 .b = {
1872 .ctl_reg = CE1_HCLK_CTL_REG,
1873 .en_mask = BIT(4),
1874 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1875 .halt_bit = 1,
1876 },
1877 .c = {
1878 .dbg_name = "ce1_p_clk",
1879 .ops = &clk_ops_branch,
1880 CLK_INIT(ce1_p_clk.c),
1881 },
1882};
1883
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001884#define F_CE3(f, s, d) \
Tianyi Gou41515e22011-09-01 19:37:43 -07001885 { \
1886 .freq_hz = f, \
1887 .src_clk = &s##_clk.c, \
1888 .ns_val = NS_DIVSRC(6, 3, d, 2, 0, s##_to_bb_mux), \
Tianyi Gou41515e22011-09-01 19:37:43 -07001889 }
1890
1891static struct clk_freq_tbl clk_tbl_ce3[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001892 F_CE3( 0, gnd, 1),
1893 F_CE3( 48000000, pll8, 8),
1894 F_CE3(100000000, pll3, 12),
Tianyi Gou41515e22011-09-01 19:37:43 -07001895 F_END
1896};
1897
1898static struct rcg_clk ce3_src_clk = {
1899 .b = {
1900 .ctl_reg = CE3_CLK_SRC_NS_REG,
1901 .halt_check = NOCHECK,
1902 },
1903 .ns_reg = CE3_CLK_SRC_NS_REG,
1904 .root_en_mask = BIT(7),
1905 .ns_mask = BM(6, 0),
1906 .set_rate = set_rate_nop,
1907 .freq_tbl = clk_tbl_ce3,
1908 .current_freq = &rcg_dummy_freq,
1909 .c = {
1910 .dbg_name = "ce3_src_clk",
1911 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07001912 VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
Tianyi Gou41515e22011-09-01 19:37:43 -07001913 CLK_INIT(ce3_src_clk.c),
1914 },
1915};
1916
1917static struct branch_clk ce3_core_clk = {
1918 .b = {
1919 .ctl_reg = CE3_CORE_CLK_CTL_REG,
1920 .en_mask = BIT(4),
1921 .reset_reg = CE3_CORE_CLK_CTL_REG,
1922 .reset_mask = BIT(7),
1923 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1924 .halt_bit = 5,
1925 },
1926 .parent = &ce3_src_clk.c,
1927 .c = {
1928 .dbg_name = "ce3_core_clk",
1929 .ops = &clk_ops_branch,
1930 CLK_INIT(ce3_core_clk.c),
1931 }
1932};
1933
1934static struct branch_clk ce3_p_clk = {
1935 .b = {
1936 .ctl_reg = CE3_HCLK_CTL_REG,
1937 .en_mask = BIT(4),
1938 .reset_reg = CE3_HCLK_CTL_REG,
1939 .reset_mask = BIT(7),
1940 .halt_reg = CLK_HALT_AFAB_SFAB_STATEB_REG,
1941 .halt_bit = 16,
1942 },
1943 .parent = &ce3_src_clk.c,
1944 .c = {
1945 .dbg_name = "ce3_p_clk",
1946 .ops = &clk_ops_branch,
1947 CLK_INIT(ce3_p_clk.c),
1948 }
1949};
1950
1951static struct branch_clk sata_phy_ref_clk = {
1952 .b = {
1953 .ctl_reg = SATA_PHY_REF_CLK_CTL_REG,
1954 .en_mask = BIT(4),
1955 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
1956 .halt_bit = 24,
1957 },
1958 .parent = &pxo_clk.c,
1959 .c = {
1960 .dbg_name = "sata_phy_ref_clk",
1961 .ops = &clk_ops_branch,
1962 CLK_INIT(sata_phy_ref_clk.c),
1963 },
1964};
1965
1966static struct branch_clk pcie_p_clk = {
1967 .b = {
1968 .ctl_reg = PCIE_HCLK_CTL_REG,
1969 .en_mask = BIT(4),
1970 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
1971 .halt_bit = 8,
1972 },
1973 .c = {
1974 .dbg_name = "pcie_p_clk",
1975 .ops = &clk_ops_branch,
1976 CLK_INIT(pcie_p_clk.c),
1977 },
1978};
1979
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001980static struct branch_clk dma_bam_p_clk = {
1981 .b = {
1982 .ctl_reg = DMA_BAM_HCLK_CTL,
1983 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08001984 .hwcg_reg = DMA_BAM_HCLK_CTL,
1985 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001986 .halt_reg = CLK_HALT_DFAB_STATE_REG,
1987 .halt_bit = 12,
1988 },
1989 .c = {
1990 .dbg_name = "dma_bam_p_clk",
1991 .ops = &clk_ops_branch,
1992 CLK_INIT(dma_bam_p_clk.c),
1993 },
1994};
1995
1996static struct branch_clk gsbi1_p_clk = {
1997 .b = {
1998 .ctl_reg = GSBIn_HCLK_CTL_REG(1),
1999 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002000 .hwcg_reg = GSBIn_HCLK_CTL_REG(1),
2001 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002002 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2003 .halt_bit = 11,
2004 },
2005 .c = {
2006 .dbg_name = "gsbi1_p_clk",
2007 .ops = &clk_ops_branch,
2008 CLK_INIT(gsbi1_p_clk.c),
2009 },
2010};
2011
2012static struct branch_clk gsbi2_p_clk = {
2013 .b = {
2014 .ctl_reg = GSBIn_HCLK_CTL_REG(2),
2015 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002016 .hwcg_reg = GSBIn_HCLK_CTL_REG(2),
2017 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002018 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2019 .halt_bit = 7,
2020 },
2021 .c = {
2022 .dbg_name = "gsbi2_p_clk",
2023 .ops = &clk_ops_branch,
2024 CLK_INIT(gsbi2_p_clk.c),
2025 },
2026};
2027
2028static struct branch_clk gsbi3_p_clk = {
2029 .b = {
2030 .ctl_reg = GSBIn_HCLK_CTL_REG(3),
2031 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002032 .hwcg_reg = GSBIn_HCLK_CTL_REG(3),
2033 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002034 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2035 .halt_bit = 3,
2036 },
2037 .c = {
2038 .dbg_name = "gsbi3_p_clk",
2039 .ops = &clk_ops_branch,
2040 CLK_INIT(gsbi3_p_clk.c),
2041 },
2042};
2043
2044static struct branch_clk gsbi4_p_clk = {
2045 .b = {
2046 .ctl_reg = GSBIn_HCLK_CTL_REG(4),
2047 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002048 .hwcg_reg = GSBIn_HCLK_CTL_REG(4),
2049 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002050 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2051 .halt_bit = 27,
2052 },
2053 .c = {
2054 .dbg_name = "gsbi4_p_clk",
2055 .ops = &clk_ops_branch,
2056 CLK_INIT(gsbi4_p_clk.c),
2057 },
2058};
2059
2060static struct branch_clk gsbi5_p_clk = {
2061 .b = {
2062 .ctl_reg = GSBIn_HCLK_CTL_REG(5),
2063 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002064 .hwcg_reg = GSBIn_HCLK_CTL_REG(5),
2065 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002066 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2067 .halt_bit = 23,
2068 },
2069 .c = {
2070 .dbg_name = "gsbi5_p_clk",
2071 .ops = &clk_ops_branch,
2072 CLK_INIT(gsbi5_p_clk.c),
2073 },
2074};
2075
2076static struct branch_clk gsbi6_p_clk = {
2077 .b = {
2078 .ctl_reg = GSBIn_HCLK_CTL_REG(6),
2079 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002080 .hwcg_reg = GSBIn_HCLK_CTL_REG(6),
2081 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002082 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2083 .halt_bit = 19,
2084 },
2085 .c = {
2086 .dbg_name = "gsbi6_p_clk",
2087 .ops = &clk_ops_branch,
2088 CLK_INIT(gsbi6_p_clk.c),
2089 },
2090};
2091
2092static struct branch_clk gsbi7_p_clk = {
2093 .b = {
2094 .ctl_reg = GSBIn_HCLK_CTL_REG(7),
2095 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002096 .hwcg_reg = GSBIn_HCLK_CTL_REG(7),
2097 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002098 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2099 .halt_bit = 15,
2100 },
2101 .c = {
2102 .dbg_name = "gsbi7_p_clk",
2103 .ops = &clk_ops_branch,
2104 CLK_INIT(gsbi7_p_clk.c),
2105 },
2106};
2107
2108static struct branch_clk gsbi8_p_clk = {
2109 .b = {
2110 .ctl_reg = GSBIn_HCLK_CTL_REG(8),
2111 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002112 .hwcg_reg = GSBIn_HCLK_CTL_REG(8),
2113 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002114 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2115 .halt_bit = 11,
2116 },
2117 .c = {
2118 .dbg_name = "gsbi8_p_clk",
2119 .ops = &clk_ops_branch,
2120 CLK_INIT(gsbi8_p_clk.c),
2121 },
2122};
2123
2124static struct branch_clk gsbi9_p_clk = {
2125 .b = {
2126 .ctl_reg = GSBIn_HCLK_CTL_REG(9),
2127 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002128 .hwcg_reg = GSBIn_HCLK_CTL_REG(9),
2129 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002130 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2131 .halt_bit = 7,
2132 },
2133 .c = {
2134 .dbg_name = "gsbi9_p_clk",
2135 .ops = &clk_ops_branch,
2136 CLK_INIT(gsbi9_p_clk.c),
2137 },
2138};
2139
2140static struct branch_clk gsbi10_p_clk = {
2141 .b = {
2142 .ctl_reg = GSBIn_HCLK_CTL_REG(10),
2143 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002144 .hwcg_reg = GSBIn_HCLK_CTL_REG(10),
2145 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002146 .halt_reg = CLK_HALT_CFPB_STATEB_REG,
2147 .halt_bit = 3,
2148 },
2149 .c = {
2150 .dbg_name = "gsbi10_p_clk",
2151 .ops = &clk_ops_branch,
2152 CLK_INIT(gsbi10_p_clk.c),
2153 },
2154};
2155
2156static struct branch_clk gsbi11_p_clk = {
2157 .b = {
2158 .ctl_reg = GSBIn_HCLK_CTL_REG(11),
2159 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002160 .hwcg_reg = GSBIn_HCLK_CTL_REG(11),
2161 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002162 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2163 .halt_bit = 18,
2164 },
2165 .c = {
2166 .dbg_name = "gsbi11_p_clk",
2167 .ops = &clk_ops_branch,
2168 CLK_INIT(gsbi11_p_clk.c),
2169 },
2170};
2171
2172static struct branch_clk gsbi12_p_clk = {
2173 .b = {
2174 .ctl_reg = GSBIn_HCLK_CTL_REG(12),
2175 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002176 .hwcg_reg = GSBIn_HCLK_CTL_REG(12),
2177 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002178 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2179 .halt_bit = 14,
2180 },
2181 .c = {
2182 .dbg_name = "gsbi12_p_clk",
2183 .ops = &clk_ops_branch,
2184 CLK_INIT(gsbi12_p_clk.c),
2185 },
2186};
2187
Tianyi Gou41515e22011-09-01 19:37:43 -07002188static struct branch_clk sata_phy_cfg_clk = {
2189 .b = {
2190 .ctl_reg = SATA_PHY_CFG_CLK_CTL_REG,
2191 .en_mask = BIT(4),
2192 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2193 .halt_bit = 12,
2194 },
2195 .c = {
2196 .dbg_name = "sata_phy_cfg_clk",
2197 .ops = &clk_ops_branch,
2198 CLK_INIT(sata_phy_cfg_clk.c),
Stephen Boyd973e4ba2011-07-12 17:06:01 -07002199 },
2200};
2201
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002202static struct branch_clk tsif_p_clk = {
2203 .b = {
2204 .ctl_reg = TSIF_HCLK_CTL_REG,
2205 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002206 .hwcg_reg = TSIF_HCLK_CTL_REG,
2207 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002208 .halt_reg = CLK_HALT_CFPB_STATEC_REG,
2209 .halt_bit = 7,
2210 },
2211 .c = {
2212 .dbg_name = "tsif_p_clk",
2213 .ops = &clk_ops_branch,
2214 CLK_INIT(tsif_p_clk.c),
2215 },
2216};
2217
2218static struct branch_clk usb_fs1_p_clk = {
2219 .b = {
2220 .ctl_reg = USB_FSn_HCLK_CTL_REG(1),
2221 .en_mask = BIT(4),
2222 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2223 .halt_bit = 17,
2224 },
2225 .c = {
2226 .dbg_name = "usb_fs1_p_clk",
2227 .ops = &clk_ops_branch,
2228 CLK_INIT(usb_fs1_p_clk.c),
2229 },
2230};
2231
2232static struct branch_clk usb_fs2_p_clk = {
2233 .b = {
2234 .ctl_reg = USB_FSn_HCLK_CTL_REG(2),
2235 .en_mask = BIT(4),
2236 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2237 .halt_bit = 14,
2238 },
2239 .c = {
2240 .dbg_name = "usb_fs2_p_clk",
2241 .ops = &clk_ops_branch,
2242 CLK_INIT(usb_fs2_p_clk.c),
2243 },
2244};
2245
2246static struct branch_clk usb_hs1_p_clk = {
2247 .b = {
2248 .ctl_reg = USB_HS1_HCLK_CTL_REG,
2249 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002250 .hwcg_reg = USB_HS1_HCLK_CTL_REG,
2251 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002252 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2253 .halt_bit = 1,
2254 },
2255 .c = {
2256 .dbg_name = "usb_hs1_p_clk",
2257 .ops = &clk_ops_branch,
2258 CLK_INIT(usb_hs1_p_clk.c),
2259 },
2260};
2261
Tianyi Gou41515e22011-09-01 19:37:43 -07002262static struct branch_clk usb_hs3_p_clk = {
2263 .b = {
2264 .ctl_reg = USB_HS3_HCLK_CTL_REG,
2265 .en_mask = BIT(4),
2266 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2267 .halt_bit = 31,
2268 },
2269 .c = {
2270 .dbg_name = "usb_hs3_p_clk",
2271 .ops = &clk_ops_branch,
2272 CLK_INIT(usb_hs3_p_clk.c),
2273 },
2274};
2275
2276static struct branch_clk usb_hs4_p_clk = {
2277 .b = {
2278 .ctl_reg = USB_HS4_HCLK_CTL_REG,
2279 .en_mask = BIT(4),
2280 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2281 .halt_bit = 7,
2282 },
2283 .c = {
2284 .dbg_name = "usb_hs4_p_clk",
2285 .ops = &clk_ops_branch,
2286 CLK_INIT(usb_hs4_p_clk.c),
2287 },
2288};
2289
Stephen Boyd94625ef2011-07-12 17:06:01 -07002290static struct branch_clk usb_hsic_p_clk = {
2291 .b = {
2292 .ctl_reg = USB_HSIC_HCLK_CTL_REG,
2293 .en_mask = BIT(4),
2294 .halt_reg = CLK_HALT_CFPB_STATEA_REG,
2295 .halt_bit = 28,
2296 },
2297 .c = {
2298 .dbg_name = "usb_hsic_p_clk",
2299 .ops = &clk_ops_branch,
2300 CLK_INIT(usb_hsic_p_clk.c),
2301 },
2302};
2303
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002304static struct branch_clk sdc1_p_clk = {
2305 .b = {
2306 .ctl_reg = SDCn_HCLK_CTL_REG(1),
2307 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002308 .hwcg_reg = SDCn_HCLK_CTL_REG(1),
2309 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002310 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2311 .halt_bit = 11,
2312 },
2313 .c = {
2314 .dbg_name = "sdc1_p_clk",
2315 .ops = &clk_ops_branch,
2316 CLK_INIT(sdc1_p_clk.c),
2317 },
2318};
2319
2320static struct branch_clk sdc2_p_clk = {
2321 .b = {
2322 .ctl_reg = SDCn_HCLK_CTL_REG(2),
2323 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002324 .hwcg_reg = SDCn_HCLK_CTL_REG(2),
2325 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002326 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2327 .halt_bit = 10,
2328 },
2329 .c = {
2330 .dbg_name = "sdc2_p_clk",
2331 .ops = &clk_ops_branch,
2332 CLK_INIT(sdc2_p_clk.c),
2333 },
2334};
2335
2336static struct branch_clk sdc3_p_clk = {
2337 .b = {
2338 .ctl_reg = SDCn_HCLK_CTL_REG(3),
2339 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002340 .hwcg_reg = SDCn_HCLK_CTL_REG(3),
2341 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002342 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2343 .halt_bit = 9,
2344 },
2345 .c = {
2346 .dbg_name = "sdc3_p_clk",
2347 .ops = &clk_ops_branch,
2348 CLK_INIT(sdc3_p_clk.c),
2349 },
2350};
2351
2352static struct branch_clk sdc4_p_clk = {
2353 .b = {
2354 .ctl_reg = SDCn_HCLK_CTL_REG(4),
2355 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002356 .hwcg_reg = SDCn_HCLK_CTL_REG(4),
2357 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002358 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2359 .halt_bit = 8,
2360 },
2361 .c = {
2362 .dbg_name = "sdc4_p_clk",
2363 .ops = &clk_ops_branch,
2364 CLK_INIT(sdc4_p_clk.c),
2365 },
2366};
2367
2368static struct branch_clk sdc5_p_clk = {
2369 .b = {
2370 .ctl_reg = SDCn_HCLK_CTL_REG(5),
2371 .en_mask = BIT(4),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002372 .hwcg_reg = SDCn_HCLK_CTL_REG(5),
2373 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002374 .halt_reg = CLK_HALT_DFAB_STATE_REG,
2375 .halt_bit = 7,
2376 },
2377 .c = {
2378 .dbg_name = "sdc5_p_clk",
2379 .ops = &clk_ops_branch,
2380 CLK_INIT(sdc5_p_clk.c),
2381 },
2382};
2383
2384/* HW-Voteable Clocks */
2385static struct branch_clk adm0_clk = {
2386 .b = {
2387 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2388 .en_mask = BIT(2),
2389 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2390 .halt_check = HALT_VOTED,
2391 .halt_bit = 14,
2392 },
2393 .c = {
2394 .dbg_name = "adm0_clk",
2395 .ops = &clk_ops_branch,
2396 CLK_INIT(adm0_clk.c),
2397 },
2398};
2399
2400static struct branch_clk adm0_p_clk = {
2401 .b = {
2402 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2403 .en_mask = BIT(3),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002404 .hwcg_reg = ADM0_PBUS_CLK_CTL_REG,
2405 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002406 .halt_reg = CLK_HALT_MSS_SMPSS_MISC_STATE_REG,
2407 .halt_check = HALT_VOTED,
2408 .halt_bit = 13,
2409 },
2410 .c = {
2411 .dbg_name = "adm0_p_clk",
2412 .ops = &clk_ops_branch,
2413 CLK_INIT(adm0_p_clk.c),
2414 },
2415};
2416
2417static struct branch_clk pmic_arb0_p_clk = {
2418 .b = {
2419 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2420 .en_mask = BIT(8),
2421 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2422 .halt_check = HALT_VOTED,
2423 .halt_bit = 22,
2424 },
2425 .c = {
2426 .dbg_name = "pmic_arb0_p_clk",
2427 .ops = &clk_ops_branch,
2428 CLK_INIT(pmic_arb0_p_clk.c),
2429 },
2430};
2431
2432static struct branch_clk pmic_arb1_p_clk = {
2433 .b = {
2434 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2435 .en_mask = BIT(9),
2436 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2437 .halt_check = HALT_VOTED,
2438 .halt_bit = 21,
2439 },
2440 .c = {
2441 .dbg_name = "pmic_arb1_p_clk",
2442 .ops = &clk_ops_branch,
2443 CLK_INIT(pmic_arb1_p_clk.c),
2444 },
2445};
2446
2447static struct branch_clk pmic_ssbi2_clk = {
2448 .b = {
2449 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2450 .en_mask = BIT(7),
2451 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2452 .halt_check = HALT_VOTED,
2453 .halt_bit = 23,
2454 },
2455 .c = {
2456 .dbg_name = "pmic_ssbi2_clk",
2457 .ops = &clk_ops_branch,
2458 CLK_INIT(pmic_ssbi2_clk.c),
2459 },
2460};
2461
2462static struct branch_clk rpm_msg_ram_p_clk = {
2463 .b = {
2464 .ctl_reg = SC0_U_CLK_BRANCH_ENA_VOTE_REG,
2465 .en_mask = BIT(6),
Stephen Boyda52d7e32011-11-10 11:59:00 -08002466 .hwcg_reg = RPM_MSG_RAM_HCLK_CTL_REG,
2467 .hwcg_mask = BIT(6),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002468 .halt_reg = CLK_HALT_SFPB_MISC_STATE_REG,
2469 .halt_check = HALT_VOTED,
2470 .halt_bit = 12,
2471 },
2472 .c = {
2473 .dbg_name = "rpm_msg_ram_p_clk",
2474 .ops = &clk_ops_branch,
2475 CLK_INIT(rpm_msg_ram_p_clk.c),
2476 },
2477};
2478
2479/*
2480 * Multimedia Clocks
2481 */
2482
2483static struct branch_clk amp_clk = {
2484 .b = {
2485 .reset_reg = SW_RESET_CORE_REG,
2486 .reset_mask = BIT(20),
2487 },
2488 .c = {
2489 .dbg_name = "amp_clk",
2490 .ops = &clk_ops_reset,
2491 CLK_INIT(amp_clk.c),
2492 },
2493};
2494
Stephen Boyd94625ef2011-07-12 17:06:01 -07002495#define CLK_CAM(name, n, hb) \
2496 struct rcg_clk name = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002497 .b = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002498 .ctl_reg = CAMCLK##n##_CC_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002499 .en_mask = BIT(0), \
2500 .halt_reg = DBG_BUS_VEC_I_REG, \
2501 .halt_bit = hb, \
2502 }, \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002503 .ns_reg = CAMCLK##n##_NS_REG, \
2504 .md_reg = CAMCLK##n##_MD_REG, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002505 .root_en_mask = BIT(2), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002506 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0), \
Matt Wagantall07c45472012-02-10 23:27:24 -08002507 .mnd_en_mask = BIT(5), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002508 .ctl_mask = BM(7, 6), \
2509 .set_rate = set_rate_mnd_8, \
2510 .freq_tbl = clk_tbl_cam, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002511 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002512 .c = { \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002513 .dbg_name = #name, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002514 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002515 VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000), \
Stephen Boyd94625ef2011-07-12 17:06:01 -07002516 CLK_INIT(name.c), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002517 }, \
2518 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002519#define F_CAM(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002520 { \
2521 .freq_hz = f, \
2522 .src_clk = &s##_clk.c, \
2523 .md_val = MD8(8, m, 0, n), \
2524 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2525 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002526 }
2527static struct clk_freq_tbl clk_tbl_cam[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002528 F_CAM( 0, gnd, 1, 0, 0),
2529 F_CAM( 6000000, pll8, 4, 1, 16),
2530 F_CAM( 8000000, pll8, 4, 1, 12),
2531 F_CAM( 12000000, pll8, 4, 1, 8),
2532 F_CAM( 16000000, pll8, 4, 1, 6),
2533 F_CAM( 19200000, pll8, 4, 1, 5),
2534 F_CAM( 24000000, pll8, 4, 1, 4),
2535 F_CAM( 32000000, pll8, 4, 1, 3),
2536 F_CAM( 48000000, pll8, 4, 1, 2),
2537 F_CAM( 64000000, pll8, 3, 1, 2),
2538 F_CAM( 96000000, pll8, 4, 0, 0),
2539 F_CAM(128000000, pll8, 3, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002540 F_END
2541};
2542
Stephen Boyd94625ef2011-07-12 17:06:01 -07002543static CLK_CAM(cam0_clk, 0, 15);
2544static CLK_CAM(cam1_clk, 1, 16);
2545static CLK_CAM(cam2_clk, 2, 31);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002546
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002547#define F_CSI(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002548 { \
2549 .freq_hz = f, \
2550 .src_clk = &s##_clk.c, \
2551 .md_val = MD8(8, m, 0, n), \
2552 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2553 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002554 }
2555static struct clk_freq_tbl clk_tbl_csi[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002556 F_CSI( 0, gnd, 1, 0, 0),
Stephen Boyd092fd182011-10-21 15:56:30 -07002557 F_CSI( 27000000, pxo, 1, 0, 0),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002558 F_CSI( 85330000, pll8, 1, 2, 9),
2559 F_CSI(177780000, pll2, 1, 2, 9),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002560 F_END
2561};
2562
2563static struct rcg_clk csi0_src_clk = {
2564 .ns_reg = CSI0_NS_REG,
2565 .b = {
2566 .ctl_reg = CSI0_CC_REG,
2567 .halt_check = NOCHECK,
2568 },
2569 .md_reg = CSI0_MD_REG,
2570 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002571 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Matt Wagantall07c45472012-02-10 23:27:24 -08002572 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002573 .ctl_mask = BM(7, 6),
2574 .set_rate = set_rate_mnd,
2575 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002576 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002577 .c = {
2578 .dbg_name = "csi0_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002579 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002580 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002581 CLK_INIT(csi0_src_clk.c),
2582 },
2583};
2584
2585static struct branch_clk csi0_clk = {
2586 .b = {
2587 .ctl_reg = CSI0_CC_REG,
2588 .en_mask = BIT(0),
2589 .reset_reg = SW_RESET_CORE_REG,
2590 .reset_mask = BIT(8),
2591 .halt_reg = DBG_BUS_VEC_B_REG,
2592 .halt_bit = 13,
2593 },
2594 .parent = &csi0_src_clk.c,
2595 .c = {
2596 .dbg_name = "csi0_clk",
2597 .ops = &clk_ops_branch,
2598 CLK_INIT(csi0_clk.c),
2599 },
2600};
2601
2602static struct branch_clk csi0_phy_clk = {
2603 .b = {
2604 .ctl_reg = CSI0_CC_REG,
2605 .en_mask = BIT(8),
2606 .reset_reg = SW_RESET_CORE_REG,
2607 .reset_mask = BIT(29),
2608 .halt_reg = DBG_BUS_VEC_I_REG,
2609 .halt_bit = 9,
2610 },
2611 .parent = &csi0_src_clk.c,
2612 .c = {
2613 .dbg_name = "csi0_phy_clk",
2614 .ops = &clk_ops_branch,
2615 CLK_INIT(csi0_phy_clk.c),
2616 },
2617};
2618
2619static struct rcg_clk csi1_src_clk = {
2620 .ns_reg = CSI1_NS_REG,
2621 .b = {
2622 .ctl_reg = CSI1_CC_REG,
2623 .halt_check = NOCHECK,
2624 },
2625 .md_reg = CSI1_MD_REG,
2626 .root_en_mask = BIT(2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002627 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Matt Wagantall07c45472012-02-10 23:27:24 -08002628 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002629 .ctl_mask = BM(7, 6),
2630 .set_rate = set_rate_mnd,
2631 .freq_tbl = clk_tbl_csi,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002632 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002633 .c = {
2634 .dbg_name = "csi1_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07002635 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002636 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002637 CLK_INIT(csi1_src_clk.c),
2638 },
2639};
2640
2641static struct branch_clk csi1_clk = {
2642 .b = {
2643 .ctl_reg = CSI1_CC_REG,
2644 .en_mask = BIT(0),
2645 .reset_reg = SW_RESET_CORE_REG,
2646 .reset_mask = BIT(18),
2647 .halt_reg = DBG_BUS_VEC_B_REG,
2648 .halt_bit = 14,
2649 },
2650 .parent = &csi1_src_clk.c,
2651 .c = {
2652 .dbg_name = "csi1_clk",
2653 .ops = &clk_ops_branch,
2654 CLK_INIT(csi1_clk.c),
2655 },
2656};
2657
2658static struct branch_clk csi1_phy_clk = {
2659 .b = {
2660 .ctl_reg = CSI1_CC_REG,
2661 .en_mask = BIT(8),
2662 .reset_reg = SW_RESET_CORE_REG,
2663 .reset_mask = BIT(28),
2664 .halt_reg = DBG_BUS_VEC_I_REG,
2665 .halt_bit = 10,
2666 },
2667 .parent = &csi1_src_clk.c,
2668 .c = {
2669 .dbg_name = "csi1_phy_clk",
2670 .ops = &clk_ops_branch,
2671 CLK_INIT(csi1_phy_clk.c),
2672 },
2673};
2674
Stephen Boyd94625ef2011-07-12 17:06:01 -07002675static struct rcg_clk csi2_src_clk = {
2676 .ns_reg = CSI2_NS_REG,
2677 .b = {
2678 .ctl_reg = CSI2_CC_REG,
2679 .halt_check = NOCHECK,
2680 },
2681 .md_reg = CSI2_MD_REG,
2682 .root_en_mask = BIT(2),
2683 .ns_mask = BM(31, 24) | BM(15, 14) | BM(2, 0),
Matt Wagantall07c45472012-02-10 23:27:24 -08002684 .mnd_en_mask = BIT(5),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002685 .ctl_mask = BM(7, 6),
2686 .set_rate = set_rate_mnd,
2687 .freq_tbl = clk_tbl_csi,
2688 .current_freq = &rcg_dummy_freq,
2689 .c = {
2690 .dbg_name = "csi2_src_clk",
2691 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002692 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002693 CLK_INIT(csi2_src_clk.c),
2694 },
2695};
2696
2697static struct branch_clk csi2_clk = {
2698 .b = {
2699 .ctl_reg = CSI2_CC_REG,
2700 .en_mask = BIT(0),
2701 .reset_reg = SW_RESET_CORE2_REG,
2702 .reset_mask = BIT(2),
2703 .halt_reg = DBG_BUS_VEC_B_REG,
2704 .halt_bit = 29,
2705 },
2706 .parent = &csi2_src_clk.c,
2707 .c = {
2708 .dbg_name = "csi2_clk",
2709 .ops = &clk_ops_branch,
2710 CLK_INIT(csi2_clk.c),
2711 },
2712};
2713
2714static struct branch_clk csi2_phy_clk = {
2715 .b = {
2716 .ctl_reg = CSI2_CC_REG,
2717 .en_mask = BIT(8),
2718 .reset_reg = SW_RESET_CORE_REG,
2719 .reset_mask = BIT(31),
2720 .halt_reg = DBG_BUS_VEC_I_REG,
2721 .halt_bit = 29,
2722 },
2723 .parent = &csi2_src_clk.c,
2724 .c = {
2725 .dbg_name = "csi2_phy_clk",
2726 .ops = &clk_ops_branch,
2727 CLK_INIT(csi2_phy_clk.c),
2728 },
2729};
2730
Stephen Boyd092fd182011-10-21 15:56:30 -07002731static struct clk *pix_rdi_mux_map[] = {
2732 [0] = &csi0_clk.c,
2733 [1] = &csi1_clk.c,
2734 [2] = &csi2_clk.c,
2735 NULL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002736};
2737
Stephen Boyd092fd182011-10-21 15:56:30 -07002738struct pix_rdi_clk {
2739 bool enabled;
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002740 unsigned long cur_rate;
Stephen Boyd092fd182011-10-21 15:56:30 -07002741
2742 void __iomem *const s_reg;
2743 u32 s_mask;
2744
2745 void __iomem *const s2_reg;
2746 u32 s2_mask;
2747
2748 struct branch b;
2749 struct clk c;
2750};
2751
2752static inline struct pix_rdi_clk *to_pix_rdi_clk(struct clk *clk)
2753{
2754 return container_of(clk, struct pix_rdi_clk, c);
2755}
2756
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002757static int pix_rdi_clk_set_rate(struct clk *c, unsigned long rate)
Stephen Boyd092fd182011-10-21 15:56:30 -07002758{
2759 int ret, i;
2760 u32 reg;
2761 unsigned long flags;
2762 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2763 struct clk **mux_map = pix_rdi_mux_map;
2764
2765 /*
2766 * These clocks select three inputs via two muxes. One mux selects
2767 * between csi0 and csi1 and the second mux selects between that mux's
2768 * output and csi2. The source and destination selections for each
2769 * mux must be clocking for the switch to succeed so just turn on
2770 * all three sources because it's easier than figuring out what source
2771 * needs to be on at what time.
2772 */
2773 for (i = 0; mux_map[i]; i++) {
2774 ret = clk_enable(mux_map[i]);
2775 if (ret)
2776 goto err;
2777 }
2778 if (rate >= i) {
2779 ret = -EINVAL;
2780 goto err;
2781 }
2782 /* Keep the new source on when switching inputs of an enabled clock */
2783 if (clk->enabled) {
2784 clk_disable(mux_map[clk->cur_rate]);
2785 clk_enable(mux_map[rate]);
2786 }
2787 spin_lock_irqsave(&local_clock_reg_lock, flags);
2788 reg = readl_relaxed(clk->s2_reg);
2789 reg &= ~clk->s2_mask;
2790 reg |= rate == 2 ? clk->s2_mask : 0;
2791 writel_relaxed(reg, clk->s2_reg);
2792 /*
2793 * Wait at least 6 cycles of slowest clock
2794 * for the glitch-free MUX to fully switch sources.
2795 */
2796 mb();
2797 udelay(1);
2798 reg = readl_relaxed(clk->s_reg);
2799 reg &= ~clk->s_mask;
2800 reg |= rate == 1 ? clk->s_mask : 0;
2801 writel_relaxed(reg, clk->s_reg);
2802 /*
2803 * Wait at least 6 cycles of slowest clock
2804 * for the glitch-free MUX to fully switch sources.
2805 */
2806 mb();
2807 udelay(1);
2808 clk->cur_rate = rate;
2809 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2810err:
2811 for (i--; i >= 0; i--)
2812 clk_disable(mux_map[i]);
2813
2814 return 0;
2815}
2816
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07002817static unsigned long pix_rdi_clk_get_rate(struct clk *c)
Stephen Boyd092fd182011-10-21 15:56:30 -07002818{
2819 return to_pix_rdi_clk(c)->cur_rate;
2820}
2821
2822static int pix_rdi_clk_enable(struct clk *c)
2823{
2824 unsigned long flags;
2825 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2826
2827 spin_lock_irqsave(&local_clock_reg_lock, flags);
2828 __branch_clk_enable_reg(&clk->b, clk->c.dbg_name);
2829 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2830 clk->enabled = true;
2831
2832 return 0;
2833}
2834
2835static void pix_rdi_clk_disable(struct clk *c)
2836{
2837 unsigned long flags;
2838 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2839
2840 spin_lock_irqsave(&local_clock_reg_lock, flags);
2841 __branch_clk_disable_reg(&clk->b, clk->c.dbg_name);
2842 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
2843 clk->enabled = false;
2844}
2845
2846static int pix_rdi_clk_reset(struct clk *clk, enum clk_reset_action action)
2847{
2848 return branch_reset(&to_pix_rdi_clk(clk)->b, action);
2849}
2850
2851static struct clk *pix_rdi_clk_get_parent(struct clk *c)
2852{
2853 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
2854
2855 return pix_rdi_mux_map[clk->cur_rate];
2856}
2857
2858static int pix_rdi_clk_list_rate(struct clk *c, unsigned n)
2859{
2860 if (pix_rdi_mux_map[n])
2861 return n;
2862 return -ENXIO;
2863}
2864
Matt Wagantalla15833b2012-04-03 11:00:56 -07002865static enum handoff pix_rdi_clk_handoff(struct clk *c)
Stephen Boyd092fd182011-10-21 15:56:30 -07002866{
2867 u32 reg;
2868 struct pix_rdi_clk *clk = to_pix_rdi_clk(c);
Matt Wagantalla15833b2012-04-03 11:00:56 -07002869 enum handoff ret;
2870
2871 ret = branch_handoff(&clk->b, &clk->c);
2872 if (ret == HANDOFF_DISABLED_CLK)
2873 return ret;
Stephen Boyd092fd182011-10-21 15:56:30 -07002874
2875 reg = readl_relaxed(clk->s_reg);
2876 clk->cur_rate = reg & clk->s_mask ? 1 : 0;
2877 reg = readl_relaxed(clk->s2_reg);
2878 clk->cur_rate = reg & clk->s2_mask ? 2 : clk->cur_rate;
Matt Wagantalla15833b2012-04-03 11:00:56 -07002879
2880 return HANDOFF_ENABLED_CLK;
Stephen Boyd092fd182011-10-21 15:56:30 -07002881}
2882
2883static struct clk_ops clk_ops_pix_rdi_8960 = {
2884 .enable = pix_rdi_clk_enable,
2885 .disable = pix_rdi_clk_disable,
2886 .auto_off = pix_rdi_clk_disable,
2887 .handoff = pix_rdi_clk_handoff,
2888 .set_rate = pix_rdi_clk_set_rate,
2889 .get_rate = pix_rdi_clk_get_rate,
2890 .list_rate = pix_rdi_clk_list_rate,
2891 .reset = pix_rdi_clk_reset,
Stephen Boyd092fd182011-10-21 15:56:30 -07002892 .get_parent = pix_rdi_clk_get_parent,
2893};
2894
2895static struct pix_rdi_clk csi_pix_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002896 .b = {
2897 .ctl_reg = MISC_CC_REG,
2898 .en_mask = BIT(26),
2899 .halt_check = DELAY,
2900 .reset_reg = SW_RESET_CORE_REG,
2901 .reset_mask = BIT(26),
2902 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002903 .s_reg = MISC_CC_REG,
2904 .s_mask = BIT(25),
2905 .s2_reg = MISC_CC3_REG,
2906 .s2_mask = BIT(13),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002907 .c = {
2908 .dbg_name = "csi_pix_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002909 .ops = &clk_ops_pix_rdi_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002910 CLK_INIT(csi_pix_clk.c),
2911 },
2912};
2913
Stephen Boyd092fd182011-10-21 15:56:30 -07002914static struct pix_rdi_clk csi_pix1_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07002915 .b = {
2916 .ctl_reg = MISC_CC3_REG,
2917 .en_mask = BIT(10),
2918 .halt_check = DELAY,
2919 .reset_reg = SW_RESET_CORE_REG,
2920 .reset_mask = BIT(30),
2921 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002922 .s_reg = MISC_CC3_REG,
2923 .s_mask = BIT(8),
2924 .s2_reg = MISC_CC3_REG,
2925 .s2_mask = BIT(9),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002926 .c = {
2927 .dbg_name = "csi_pix1_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002928 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07002929 CLK_INIT(csi_pix1_clk.c),
2930 },
2931};
2932
Stephen Boyd092fd182011-10-21 15:56:30 -07002933static struct pix_rdi_clk csi_rdi_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002934 .b = {
2935 .ctl_reg = MISC_CC_REG,
2936 .en_mask = BIT(13),
2937 .halt_check = DELAY,
2938 .reset_reg = SW_RESET_CORE_REG,
2939 .reset_mask = BIT(27),
2940 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002941 .s_reg = MISC_CC_REG,
2942 .s_mask = BIT(12),
2943 .s2_reg = MISC_CC3_REG,
2944 .s2_mask = BIT(12),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002945 .c = {
2946 .dbg_name = "csi_rdi_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002947 .ops = &clk_ops_pix_rdi_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002948 CLK_INIT(csi_rdi_clk.c),
2949 },
2950};
2951
Stephen Boyd092fd182011-10-21 15:56:30 -07002952static struct pix_rdi_clk csi_rdi1_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07002953 .b = {
2954 .ctl_reg = MISC_CC3_REG,
2955 .en_mask = BIT(2),
2956 .halt_check = DELAY,
2957 .reset_reg = SW_RESET_CORE2_REG,
2958 .reset_mask = BIT(1),
2959 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002960 .s_reg = MISC_CC3_REG,
2961 .s_mask = BIT(0),
2962 .s2_reg = MISC_CC3_REG,
2963 .s2_mask = BIT(1),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002964 .c = {
2965 .dbg_name = "csi_rdi1_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002966 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07002967 CLK_INIT(csi_rdi1_clk.c),
2968 },
2969};
2970
Stephen Boyd092fd182011-10-21 15:56:30 -07002971static struct pix_rdi_clk csi_rdi2_clk = {
Stephen Boyd94625ef2011-07-12 17:06:01 -07002972 .b = {
2973 .ctl_reg = MISC_CC3_REG,
2974 .en_mask = BIT(6),
2975 .halt_check = DELAY,
2976 .reset_reg = SW_RESET_CORE2_REG,
2977 .reset_mask = BIT(0),
2978 },
Stephen Boyd092fd182011-10-21 15:56:30 -07002979 .s_reg = MISC_CC3_REG,
2980 .s_mask = BIT(4),
2981 .s2_reg = MISC_CC3_REG,
2982 .s2_mask = BIT(5),
Stephen Boyd94625ef2011-07-12 17:06:01 -07002983 .c = {
2984 .dbg_name = "csi_rdi2_clk",
Stephen Boyd092fd182011-10-21 15:56:30 -07002985 .ops = &clk_ops_pix_rdi_8960,
Stephen Boyd94625ef2011-07-12 17:06:01 -07002986 CLK_INIT(csi_rdi2_clk.c),
2987 },
2988};
2989
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002990#define F_CSI_PHYTIMER(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002991 { \
2992 .freq_hz = f, \
2993 .src_clk = &s##_clk.c, \
2994 .md_val = MD8(8, m, 0, n), \
2995 .ns_val = NS_MM(31, 24, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
2996 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002997 }
2998static struct clk_freq_tbl clk_tbl_csi_phytimer[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07002999 F_CSI_PHYTIMER( 0, gnd, 1, 0, 0),
3000 F_CSI_PHYTIMER( 85330000, pll8, 1, 2, 9),
3001 F_CSI_PHYTIMER(177780000, pll2, 1, 2, 9),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003002 F_END
3003};
3004
3005static struct rcg_clk csiphy_timer_src_clk = {
3006 .ns_reg = CSIPHYTIMER_NS_REG,
3007 .b = {
3008 .ctl_reg = CSIPHYTIMER_CC_REG,
3009 .halt_check = NOCHECK,
3010 },
3011 .md_reg = CSIPHYTIMER_MD_REG,
3012 .root_en_mask = BIT(2),
3013 .ns_mask = (BM(31, 24) | BM(15, 14) | BM(2, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08003014 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003015 .ctl_mask = BM(7, 6),
3016 .set_rate = set_rate_mnd_8,
3017 .freq_tbl = clk_tbl_csi_phytimer,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003018 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003019 .c = {
3020 .dbg_name = "csiphy_timer_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003021 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003022 VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003023 CLK_INIT(csiphy_timer_src_clk.c),
3024 },
3025};
3026
3027static struct branch_clk csi0phy_timer_clk = {
3028 .b = {
3029 .ctl_reg = CSIPHYTIMER_CC_REG,
3030 .en_mask = BIT(0),
3031 .halt_reg = DBG_BUS_VEC_I_REG,
3032 .halt_bit = 17,
3033 },
3034 .parent = &csiphy_timer_src_clk.c,
3035 .c = {
3036 .dbg_name = "csi0phy_timer_clk",
3037 .ops = &clk_ops_branch,
3038 CLK_INIT(csi0phy_timer_clk.c),
3039 },
3040};
3041
3042static struct branch_clk csi1phy_timer_clk = {
3043 .b = {
3044 .ctl_reg = CSIPHYTIMER_CC_REG,
3045 .en_mask = BIT(9),
3046 .halt_reg = DBG_BUS_VEC_I_REG,
3047 .halt_bit = 18,
3048 },
3049 .parent = &csiphy_timer_src_clk.c,
3050 .c = {
3051 .dbg_name = "csi1phy_timer_clk",
3052 .ops = &clk_ops_branch,
3053 CLK_INIT(csi1phy_timer_clk.c),
3054 },
3055};
3056
Stephen Boyd94625ef2011-07-12 17:06:01 -07003057static struct branch_clk csi2phy_timer_clk = {
3058 .b = {
3059 .ctl_reg = CSIPHYTIMER_CC_REG,
3060 .en_mask = BIT(11),
3061 .halt_reg = DBG_BUS_VEC_I_REG,
3062 .halt_bit = 30,
3063 },
3064 .parent = &csiphy_timer_src_clk.c,
3065 .c = {
3066 .dbg_name = "csi2phy_timer_clk",
3067 .ops = &clk_ops_branch,
3068 CLK_INIT(csi2phy_timer_clk.c),
3069 },
3070};
3071
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003072#define F_DSI(d) \
3073 { \
3074 .freq_hz = d, \
3075 .ns_val = BVAL(15, 12, (d-1)), \
3076 }
3077/*
3078 * The DSI_BYTE/ESC clock is sourced from the DSI PHY PLL, which may change rate
3079 * without this clock driver knowing. So, overload the clk_set_rate() to set
3080 * the divider (1 to 16) of the clock with respect to the PLL rate.
3081 */
3082static struct clk_freq_tbl clk_tbl_dsi_byte[] = {
3083 F_DSI(1), F_DSI(2), F_DSI(3), F_DSI(4),
3084 F_DSI(5), F_DSI(6), F_DSI(7), F_DSI(8),
3085 F_DSI(9), F_DSI(10), F_DSI(11), F_DSI(12),
3086 F_DSI(13), F_DSI(14), F_DSI(15), F_DSI(16),
3087 F_END
3088};
3089
3090static struct rcg_clk dsi1_byte_clk = {
3091 .b = {
3092 .ctl_reg = DSI1_BYTE_CC_REG,
3093 .en_mask = BIT(0),
3094 .reset_reg = SW_RESET_CORE_REG,
3095 .reset_mask = BIT(7),
3096 .halt_reg = DBG_BUS_VEC_B_REG,
3097 .halt_bit = 21,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003098 .retain_reg = DSI1_BYTE_CC_REG,
3099 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003100 },
3101 .ns_reg = DSI1_BYTE_NS_REG,
3102 .root_en_mask = BIT(2),
3103 .ns_mask = BM(15, 12),
3104 .set_rate = set_rate_nop,
3105 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003106 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003107 .c = {
3108 .dbg_name = "dsi1_byte_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003109 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003110 CLK_INIT(dsi1_byte_clk.c),
3111 },
3112};
3113
3114static struct rcg_clk dsi2_byte_clk = {
3115 .b = {
3116 .ctl_reg = DSI2_BYTE_CC_REG,
3117 .en_mask = BIT(0),
3118 .reset_reg = SW_RESET_CORE_REG,
3119 .reset_mask = BIT(25),
3120 .halt_reg = DBG_BUS_VEC_B_REG,
3121 .halt_bit = 20,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003122 .retain_reg = DSI2_BYTE_CC_REG,
3123 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003124 },
3125 .ns_reg = DSI2_BYTE_NS_REG,
3126 .root_en_mask = BIT(2),
3127 .ns_mask = BM(15, 12),
3128 .set_rate = set_rate_nop,
3129 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003130 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003131 .c = {
3132 .dbg_name = "dsi2_byte_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003133 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003134 CLK_INIT(dsi2_byte_clk.c),
3135 },
3136};
3137
3138static struct rcg_clk dsi1_esc_clk = {
3139 .b = {
3140 .ctl_reg = DSI1_ESC_CC_REG,
3141 .en_mask = BIT(0),
3142 .reset_reg = SW_RESET_CORE_REG,
3143 .halt_reg = DBG_BUS_VEC_I_REG,
3144 .halt_bit = 1,
3145 },
3146 .ns_reg = DSI1_ESC_NS_REG,
3147 .root_en_mask = BIT(2),
3148 .ns_mask = BM(15, 12),
3149 .set_rate = set_rate_nop,
3150 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003151 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003152 .c = {
3153 .dbg_name = "dsi1_esc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003154 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003155 CLK_INIT(dsi1_esc_clk.c),
3156 },
3157};
3158
3159static struct rcg_clk dsi2_esc_clk = {
3160 .b = {
3161 .ctl_reg = DSI2_ESC_CC_REG,
3162 .en_mask = BIT(0),
3163 .halt_reg = DBG_BUS_VEC_I_REG,
3164 .halt_bit = 3,
3165 },
3166 .ns_reg = DSI2_ESC_NS_REG,
3167 .root_en_mask = BIT(2),
3168 .ns_mask = BM(15, 12),
3169 .set_rate = set_rate_nop,
3170 .freq_tbl = clk_tbl_dsi_byte,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003171 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003172 .c = {
3173 .dbg_name = "dsi2_esc_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003174 .ops = &clk_ops_rcg_8960,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003175 CLK_INIT(dsi2_esc_clk.c),
3176 },
3177};
3178
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003179#define F_GFX2D(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003180 { \
3181 .freq_hz = f, \
3182 .src_clk = &s##_clk.c, \
3183 .md_val = MD4(4, m, 0, n), \
3184 .ns_val = NS_MND_BANKED4(20, 16, n, m, 3, 0, s##_to_mm_mux), \
3185 .ctl_val = CC_BANKED(9, 6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003186 }
3187static struct clk_freq_tbl clk_tbl_gfx2d[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003188 F_GFX2D( 0, gnd, 0, 0),
3189 F_GFX2D( 27000000, pxo, 0, 0),
3190 F_GFX2D( 48000000, pll8, 1, 8),
3191 F_GFX2D( 54857000, pll8, 1, 7),
3192 F_GFX2D( 64000000, pll8, 1, 6),
3193 F_GFX2D( 76800000, pll8, 1, 5),
3194 F_GFX2D( 96000000, pll8, 1, 4),
3195 F_GFX2D(128000000, pll8, 1, 3),
3196 F_GFX2D(145455000, pll2, 2, 11),
3197 F_GFX2D(160000000, pll2, 1, 5),
3198 F_GFX2D(177778000, pll2, 2, 9),
3199 F_GFX2D(200000000, pll2, 1, 4),
3200 F_GFX2D(228571000, pll2, 2, 7),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003201 F_END
3202};
3203
3204static struct bank_masks bmnd_info_gfx2d0 = {
3205 .bank_sel_mask = BIT(11),
3206 .bank0_mask = {
3207 .md_reg = GFX2D0_MD0_REG,
3208 .ns_mask = BM(23, 20) | BM(5, 3),
3209 .rst_mask = BIT(25),
3210 .mnd_en_mask = BIT(8),
3211 .mode_mask = BM(10, 9),
3212 },
3213 .bank1_mask = {
3214 .md_reg = GFX2D0_MD1_REG,
3215 .ns_mask = BM(19, 16) | BM(2, 0),
3216 .rst_mask = BIT(24),
3217 .mnd_en_mask = BIT(5),
3218 .mode_mask = BM(7, 6),
3219 },
3220};
3221
3222static struct rcg_clk gfx2d0_clk = {
3223 .b = {
3224 .ctl_reg = GFX2D0_CC_REG,
3225 .en_mask = BIT(0),
3226 .reset_reg = SW_RESET_CORE_REG,
3227 .reset_mask = BIT(14),
3228 .halt_reg = DBG_BUS_VEC_A_REG,
3229 .halt_bit = 9,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003230 .retain_reg = GFX2D0_CC_REG,
3231 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003232 },
3233 .ns_reg = GFX2D0_NS_REG,
3234 .root_en_mask = BIT(2),
3235 .set_rate = set_rate_mnd_banked,
3236 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003237 .bank_info = &bmnd_info_gfx2d0,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003238 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003239 .c = {
3240 .dbg_name = "gfx2d0_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003241 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003242 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
3243 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003244 CLK_INIT(gfx2d0_clk.c),
3245 },
3246};
3247
3248static struct bank_masks bmnd_info_gfx2d1 = {
3249 .bank_sel_mask = BIT(11),
3250 .bank0_mask = {
3251 .md_reg = GFX2D1_MD0_REG,
3252 .ns_mask = BM(23, 20) | BM(5, 3),
3253 .rst_mask = BIT(25),
3254 .mnd_en_mask = BIT(8),
3255 .mode_mask = BM(10, 9),
3256 },
3257 .bank1_mask = {
3258 .md_reg = GFX2D1_MD1_REG,
3259 .ns_mask = BM(19, 16) | BM(2, 0),
3260 .rst_mask = BIT(24),
3261 .mnd_en_mask = BIT(5),
3262 .mode_mask = BM(7, 6),
3263 },
3264};
3265
3266static struct rcg_clk gfx2d1_clk = {
3267 .b = {
3268 .ctl_reg = GFX2D1_CC_REG,
3269 .en_mask = BIT(0),
3270 .reset_reg = SW_RESET_CORE_REG,
3271 .reset_mask = BIT(13),
3272 .halt_reg = DBG_BUS_VEC_A_REG,
3273 .halt_bit = 14,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003274 .retain_reg = GFX2D1_CC_REG,
3275 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003276 },
3277 .ns_reg = GFX2D1_NS_REG,
3278 .root_en_mask = BIT(2),
3279 .set_rate = set_rate_mnd_banked,
3280 .freq_tbl = clk_tbl_gfx2d,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003281 .bank_info = &bmnd_info_gfx2d1,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003282 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003283 .c = {
3284 .dbg_name = "gfx2d1_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003285 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003286 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
3287 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003288 CLK_INIT(gfx2d1_clk.c),
3289 },
3290};
3291
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003292#define F_GFX3D(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003293 { \
3294 .freq_hz = f, \
3295 .src_clk = &s##_clk.c, \
3296 .md_val = MD4(4, m, 0, n), \
3297 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3298 .ctl_val = CC_BANKED(9, 6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003299 }
Tianyi Gou41515e22011-09-01 19:37:43 -07003300
3301static struct clk_freq_tbl clk_tbl_gfx3d_8960[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003302 F_GFX3D( 0, gnd, 0, 0),
3303 F_GFX3D( 27000000, pxo, 0, 0),
3304 F_GFX3D( 48000000, pll8, 1, 8),
3305 F_GFX3D( 54857000, pll8, 1, 7),
3306 F_GFX3D( 64000000, pll8, 1, 6),
3307 F_GFX3D( 76800000, pll8, 1, 5),
3308 F_GFX3D( 96000000, pll8, 1, 4),
3309 F_GFX3D(128000000, pll8, 1, 3),
3310 F_GFX3D(145455000, pll2, 2, 11),
3311 F_GFX3D(160000000, pll2, 1, 5),
3312 F_GFX3D(177778000, pll2, 2, 9),
3313 F_GFX3D(200000000, pll2, 1, 4),
3314 F_GFX3D(228571000, pll2, 2, 7),
3315 F_GFX3D(266667000, pll2, 1, 3),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003316 F_GFX3D(300000000, pll3, 1, 4),
3317 F_GFX3D(320000000, pll2, 2, 5),
3318 F_GFX3D(400000000, pll2, 1, 2),
Stephen Boyd94625ef2011-07-12 17:06:01 -07003319 F_END
3320};
3321
Tianyi Gou41515e22011-09-01 19:37:43 -07003322static struct clk_freq_tbl clk_tbl_gfx3d_8064[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003323 F_GFX3D( 0, gnd, 0, 0),
3324 F_GFX3D( 27000000, pxo, 0, 0),
3325 F_GFX3D( 48000000, pll8, 1, 8),
3326 F_GFX3D( 54857000, pll8, 1, 7),
3327 F_GFX3D( 64000000, pll8, 1, 6),
3328 F_GFX3D( 76800000, pll8, 1, 5),
3329 F_GFX3D( 96000000, pll8, 1, 4),
3330 F_GFX3D(128000000, pll8, 1, 3),
3331 F_GFX3D(145455000, pll2, 2, 11),
3332 F_GFX3D(160000000, pll2, 1, 5),
3333 F_GFX3D(177778000, pll2, 2, 9),
3334 F_GFX3D(200000000, pll2, 1, 4),
3335 F_GFX3D(228571000, pll2, 2, 7),
3336 F_GFX3D(266667000, pll2, 1, 3),
Tianyi Gou0c50fe32011-10-19 15:50:35 -07003337 F_GFX3D(325000000, pll15, 1, 3),
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003338 F_GFX3D(400000000, pll2, 1, 2),
Tianyi Gou41515e22011-09-01 19:37:43 -07003339 F_END
3340};
3341
Tianyi Goue3d4f542012-03-15 17:06:45 -07003342static struct clk_freq_tbl clk_tbl_gfx3d_8930[] = {
3343 F_GFX3D( 0, gnd, 0, 0),
3344 F_GFX3D( 27000000, pxo, 0, 0),
3345 F_GFX3D( 48000000, pll8, 1, 8),
3346 F_GFX3D( 54857000, pll8, 1, 7),
3347 F_GFX3D( 64000000, pll8, 1, 6),
3348 F_GFX3D( 76800000, pll8, 1, 5),
3349 F_GFX3D( 96000000, pll8, 1, 4),
3350 F_GFX3D(128000000, pll8, 1, 3),
3351 F_GFX3D(145455000, pll2, 2, 11),
3352 F_GFX3D(160000000, pll2, 1, 5),
3353 F_GFX3D(177778000, pll2, 2, 9),
Tianyi Gou4d33c9c2012-03-30 11:10:15 -07003354 F_GFX3D(192000000, pll8, 1, 2),
Tianyi Goue3d4f542012-03-15 17:06:45 -07003355 F_GFX3D(200000000, pll2, 1, 4),
3356 F_GFX3D(228571000, pll2, 2, 7),
3357 F_GFX3D(266667000, pll2, 1, 3),
3358 F_GFX3D(300000000, pll3, 1, 4),
3359 F_GFX3D(320000000, pll2, 2, 5),
3360 F_GFX3D(400000000, pll2, 1, 2),
3361 F_GFX3D(450000000, pll15, 1, 2),
3362 F_END
3363};
3364
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003365static unsigned long fmax_gfx3d_8064[MAX_VDD_LEVELS] __initdata = {
3366 [VDD_DIG_LOW] = 128000000,
3367 [VDD_DIG_NOMINAL] = 325000000,
3368 [VDD_DIG_HIGH] = 400000000
3369};
3370
Tianyi Goue3d4f542012-03-15 17:06:45 -07003371static unsigned long fmax_gfx3d_8930[MAX_VDD_LEVELS] __initdata = {
Tianyi Gou4d33c9c2012-03-30 11:10:15 -07003372 [VDD_DIG_LOW] = 192000000,
Tianyi Goue3d4f542012-03-15 17:06:45 -07003373 [VDD_DIG_NOMINAL] = 320000000,
3374 [VDD_DIG_HIGH] = 450000000
3375};
3376
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003377static struct bank_masks bmnd_info_gfx3d = {
3378 .bank_sel_mask = BIT(11),
3379 .bank0_mask = {
3380 .md_reg = GFX3D_MD0_REG,
3381 .ns_mask = BM(21, 18) | BM(5, 3),
3382 .rst_mask = BIT(23),
3383 .mnd_en_mask = BIT(8),
3384 .mode_mask = BM(10, 9),
3385 },
3386 .bank1_mask = {
3387 .md_reg = GFX3D_MD1_REG,
3388 .ns_mask = BM(17, 14) | BM(2, 0),
3389 .rst_mask = BIT(22),
3390 .mnd_en_mask = BIT(5),
3391 .mode_mask = BM(7, 6),
3392 },
3393};
3394
3395static struct rcg_clk gfx3d_clk = {
3396 .b = {
3397 .ctl_reg = GFX3D_CC_REG,
3398 .en_mask = BIT(0),
3399 .reset_reg = SW_RESET_CORE_REG,
3400 .reset_mask = BIT(12),
3401 .halt_reg = DBG_BUS_VEC_A_REG,
3402 .halt_bit = 4,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003403 .retain_reg = GFX3D_CC_REG,
3404 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003405 },
3406 .ns_reg = GFX3D_NS_REG,
3407 .root_en_mask = BIT(2),
3408 .set_rate = set_rate_mnd_banked,
Tianyi Gou41515e22011-09-01 19:37:43 -07003409 .freq_tbl = clk_tbl_gfx3d_8960,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003410 .bank_info = &bmnd_info_gfx3d,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003411 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003412 .c = {
3413 .dbg_name = "gfx3d_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003414 .ops = &clk_ops_rcg_8960,
Tianyi Gou3022dfd2012-01-25 15:50:05 -08003415 VDD_DIG_FMAX_MAP3(LOW, 128000000, NOMINAL, 300000000,
3416 HIGH, 400000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003417 CLK_INIT(gfx3d_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003418 .depends = &gmem_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003419 },
3420};
3421
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003422#define F_VCAP(f, s, m, n) \
Tianyi Gou621f8742011-09-01 21:45:01 -07003423 { \
3424 .freq_hz = f, \
3425 .src_clk = &s##_clk.c, \
3426 .md_val = MD4(4, m, 0, n), \
3427 .ns_val = NS_MND_BANKED4(18, 14, n, m, 3, 0, s##_to_mm_mux), \
3428 .ctl_val = CC_BANKED(9, 6, n), \
Tianyi Gou621f8742011-09-01 21:45:01 -07003429 }
3430
3431static struct clk_freq_tbl clk_tbl_vcap[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003432 F_VCAP( 0, gnd, 0, 0),
3433 F_VCAP( 27000000, pxo, 0, 0),
3434 F_VCAP( 54860000, pll8, 1, 7),
3435 F_VCAP( 64000000, pll8, 1, 6),
3436 F_VCAP( 76800000, pll8, 1, 5),
3437 F_VCAP(128000000, pll8, 1, 3),
3438 F_VCAP(160000000, pll2, 1, 5),
3439 F_VCAP(200000000, pll2, 1, 4),
Tianyi Gou621f8742011-09-01 21:45:01 -07003440 F_END
3441};
3442
3443static struct bank_masks bmnd_info_vcap = {
3444 .bank_sel_mask = BIT(11),
3445 .bank0_mask = {
3446 .md_reg = VCAP_MD0_REG,
3447 .ns_mask = BM(21, 18) | BM(5, 3),
3448 .rst_mask = BIT(23),
3449 .mnd_en_mask = BIT(8),
3450 .mode_mask = BM(10, 9),
3451 },
3452 .bank1_mask = {
3453 .md_reg = VCAP_MD1_REG,
3454 .ns_mask = BM(17, 14) | BM(2, 0),
3455 .rst_mask = BIT(22),
3456 .mnd_en_mask = BIT(5),
3457 .mode_mask = BM(7, 6),
3458 },
3459};
3460
3461static struct rcg_clk vcap_clk = {
3462 .b = {
3463 .ctl_reg = VCAP_CC_REG,
3464 .en_mask = BIT(0),
3465 .halt_reg = DBG_BUS_VEC_J_REG,
3466 .halt_bit = 15,
3467 },
3468 .ns_reg = VCAP_NS_REG,
3469 .root_en_mask = BIT(2),
3470 .set_rate = set_rate_mnd_banked,
3471 .freq_tbl = clk_tbl_vcap,
3472 .bank_info = &bmnd_info_vcap,
3473 .current_freq = &rcg_dummy_freq,
3474 .c = {
3475 .dbg_name = "vcap_clk",
3476 .ops = &clk_ops_rcg_8960,
3477 .depends = &vcap_axi_clk.c,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003478 VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
Tianyi Gou621f8742011-09-01 21:45:01 -07003479 CLK_INIT(vcap_clk.c),
3480 },
3481};
3482
3483static struct branch_clk vcap_npl_clk = {
3484 .b = {
3485 .ctl_reg = VCAP_CC_REG,
3486 .en_mask = BIT(13),
3487 .halt_reg = DBG_BUS_VEC_J_REG,
3488 .halt_bit = 25,
3489 },
3490 .parent = &vcap_clk.c,
3491 .c = {
3492 .dbg_name = "vcap_npl_clk",
3493 .ops = &clk_ops_branch,
3494 CLK_INIT(vcap_npl_clk.c),
3495 },
3496};
3497
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003498#define F_IJPEG(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003499 { \
3500 .freq_hz = f, \
3501 .src_clk = &s##_clk.c, \
3502 .md_val = MD8(8, m, 0, n), \
3503 .ns_val = NS_MM(23, 16, n, m, 15, 12, d, 2, 0, s##_to_mm_mux), \
3504 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003505 }
Tianyi Gou41515e22011-09-01 19:37:43 -07003506
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003507static struct clk_freq_tbl clk_tbl_ijpeg[] = {
3508 F_IJPEG( 0, gnd, 1, 0, 0),
3509 F_IJPEG( 27000000, pxo, 1, 0, 0),
3510 F_IJPEG( 36570000, pll8, 1, 2, 21),
3511 F_IJPEG( 54860000, pll8, 7, 0, 0),
3512 F_IJPEG( 96000000, pll8, 4, 0, 0),
3513 F_IJPEG(109710000, pll8, 1, 2, 7),
3514 F_IJPEG(128000000, pll8, 3, 0, 0),
3515 F_IJPEG(153600000, pll8, 1, 2, 5),
3516 F_IJPEG(200000000, pll2, 4, 0, 0),
3517 F_IJPEG(228571000, pll2, 1, 2, 7),
3518 F_IJPEG(266667000, pll2, 1, 1, 3),
3519 F_IJPEG(320000000, pll2, 1, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003520 F_END
3521};
3522
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003523static unsigned long fmax_ijpeg_8064[MAX_VDD_LEVELS] __initdata = {
3524 [VDD_DIG_LOW] = 128000000,
3525 [VDD_DIG_NOMINAL] = 266667000,
3526 [VDD_DIG_HIGH] = 320000000
Tianyi Gou41515e22011-09-01 19:37:43 -07003527};
3528
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003529static struct rcg_clk ijpeg_clk = {
3530 .b = {
3531 .ctl_reg = IJPEG_CC_REG,
3532 .en_mask = BIT(0),
3533 .reset_reg = SW_RESET_CORE_REG,
3534 .reset_mask = BIT(9),
3535 .halt_reg = DBG_BUS_VEC_A_REG,
3536 .halt_bit = 24,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003537 .retain_reg = IJPEG_CC_REG,
3538 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003539 },
3540 .ns_reg = IJPEG_NS_REG,
3541 .md_reg = IJPEG_MD_REG,
3542 .root_en_mask = BIT(2),
3543 .ns_mask = (BM(23, 16) | BM(15, 12) | BM(2, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08003544 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003545 .ctl_mask = BM(7, 6),
3546 .set_rate = set_rate_mnd,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003547 .freq_tbl = clk_tbl_ijpeg,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003548 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003549 .c = {
3550 .dbg_name = "ijpeg_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003551 .ops = &clk_ops_rcg_8960,
Tianyi Gou3022dfd2012-01-25 15:50:05 -08003552 VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 266667000,
3553 HIGH, 320000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003554 CLK_INIT(ijpeg_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003555 .depends = &ijpeg_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003556 },
3557};
3558
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003559#define F_JPEGD(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003560 { \
3561 .freq_hz = f, \
3562 .src_clk = &s##_clk.c, \
3563 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003564 }
3565static struct clk_freq_tbl clk_tbl_jpegd[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003566 F_JPEGD( 0, gnd, 1),
3567 F_JPEGD( 64000000, pll8, 6),
3568 F_JPEGD( 76800000, pll8, 5),
3569 F_JPEGD( 96000000, pll8, 4),
3570 F_JPEGD(160000000, pll2, 5),
3571 F_JPEGD(200000000, pll2, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003572 F_END
3573};
3574
3575static struct rcg_clk jpegd_clk = {
3576 .b = {
3577 .ctl_reg = JPEGD_CC_REG,
3578 .en_mask = BIT(0),
3579 .reset_reg = SW_RESET_CORE_REG,
3580 .reset_mask = BIT(19),
3581 .halt_reg = DBG_BUS_VEC_A_REG,
3582 .halt_bit = 19,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003583 .retain_reg = JPEGD_CC_REG,
3584 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003585 },
3586 .ns_reg = JPEGD_NS_REG,
3587 .root_en_mask = BIT(2),
3588 .ns_mask = (BM(15, 12) | BM(2, 0)),
3589 .set_rate = set_rate_nop,
3590 .freq_tbl = clk_tbl_jpegd,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003591 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003592 .c = {
3593 .dbg_name = "jpegd_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003594 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003595 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003596 CLK_INIT(jpegd_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003597 .depends = &jpegd_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003598 },
3599};
3600
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003601#define F_MDP(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003602 { \
3603 .freq_hz = f, \
3604 .src_clk = &s##_clk.c, \
3605 .md_val = MD8(8, m, 0, n), \
3606 .ns_val = NS_MND_BANKED8(22, 14, n, m, 3, 0, s##_to_mm_mux), \
3607 .ctl_val = CC_BANKED(9, 6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003608 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003609static struct clk_freq_tbl clk_tbl_mdp[] = {
3610 F_MDP( 0, gnd, 0, 0),
3611 F_MDP( 9600000, pll8, 1, 40),
3612 F_MDP( 13710000, pll8, 1, 28),
3613 F_MDP( 27000000, pxo, 0, 0),
3614 F_MDP( 29540000, pll8, 1, 13),
3615 F_MDP( 34910000, pll8, 1, 11),
3616 F_MDP( 38400000, pll8, 1, 10),
3617 F_MDP( 59080000, pll8, 2, 13),
3618 F_MDP( 76800000, pll8, 1, 5),
3619 F_MDP( 85330000, pll8, 2, 9),
3620 F_MDP( 96000000, pll8, 1, 4),
3621 F_MDP(128000000, pll8, 1, 3),
3622 F_MDP(160000000, pll2, 1, 5),
3623 F_MDP(177780000, pll2, 2, 9),
3624 F_MDP(200000000, pll2, 1, 4),
3625 F_MDP(266667000, pll2, 1, 3),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003626 F_END
3627};
3628
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003629static unsigned long fmax_mdp_8064[MAX_VDD_LEVELS] __initdata = {
3630 [VDD_DIG_LOW] = 128000000,
3631 [VDD_DIG_NOMINAL] = 266667000
Tianyi Gou621f8742011-09-01 21:45:01 -07003632};
3633
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003634static struct bank_masks bmnd_info_mdp = {
3635 .bank_sel_mask = BIT(11),
3636 .bank0_mask = {
3637 .md_reg = MDP_MD0_REG,
3638 .ns_mask = BM(29, 22) | BM(5, 3),
3639 .rst_mask = BIT(31),
3640 .mnd_en_mask = BIT(8),
3641 .mode_mask = BM(10, 9),
3642 },
3643 .bank1_mask = {
3644 .md_reg = MDP_MD1_REG,
3645 .ns_mask = BM(21, 14) | BM(2, 0),
3646 .rst_mask = BIT(30),
3647 .mnd_en_mask = BIT(5),
3648 .mode_mask = BM(7, 6),
3649 },
3650};
3651
3652static struct rcg_clk mdp_clk = {
3653 .b = {
3654 .ctl_reg = MDP_CC_REG,
3655 .en_mask = BIT(0),
3656 .reset_reg = SW_RESET_CORE_REG,
3657 .reset_mask = BIT(21),
3658 .halt_reg = DBG_BUS_VEC_C_REG,
3659 .halt_bit = 10,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003660 .retain_reg = MDP_CC_REG,
3661 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003662 },
3663 .ns_reg = MDP_NS_REG,
3664 .root_en_mask = BIT(2),
3665 .set_rate = set_rate_mnd_banked,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003666 .freq_tbl = clk_tbl_mdp,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003667 .bank_info = &bmnd_info_mdp,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003668 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003669 .c = {
3670 .dbg_name = "mdp_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003671 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003672 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003673 CLK_INIT(mdp_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003674 .depends = &mdp_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003675 },
3676};
3677
3678static struct branch_clk lut_mdp_clk = {
3679 .b = {
3680 .ctl_reg = MDP_LUT_CC_REG,
3681 .en_mask = BIT(0),
3682 .halt_reg = DBG_BUS_VEC_I_REG,
3683 .halt_bit = 13,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003684 .retain_reg = MDP_LUT_CC_REG,
3685 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003686 },
3687 .parent = &mdp_clk.c,
3688 .c = {
3689 .dbg_name = "lut_mdp_clk",
3690 .ops = &clk_ops_branch,
3691 CLK_INIT(lut_mdp_clk.c),
3692 },
3693};
3694
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003695#define F_MDP_VSYNC(f, s) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003696 { \
3697 .freq_hz = f, \
3698 .src_clk = &s##_clk.c, \
3699 .ns_val = NS_SRC_SEL(13, 13, s##_to_bb_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003700 }
3701static struct clk_freq_tbl clk_tbl_mdp_vsync[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003702 F_MDP_VSYNC(27000000, pxo),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003703 F_END
3704};
3705
3706static struct rcg_clk mdp_vsync_clk = {
3707 .b = {
3708 .ctl_reg = MISC_CC_REG,
3709 .en_mask = BIT(6),
3710 .reset_reg = SW_RESET_CORE_REG,
3711 .reset_mask = BIT(3),
3712 .halt_reg = DBG_BUS_VEC_B_REG,
3713 .halt_bit = 22,
3714 },
3715 .ns_reg = MISC_CC2_REG,
3716 .ns_mask = BIT(13),
3717 .set_rate = set_rate_nop,
3718 .freq_tbl = clk_tbl_mdp_vsync,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003719 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003720 .c = {
3721 .dbg_name = "mdp_vsync_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003722 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003723 VDD_DIG_FMAX_MAP1(LOW, 27000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003724 CLK_INIT(mdp_vsync_clk.c),
3725 },
3726};
3727
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003728#define F_ROT(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003729 { \
3730 .freq_hz = f, \
3731 .src_clk = &s##_clk.c, \
3732 .ns_val = NS_DIVSRC_BANKED(29, 26, 25, 22, d, \
3733 21, 19, 18, 16, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003734 }
3735static struct clk_freq_tbl clk_tbl_rot[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003736 F_ROT( 0, gnd, 1),
3737 F_ROT( 27000000, pxo, 1),
3738 F_ROT( 29540000, pll8, 13),
3739 F_ROT( 32000000, pll8, 12),
3740 F_ROT( 38400000, pll8, 10),
3741 F_ROT( 48000000, pll8, 8),
3742 F_ROT( 54860000, pll8, 7),
3743 F_ROT( 64000000, pll8, 6),
3744 F_ROT( 76800000, pll8, 5),
3745 F_ROT( 96000000, pll8, 4),
3746 F_ROT(100000000, pll2, 8),
3747 F_ROT(114290000, pll2, 7),
3748 F_ROT(133330000, pll2, 6),
3749 F_ROT(160000000, pll2, 5),
3750 F_ROT(200000000, pll2, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003751 F_END
3752};
3753
3754static struct bank_masks bdiv_info_rot = {
3755 .bank_sel_mask = BIT(30),
3756 .bank0_mask = {
3757 .ns_mask = BM(25, 22) | BM(18, 16),
3758 },
3759 .bank1_mask = {
3760 .ns_mask = BM(29, 26) | BM(21, 19),
3761 },
3762};
3763
3764static struct rcg_clk rot_clk = {
3765 .b = {
3766 .ctl_reg = ROT_CC_REG,
3767 .en_mask = BIT(0),
3768 .reset_reg = SW_RESET_CORE_REG,
3769 .reset_mask = BIT(2),
3770 .halt_reg = DBG_BUS_VEC_C_REG,
3771 .halt_bit = 15,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003772 .retain_reg = ROT_CC_REG,
3773 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003774 },
3775 .ns_reg = ROT_NS_REG,
3776 .root_en_mask = BIT(2),
3777 .set_rate = set_rate_div_banked,
3778 .freq_tbl = clk_tbl_rot,
Stephen Boydc78d9a72011-07-20 00:46:24 -07003779 .bank_info = &bdiv_info_rot,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003780 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003781 .c = {
3782 .dbg_name = "rot_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003783 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003784 VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003785 CLK_INIT(rot_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07003786 .depends = &rot_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003787 },
3788};
3789
3790static int hdmi_pll_clk_enable(struct clk *clk)
3791{
3792 int ret;
3793 unsigned long flags;
3794 spin_lock_irqsave(&local_clock_reg_lock, flags);
3795 ret = hdmi_pll_enable();
3796 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3797 return ret;
3798}
3799
3800static void hdmi_pll_clk_disable(struct clk *clk)
3801{
3802 unsigned long flags;
3803 spin_lock_irqsave(&local_clock_reg_lock, flags);
3804 hdmi_pll_disable();
3805 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
3806}
3807
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07003808static unsigned long hdmi_pll_clk_get_rate(struct clk *clk)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003809{
3810 return hdmi_pll_get_rate();
3811}
3812
Stephen Boyd5b35dee2011-09-21 12:17:38 -07003813static struct clk *hdmi_pll_clk_get_parent(struct clk *clk)
3814{
3815 return &pxo_clk.c;
3816}
3817
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003818static struct clk_ops clk_ops_hdmi_pll = {
3819 .enable = hdmi_pll_clk_enable,
3820 .disable = hdmi_pll_clk_disable,
3821 .get_rate = hdmi_pll_clk_get_rate,
Stephen Boyd5b35dee2011-09-21 12:17:38 -07003822 .get_parent = hdmi_pll_clk_get_parent,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003823};
3824
3825static struct clk hdmi_pll_clk = {
3826 .dbg_name = "hdmi_pll_clk",
3827 .ops = &clk_ops_hdmi_pll,
3828 CLK_INIT(hdmi_pll_clk),
3829};
3830
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003831#define F_TV_GND(f, s, p_r, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003832 { \
3833 .freq_hz = f, \
3834 .src_clk = &s##_clk.c, \
3835 .md_val = MD8(8, m, 0, n), \
3836 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3837 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003838 }
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003839#define F_TV(f, s, p_r, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003840 { \
3841 .freq_hz = f, \
3842 .src_clk = &s##_clk, \
3843 .md_val = MD8(8, m, 0, n), \
3844 .ns_val = NS_MM(23, 16, n, m, 15, 14, d, 2, 0, s##_to_mm_mux), \
3845 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003846 .extra_freq_data = (void *)p_r, \
3847 }
3848/* Switching TV freqs requires PLL reconfiguration. */
3849static struct clk_freq_tbl clk_tbl_tv[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003850 F_TV_GND( 0, gnd, 0, 1, 0, 0),
3851 F_TV( 25200000, hdmi_pll, 25200000, 1, 0, 0),
3852 F_TV( 27000000, hdmi_pll, 27000000, 1, 0, 0),
3853 F_TV( 27030000, hdmi_pll, 27030000, 1, 0, 0),
3854 F_TV( 74250000, hdmi_pll, 74250000, 1, 0, 0),
3855 F_TV(148500000, hdmi_pll, 148500000, 1, 0, 0),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003856 F_END
3857};
3858
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003859static unsigned long fmax_tv_src_8064[MAX_VDD_LEVELS] __initdata = {
3860 [VDD_DIG_LOW] = 74250000,
3861 [VDD_DIG_NOMINAL] = 149000000
3862};
3863
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003864/*
3865 * Unlike other clocks, the TV rate is adjusted through PLL
3866 * re-programming. It is also routed through an MND divider.
3867 */
3868void set_rate_tv(struct rcg_clk *clk, struct clk_freq_tbl *nf)
3869{
3870 unsigned long pll_rate = (unsigned long)nf->extra_freq_data;
3871 if (pll_rate)
3872 hdmi_pll_set_rate(pll_rate);
3873 set_rate_mnd(clk, nf);
3874}
3875
3876static struct rcg_clk tv_src_clk = {
3877 .ns_reg = TV_NS_REG,
3878 .b = {
3879 .ctl_reg = TV_CC_REG,
3880 .halt_check = NOCHECK,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003881 .retain_reg = TV_CC_REG,
3882 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003883 },
3884 .md_reg = TV_MD_REG,
3885 .root_en_mask = BIT(2),
3886 .ns_mask = (BM(23, 16) | BM(15, 14) | BM(2, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08003887 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003888 .ctl_mask = BM(7, 6),
3889 .set_rate = set_rate_tv,
3890 .freq_tbl = clk_tbl_tv,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003891 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003892 .c = {
3893 .dbg_name = "tv_src_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07003894 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07003895 VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003896 CLK_INIT(tv_src_clk.c),
3897 },
3898};
3899
Tianyi Gou51918802012-01-26 14:05:43 -08003900static struct cdiv_clk tv_src_div_clk = {
3901 .b = {
3902 .ctl_reg = TV_NS_REG,
3903 .halt_check = NOCHECK,
3904 },
3905 .ns_reg = TV_NS_REG,
3906 .div_offset = 6,
3907 .max_div = 2,
3908 .c = {
3909 .dbg_name = "tv_src_div_clk",
3910 .ops = &clk_ops_cdiv,
3911 CLK_INIT(tv_src_div_clk.c),
3912 },
3913};
3914
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003915static struct branch_clk tv_enc_clk = {
3916 .b = {
3917 .ctl_reg = TV_CC_REG,
3918 .en_mask = BIT(8),
3919 .reset_reg = SW_RESET_CORE_REG,
3920 .reset_mask = BIT(0),
3921 .halt_reg = DBG_BUS_VEC_D_REG,
3922 .halt_bit = 9,
3923 },
3924 .parent = &tv_src_clk.c,
3925 .c = {
3926 .dbg_name = "tv_enc_clk",
3927 .ops = &clk_ops_branch,
3928 CLK_INIT(tv_enc_clk.c),
3929 },
3930};
3931
3932static struct branch_clk tv_dac_clk = {
3933 .b = {
3934 .ctl_reg = TV_CC_REG,
3935 .en_mask = BIT(10),
3936 .halt_reg = DBG_BUS_VEC_D_REG,
3937 .halt_bit = 10,
3938 },
3939 .parent = &tv_src_clk.c,
3940 .c = {
3941 .dbg_name = "tv_dac_clk",
3942 .ops = &clk_ops_branch,
3943 CLK_INIT(tv_dac_clk.c),
3944 },
3945};
3946
3947static struct branch_clk mdp_tv_clk = {
3948 .b = {
3949 .ctl_reg = TV_CC_REG,
3950 .en_mask = BIT(0),
3951 .reset_reg = SW_RESET_CORE_REG,
3952 .reset_mask = BIT(4),
3953 .halt_reg = DBG_BUS_VEC_D_REG,
3954 .halt_bit = 12,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08003955 .retain_reg = TV_CC2_REG,
3956 .retain_mask = BIT(10),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003957 },
3958 .parent = &tv_src_clk.c,
3959 .c = {
3960 .dbg_name = "mdp_tv_clk",
3961 .ops = &clk_ops_branch,
3962 CLK_INIT(mdp_tv_clk.c),
3963 },
3964};
3965
3966static struct branch_clk hdmi_tv_clk = {
3967 .b = {
3968 .ctl_reg = TV_CC_REG,
3969 .en_mask = BIT(12),
3970 .reset_reg = SW_RESET_CORE_REG,
3971 .reset_mask = BIT(1),
3972 .halt_reg = DBG_BUS_VEC_D_REG,
3973 .halt_bit = 11,
3974 },
3975 .parent = &tv_src_clk.c,
3976 .c = {
3977 .dbg_name = "hdmi_tv_clk",
3978 .ops = &clk_ops_branch,
3979 CLK_INIT(hdmi_tv_clk.c),
3980 },
3981};
3982
Tianyi Gou51918802012-01-26 14:05:43 -08003983static struct branch_clk rgb_tv_clk = {
3984 .b = {
3985 .ctl_reg = TV_CC2_REG,
3986 .en_mask = BIT(14),
3987 .halt_reg = DBG_BUS_VEC_J_REG,
3988 .halt_bit = 27,
3989 },
3990 .parent = &tv_src_clk.c,
3991 .c = {
3992 .dbg_name = "rgb_tv_clk",
3993 .ops = &clk_ops_branch,
3994 CLK_INIT(rgb_tv_clk.c),
3995 },
3996};
3997
3998static struct branch_clk npl_tv_clk = {
3999 .b = {
4000 .ctl_reg = TV_CC2_REG,
4001 .en_mask = BIT(16),
4002 .halt_reg = DBG_BUS_VEC_J_REG,
4003 .halt_bit = 26,
4004 },
4005 .parent = &tv_src_clk.c,
4006 .c = {
4007 .dbg_name = "npl_tv_clk",
4008 .ops = &clk_ops_branch,
4009 CLK_INIT(npl_tv_clk.c),
4010 },
4011};
4012
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004013static struct branch_clk hdmi_app_clk = {
4014 .b = {
4015 .ctl_reg = MISC_CC2_REG,
4016 .en_mask = BIT(11),
4017 .reset_reg = SW_RESET_CORE_REG,
4018 .reset_mask = BIT(11),
4019 .halt_reg = DBG_BUS_VEC_B_REG,
4020 .halt_bit = 25,
4021 },
4022 .c = {
4023 .dbg_name = "hdmi_app_clk",
4024 .ops = &clk_ops_branch,
4025 CLK_INIT(hdmi_app_clk.c),
4026 },
4027};
4028
4029static struct bank_masks bmnd_info_vcodec = {
4030 .bank_sel_mask = BIT(13),
4031 .bank0_mask = {
4032 .md_reg = VCODEC_MD0_REG,
4033 .ns_mask = BM(18, 11) | BM(2, 0),
4034 .rst_mask = BIT(31),
4035 .mnd_en_mask = BIT(5),
4036 .mode_mask = BM(7, 6),
4037 },
4038 .bank1_mask = {
4039 .md_reg = VCODEC_MD1_REG,
4040 .ns_mask = BM(26, 19) | BM(29, 27),
4041 .rst_mask = BIT(30),
4042 .mnd_en_mask = BIT(10),
4043 .mode_mask = BM(12, 11),
4044 },
4045};
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004046#define F_VCODEC(f, s, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004047 { \
4048 .freq_hz = f, \
4049 .src_clk = &s##_clk.c, \
4050 .md_val = MD8(8, m, 0, n), \
4051 .ns_val = NS_MND_BANKED8(11, 19, n, m, 0, 27, s##_to_mm_mux), \
4052 .ctl_val = CC_BANKED(6, 11, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004053 }
4054static struct clk_freq_tbl clk_tbl_vcodec[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004055 F_VCODEC( 0, gnd, 0, 0),
4056 F_VCODEC( 27000000, pxo, 0, 0),
4057 F_VCODEC( 32000000, pll8, 1, 12),
4058 F_VCODEC( 48000000, pll8, 1, 8),
4059 F_VCODEC( 54860000, pll8, 1, 7),
4060 F_VCODEC( 96000000, pll8, 1, 4),
4061 F_VCODEC(133330000, pll2, 1, 6),
4062 F_VCODEC(200000000, pll2, 1, 4),
4063 F_VCODEC(228570000, pll2, 2, 7),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004064 F_END
4065};
4066
4067static struct rcg_clk vcodec_clk = {
4068 .b = {
4069 .ctl_reg = VCODEC_CC_REG,
4070 .en_mask = BIT(0),
4071 .reset_reg = SW_RESET_CORE_REG,
4072 .reset_mask = BIT(6),
4073 .halt_reg = DBG_BUS_VEC_C_REG,
4074 .halt_bit = 29,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004075 .retain_reg = VCODEC_CC_REG,
4076 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004077 },
4078 .ns_reg = VCODEC_NS_REG,
4079 .root_en_mask = BIT(2),
4080 .set_rate = set_rate_mnd_banked,
Stephen Boydc78d9a72011-07-20 00:46:24 -07004081 .bank_info = &bmnd_info_vcodec,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004082 .freq_tbl = clk_tbl_vcodec,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004083 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004084 .c = {
4085 .dbg_name = "vcodec_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004086 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004087 VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
4088 HIGH, 228571000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004089 CLK_INIT(vcodec_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004090 .depends = &vcodec_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004091 },
4092};
4093
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004094#define F_VPE(f, s, d) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004095 { \
4096 .freq_hz = f, \
4097 .src_clk = &s##_clk.c, \
4098 .ns_val = NS_DIVSRC(15, 12, d, 2, 0, s##_to_mm_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004099 }
4100static struct clk_freq_tbl clk_tbl_vpe[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004101 F_VPE( 0, gnd, 1),
4102 F_VPE( 27000000, pxo, 1),
4103 F_VPE( 34909000, pll8, 11),
4104 F_VPE( 38400000, pll8, 10),
4105 F_VPE( 64000000, pll8, 6),
4106 F_VPE( 76800000, pll8, 5),
4107 F_VPE( 96000000, pll8, 4),
4108 F_VPE(100000000, pll2, 8),
4109 F_VPE(160000000, pll2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004110 F_END
4111};
4112
4113static struct rcg_clk vpe_clk = {
4114 .b = {
4115 .ctl_reg = VPE_CC_REG,
4116 .en_mask = BIT(0),
4117 .reset_reg = SW_RESET_CORE_REG,
4118 .reset_mask = BIT(17),
4119 .halt_reg = DBG_BUS_VEC_A_REG,
4120 .halt_bit = 28,
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004121 .retain_reg = VPE_CC_REG,
4122 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004123 },
4124 .ns_reg = VPE_NS_REG,
4125 .root_en_mask = BIT(2),
4126 .ns_mask = (BM(15, 12) | BM(2, 0)),
4127 .set_rate = set_rate_nop,
4128 .freq_tbl = clk_tbl_vpe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004129 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004130 .c = {
4131 .dbg_name = "vpe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004132 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004133 VDD_DIG_FMAX_MAP2(LOW, 76800000, NOMINAL, 160000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004134 CLK_INIT(vpe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004135 .depends = &vpe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004136 },
4137};
4138
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004139#define F_VFE(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004140 { \
4141 .freq_hz = f, \
4142 .src_clk = &s##_clk.c, \
4143 .md_val = MD8(8, m, 0, n), \
4144 .ns_val = NS_MM(23, 16, n, m, 11, 10, d, 2, 0, s##_to_mm_mux), \
4145 .ctl_val = CC(6, n), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004146 }
Tianyi Gou41515e22011-09-01 19:37:43 -07004147
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004148static struct clk_freq_tbl clk_tbl_vfe[] = {
4149 F_VFE( 0, gnd, 1, 0, 0),
4150 F_VFE( 13960000, pll8, 1, 2, 55),
4151 F_VFE( 27000000, pxo, 1, 0, 0),
4152 F_VFE( 36570000, pll8, 1, 2, 21),
4153 F_VFE( 38400000, pll8, 2, 1, 5),
4154 F_VFE( 45180000, pll8, 1, 2, 17),
4155 F_VFE( 48000000, pll8, 2, 1, 4),
4156 F_VFE( 54860000, pll8, 1, 1, 7),
4157 F_VFE( 64000000, pll8, 2, 1, 3),
4158 F_VFE( 76800000, pll8, 1, 1, 5),
4159 F_VFE( 96000000, pll8, 2, 1, 2),
4160 F_VFE(109710000, pll8, 1, 2, 7),
4161 F_VFE(128000000, pll8, 1, 1, 3),
4162 F_VFE(153600000, pll8, 1, 2, 5),
4163 F_VFE(200000000, pll2, 2, 1, 2),
4164 F_VFE(228570000, pll2, 1, 2, 7),
4165 F_VFE(266667000, pll2, 1, 1, 3),
4166 F_VFE(320000000, pll2, 1, 2, 5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004167 F_END
4168};
4169
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004170static unsigned long fmax_vfe_8064[MAX_VDD_LEVELS] __initdata = {
4171 [VDD_DIG_LOW] = 128000000,
4172 [VDD_DIG_NOMINAL] = 266667000,
4173 [VDD_DIG_HIGH] = 320000000
Tianyi Gou41515e22011-09-01 19:37:43 -07004174};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004175
4176static struct rcg_clk vfe_clk = {
4177 .b = {
4178 .ctl_reg = VFE_CC_REG,
4179 .reset_reg = SW_RESET_CORE_REG,
4180 .reset_mask = BIT(15),
4181 .halt_reg = DBG_BUS_VEC_B_REG,
4182 .halt_bit = 6,
4183 .en_mask = BIT(0),
Matt Wagantall7e0b6c92012-01-20 18:48:05 -08004184 .retain_reg = VFE_CC2_REG,
4185 .retain_mask = BIT(31),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004186 },
4187 .ns_reg = VFE_NS_REG,
4188 .md_reg = VFE_MD_REG,
4189 .root_en_mask = BIT(2),
4190 .ns_mask = (BM(23, 16) | BM(11, 10) | BM(2, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08004191 .mnd_en_mask = BIT(5),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004192 .ctl_mask = BM(7, 6),
4193 .set_rate = set_rate_mnd,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004194 .freq_tbl = clk_tbl_vfe,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004195 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004196 .c = {
4197 .dbg_name = "vfe_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004198 .ops = &clk_ops_rcg_8960,
Tianyi Gou3022dfd2012-01-25 15:50:05 -08004199 VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 266667000,
4200 HIGH, 320000000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004201 CLK_INIT(vfe_clk.c),
Stephen Boyd7fa26742011-08-11 23:22:29 -07004202 .depends = &vfe_axi_clk.c,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004203 },
4204};
4205
Matt Wagantallc23eee92011-08-16 23:06:52 -07004206static struct branch_clk csi_vfe_clk = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004207 .b = {
4208 .ctl_reg = VFE_CC_REG,
4209 .en_mask = BIT(12),
4210 .reset_reg = SW_RESET_CORE_REG,
4211 .reset_mask = BIT(24),
4212 .halt_reg = DBG_BUS_VEC_B_REG,
4213 .halt_bit = 8,
4214 },
4215 .parent = &vfe_clk.c,
4216 .c = {
Matt Wagantallc23eee92011-08-16 23:06:52 -07004217 .dbg_name = "csi_vfe_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004218 .ops = &clk_ops_branch,
Matt Wagantallc23eee92011-08-16 23:06:52 -07004219 CLK_INIT(csi_vfe_clk.c),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004220 },
4221};
4222
4223/*
4224 * Low Power Audio Clocks
4225 */
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004226#define F_AIF_OSR(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004227 { \
4228 .freq_hz = f, \
4229 .src_clk = &s##_clk.c, \
4230 .md_val = MD8(8, m, 0, n), \
4231 .ns_val = NS(31, 24, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004232 }
4233static struct clk_freq_tbl clk_tbl_aif_osr[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004234 F_AIF_OSR( 0, gnd, 1, 0, 0),
4235 F_AIF_OSR( 512000, pll4, 4, 1, 192),
4236 F_AIF_OSR( 768000, pll4, 4, 1, 128),
4237 F_AIF_OSR( 1024000, pll4, 4, 1, 96),
4238 F_AIF_OSR( 1536000, pll4, 4, 1, 64),
4239 F_AIF_OSR( 2048000, pll4, 4, 1, 48),
4240 F_AIF_OSR( 3072000, pll4, 4, 1, 32),
4241 F_AIF_OSR( 4096000, pll4, 4, 1, 24),
4242 F_AIF_OSR( 6144000, pll4, 4, 1, 16),
4243 F_AIF_OSR( 8192000, pll4, 4, 1, 12),
4244 F_AIF_OSR(12288000, pll4, 4, 1, 8),
4245 F_AIF_OSR(24576000, pll4, 4, 1, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004246 F_END
4247};
4248
4249#define CLK_AIF_OSR(i, ns, md, h_r) \
4250 struct rcg_clk i##_clk = { \
4251 .b = { \
4252 .ctl_reg = ns, \
4253 .en_mask = BIT(17), \
4254 .reset_reg = ns, \
4255 .reset_mask = BIT(19), \
4256 .halt_reg = h_r, \
4257 .halt_check = ENABLE, \
4258 .halt_bit = 1, \
4259 }, \
4260 .ns_reg = ns, \
4261 .md_reg = md, \
4262 .root_en_mask = BIT(9), \
4263 .ns_mask = (BM(31, 24) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08004264 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004265 .set_rate = set_rate_mnd, \
4266 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004267 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004268 .c = { \
4269 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004270 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004271 VDD_DIG_FMAX_MAP1(LOW, 24576000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004272 CLK_INIT(i##_clk.c), \
4273 }, \
4274 }
4275#define CLK_AIF_OSR_DIV(i, ns, md, h_r) \
4276 struct rcg_clk i##_clk = { \
4277 .b = { \
4278 .ctl_reg = ns, \
4279 .en_mask = BIT(21), \
4280 .reset_reg = ns, \
4281 .reset_mask = BIT(23), \
4282 .halt_reg = h_r, \
4283 .halt_check = ENABLE, \
4284 .halt_bit = 1, \
4285 }, \
4286 .ns_reg = ns, \
4287 .md_reg = md, \
4288 .root_en_mask = BIT(9), \
4289 .ns_mask = (BM(31, 24) | BM(6, 0)), \
Matt Wagantall07c45472012-02-10 23:27:24 -08004290 .mnd_en_mask = BIT(8), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004291 .set_rate = set_rate_mnd, \
4292 .freq_tbl = clk_tbl_aif_osr, \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004293 .current_freq = &rcg_dummy_freq, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004294 .c = { \
4295 .dbg_name = #i "_clk", \
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004296 .ops = &clk_ops_rcg_8960, \
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004297 VDD_DIG_FMAX_MAP1(LOW, 24576000), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004298 CLK_INIT(i##_clk.c), \
4299 }, \
4300 }
4301
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004302#define CLK_AIF_BIT(i, ns, h_r) \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004303 struct cdiv_clk i##_clk = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004304 .b = { \
4305 .ctl_reg = ns, \
4306 .en_mask = BIT(15), \
4307 .halt_reg = h_r, \
4308 .halt_check = DELAY, \
4309 }, \
4310 .ns_reg = ns, \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004311 .ext_mask = BIT(14), \
4312 .div_offset = 10, \
4313 .max_div = 16, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004314 .c = { \
4315 .dbg_name = #i "_clk", \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004316 .ops = &clk_ops_cdiv, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004317 CLK_INIT(i##_clk.c), \
4318 }, \
4319 }
4320
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004321#define CLK_AIF_BIT_DIV(i, ns, h_r) \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004322 struct cdiv_clk i##_clk = { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004323 .b = { \
4324 .ctl_reg = ns, \
4325 .en_mask = BIT(19), \
4326 .halt_reg = h_r, \
Stephen Boyd7bb9cf82012-01-25 18:09:01 -08004327 .halt_check = DELAY, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004328 }, \
4329 .ns_reg = ns, \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004330 .ext_mask = BIT(18), \
4331 .div_offset = 10, \
4332 .max_div = 256, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004333 .c = { \
4334 .dbg_name = #i "_clk", \
Stephen Boyd9fd19642011-11-16 11:11:09 -08004335 .ops = &clk_ops_cdiv, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004336 CLK_INIT(i##_clk.c), \
4337 }, \
4338 }
4339
4340static CLK_AIF_OSR(mi2s_osr, LCC_MI2S_NS_REG, LCC_MI2S_MD_REG,
4341 LCC_MI2S_STATUS_REG);
4342static CLK_AIF_BIT(mi2s_bit, LCC_MI2S_NS_REG, LCC_MI2S_STATUS_REG);
4343
4344static CLK_AIF_OSR_DIV(codec_i2s_mic_osr, LCC_CODEC_I2S_MIC_NS_REG,
4345 LCC_CODEC_I2S_MIC_MD_REG, LCC_CODEC_I2S_MIC_STATUS_REG);
4346static CLK_AIF_BIT_DIV(codec_i2s_mic_bit, LCC_CODEC_I2S_MIC_NS_REG,
4347 LCC_CODEC_I2S_MIC_STATUS_REG);
4348
4349static CLK_AIF_OSR_DIV(spare_i2s_mic_osr, LCC_SPARE_I2S_MIC_NS_REG,
4350 LCC_SPARE_I2S_MIC_MD_REG, LCC_SPARE_I2S_MIC_STATUS_REG);
4351static CLK_AIF_BIT_DIV(spare_i2s_mic_bit, LCC_SPARE_I2S_MIC_NS_REG,
4352 LCC_SPARE_I2S_MIC_STATUS_REG);
4353
4354static CLK_AIF_OSR_DIV(codec_i2s_spkr_osr, LCC_CODEC_I2S_SPKR_NS_REG,
4355 LCC_CODEC_I2S_SPKR_MD_REG, LCC_CODEC_I2S_SPKR_STATUS_REG);
4356static CLK_AIF_BIT_DIV(codec_i2s_spkr_bit, LCC_CODEC_I2S_SPKR_NS_REG,
4357 LCC_CODEC_I2S_SPKR_STATUS_REG);
4358
4359static CLK_AIF_OSR_DIV(spare_i2s_spkr_osr, LCC_SPARE_I2S_SPKR_NS_REG,
4360 LCC_SPARE_I2S_SPKR_MD_REG, LCC_SPARE_I2S_SPKR_STATUS_REG);
4361static CLK_AIF_BIT_DIV(spare_i2s_spkr_bit, LCC_SPARE_I2S_SPKR_NS_REG,
4362 LCC_SPARE_I2S_SPKR_STATUS_REG);
4363
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004364#define F_PCM(f, s, d, m, n) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004365 { \
4366 .freq_hz = f, \
4367 .src_clk = &s##_clk.c, \
4368 .md_val = MD16(m, n), \
4369 .ns_val = NS(31, 16, n, m, 5, 4, 3, d, 2, 0, s##_to_lpa_mux), \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004370 }
4371static struct clk_freq_tbl clk_tbl_pcm[] = {
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004372 F_PCM( 0, gnd, 1, 0, 0),
4373 F_PCM( 512000, pll4, 4, 1, 192),
4374 F_PCM( 768000, pll4, 4, 1, 128),
4375 F_PCM( 1024000, pll4, 4, 1, 96),
4376 F_PCM( 1536000, pll4, 4, 1, 64),
4377 F_PCM( 2048000, pll4, 4, 1, 48),
4378 F_PCM( 3072000, pll4, 4, 1, 32),
4379 F_PCM( 4096000, pll4, 4, 1, 24),
4380 F_PCM( 6144000, pll4, 4, 1, 16),
4381 F_PCM( 8192000, pll4, 4, 1, 12),
4382 F_PCM(12288000, pll4, 4, 1, 8),
4383 F_PCM(24576000, pll4, 4, 1, 4),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004384 F_END
4385};
4386
4387static struct rcg_clk pcm_clk = {
4388 .b = {
4389 .ctl_reg = LCC_PCM_NS_REG,
4390 .en_mask = BIT(11),
4391 .reset_reg = LCC_PCM_NS_REG,
4392 .reset_mask = BIT(13),
4393 .halt_reg = LCC_PCM_STATUS_REG,
4394 .halt_check = ENABLE,
4395 .halt_bit = 0,
4396 },
4397 .ns_reg = LCC_PCM_NS_REG,
4398 .md_reg = LCC_PCM_MD_REG,
4399 .root_en_mask = BIT(9),
4400 .ns_mask = (BM(31, 16) | BM(6, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08004401 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004402 .set_rate = set_rate_mnd,
4403 .freq_tbl = clk_tbl_pcm,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004404 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004405 .c = {
4406 .dbg_name = "pcm_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004407 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004408 VDD_DIG_FMAX_MAP1(LOW, 24576000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004409 CLK_INIT(pcm_clk.c),
4410 },
4411};
4412
4413static struct rcg_clk audio_slimbus_clk = {
4414 .b = {
4415 .ctl_reg = LCC_SLIMBUS_NS_REG,
4416 .en_mask = BIT(10),
4417 .reset_reg = LCC_AHBEX_BRANCH_CTL_REG,
4418 .reset_mask = BIT(5),
4419 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4420 .halt_check = ENABLE,
4421 .halt_bit = 0,
4422 },
4423 .ns_reg = LCC_SLIMBUS_NS_REG,
4424 .md_reg = LCC_SLIMBUS_MD_REG,
4425 .root_en_mask = BIT(9),
4426 .ns_mask = (BM(31, 24) | BM(6, 0)),
Matt Wagantall07c45472012-02-10 23:27:24 -08004427 .mnd_en_mask = BIT(8),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004428 .set_rate = set_rate_mnd,
4429 .freq_tbl = clk_tbl_aif_osr,
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004430 .current_freq = &rcg_dummy_freq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004431 .c = {
4432 .dbg_name = "audio_slimbus_clk",
Matt Wagantall84f43fd2011-08-16 23:28:38 -07004433 .ops = &clk_ops_rcg_8960,
Matt Wagantalle18bbc82011-10-06 10:07:28 -07004434 VDD_DIG_FMAX_MAP1(LOW, 24576000),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004435 CLK_INIT(audio_slimbus_clk.c),
4436 },
4437};
4438
4439static struct branch_clk sps_slimbus_clk = {
4440 .b = {
4441 .ctl_reg = LCC_SLIMBUS_NS_REG,
4442 .en_mask = BIT(12),
4443 .halt_reg = LCC_SLIMBUS_STATUS_REG,
4444 .halt_check = ENABLE,
4445 .halt_bit = 1,
4446 },
4447 .parent = &audio_slimbus_clk.c,
4448 .c = {
4449 .dbg_name = "sps_slimbus_clk",
4450 .ops = &clk_ops_branch,
4451 CLK_INIT(sps_slimbus_clk.c),
4452 },
4453};
4454
4455static struct branch_clk slimbus_xo_src_clk = {
4456 .b = {
4457 .ctl_reg = SLIMBUS_XO_SRC_CLK_CTL_REG,
4458 .en_mask = BIT(2),
4459 .halt_reg = CLK_HALT_DFAB_STATE_REG,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004460 .halt_bit = 28,
4461 },
4462 .parent = &sps_slimbus_clk.c,
4463 .c = {
4464 .dbg_name = "slimbus_xo_src_clk",
4465 .ops = &clk_ops_branch,
4466 CLK_INIT(slimbus_xo_src_clk.c),
4467 },
4468};
4469
Matt Wagantall735f01a2011-08-12 12:40:28 -07004470DEFINE_CLK_RPM(afab_clk, afab_a_clk, APPS_FABRIC, NULL);
4471DEFINE_CLK_RPM(cfpb_clk, cfpb_a_clk, CFPB, NULL);
4472DEFINE_CLK_RPM(dfab_clk, dfab_a_clk, DAYTONA_FABRIC, NULL);
4473DEFINE_CLK_RPM(ebi1_clk, ebi1_a_clk, EBI1, NULL);
4474DEFINE_CLK_RPM(mmfab_clk, mmfab_a_clk, MM_FABRIC, NULL);
4475DEFINE_CLK_RPM(mmfpb_clk, mmfpb_a_clk, MMFPB, NULL);
4476DEFINE_CLK_RPM(sfab_clk, sfab_a_clk, SYSTEM_FABRIC, NULL);
4477DEFINE_CLK_RPM(sfpb_clk, sfpb_a_clk, SFPB, NULL);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004478
Stephen Boydd7a143a2012-02-16 17:59:26 -08004479static DEFINE_CLK_VOTER(sfab_msmbus_a_clk, &sfab_a_clk.c);
4480static DEFINE_CLK_VOTER(sfab_tmr_a_clk, &sfab_a_clk.c);
4481
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004482static DEFINE_CLK_VOTER(dfab_dsps_clk, &dfab_clk.c);
4483static DEFINE_CLK_VOTER(dfab_usb_hs_clk, &dfab_clk.c);
Manu Gautam7483f172011-11-08 15:22:26 +05304484static DEFINE_CLK_VOTER(dfab_usb_hs3_clk, &dfab_clk.c);
4485static DEFINE_CLK_VOTER(dfab_usb_hs4_clk, &dfab_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004486static DEFINE_CLK_VOTER(dfab_sdc1_clk, &dfab_clk.c);
4487static DEFINE_CLK_VOTER(dfab_sdc2_clk, &dfab_clk.c);
4488static DEFINE_CLK_VOTER(dfab_sdc3_clk, &dfab_clk.c);
4489static DEFINE_CLK_VOTER(dfab_sdc4_clk, &dfab_clk.c);
4490static DEFINE_CLK_VOTER(dfab_sdc5_clk, &dfab_clk.c);
4491static DEFINE_CLK_VOTER(dfab_sps_clk, &dfab_clk.c);
Stephen Boyd1c51a492011-10-26 12:11:47 -07004492static DEFINE_CLK_VOTER(dfab_bam_dmux_clk, &dfab_clk.c);
Stephen Boydef5d1c42011-12-15 20:47:14 -08004493static DEFINE_CLK_VOTER(dfab_scm_clk, &dfab_clk.c);
Ramesh Masavarapua1bc0e42012-03-05 07:42:48 -08004494static DEFINE_CLK_VOTER(dfab_qseecom_clk, &dfab_clk.c);
Ramesh Masavarapueb6e9342012-02-13 19:59:50 -08004495static DEFINE_CLK_VOTER(dfab_tzcom_clk, &dfab_clk.c);
Gagan Macbc5f81d2012-04-04 15:03:12 -06004496static DEFINE_CLK_VOTER(dfab_msmbus_clk, &dfab_clk.c);
4497static DEFINE_CLK_VOTER(dfab_msmbus_a_clk, &dfab_a_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004498
4499static DEFINE_CLK_VOTER(ebi1_msmbus_clk, &ebi1_clk.c);
Stephen Boyd36466ae2012-01-18 20:58:27 -08004500static DEFINE_CLK_VOTER(ebi1_adm_clk, &ebi1_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004501
4502#ifdef CONFIG_DEBUG_FS
4503struct measure_sel {
4504 u32 test_vector;
4505 struct clk *clk;
4506};
4507
Matt Wagantall8b38f942011-08-02 18:23:18 -07004508static DEFINE_CLK_MEASURE(l2_m_clk);
4509static DEFINE_CLK_MEASURE(krait0_m_clk);
4510static DEFINE_CLK_MEASURE(krait1_m_clk);
Tianyi Gou455c13c2012-02-02 16:33:24 -08004511static DEFINE_CLK_MEASURE(krait2_m_clk);
4512static DEFINE_CLK_MEASURE(krait3_m_clk);
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004513static DEFINE_CLK_MEASURE(q6sw_clk);
4514static DEFINE_CLK_MEASURE(q6fw_clk);
4515static DEFINE_CLK_MEASURE(q6_func_clk);
Matt Wagantall8b38f942011-08-02 18:23:18 -07004516
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004517static struct measure_sel measure_mux[] = {
4518 { TEST_PER_LS(0x08), &slimbus_xo_src_clk.c },
4519 { TEST_PER_LS(0x12), &sdc1_p_clk.c },
4520 { TEST_PER_LS(0x13), &sdc1_clk.c },
4521 { TEST_PER_LS(0x14), &sdc2_p_clk.c },
4522 { TEST_PER_LS(0x15), &sdc2_clk.c },
4523 { TEST_PER_LS(0x16), &sdc3_p_clk.c },
4524 { TEST_PER_LS(0x17), &sdc3_clk.c },
4525 { TEST_PER_LS(0x18), &sdc4_p_clk.c },
4526 { TEST_PER_LS(0x19), &sdc4_clk.c },
4527 { TEST_PER_LS(0x1A), &sdc5_p_clk.c },
4528 { TEST_PER_LS(0x1B), &sdc5_clk.c },
Matt Wagantall7625a4c2011-11-01 16:17:53 -07004529 { TEST_PER_LS(0x1F), &gp0_clk.c },
4530 { TEST_PER_LS(0x20), &gp1_clk.c },
4531 { TEST_PER_LS(0x21), &gp2_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004532 { TEST_PER_LS(0x25), &dfab_clk.c },
4533 { TEST_PER_LS(0x25), &dfab_a_clk.c },
4534 { TEST_PER_LS(0x26), &pmem_clk.c },
4535 { TEST_PER_LS(0x32), &dma_bam_p_clk.c },
4536 { TEST_PER_LS(0x33), &cfpb_clk.c },
4537 { TEST_PER_LS(0x33), &cfpb_a_clk.c },
4538 { TEST_PER_LS(0x3D), &gsbi1_p_clk.c },
4539 { TEST_PER_LS(0x3E), &gsbi1_uart_clk.c },
4540 { TEST_PER_LS(0x3F), &gsbi1_qup_clk.c },
4541 { TEST_PER_LS(0x41), &gsbi2_p_clk.c },
4542 { TEST_PER_LS(0x42), &gsbi2_uart_clk.c },
4543 { TEST_PER_LS(0x44), &gsbi2_qup_clk.c },
4544 { TEST_PER_LS(0x45), &gsbi3_p_clk.c },
4545 { TEST_PER_LS(0x46), &gsbi3_uart_clk.c },
4546 { TEST_PER_LS(0x48), &gsbi3_qup_clk.c },
4547 { TEST_PER_LS(0x49), &gsbi4_p_clk.c },
4548 { TEST_PER_LS(0x4A), &gsbi4_uart_clk.c },
4549 { TEST_PER_LS(0x4C), &gsbi4_qup_clk.c },
4550 { TEST_PER_LS(0x4D), &gsbi5_p_clk.c },
4551 { TEST_PER_LS(0x4E), &gsbi5_uart_clk.c },
4552 { TEST_PER_LS(0x50), &gsbi5_qup_clk.c },
4553 { TEST_PER_LS(0x51), &gsbi6_p_clk.c },
4554 { TEST_PER_LS(0x52), &gsbi6_uart_clk.c },
4555 { TEST_PER_LS(0x54), &gsbi6_qup_clk.c },
4556 { TEST_PER_LS(0x55), &gsbi7_p_clk.c },
4557 { TEST_PER_LS(0x56), &gsbi7_uart_clk.c },
4558 { TEST_PER_LS(0x58), &gsbi7_qup_clk.c },
4559 { TEST_PER_LS(0x59), &gsbi8_p_clk.c },
4560 { TEST_PER_LS(0x5A), &gsbi8_uart_clk.c },
4561 { TEST_PER_LS(0x5C), &gsbi8_qup_clk.c },
4562 { TEST_PER_LS(0x5D), &gsbi9_p_clk.c },
4563 { TEST_PER_LS(0x5E), &gsbi9_uart_clk.c },
4564 { TEST_PER_LS(0x60), &gsbi9_qup_clk.c },
4565 { TEST_PER_LS(0x61), &gsbi10_p_clk.c },
4566 { TEST_PER_LS(0x62), &gsbi10_uart_clk.c },
4567 { TEST_PER_LS(0x64), &gsbi10_qup_clk.c },
4568 { TEST_PER_LS(0x65), &gsbi11_p_clk.c },
4569 { TEST_PER_LS(0x66), &gsbi11_uart_clk.c },
4570 { TEST_PER_LS(0x68), &gsbi11_qup_clk.c },
4571 { TEST_PER_LS(0x69), &gsbi12_p_clk.c },
4572 { TEST_PER_LS(0x6A), &gsbi12_uart_clk.c },
4573 { TEST_PER_LS(0x6C), &gsbi12_qup_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004574 { TEST_PER_LS(0x5E), &pcie_p_clk.c },
4575 { TEST_PER_LS(0x5F), &ce3_p_clk.c },
4576 { TEST_PER_LS(0x60), &ce3_core_clk.c },
4577 { TEST_PER_LS(0x63), &usb_hs3_p_clk.c },
4578 { TEST_PER_LS(0x64), &usb_hs3_xcvr_clk.c },
4579 { TEST_PER_LS(0x65), &usb_hs4_p_clk.c },
4580 { TEST_PER_LS(0x66), &usb_hs4_xcvr_clk.c },
4581 { TEST_PER_LS(0x6B), &sata_phy_ref_clk.c },
4582 { TEST_PER_LS(0x6C), &sata_phy_cfg_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004583 { TEST_PER_LS(0x78), &sfpb_clk.c },
4584 { TEST_PER_LS(0x78), &sfpb_a_clk.c },
4585 { TEST_PER_LS(0x7A), &pmic_ssbi2_clk.c },
4586 { TEST_PER_LS(0x7B), &pmic_arb0_p_clk.c },
4587 { TEST_PER_LS(0x7C), &pmic_arb1_p_clk.c },
4588 { TEST_PER_LS(0x7D), &prng_clk.c },
4589 { TEST_PER_LS(0x7F), &rpm_msg_ram_p_clk.c },
4590 { TEST_PER_LS(0x80), &adm0_p_clk.c },
4591 { TEST_PER_LS(0x84), &usb_hs1_p_clk.c },
4592 { TEST_PER_LS(0x85), &usb_hs1_xcvr_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004593 { TEST_PER_LS(0x86), &usb_hsic_p_clk.c },
4594 { TEST_PER_LS(0x87), &usb_hsic_system_clk.c },
4595 { TEST_PER_LS(0x88), &usb_hsic_xcvr_fs_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004596 { TEST_PER_LS(0x89), &usb_fs1_p_clk.c },
4597 { TEST_PER_LS(0x8A), &usb_fs1_sys_clk.c },
4598 { TEST_PER_LS(0x8B), &usb_fs1_xcvr_clk.c },
4599 { TEST_PER_LS(0x8C), &usb_fs2_p_clk.c },
4600 { TEST_PER_LS(0x8D), &usb_fs2_sys_clk.c },
4601 { TEST_PER_LS(0x8E), &usb_fs2_xcvr_clk.c },
4602 { TEST_PER_LS(0x8F), &tsif_p_clk.c },
4603 { TEST_PER_LS(0x91), &tsif_ref_clk.c },
4604 { TEST_PER_LS(0x92), &ce1_p_clk.c },
4605 { TEST_PER_LS(0x94), &tssc_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004606 { TEST_PER_LS(0x9D), &usb_hsic_hsio_cal_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004607 { TEST_PER_LS(0xA4), &ce1_core_clk.c },
4608
4609 { TEST_PER_HS(0x07), &afab_clk.c },
4610 { TEST_PER_HS(0x07), &afab_a_clk.c },
4611 { TEST_PER_HS(0x18), &sfab_clk.c },
4612 { TEST_PER_HS(0x18), &sfab_a_clk.c },
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004613 { TEST_PER_HS(0x26), &q6sw_clk },
4614 { TEST_PER_HS(0x27), &q6fw_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004615 { TEST_PER_HS(0x2A), &adm0_clk.c },
4616 { TEST_PER_HS(0x34), &ebi1_clk.c },
4617 { TEST_PER_HS(0x34), &ebi1_a_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004618 { TEST_PER_HS(0x50), &usb_hsic_hsic_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004619
4620 { TEST_MM_LS(0x00), &dsi1_byte_clk.c },
4621 { TEST_MM_LS(0x01), &dsi2_byte_clk.c },
4622 { TEST_MM_LS(0x02), &cam1_clk.c },
4623 { TEST_MM_LS(0x06), &amp_p_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004624 { TEST_MM_LS(0x07), &csi_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004625 { TEST_MM_LS(0x08), &dsi2_s_p_clk.c },
4626 { TEST_MM_LS(0x09), &dsi1_m_p_clk.c },
4627 { TEST_MM_LS(0x0A), &dsi1_s_p_clk.c },
4628 { TEST_MM_LS(0x0C), &gfx2d0_p_clk.c },
4629 { TEST_MM_LS(0x0D), &gfx2d1_p_clk.c },
4630 { TEST_MM_LS(0x0E), &gfx3d_p_clk.c },
4631 { TEST_MM_LS(0x0F), &hdmi_m_p_clk.c },
4632 { TEST_MM_LS(0x10), &hdmi_s_p_clk.c },
4633 { TEST_MM_LS(0x11), &ijpeg_p_clk.c },
4634 { TEST_MM_LS(0x12), &imem_p_clk.c },
4635 { TEST_MM_LS(0x13), &jpegd_p_clk.c },
4636 { TEST_MM_LS(0x14), &mdp_p_clk.c },
4637 { TEST_MM_LS(0x16), &rot_p_clk.c },
4638 { TEST_MM_LS(0x17), &dsi1_esc_clk.c },
4639 { TEST_MM_LS(0x18), &smmu_p_clk.c },
4640 { TEST_MM_LS(0x19), &tv_enc_p_clk.c },
4641 { TEST_MM_LS(0x1A), &vcodec_p_clk.c },
4642 { TEST_MM_LS(0x1B), &vfe_p_clk.c },
4643 { TEST_MM_LS(0x1C), &vpe_p_clk.c },
4644 { TEST_MM_LS(0x1D), &cam0_clk.c },
4645 { TEST_MM_LS(0x1F), &hdmi_app_clk.c },
4646 { TEST_MM_LS(0x20), &mdp_vsync_clk.c },
4647 { TEST_MM_LS(0x21), &tv_dac_clk.c },
4648 { TEST_MM_LS(0x22), &tv_enc_clk.c },
4649 { TEST_MM_LS(0x23), &dsi2_esc_clk.c },
4650 { TEST_MM_LS(0x25), &mmfpb_clk.c },
4651 { TEST_MM_LS(0x25), &mmfpb_a_clk.c },
4652 { TEST_MM_LS(0x26), &dsi2_m_p_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004653 { TEST_MM_LS(0x27), &cam2_clk.c },
Tianyi Gou41515e22011-09-01 19:37:43 -07004654 { TEST_MM_LS(0x28), &vcap_p_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004655
4656 { TEST_MM_HS(0x00), &csi0_clk.c },
4657 { TEST_MM_HS(0x01), &csi1_clk.c },
Matt Wagantallc23eee92011-08-16 23:06:52 -07004658 { TEST_MM_HS(0x04), &csi_vfe_clk.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004659 { TEST_MM_HS(0x05), &ijpeg_clk.c },
4660 { TEST_MM_HS(0x06), &vfe_clk.c },
4661 { TEST_MM_HS(0x07), &gfx2d0_clk.c },
4662 { TEST_MM_HS(0x08), &gfx2d1_clk.c },
4663 { TEST_MM_HS(0x09), &gfx3d_clk.c },
4664 { TEST_MM_HS(0x0A), &jpegd_clk.c },
4665 { TEST_MM_HS(0x0B), &vcodec_clk.c },
4666 { TEST_MM_HS(0x0F), &mmfab_clk.c },
4667 { TEST_MM_HS(0x0F), &mmfab_a_clk.c },
4668 { TEST_MM_HS(0x11), &gmem_axi_clk.c },
4669 { TEST_MM_HS(0x12), &ijpeg_axi_clk.c },
4670 { TEST_MM_HS(0x13), &imem_axi_clk.c },
4671 { TEST_MM_HS(0x14), &jpegd_axi_clk.c },
4672 { TEST_MM_HS(0x15), &mdp_axi_clk.c },
4673 { TEST_MM_HS(0x16), &rot_axi_clk.c },
4674 { TEST_MM_HS(0x17), &vcodec_axi_clk.c },
4675 { TEST_MM_HS(0x18), &vfe_axi_clk.c },
4676 { TEST_MM_HS(0x19), &vpe_axi_clk.c },
4677 { TEST_MM_HS(0x1A), &mdp_clk.c },
4678 { TEST_MM_HS(0x1B), &rot_clk.c },
4679 { TEST_MM_HS(0x1C), &vpe_clk.c },
4680 { TEST_MM_HS(0x1E), &hdmi_tv_clk.c },
4681 { TEST_MM_HS(0x1F), &mdp_tv_clk.c },
4682 { TEST_MM_HS(0x24), &csi0_phy_clk.c },
4683 { TEST_MM_HS(0x25), &csi1_phy_clk.c },
4684 { TEST_MM_HS(0x26), &csi_pix_clk.c },
4685 { TEST_MM_HS(0x27), &csi_rdi_clk.c },
4686 { TEST_MM_HS(0x28), &lut_mdp_clk.c },
4687 { TEST_MM_HS(0x29), &vcodec_axi_a_clk.c },
4688 { TEST_MM_HS(0x2A), &vcodec_axi_b_clk.c },
4689 { TEST_MM_HS(0x2B), &csi1phy_timer_clk.c },
4690 { TEST_MM_HS(0x2C), &csi0phy_timer_clk.c },
Stephen Boyd94625ef2011-07-12 17:06:01 -07004691 { TEST_MM_HS(0x2D), &csi2_clk.c },
4692 { TEST_MM_HS(0x2E), &csi2_phy_clk.c },
4693 { TEST_MM_HS(0x2F), &csi2phy_timer_clk.c },
4694 { TEST_MM_HS(0x30), &csi_pix1_clk.c },
4695 { TEST_MM_HS(0x31), &csi_rdi1_clk.c },
4696 { TEST_MM_HS(0x32), &csi_rdi2_clk.c },
Tianyi Gou621f8742011-09-01 21:45:01 -07004697 { TEST_MM_HS(0x33), &vcap_clk.c },
4698 { TEST_MM_HS(0x34), &vcap_npl_clk.c },
Tianyi Goue3d4f542012-03-15 17:06:45 -07004699 { TEST_MM_HS(0x34), &gfx3d_axi_clk_8930.c },
Tianyi Gou7747a962012-02-03 15:03:55 -08004700 { TEST_MM_HS(0x35), &vcap_axi_clk.c },
Tianyi Gou51918802012-01-26 14:05:43 -08004701 { TEST_MM_HS(0x36), &rgb_tv_clk.c },
4702 { TEST_MM_HS(0x37), &npl_tv_clk.c },
Tianyi Goue3d4f542012-03-15 17:06:45 -07004703 { TEST_MM_HS(0x38), &gfx3d_axi_clk_8064.c },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004704
4705 { TEST_LPA(0x0F), &mi2s_bit_clk.c },
4706 { TEST_LPA(0x10), &codec_i2s_mic_bit_clk.c },
4707 { TEST_LPA(0x11), &codec_i2s_spkr_bit_clk.c },
4708 { TEST_LPA(0x12), &spare_i2s_mic_bit_clk.c },
4709 { TEST_LPA(0x13), &spare_i2s_spkr_bit_clk.c },
4710 { TEST_LPA(0x14), &pcm_clk.c },
4711 { TEST_LPA(0x1D), &audio_slimbus_clk.c },
Matt Wagantall8b38f942011-08-02 18:23:18 -07004712
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004713 { TEST_LPA_HS(0x00), &q6_func_clk },
4714
Stephen Boyd46fdf0d2011-11-22 12:25:09 -08004715 { TEST_CPUL2(0x2), &l2_m_clk },
4716 { TEST_CPUL2(0x0), &krait0_m_clk },
4717 { TEST_CPUL2(0x1), &krait1_m_clk },
Tianyi Gou455c13c2012-02-02 16:33:24 -08004718 { TEST_CPUL2(0x4), &krait2_m_clk },
4719 { TEST_CPUL2(0x5), &krait3_m_clk },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004720};
4721
4722static struct measure_sel *find_measure_sel(struct clk *clk)
4723{
4724 int i;
4725
4726 for (i = 0; i < ARRAY_SIZE(measure_mux); i++)
4727 if (measure_mux[i].clk == clk)
4728 return &measure_mux[i];
4729 return NULL;
4730}
4731
Matt Wagantall8b38f942011-08-02 18:23:18 -07004732static int measure_clk_set_parent(struct clk *c, struct clk *parent)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004733{
4734 int ret = 0;
4735 u32 clk_sel;
4736 struct measure_sel *p;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004737 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004738 unsigned long flags;
4739
4740 if (!parent)
4741 return -EINVAL;
4742
4743 p = find_measure_sel(parent);
4744 if (!p)
4745 return -EINVAL;
4746
4747 spin_lock_irqsave(&local_clock_reg_lock, flags);
4748
Matt Wagantall8b38f942011-08-02 18:23:18 -07004749 /*
4750 * Program the test vector, measurement period (sample_ticks)
4751 * and scaling multiplier.
4752 */
4753 clk->sample_ticks = 0x10000;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004754 clk_sel = p->test_vector & TEST_CLK_SEL_MASK;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004755 clk->multiplier = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004756 switch (p->test_vector >> TEST_TYPE_SHIFT) {
4757 case TEST_TYPE_PER_LS:
4758 writel_relaxed(0x4030D00|BVAL(7, 0, clk_sel), CLK_TEST_REG);
4759 break;
4760 case TEST_TYPE_PER_HS:
4761 writel_relaxed(0x4020000|BVAL(16, 10, clk_sel), CLK_TEST_REG);
4762 break;
4763 case TEST_TYPE_MM_LS:
4764 writel_relaxed(0x4030D97, CLK_TEST_REG);
4765 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_LS_REG);
4766 break;
4767 case TEST_TYPE_MM_HS:
4768 writel_relaxed(0x402B800, CLK_TEST_REG);
4769 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0), DBG_CFG_REG_HS_REG);
4770 break;
4771 case TEST_TYPE_LPA:
4772 writel_relaxed(0x4030D98, CLK_TEST_REG);
4773 writel_relaxed(BVAL(6, 1, clk_sel)|BIT(0),
4774 LCC_CLK_LS_DEBUG_CFG_REG);
4775 break;
Stephen Boyd3939c8d2011-08-29 17:36:22 -07004776 case TEST_TYPE_LPA_HS:
4777 writel_relaxed(0x402BC00, CLK_TEST_REG);
4778 writel_relaxed(BVAL(2, 1, clk_sel)|BIT(0),
4779 LCC_CLK_HS_DEBUG_CFG_REG);
4780 break;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004781 case TEST_TYPE_CPUL2:
4782 writel_relaxed(0x4030400, CLK_TEST_REG);
4783 writel_relaxed(0x80|BVAL(5, 3, clk_sel), GCC_APCS_CLK_DIAG);
4784 clk->sample_ticks = 0x4000;
4785 clk->multiplier = 2;
4786 break;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004787 default:
4788 ret = -EPERM;
4789 }
4790 /* Make sure test vector is set before starting measurements. */
4791 mb();
4792
4793 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4794
4795 return ret;
4796}
4797
4798/* Sample clock for 'ticks' reference clock ticks. */
4799static u32 run_measurement(unsigned ticks)
4800{
4801 /* Stop counters and set the XO4 counter start value. */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004802 writel_relaxed(ticks, RINGOSC_TCXO_CTL_REG);
4803
4804 /* Wait for timer to become ready. */
4805 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) != 0)
4806 cpu_relax();
4807
4808 /* Run measurement and wait for completion. */
4809 writel_relaxed(BIT(20)|ticks, RINGOSC_TCXO_CTL_REG);
4810 while ((readl_relaxed(RINGOSC_STATUS_REG) & BIT(25)) == 0)
4811 cpu_relax();
4812
4813 /* Stop counters. */
4814 writel_relaxed(0x0, RINGOSC_TCXO_CTL_REG);
4815
4816 /* Return measured ticks. */
4817 return readl_relaxed(RINGOSC_STATUS_REG) & BM(24, 0);
4818}
4819
4820
4821/* Perform a hardware rate measurement for a given clock.
4822 FOR DEBUG USE ONLY: Measurements take ~15 ms! */
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07004823static unsigned long measure_clk_get_rate(struct clk *c)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004824{
4825 unsigned long flags;
4826 u32 pdm_reg_backup, ringosc_reg_backup;
4827 u64 raw_count_short, raw_count_full;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004828 struct measure_clk *clk = to_measure_clk(c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004829 unsigned ret;
4830
Stephen Boyde334aeb2012-01-24 12:17:29 -08004831 ret = clk_prepare_enable(&cxo_clk.c);
Stephen Boyd3a35f0b2012-01-11 16:18:26 -08004832 if (ret) {
4833 pr_warning("CXO clock failed to enable. Can't measure\n");
4834 return 0;
4835 }
4836
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004837 spin_lock_irqsave(&local_clock_reg_lock, flags);
4838
4839 /* Enable CXO/4 and RINGOSC branch and root. */
4840 pdm_reg_backup = readl_relaxed(PDM_CLK_NS_REG);
4841 ringosc_reg_backup = readl_relaxed(RINGOSC_NS_REG);
4842 writel_relaxed(0x2898, PDM_CLK_NS_REG);
4843 writel_relaxed(0xA00, RINGOSC_NS_REG);
4844
4845 /*
4846 * The ring oscillator counter will not reset if the measured clock
4847 * is not running. To detect this, run a short measurement before
4848 * the full measurement. If the raw results of the two are the same
4849 * then the clock must be off.
4850 */
4851
4852 /* Run a short measurement. (~1 ms) */
4853 raw_count_short = run_measurement(0x1000);
4854 /* Run a full measurement. (~14 ms) */
Matt Wagantall8b38f942011-08-02 18:23:18 -07004855 raw_count_full = run_measurement(clk->sample_ticks);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004856
4857 writel_relaxed(ringosc_reg_backup, RINGOSC_NS_REG);
4858 writel_relaxed(pdm_reg_backup, PDM_CLK_NS_REG);
4859
4860 /* Return 0 if the clock is off. */
4861 if (raw_count_full == raw_count_short)
4862 ret = 0;
4863 else {
4864 /* Compute rate in Hz. */
4865 raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
Matt Wagantall8b38f942011-08-02 18:23:18 -07004866 do_div(raw_count_full, ((clk->sample_ticks * 10) + 35));
4867 ret = (raw_count_full * clk->multiplier);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004868 }
4869
4870 /* Route dbg_hs_clk to PLLTEST. 300mV single-ended amplitude. */
Stephen Boyd69da8402011-07-14 17:45:31 -07004871 writel_relaxed(0x38F8, PLLTEST_PAD_CFG_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004872 spin_unlock_irqrestore(&local_clock_reg_lock, flags);
4873
Stephen Boyde334aeb2012-01-24 12:17:29 -08004874 clk_disable_unprepare(&cxo_clk.c);
Stephen Boyd3a35f0b2012-01-11 16:18:26 -08004875
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004876 return ret;
4877}
4878#else /* !CONFIG_DEBUG_FS */
4879static int measure_clk_set_parent(struct clk *clk, struct clk *parent)
4880{
4881 return -EINVAL;
4882}
4883
Matt Wagantall9de3bfb2011-11-03 20:13:12 -07004884static unsigned long measure_clk_get_rate(struct clk *clk)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004885{
4886 return 0;
4887}
4888#endif /* CONFIG_DEBUG_FS */
4889
4890static struct clk_ops measure_clk_ops = {
4891 .set_parent = measure_clk_set_parent,
4892 .get_rate = measure_clk_get_rate,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004893};
4894
Matt Wagantall8b38f942011-08-02 18:23:18 -07004895static struct measure_clk measure_clk = {
4896 .c = {
4897 .dbg_name = "measure_clk",
4898 .ops = &measure_clk_ops,
4899 CLK_INIT(measure_clk.c),
4900 },
4901 .multiplier = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004902};
4903
Tianyi Goua8b3cce2011-11-08 14:37:26 -08004904static struct clk_lookup msm_clocks_8064[] = {
Stephen Boyd72a80352012-01-26 15:57:38 -08004905 CLK_LOOKUP("xo", cxo_a_clk.c, ""),
4906 CLK_LOOKUP("xo", pxo_a_clk.c, ""),
Stephen Boyded630b02012-01-26 15:26:47 -08004907 CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"),
4908 CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"),
4909 CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"),
4910 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"),
4911 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"),
Matt Wagantall292aace2012-01-26 19:12:34 -08004912 CLK_LOOKUP("xo", cxo_clk.c, "pil_gss"),
Stephen Boyd69d35e32012-02-14 15:33:30 -08004913 CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"),
Stephen Boyd5a190a82012-03-01 14:45:15 -08004914 CLK_LOOKUP("xo", cxo_clk.c, "msm_xo"),
Stephen Boyded630b02012-01-26 15:26:47 -08004915 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
4916 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
4917 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
4918 CLK_LOOKUP("measure", measure_clk.c, "debug"),
Tianyi Gou41515e22011-09-01 19:37:43 -07004919
Tianyi Gou21a0e802012-02-04 22:34:10 -08004920 CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"),
4921 CLK_LOOKUP("bus_a_clk", afab_a_clk.c, "msm_apps_fab"),
4922 CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"),
4923 CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"),
4924 CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"),
Stephen Boydd7a143a2012-02-16 17:59:26 -08004925 CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"),
Tianyi Gou21a0e802012-02-04 22:34:10 -08004926 CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"),
4927 CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"),
4928 CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"),
4929 CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"),
4930 CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"),
4931 CLK_LOOKUP("mem_a_clk", ebi1_a_clk.c, "msm_bus"),
Gagan Macbc5f81d2012-04-04 15:03:12 -06004932 CLK_LOOKUP("dfab_clk", dfab_msmbus_clk.c, "msm_bus"),
4933 CLK_LOOKUP("dfab_a_clk", dfab_msmbus_a_clk.c, "msm_bus"),
Matt Wagantallb2710b82011-11-16 19:55:17 -08004934
Tianyi Gou21a0e802012-02-04 22:34:10 -08004935 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, ""),
Tianyi Gou21a0e802012-02-04 22:34:10 -08004936 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, ""),
4937 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
4938 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
Tianyi Gou41515e22011-09-01 19:37:43 -07004939
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004940 CLK_LOOKUP("core_clk", gp0_clk.c, ""),
4941 CLK_LOOKUP("core_clk", gp1_clk.c, ""),
4942 CLK_LOOKUP("core_clk", gp2_clk.c, ""),
Jin Hong4bbbfba2012-02-02 21:48:07 -08004943 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, "msm_serial_hsl.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004944 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""),
4945 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""),
4946 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""),
4947 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, ""),
4948 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, ""),
Jin Hong4bbbfba2012-02-02 21:48:07 -08004949 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, "msm_serial_hsl.0"),
David Keitel3c40fc52012-02-09 17:53:52 -08004950 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "qup_i2c.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004951 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""),
Jing Lin04601f92012-02-05 15:36:07 -08004952 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
Kevin Chand07220e2012-02-13 15:52:22 -08004953 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
Stepan Moskovchenko64999002012-01-31 15:52:59 -08004954 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, "spi_qsd.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004955 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""),
4956 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""),
4957 CLK_LOOKUP("core_clk", pdm_clk.c, ""),
Tianyi Gou50f23812012-02-06 16:04:19 -08004958 CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
Tianyi Gou05e01102012-02-08 22:15:49 -08004959 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
Tianyi Gou43208a02011-09-27 15:35:13 -07004960 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
4961 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
4962 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
4963 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004964 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, ""),
4965 CLK_LOOKUP("core_clk", tssc_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08004966 CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"),
4967 CLK_LOOKUP("alt_core_clk", usb_hs3_xcvr_clk.c, "msm_ehci_host.0"),
4968 CLK_LOOKUP("alt_core_clk", usb_hs4_xcvr_clk.c, "msm_ehci_host.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004969 CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""),
4970 CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""),
4971 CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""),
4972 CLK_LOOKUP("iface_clk", ce1_p_clk.c, ""),
4973 CLK_LOOKUP("core_clk", ce1_core_clk.c, ""),
4974 CLK_LOOKUP("ref_clk", sata_phy_ref_clk.c, ""),
4975 CLK_LOOKUP("cfg_clk", sata_phy_cfg_clk.c, ""),
Ramesh Masavarapu28311912011-10-27 11:04:12 -07004976 CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qce.0"),
4977 CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qcrypto.0"),
4978 CLK_LOOKUP("core_clk", ce3_core_clk.c, "qce.0"),
4979 CLK_LOOKUP("core_clk", ce3_core_clk.c, "qcrypto.0"),
4980 CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qce.0"),
4981 CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qcrypto.0"),
Tianyi Gou41515e22011-09-01 19:37:43 -07004982 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
Jin Hong4bbbfba2012-02-02 21:48:07 -08004983 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "msm_serial_hsl.1"),
David Keitel3c40fc52012-02-09 17:53:52 -08004984 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "qup_i2c.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004985 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""),
Jing Lin04601f92012-02-05 15:36:07 -08004986 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
Kevin Chand07220e2012-02-13 15:52:22 -08004987 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
Stepan Moskovchenko64999002012-01-31 15:52:59 -08004988 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "spi_qsd.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004989 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, ""),
Jin Hong4bbbfba2012-02-02 21:48:07 -08004990 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, "msm_serial_hsl.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08004991 CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""),
4992 CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08004993 CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"),
Manu Gautam7483f172011-11-08 15:22:26 +05304994 CLK_LOOKUP("iface_clk", usb_hs3_p_clk.c, "msm_ehci_host.0"),
4995 CLK_LOOKUP("iface_clk", usb_hs4_p_clk.c, "msm_ehci_host.1"),
Tianyi Gou43208a02011-09-27 15:35:13 -07004996 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
4997 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
4998 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
4999 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005000 CLK_LOOKUP("iface_clk", pcie_p_clk.c, ""),
Tianyi Gou41515e22011-09-01 19:37:43 -07005001 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
5002 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005003 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""),
5004 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""),
5005 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""),
5006 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""),
5007 CLK_LOOKUP("core_clk", amp_clk.c, ""),
Kevin Chand07220e2012-02-13 15:52:22 -08005008 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"),
Sreesudhan Ramakrish Ramkumar3381da72012-01-27 08:08:32 -08005009 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0034"),
Sreesudhan Ramakrish Ramkumar6c6f57c2012-02-21 15:12:44 -08005010 CLK_LOOKUP("cam_clk", cam1_clk.c, "4-0048"),
Kevin Chand07220e2012-02-13 15:52:22 -08005011 CLK_LOOKUP("cam_clk", cam1_clk.c, "4-006c"),
5012 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"),
5013 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"),
5014 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"),
5015 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"),
5016 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"),
5017 CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"),
5018 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"),
5019 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"),
5020 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"),
5021 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"),
5022 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"),
5023 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"),
5024 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"),
5025 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"),
5026 CLK_LOOKUP("csiphy_timer_src_clk",
5027 csiphy_timer_src_clk.c, "msm_csiphy.0"),
5028 CLK_LOOKUP("csiphy_timer_src_clk",
5029 csiphy_timer_src_clk.c, "msm_csiphy.1"),
5030 CLK_LOOKUP("csiphy_timer_src_clk",
5031 csiphy_timer_src_clk.c, "msm_csiphy.2"),
5032 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"),
5033 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"),
5034 CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08005035 CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, NULL),
5036 CLK_LOOKUP("dsi_byte_div_clk", dsi2_byte_clk.c, NULL),
5037 CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, NULL),
5038 CLK_LOOKUP("dsi_esc_clk", dsi2_esc_clk.c, NULL),
Tianyi Gou51918802012-01-26 14:05:43 -08005039 CLK_LOOKUP("rgb_clk", rgb_tv_clk.c, ""),
5040 CLK_LOOKUP("npl_clk", npl_tv_clk.c, ""),
5041
Pu Chen86b4be92011-11-03 17:27:57 -07005042 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005043 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005044 CLK_LOOKUP("bus_clk",
5045 gfx3d_axi_clk_8064.c, "footswitch-8x60.2"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005046 CLK_LOOKUP("iface_clk", vcap_p_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005047 CLK_LOOKUP("iface_clk", vcap_p_clk.c, "footswitch-8x60.10"),
5048 CLK_LOOKUP("bus_clk", vcap_axi_clk.c, "footswitch-8x60.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005049 CLK_LOOKUP("core_clk", vcap_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005050 CLK_LOOKUP("core_clk", vcap_clk.c, "footswitch-8x60.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005051 CLK_LOOKUP("vcap_npl_clk", vcap_npl_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005052 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005053 CLK_LOOKUP("mem_clk", imem_axi_clk.c, ""),
5054 CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005055 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005056 CLK_LOOKUP("core_clk", jpegd_clk.c, ""),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08005057 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005058 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08005059 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005060 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08005061 CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005062 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005063 CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005064 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Matt Wagantall61286312012-02-22 15:55:09 -08005065 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"),
Aravind Venkateswaran0507c8c2012-02-16 17:16:05 -08005066 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, NULL),
5067 CLK_LOOKUP("tv_src_div_clk", tv_src_div_clk.c, NULL),
Greg Griscofa47b532011-11-11 10:32:06 -08005068 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005069 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Aravind Venkateswaran0507c8c2012-02-16 17:16:05 -08005070 CLK_LOOKUP("mdp_tv_clk", mdp_tv_clk.c, NULL),
Tianyi Gou51918802012-01-26 14:05:43 -08005071 CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"),
Aravind Venkateswaran0507c8c2012-02-16 17:16:05 -08005072 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, NULL),
5073 CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"),
Ujwal Pateld041f982012-03-27 19:51:44 -07005074 CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005075 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
Kevin Chand07220e2012-02-13 15:52:22 -08005076 CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005077 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
Kevin Chand07220e2012-02-13 15:52:22 -08005078 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005079 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
5080 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
5081 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
5082 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
5083 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
5084 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
5085 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08005086 CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL),
Kevin Chand07220e2012-02-13 15:52:22 -08005087 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"),
5088 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"),
5089 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08005090 CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL),
5091 CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, NULL),
5092 CLK_LOOKUP("dsi_m_pclk", dsi2_m_p_clk.c, NULL),
5093 CLK_LOOKUP("dsi_s_pclk", dsi2_s_p_clk.c, NULL),
Pu Chen86b4be92011-11-03 17:27:57 -07005094 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005095 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
Aravind Venkateswaran0507c8c2012-02-16 17:16:05 -08005096 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"),
5097 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005098 CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, ""),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005099 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005100 CLK_LOOKUP("iface_clk", jpegd_p_clk.c, ""),
Matt Wagantall5d44ef22012-01-23 11:01:05 -08005101 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"),
Ravishangar Kalyanamc2fee312012-02-09 19:11:22 -08005102 CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005103 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
Stepan Moskovchenko279b7852012-01-31 20:42:46 -08005104 CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005105 CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005106 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
Greg Griscofa47b532011-11-11 10:32:06 -08005107 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005108 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
Kevin Chand07220e2012-02-13 15:52:22 -08005109 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"),
Matt Wagantallc9a780c2011-10-28 12:12:18 -07005110 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
Kevin Chanb20742b2012-02-27 15:47:35 -08005111 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"),
Matt Wagantall61286312012-02-22 15:55:09 -08005112 CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005113
Kuirong Wanga9c3acc2012-02-09 17:00:45 -08005114 CLK_LOOKUP("bit_clk", mi2s_bit_clk.c, "msm-dai-q6.6"),
5115 CLK_LOOKUP("osr_clk", mi2s_osr_clk.c, "msm-dai-q6.6"),
5116 CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c,
5117 "msm-dai-q6.1"),
5118 CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c,
5119 "msm-dai-q6.1"),
5120 CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c,
5121 "msm-dai-q6.5"),
5122 CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c,
5123 "msm-dai-q6.5"),
5124 CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c,
5125 "msm-dai-q6.16384"),
5126 CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c,
5127 "msm-dai-q6.16384"),
5128 CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c,
5129 "msm-dai-q6.4"),
5130 CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c,
5131 "msm-dai-q6.4"),
5132 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"),
Kiran Kandi5f4ab692012-02-23 11:23:56 -08005133 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005134 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, ""),
Tianyi Gou44a81b02012-02-06 17:49:07 -08005135 CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005136 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, ""),
5137 CLK_LOOKUP("core_clk", vpe_axi_clk.c, ""),
5138 CLK_LOOKUP("core_clk", mdp_axi_clk.c, ""),
5139 CLK_LOOKUP("core_clk", vcap_axi_clk.c, ""),
5140 CLK_LOOKUP("core_clk", rot_axi_clk.c, ""),
5141 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, ""),
5142 CLK_LOOKUP("core_clk", vfe_axi_clk.c, ""),
5143 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, ""),
5144 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, ""),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005145 CLK_LOOKUP("core_clk", gfx3d_axi_clk_8064.c, ""),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005146
5147 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
5148 CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"),
5149 CLK_LOOKUP("core_clk", dfab_usb_hs3_clk.c, "msm_ehci_host.0"),
5150 CLK_LOOKUP("core_clk", dfab_usb_hs3_clk.c, "msm_ehci_host.1"),
5151 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
5152 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
5153 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
5154 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
5155 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
5156 CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
5157 CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
Ramesh Masavarapua1bc0e42012-03-05 07:42:48 -08005158 CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"),
Ramesh Masavarapueb6e9342012-02-13 19:59:50 -08005159 CLK_LOOKUP("bus_clk", dfab_tzcom_clk.c, "tzcom"),
Tianyi Gou21a0e802012-02-04 22:34:10 -08005160
Manu Gautam5143b252012-01-05 19:25:23 -08005161 CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
5162 CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
5163 CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"),
5164 CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"),
5165 CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005166
Stepan Moskovchenko279b7852012-01-31 20:42:46 -08005167 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"),
5168 CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
5169 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
5170 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
5171 CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
5172 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
5173 CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
5174 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
5175 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005176 CLK_LOOKUP("core_clk", gfx3d_axi_clk_8064.c, "msm_iommu.9"),
5177 CLK_LOOKUP("core_clk", gfx3d_axi_clk_8064.c, "msm_iommu.10"),
Stepan Moskovchenko279b7852012-01-31 20:42:46 -08005178 CLK_LOOKUP("core_clk", vcap_axi_clk.c, "msm_iommu.11"),
5179
Jeff Ohlstein8c116c72011-10-27 17:34:48 -07005180 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Tianyi Gou41515e22011-09-01 19:37:43 -07005181
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005182 CLK_LOOKUP("l2_mclk", l2_m_clk, ""),
5183 CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""),
5184 CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""),
Tianyi Gou455c13c2012-02-02 16:33:24 -08005185 CLK_LOOKUP("krait2_mclk", krait2_m_clk, ""),
5186 CLK_LOOKUP("krait3_mclk", krait3_m_clk, ""),
Tianyi Gou41515e22011-09-01 19:37:43 -07005187};
5188
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005189static struct clk_lookup msm_clocks_8960[] = {
Stephen Boyd72a80352012-01-26 15:57:38 -08005190 CLK_LOOKUP("xo", cxo_a_clk.c, ""),
5191 CLK_LOOKUP("xo", pxo_a_clk.c, ""),
Stephen Boyded630b02012-01-26 15:26:47 -08005192 CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"),
5193 CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"),
5194 CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"),
5195 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"),
5196 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"),
Stephen Boyd69d35e32012-02-14 15:33:30 -08005197 CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"),
Stephen Boyd5a190a82012-03-01 14:45:15 -08005198 CLK_LOOKUP("xo", cxo_clk.c, "msm_xo"),
Stephen Boyded630b02012-01-26 15:26:47 -08005199 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
5200 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
5201 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
5202 CLK_LOOKUP("measure", measure_clk.c, "debug"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005203
Matt Wagantallb2710b82011-11-16 19:55:17 -08005204 CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"),
5205 CLK_LOOKUP("bus_a_clk", afab_a_clk.c, "msm_apps_fab"),
5206 CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"),
5207 CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"),
5208 CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"),
Stephen Boydd7a143a2012-02-16 17:59:26 -08005209 CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"),
Matt Wagantallb2710b82011-11-16 19:55:17 -08005210 CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"),
5211 CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"),
5212 CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"),
5213 CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"),
5214 CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"),
5215 CLK_LOOKUP("mem_a_clk", ebi1_a_clk.c, "msm_bus"),
Gagan Macbc5f81d2012-04-04 15:03:12 -06005216 CLK_LOOKUP("dfab_clk", dfab_msmbus_clk.c, "msm_bus"),
5217 CLK_LOOKUP("dfab_a_clk", dfab_msmbus_a_clk.c, "msm_bus"),
Matt Wagantallb2710b82011-11-16 19:55:17 -08005218
5219 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
Matt Wagantallb2710b82011-11-16 19:55:17 -08005220 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL),
5221 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
5222 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005223
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005224 CLK_LOOKUP("core_clk", gp0_clk.c, ""),
5225 CLK_LOOKUP("core_clk", gp1_clk.c, ""),
5226 CLK_LOOKUP("core_clk", gp2_clk.c, ""),
5227 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, ""),
5228 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""),
5229 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""),
5230 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""),
Matt Wagantalle2522372011-08-17 14:52:21 -07005231 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"),
5232 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005233 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, ""),
5234 CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, ""),
5235 CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, ""),
5236 CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, ""),
5237 CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, ""),
5238 CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005239 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005240 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005241 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
5242 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005243 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, ""),
5244 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""),
5245 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""),
5246 CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, ""),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005247 CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005248 CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005249 CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005250 CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005251 CLK_LOOKUP("core_clk", pdm_clk.c, ""),
Vikram Mulukutladd0a2372011-09-19 15:58:21 -07005252 CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
Matt Wagantallc1205292011-08-11 17:19:31 -07005253 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005254 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
5255 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
5256 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
5257 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
5258 CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005259 CLK_LOOKUP("slimbus_xo_src_clk", slimbus_xo_src_clk.c, NULL),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005260 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, ""),
5261 CLK_LOOKUP("core_clk", tssc_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08005262 CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"),
5263 CLK_LOOKUP("phy_clk", usb_phy0_clk.c, "msm_otg"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005264 CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""),
5265 CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""),
5266 CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""),
5267 CLK_LOOKUP("alt_core_clk", usb_fs2_xcvr_clk.c, ""),
5268 CLK_LOOKUP("sys_clk", usb_fs2_sys_clk.c, ""),
5269 CLK_LOOKUP("src_clk", usb_fs2_src_clk.c, ""),
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005270 CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
5271 CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
5272 CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"),
5273 CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"),
5274 CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07005275 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07005276 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"),
Matt Wagantallc4b3a4d2011-08-17 16:58:39 -07005277 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"),
Matt Wagantalle0b11452011-09-13 17:25:33 -07005278 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005279 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
Matt Wagantallac294852011-08-17 15:44:58 -07005280 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005281 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005282 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
5283 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
Matt Wagantalle2522372011-08-17 14:52:21 -07005284 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"),
5285 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005286 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, ""),
5287 CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, ""),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005288 CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005289 CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005290 CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, ""),
Matt Wagantallac294852011-08-17 15:44:58 -07005291 CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005292 CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""),
5293 CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""),
5294 CLK_LOOKUP("iface_clk", usb_fs2_p_clk.c, ""),
Manu Gautam5143b252012-01-05 19:25:23 -08005295 CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005296 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
5297 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
5298 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
5299 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
5300 CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"),
Matt Wagantalle1a86062011-08-18 17:46:10 -07005301 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
5302 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005303 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""),
5304 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""),
5305 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""),
5306 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""),
5307 CLK_LOOKUP("core_clk", amp_clk.c, ""),
Kevin Chan09f4e662011-12-16 08:17:02 -08005308 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"),
5309 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-006c"),
5310 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0048"),
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005311 CLK_LOOKUP("cam_clk", cam2_clk.c, NULL),
Sreesudhan Ramakrish Ramkumar8f11b8b2012-01-04 17:09:05 -08005312 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0020"),
Sreesudhan Ramakrish Ramkumar3381da72012-01-27 08:08:32 -08005313 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0034"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005314 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"),
5315 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005316 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005317 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"),
5318 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005319 CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005320 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"),
5321 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005322 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"),
Kevin Chane12c6672011-10-26 11:55:26 -07005323 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"),
5324 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"),
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005325 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
5326 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
5327 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"),
5328 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"),
5329 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"),
5330 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
5331 CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL),
Kevin Chanf6216f22011-10-25 18:40:11 -07005332 CLK_LOOKUP("csiphy_timer_src_clk",
5333 csiphy_timer_src_clk.c, "msm_csiphy.0"),
5334 CLK_LOOKUP("csiphy_timer_src_clk",
5335 csiphy_timer_src_clk.c, "msm_csiphy.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005336 CLK_LOOKUP("csiphy_timer_src_clk",
5337 csiphy_timer_src_clk.c, "msm_csiphy.2"),
Kevin Chanf6216f22011-10-25 18:40:11 -07005338 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"),
5339 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005340 CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005341 CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, NULL),
5342 CLK_LOOKUP("dsi_byte_div_clk", dsi2_byte_clk.c, NULL),
5343 CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, NULL),
5344 CLK_LOOKUP("dsi_esc_clk", dsi2_esc_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005345 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "kgsl-2d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005346 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "footswitch-8x60.0"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005347 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "kgsl-2d1.1"),
Matt Wagantall49722712011-08-17 18:50:53 -07005348 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "footswitch-8x60.1"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005349 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005350 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
5351 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
Jignesh Mehta95dd6e12011-11-18 17:21:16 -08005352 CLK_LOOKUP("imem_clk", imem_axi_clk.c, NULL),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005353 CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005354 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005355 CLK_LOOKUP("core_clk", jpegd_clk.c, ""),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005356 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005357 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005358 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005359 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005360 CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005361 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005362 CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005363 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005364 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005365 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005366 CLK_LOOKUP("tv_enc_clk", tv_enc_clk.c, NULL),
5367 CLK_LOOKUP("tv_dac_clk", tv_dac_clk.c, NULL),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07005368 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005369 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005370 CLK_LOOKUP("mdp_tv_clk", mdp_tv_clk.c, NULL),
Matt Wagantallb82a5132011-12-12 22:26:41 -08005371 CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005372 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, NULL),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -07005373 CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"),
Kevin Chana0853122011-11-07 19:48:44 -08005374 CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005375 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
Kevin Chan5827c552011-10-28 18:36:32 -07005376 CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005377 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
Kevin Chan5827c552011-10-28 18:36:32 -07005378 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005379 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
5380 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
5381 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
5382 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
5383 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
5384 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
5385 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005386 CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL),
Kevin Chanc8b52e82011-10-25 23:20:21 -07005387 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"),
5388 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"),
Sreesudhan Ramakrish Ramkumarb1edcd02012-01-17 11:33:05 -08005389 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005390 CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL),
5391 CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, NULL),
5392 CLK_LOOKUP("dsi_m_pclk", dsi2_m_p_clk.c, NULL),
5393 CLK_LOOKUP("dsi_s_pclk", dsi2_s_p_clk.c, NULL),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005394 CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "kgsl-2d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005395 CLK_LOOKUP("iface_clk", gfx2d0_p_clk.c, "footswitch-8x60.0"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005396 CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "kgsl-2d1.1"),
Matt Wagantall49722712011-08-17 18:50:53 -07005397 CLK_LOOKUP("iface_clk", gfx2d1_p_clk.c, "footswitch-8x60.1"),
Matt Wagantall9dc01632011-08-17 18:55:04 -07005398 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005399 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
Matt Wagantall5a4f1ba2011-08-18 18:13:03 -07005400 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"),
5401 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005402 CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005403 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005404 CLK_LOOKUP("iface_clk", jpegd_p_clk.c, ""),
Matt Wagantall5d44ef22012-01-23 11:01:05 -08005405 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005406 CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
Matt Wagantall49722712011-08-17 18:50:53 -07005407 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
Matt Wagantalle604d712011-10-21 15:38:18 -07005408 CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
Matt Wagantallbb90da92011-10-25 15:07:52 -07005409 CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005410 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005411 CLK_LOOKUP("tv_enc_pclk", tv_enc_p_clk.c, NULL),
Matt Wagantall3f7660b2011-08-17 21:25:13 -07005412 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005413 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
Kevin Chan5827c552011-10-28 18:36:32 -07005414 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005415 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
Kevin Chana0853122011-11-07 19:48:44 -08005416 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"),
Matt Wagantall49722712011-08-17 18:50:53 -07005417 CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"),
Kuirong Wanga9c3acc2012-02-09 17:00:45 -08005418 CLK_LOOKUP("bit_clk", mi2s_bit_clk.c, "msm-dai-q6.6"),
5419 CLK_LOOKUP("osr_clk", mi2s_osr_clk.c, "msm-dai-q6.6"),
5420 CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c,
5421 "msm-dai-q6.1"),
5422 CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c,
5423 "msm-dai-q6.1"),
5424 CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c,
5425 "msm-dai-q6.5"),
5426 CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c,
5427 "msm-dai-q6.5"),
5428 CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c,
5429 "msm-dai-q6.16384"),
5430 CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c,
5431 "msm-dai-q6.16384"),
5432 CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c,
5433 "msm-dai-q6.4"),
5434 CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c,
5435 "msm-dai-q6.4"),
5436 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"),
Kiran Kandi5f4ab692012-02-23 11:23:56 -08005437 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.3"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005438 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
Tianyi Gou44a81b02012-02-06 17:49:07 -08005439 CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"),
Matt Wagantalle604d712011-10-21 15:38:18 -07005440 CLK_LOOKUP("core_clk", jpegd_axi_clk.c, "msm_iommu.0"),
5441 CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
5442 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
5443 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
5444 CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
5445 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
5446 CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
5447 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
5448 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
5449 CLK_LOOKUP("core_clk", gfx3d_clk.c, "msm_iommu.9"),
5450 CLK_LOOKUP("core_clk", gfx2d0_clk.c, "msm_iommu.10"),
5451 CLK_LOOKUP("core_clk", gfx2d1_clk.c, "msm_iommu.11"),
Gopikrishnaiah Anandan4d05ed32012-01-13 11:08:44 -08005452
5453 CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"),
5454 CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"),
5455 CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"),
5456 CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"),
5457 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"),
5458
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005459 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
Manu Gautam5143b252012-01-05 19:25:23 -08005460 CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"),
Matt Wagantall37ce3842011-08-17 16:00:36 -07005461 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
5462 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
5463 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
5464 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
5465 CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"),
Yan He160633e2011-06-30 12:18:56 -07005466 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
Stephen Boyd1c51a492011-10-26 12:11:47 -07005467 CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
Stephen Boydef5d1c42011-12-15 20:47:14 -08005468 CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
Ramesh Masavarapua1bc0e42012-03-05 07:42:48 -08005469 CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"),
Ramesh Masavarapueb6e9342012-02-13 19:59:50 -08005470 CLK_LOOKUP("bus_clk", dfab_tzcom_clk.c, "tzcom"),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005471
Matt Wagantalle1a86062011-08-18 17:46:10 -07005472 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
Matt Wagantall8b38f942011-08-02 18:23:18 -07005473
Matt Wagantallc00f95d2012-01-05 14:22:45 -08005474 CLK_LOOKUP("l2_mclk", l2_m_clk, ""),
5475 CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""),
5476 CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""),
5477 CLK_LOOKUP("q6sw_clk", q6sw_clk, ""),
5478 CLK_LOOKUP("q6fw_clk", q6fw_clk, ""),
5479 CLK_LOOKUP("q6_func_clk", q6_func_clk, ""),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005480};
5481
Tianyi Goue3d4f542012-03-15 17:06:45 -07005482static struct clk_lookup msm_clocks_8930[] = {
Stephen Boydbe1a7392012-04-02 20:17:11 -07005483 CLK_LOOKUP("xo", cxo_clk.c, "msm_xo"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005484 CLK_LOOKUP("cxo", cxo_clk.c, "wcnss_wlan.0"),
5485 CLK_LOOKUP("cxo", cxo_clk.c, "pil_riva"),
5486 CLK_LOOKUP("xo", pxo_clk.c, "pil_qdsp6v4.0"),
5487 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.1"),
5488 CLK_LOOKUP("xo", cxo_clk.c, "pil_qdsp6v4.2"),
5489 CLK_LOOKUP("xo", cxo_clk.c, "BAM_RMNT"),
5490 CLK_LOOKUP("pll2", pll2_clk.c, NULL),
5491 CLK_LOOKUP("pll8", pll8_clk.c, NULL),
5492 CLK_LOOKUP("pll4", pll4_clk.c, NULL),
5493 CLK_LOOKUP("measure", measure_clk.c, "debug"),
5494
5495 CLK_LOOKUP("bus_clk", afab_clk.c, "msm_apps_fab"),
5496 CLK_LOOKUP("bus_a_clk", afab_a_clk.c, "msm_apps_fab"),
5497 CLK_LOOKUP("bus_clk", cfpb_clk.c, "msm_cpss_fpb"),
5498 CLK_LOOKUP("bus_a_clk", cfpb_a_clk.c, "msm_cpss_fpb"),
5499 CLK_LOOKUP("bus_clk", sfab_clk.c, "msm_sys_fab"),
5500 CLK_LOOKUP("bus_a_clk", sfab_msmbus_a_clk.c, "msm_sys_fab"),
5501 CLK_LOOKUP("bus_clk", sfpb_clk.c, "msm_sys_fpb"),
5502 CLK_LOOKUP("bus_a_clk", sfpb_a_clk.c, "msm_sys_fpb"),
5503 CLK_LOOKUP("bus_clk", mmfab_clk.c, "msm_mm_fab"),
5504 CLK_LOOKUP("bus_a_clk", mmfab_a_clk.c, "msm_mm_fab"),
5505 CLK_LOOKUP("mem_clk", ebi1_msmbus_clk.c, "msm_bus"),
5506 CLK_LOOKUP("mem_a_clk", ebi1_a_clk.c, "msm_bus"),
Gagan Macbc5f81d2012-04-04 15:03:12 -06005507 CLK_LOOKUP("dfab_clk", dfab_msmbus_clk.c, "msm_bus"),
5508 CLK_LOOKUP("dfab_a_clk", dfab_msmbus_a_clk.c, "msm_bus"),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005509
5510 CLK_LOOKUP("ebi1_clk", ebi1_clk.c, NULL),
Tianyi Goue3d4f542012-03-15 17:06:45 -07005511 CLK_LOOKUP("mmfpb_clk", mmfpb_clk.c, NULL),
5512 CLK_LOOKUP("mmfpb_a_clk", mmfpb_a_clk.c, "clock-8960"),
5513 CLK_LOOKUP("cfpb_a_clk", cfpb_a_clk.c, "clock-8960"),
5514
5515 CLK_LOOKUP("core_clk", gp0_clk.c, ""),
5516 CLK_LOOKUP("core_clk", gp1_clk.c, ""),
5517 CLK_LOOKUP("core_clk", gp2_clk.c, ""),
5518 CLK_LOOKUP("core_clk", gsbi1_uart_clk.c, ""),
5519 CLK_LOOKUP("core_clk", gsbi2_uart_clk.c, ""),
5520 CLK_LOOKUP("core_clk", gsbi3_uart_clk.c, ""),
5521 CLK_LOOKUP("core_clk", gsbi4_uart_clk.c, ""),
5522 CLK_LOOKUP("core_clk", gsbi5_uart_clk.c, "msm_serial_hsl.0"),
5523 CLK_LOOKUP("core_clk", gsbi6_uart_clk.c, "msm_serial_hs.0"),
5524 CLK_LOOKUP("core_clk", gsbi7_uart_clk.c, ""),
5525 CLK_LOOKUP("core_clk", gsbi8_uart_clk.c, ""),
5526 CLK_LOOKUP("core_clk", gsbi9_uart_clk.c, ""),
5527 CLK_LOOKUP("core_clk", gsbi10_uart_clk.c, ""),
5528 CLK_LOOKUP("core_clk", gsbi11_uart_clk.c, ""),
5529 CLK_LOOKUP("core_clk", gsbi12_uart_clk.c, ""),
5530 CLK_LOOKUP("core_clk", gsbi1_qup_clk.c, "spi_qsd.0"),
5531 CLK_LOOKUP("core_clk", gsbi2_qup_clk.c, ""),
5532 CLK_LOOKUP("core_clk", gsbi3_qup_clk.c, "qup_i2c.3"),
5533 CLK_LOOKUP("core_clk", gsbi4_qup_clk.c, "qup_i2c.4"),
5534 CLK_LOOKUP("core_clk", gsbi5_qup_clk.c, ""),
5535 CLK_LOOKUP("core_clk", gsbi6_qup_clk.c, ""),
5536 CLK_LOOKUP("core_clk", gsbi7_qup_clk.c, ""),
5537 CLK_LOOKUP("core_clk", gsbi8_qup_clk.c, ""),
5538 CLK_LOOKUP("core_clk", gsbi9_qup_clk.c, "qup_i2c.0"),
5539 CLK_LOOKUP("core_clk", gsbi10_qup_clk.c, "qup_i2c.10"),
5540 CLK_LOOKUP("core_clk", gsbi11_qup_clk.c, ""),
5541 CLK_LOOKUP("core_clk", gsbi12_qup_clk.c, "qup_i2c.12"),
5542 CLK_LOOKUP("core_clk", pdm_clk.c, ""),
5543 CLK_LOOKUP("mem_clk", pmem_clk.c, "msm_sps"),
5544 CLK_LOOKUP("core_clk", prng_clk.c, "msm_rng.0"),
5545 CLK_LOOKUP("core_clk", sdc1_clk.c, "msm_sdcc.1"),
5546 CLK_LOOKUP("core_clk", sdc2_clk.c, "msm_sdcc.2"),
5547 CLK_LOOKUP("core_clk", sdc3_clk.c, "msm_sdcc.3"),
5548 CLK_LOOKUP("core_clk", sdc4_clk.c, "msm_sdcc.4"),
5549 CLK_LOOKUP("core_clk", sdc5_clk.c, "msm_sdcc.5"),
5550 CLK_LOOKUP("ref_clk", tsif_ref_clk.c, ""),
5551 CLK_LOOKUP("core_clk", tssc_clk.c, ""),
5552 CLK_LOOKUP("alt_core_clk", usb_hs1_xcvr_clk.c, "msm_otg"),
5553 CLK_LOOKUP("phy_clk", usb_phy0_clk.c, "msm_otg"),
5554 CLK_LOOKUP("alt_core_clk", usb_fs1_xcvr_clk.c, ""),
5555 CLK_LOOKUP("sys_clk", usb_fs1_sys_clk.c, ""),
5556 CLK_LOOKUP("src_clk", usb_fs1_src_clk.c, ""),
5557 CLK_LOOKUP("alt_core_clk", usb_fs2_xcvr_clk.c, ""),
5558 CLK_LOOKUP("sys_clk", usb_fs2_sys_clk.c, ""),
5559 CLK_LOOKUP("src_clk", usb_fs2_src_clk.c, ""),
5560 CLK_LOOKUP("alt_core_clk", usb_hsic_xcvr_fs_clk.c, "msm_hsic_host"),
5561 CLK_LOOKUP("phy_clk", usb_hsic_hsic_clk.c, "msm_hsic_host"),
5562 CLK_LOOKUP("cal_clk", usb_hsic_hsio_cal_clk.c, "msm_hsic_host"),
5563 CLK_LOOKUP("core_clk", usb_hsic_system_clk.c, "msm_hsic_host"),
5564 CLK_LOOKUP("iface_clk", usb_hsic_p_clk.c, "msm_hsic_host"),
5565 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"),
5566 CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"),
5567 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"),
5568 CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"),
5569 CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
5570 CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, "spi_qsd.0"),
5571 CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, ""),
5572 CLK_LOOKUP("iface_clk", gsbi3_p_clk.c, "qup_i2c.3"),
5573 CLK_LOOKUP("iface_clk", gsbi4_p_clk.c, "qup_i2c.4"),
5574 CLK_LOOKUP("iface_clk", gsbi5_p_clk.c, "msm_serial_hsl.0"),
5575 CLK_LOOKUP("iface_clk", gsbi6_p_clk.c, "msm_serial_hs.0"),
5576 CLK_LOOKUP("iface_clk", gsbi7_p_clk.c, ""),
5577 CLK_LOOKUP("iface_clk", gsbi8_p_clk.c, ""),
5578 CLK_LOOKUP("iface_clk", gsbi9_p_clk.c, "qup_i2c.0"),
5579 CLK_LOOKUP("iface_clk", gsbi10_p_clk.c, "qup_i2c.10"),
5580 CLK_LOOKUP("iface_clk", gsbi11_p_clk.c, ""),
5581 CLK_LOOKUP("iface_clk", gsbi12_p_clk.c, "qup_i2c.12"),
5582 CLK_LOOKUP("iface_clk", tsif_p_clk.c, ""),
5583 CLK_LOOKUP("iface_clk", usb_fs1_p_clk.c, ""),
5584 CLK_LOOKUP("iface_clk", usb_fs2_p_clk.c, ""),
5585 CLK_LOOKUP("iface_clk", usb_hs1_p_clk.c, "msm_otg"),
5586 CLK_LOOKUP("iface_clk", sdc1_p_clk.c, "msm_sdcc.1"),
5587 CLK_LOOKUP("iface_clk", sdc2_p_clk.c, "msm_sdcc.2"),
5588 CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
5589 CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
5590 CLK_LOOKUP("iface_clk", sdc5_p_clk.c, "msm_sdcc.5"),
5591 CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
5592 CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
5593 CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, ""),
5594 CLK_LOOKUP("iface_clk", pmic_arb1_p_clk.c, ""),
5595 CLK_LOOKUP("core_clk", pmic_ssbi2_clk.c, ""),
5596 CLK_LOOKUP("mem_clk", rpm_msg_ram_p_clk.c, ""),
5597 CLK_LOOKUP("core_clk", amp_clk.c, ""),
5598 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-001a"),
5599 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-006c"),
5600 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0048"),
5601 CLK_LOOKUP("cam_clk", cam2_clk.c, NULL),
5602 CLK_LOOKUP("cam_clk", cam0_clk.c, "4-0020"),
5603 CLK_LOOKUP("csi_src_clk", csi0_src_clk.c, "msm_csid.0"),
5604 CLK_LOOKUP("csi_src_clk", csi1_src_clk.c, "msm_csid.1"),
5605 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, "msm_csid.2"),
5606 CLK_LOOKUP("csi_clk", csi0_clk.c, "msm_csid.0"),
5607 CLK_LOOKUP("csi_clk", csi1_clk.c, "msm_csid.1"),
5608 CLK_LOOKUP("csi_clk", csi2_clk.c, "msm_csid.2"),
5609 CLK_LOOKUP("csi_phy_clk", csi0_phy_clk.c, "msm_csid.0"),
5610 CLK_LOOKUP("csi_phy_clk", csi1_phy_clk.c, "msm_csid.1"),
5611 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, "msm_csid.2"),
5612 CLK_LOOKUP("csi_pix_clk", csi_pix_clk.c, "msm_ispif.0"),
5613 CLK_LOOKUP("csi_rdi_clk", csi_rdi_clk.c, "msm_ispif.0"),
5614 CLK_LOOKUP("csi_src_clk", csi2_src_clk.c, NULL),
5615 CLK_LOOKUP("csi_clk", csi2_clk.c, NULL),
5616 CLK_LOOKUP("csi_pix1_clk", csi_pix1_clk.c, "msm_ispif.0"),
5617 CLK_LOOKUP("csi_rdi1_clk", csi_rdi1_clk.c, "msm_ispif.0"),
5618 CLK_LOOKUP("csi_rdi2_clk", csi_rdi2_clk.c, "msm_ispif.0"),
5619 CLK_LOOKUP("csi_phy_clk", csi2_phy_clk.c, NULL),
5620 CLK_LOOKUP("csi2phy_timer_clk", csi2phy_timer_clk.c, NULL),
5621 CLK_LOOKUP("csiphy_timer_src_clk",
5622 csiphy_timer_src_clk.c, "msm_csiphy.0"),
5623 CLK_LOOKUP("csiphy_timer_src_clk",
5624 csiphy_timer_src_clk.c, "msm_csiphy.1"),
5625 CLK_LOOKUP("csiphy_timer_src_clk",
5626 csiphy_timer_src_clk.c, "msm_csiphy.2"),
5627 CLK_LOOKUP("csiphy_timer_clk", csi0phy_timer_clk.c, "msm_csiphy.0"),
5628 CLK_LOOKUP("csiphy_timer_clk", csi1phy_timer_clk.c, "msm_csiphy.1"),
5629 CLK_LOOKUP("csiphy_timer_clk", csi2phy_timer_clk.c, "msm_csiphy.2"),
5630 CLK_LOOKUP("dsi_byte_div_clk", dsi1_byte_clk.c, NULL),
5631 CLK_LOOKUP("dsi_esc_clk", dsi1_esc_clk.c, NULL),
5632 CLK_LOOKUP("core_clk", gfx3d_clk.c, "kgsl-3d0.0"),
5633 CLK_LOOKUP("core_clk", gfx3d_clk.c, "footswitch-8x60.2"),
5634 CLK_LOOKUP("bus_clk",
5635 gfx3d_axi_clk_8930.c, "footswitch-8x60.2"),
5636 CLK_LOOKUP("bus_clk", ijpeg_axi_clk.c, "footswitch-8x60.3"),
5637 CLK_LOOKUP("imem_clk", imem_axi_clk.c, NULL),
5638 CLK_LOOKUP("ijpeg_clk", ijpeg_clk.c, NULL),
5639 CLK_LOOKUP("core_clk", ijpeg_clk.c, "footswitch-8x60.3"),
5640 CLK_LOOKUP("mdp_clk", mdp_clk.c, NULL),
5641 CLK_LOOKUP("core_clk", mdp_clk.c, "footswitch-8x60.4"),
5642 CLK_LOOKUP("mdp_vsync_clk", mdp_vsync_clk.c, NULL),
5643 CLK_LOOKUP("vsync_clk", mdp_vsync_clk.c, "footswitch-8x60.4"),
5644 CLK_LOOKUP("lut_mdp", lut_mdp_clk.c, NULL),
5645 CLK_LOOKUP("lut_clk", lut_mdp_clk.c, "footswitch-8x60.4"),
5646 CLK_LOOKUP("core_clk", rot_clk.c, "msm_rotator.0"),
5647 CLK_LOOKUP("core_clk", rot_clk.c, "footswitch-8x60.6"),
5648 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, NULL),
5649 CLK_LOOKUP("tv_src_clk", tv_src_clk.c, "footswitch-8x60.4"),
5650 CLK_LOOKUP("tv_dac_clk", tv_dac_clk.c, NULL),
5651 CLK_LOOKUP("core_clk", vcodec_clk.c, "msm_vidc.0"),
5652 CLK_LOOKUP("core_clk", vcodec_clk.c, "footswitch-8x60.7"),
5653 CLK_LOOKUP("mdp_tv_clk", mdp_tv_clk.c, NULL),
5654 CLK_LOOKUP("tv_clk", mdp_tv_clk.c, "footswitch-8x60.4"),
5655 CLK_LOOKUP("hdmi_clk", hdmi_tv_clk.c, NULL),
5656 CLK_LOOKUP("core_clk", hdmi_app_clk.c, "hdmi_msm.1"),
5657 CLK_LOOKUP("vpe_clk", vpe_clk.c, "msm_vpe.0"),
5658 CLK_LOOKUP("core_clk", vpe_clk.c, "footswitch-8x60.9"),
5659 CLK_LOOKUP("vfe_clk", vfe_clk.c, "msm_vfe.0"),
5660 CLK_LOOKUP("core_clk", vfe_clk.c, "footswitch-8x60.8"),
5661 CLK_LOOKUP("csi_vfe_clk", csi_vfe_clk.c, "msm_vfe.0"),
5662 CLK_LOOKUP("bus_clk", vfe_axi_clk.c, "footswitch-8x60.8"),
5663 CLK_LOOKUP("bus_clk", mdp_axi_clk.c, "footswitch-8x60.4"),
5664 CLK_LOOKUP("bus_clk", rot_axi_clk.c, "footswitch-8x60.6"),
5665 CLK_LOOKUP("bus_clk", vcodec_axi_clk.c, "footswitch-8x60.7"),
5666 CLK_LOOKUP("bus_a_clk", vcodec_axi_a_clk.c, "footswitch-8x60.7"),
5667 CLK_LOOKUP("bus_b_clk", vcodec_axi_b_clk.c, "footswitch-8x60.7"),
5668 CLK_LOOKUP("bus_clk", vpe_axi_clk.c, "footswitch-8x60.9"),
5669 CLK_LOOKUP("amp_pclk", amp_p_clk.c, NULL),
5670 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.0"),
5671 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.1"),
5672 CLK_LOOKUP("csi_pclk", csi_p_clk.c, "msm_csid.2"),
5673 CLK_LOOKUP("dsi_m_pclk", dsi1_m_p_clk.c, NULL),
5674 CLK_LOOKUP("dsi_s_pclk", dsi1_s_p_clk.c, NULL),
5675 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "kgsl-3d0.0"),
5676 CLK_LOOKUP("iface_clk", gfx3d_p_clk.c, "footswitch-8x60.2"),
5677 CLK_LOOKUP("master_iface_clk", hdmi_m_p_clk.c, "hdmi_msm.1"),
5678 CLK_LOOKUP("slave_iface_clk", hdmi_s_p_clk.c, "hdmi_msm.1"),
5679 CLK_LOOKUP("ijpeg_pclk", ijpeg_p_clk.c, NULL),
5680 CLK_LOOKUP("iface_clk", ijpeg_p_clk.c, "footswitch-8x60.3"),
5681 CLK_LOOKUP("mem_iface_clk", imem_p_clk.c, "kgsl-3d0.0"),
5682 CLK_LOOKUP("mdp_pclk", mdp_p_clk.c, NULL),
5683 CLK_LOOKUP("iface_clk", mdp_p_clk.c, "footswitch-8x60.4"),
5684 CLK_LOOKUP("iface_clk", smmu_p_clk.c, "msm_iommu"),
5685 CLK_LOOKUP("iface_clk", rot_p_clk.c, "msm_rotator.0"),
5686 CLK_LOOKUP("iface_clk", rot_p_clk.c, "footswitch-8x60.6"),
5687 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "msm_vidc.0"),
5688 CLK_LOOKUP("iface_clk", vcodec_p_clk.c, "footswitch-8x60.7"),
5689 CLK_LOOKUP("vfe_pclk", vfe_p_clk.c, "msm_vfe.0"),
5690 CLK_LOOKUP("iface_clk", vfe_p_clk.c, "footswitch-8x60.8"),
5691 CLK_LOOKUP("vpe_pclk", vpe_p_clk.c, "msm_vpe.0"),
5692 CLK_LOOKUP("iface_clk", vpe_p_clk.c, "footswitch-8x60.9"),
5693 CLK_LOOKUP("bit_clk", mi2s_bit_clk.c, "msm-dai-q6.6"),
5694 CLK_LOOKUP("osr_clk", mi2s_osr_clk.c, "msm-dai-q6.6"),
5695 CLK_LOOKUP("bit_clk", codec_i2s_mic_bit_clk.c,
5696 "msm-dai-q6.1"),
5697 CLK_LOOKUP("osr_clk", codec_i2s_mic_osr_clk.c,
5698 "msm-dai-q6.1"),
5699 CLK_LOOKUP("bit_clk", spare_i2s_mic_bit_clk.c,
5700 "msm-dai-q6.5"),
5701 CLK_LOOKUP("osr_clk", spare_i2s_mic_osr_clk.c,
5702 "msm-dai-q6.5"),
5703 CLK_LOOKUP("bit_clk", codec_i2s_spkr_bit_clk.c,
5704 "msm-dai-q6.16384"),
5705 CLK_LOOKUP("osr_clk", codec_i2s_spkr_osr_clk.c,
5706 "msm-dai-q6.16384"),
5707 CLK_LOOKUP("bit_clk", spare_i2s_spkr_bit_clk.c,
5708 "msm-dai-q6.4"),
5709 CLK_LOOKUP("osr_clk", spare_i2s_spkr_osr_clk.c,
5710 "msm-dai-q6.4"),
5711 CLK_LOOKUP("pcm_clk", pcm_clk.c, "msm-dai-q6.2"),
5712 CLK_LOOKUP("sps_slimbus_clk", sps_slimbus_clk.c, NULL),
5713 CLK_LOOKUP("core_clk", audio_slimbus_clk.c, "msm_slim_ctrl.1"),
5714 CLK_LOOKUP("core_clk", vpe_axi_clk.c, "msm_iommu.1"),
5715 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.2"),
5716 CLK_LOOKUP("core_clk", mdp_axi_clk.c, "msm_iommu.3"),
5717 CLK_LOOKUP("core_clk", rot_axi_clk.c, "msm_iommu.4"),
5718 CLK_LOOKUP("core_clk", ijpeg_axi_clk.c, "msm_iommu.5"),
5719 CLK_LOOKUP("core_clk", vfe_axi_clk.c, "msm_iommu.6"),
5720 CLK_LOOKUP("core_clk", vcodec_axi_a_clk.c, "msm_iommu.7"),
5721 CLK_LOOKUP("core_clk", vcodec_axi_b_clk.c, "msm_iommu.8"),
5722 CLK_LOOKUP("core_clk", gfx3d_axi_clk_8930.c, "msm_iommu.9"),
5723 CLK_LOOKUP("core_clk", gfx3d_axi_clk_8930.c, "msm_iommu.10"),
5724
5725 CLK_LOOKUP("mdp_iommu_clk", mdp_axi_clk.c, "msm_vidc.0"),
5726 CLK_LOOKUP("rot_iommu_clk", rot_axi_clk.c, "msm_vidc.0"),
5727 CLK_LOOKUP("vcodec_iommu0_clk", vcodec_axi_a_clk.c, "msm_vidc.0"),
5728 CLK_LOOKUP("vcodec_iommu1_clk", vcodec_axi_b_clk.c, "msm_vidc.0"),
5729 CLK_LOOKUP("smmu_iface_clk", smmu_p_clk.c, "msm_vidc.0"),
5730
5731 CLK_LOOKUP("dfab_dsps_clk", dfab_dsps_clk.c, NULL),
5732 CLK_LOOKUP("core_clk", dfab_usb_hs_clk.c, "msm_otg"),
5733 CLK_LOOKUP("bus_clk", dfab_sdc1_clk.c, "msm_sdcc.1"),
5734 CLK_LOOKUP("bus_clk", dfab_sdc2_clk.c, "msm_sdcc.2"),
5735 CLK_LOOKUP("bus_clk", dfab_sdc3_clk.c, "msm_sdcc.3"),
5736 CLK_LOOKUP("bus_clk", dfab_sdc4_clk.c, "msm_sdcc.4"),
5737 CLK_LOOKUP("bus_clk", dfab_sdc5_clk.c, "msm_sdcc.5"),
5738 CLK_LOOKUP("dfab_clk", dfab_sps_clk.c, "msm_sps"),
5739 CLK_LOOKUP("bus_clk", dfab_bam_dmux_clk.c, "BAM_RMNT"),
5740 CLK_LOOKUP("bus_clk", dfab_scm_clk.c, "scm"),
5741 CLK_LOOKUP("bus_clk", dfab_qseecom_clk.c, "qseecom"),
5742
5743 CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"),
5744
5745 CLK_LOOKUP("l2_mclk", l2_m_clk, ""),
5746 CLK_LOOKUP("krait0_mclk", krait0_m_clk, ""),
5747 CLK_LOOKUP("krait1_mclk", krait1_m_clk, ""),
5748 CLK_LOOKUP("q6sw_clk", q6sw_clk, ""),
5749 CLK_LOOKUP("q6fw_clk", q6fw_clk, ""),
5750 CLK_LOOKUP("q6_func_clk", q6_func_clk, ""),
5751};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005752/*
5753 * Miscellaneous clock register initializations
5754 */
5755
5756/* Read, modify, then write-back a register. */
5757static void __init rmwreg(uint32_t val, void *reg, uint32_t mask)
5758{
5759 uint32_t regval = readl_relaxed(reg);
5760 regval &= ~mask;
5761 regval |= val;
5762 writel_relaxed(regval, reg);
5763}
5764
Tianyi Gou41515e22011-09-01 19:37:43 -07005765static void __init set_fsm_mode(void __iomem *mode_reg)
5766{
5767 u32 regval = readl_relaxed(mode_reg);
5768
5769 /*De-assert reset to FSM */
5770 regval &= ~BIT(21);
5771 writel_relaxed(regval, mode_reg);
5772
5773 /* Program bias count */
Tianyi Gou358c3862011-10-18 17:03:41 -07005774 regval &= ~BM(19, 14);
5775 regval |= BVAL(19, 14, 0x1);
5776 writel_relaxed(regval, mode_reg);
5777
5778 /* Program lock count */
Tianyi Gou41515e22011-09-01 19:37:43 -07005779 regval &= ~BM(13, 8);
5780 regval |= BVAL(13, 8, 0x8);
5781 writel_relaxed(regval, mode_reg);
5782
5783 /*Enable PLL FSM voting */
5784 regval |= BIT(20);
5785 writel_relaxed(regval, mode_reg);
5786}
5787
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005788static void __init reg_init(void)
5789{
Stephen Boydd471e7a2011-11-19 01:37:39 -08005790 void __iomem *imem_reg;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005791 /* Deassert MM SW_RESET_ALL signal. */
5792 writel_relaxed(0, SW_RESET_ALL_REG);
5793
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005794 /*
Tianyi Goue3d4f542012-03-15 17:06:45 -07005795 * Some bits are only used on 8960 or 8064 or 8930 and are marked as
5796 * reserved bits on the other SoCs. Writing to these reserved bits
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005797 * should have no effect.
5798 */
Stephen Boydd471e7a2011-11-19 01:37:39 -08005799 /*
5800 * Initialize MM AHB registers: Enable the FPB clock and disable HW
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005801 * gating on non-8960 for all clocks. Also set VFE_AHB's
Stephen Boydd471e7a2011-11-19 01:37:39 -08005802 * FORCE_CORE_ON bit to prevent its memory from being collapsed when
5803 * the clock is halted. The sleep and wake-up delays are set to safe
5804 * values.
5805 */
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005806 if (cpu_is_msm8960()) {
Stephen Boydd471e7a2011-11-19 01:37:39 -08005807 rmwreg(0x44000000, AHB_EN_REG, 0x6C000103);
5808 writel_relaxed(0x3C7097F9, AHB_EN2_REG);
5809 } else {
5810 rmwreg(0x00000003, AHB_EN_REG, 0x6C000103);
5811 writel_relaxed(0x000007F9, AHB_EN2_REG);
5812 }
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005813 if (cpu_is_apq8064())
5814 rmwreg(0x00000000, AHB_EN3_REG, 0x00000001);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005815
5816 /* Deassert all locally-owned MM AHB resets. */
5817 rmwreg(0, SW_RESET_AHB_REG, 0xFFF7DFFF);
Tianyi Gou41515e22011-09-01 19:37:43 -07005818 rmwreg(0, SW_RESET_AHB2_REG, 0x0000000F);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005819
5820 /* Initialize MM AXI registers: Enable HW gating for all clocks that
5821 * support it. Also set FORCE_CORE_ON bits, and any sleep and wake-up
5822 * delays to safe values. */
Stephen Boydd471e7a2011-11-19 01:37:39 -08005823 if (cpu_is_msm8960() &&
5824 SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 3) {
5825 rmwreg(0x0003AFF9, MAXI_EN_REG, 0x0803FFFF);
5826 rmwreg(0x3A27FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
Gopikrishnaiah Anandan83b6e852012-01-05 17:47:02 -08005827 rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
Stephen Boydd471e7a2011-11-19 01:37:39 -08005828 } else {
5829 rmwreg(0x000007F9, MAXI_EN_REG, 0x0803FFFF);
5830 rmwreg(0x3027FCFF, MAXI_EN2_REG, 0x3A3FFFFF);
5831 rmwreg(0x0027FCFF, MAXI_EN4_REG, 0x017FFFFF);
5832 }
Matt Wagantall53d968f2011-07-19 13:22:53 -07005833 rmwreg(0x0027FCFF, MAXI_EN3_REG, 0x003FFFFF);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005834 if (cpu_is_apq8064())
5835 rmwreg(0x009FE4FF, MAXI_EN5_REG, 0x01FFEFFF);
Tianyi Goue3d4f542012-03-15 17:06:45 -07005836 if (cpu_is_msm8930())
5837 rmwreg(0x000004FF, MAXI_EN5_REG, 0x00000FFF);
Tianyi Gou3022dfd2012-01-25 15:50:05 -08005838 if (cpu_is_msm8960())
Stephen Boydd471e7a2011-11-19 01:37:39 -08005839 rmwreg(0x00003C38, SAXI_EN_REG, 0x00003FFF);
5840 else
5841 rmwreg(0x000003C7, SAXI_EN_REG, 0x00003FFF);
5842
5843 /* Enable IMEM's clk_on signal */
5844 imem_reg = ioremap(0x04b00040, 4);
5845 if (imem_reg) {
5846 writel_relaxed(0x3, imem_reg);
5847 iounmap(imem_reg);
5848 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005849
5850 /* Initialize MM CC registers: Set MM FORCE_CORE_ON bits so that core
5851 * memories retain state even when not clocked. Also, set sleep and
5852 * wake-up delays to safe values. */
Matt Wagantall53d968f2011-07-19 13:22:53 -07005853 rmwreg(0x00000000, CSI0_CC_REG, 0x00000410);
5854 rmwreg(0x00000000, CSI1_CC_REG, 0x00000410);
5855 rmwreg(0x80FF0000, DSI1_BYTE_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005856 rmwreg(0x80FF0000, DSI_PIXEL_CC_REG, 0xE0FF0010);
Tarun Karra6fbc00a2011-12-13 09:23:47 -07005857 rmwreg(0xC0FF0000, GFX3D_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005858 rmwreg(0x80FF0000, IJPEG_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005859 rmwreg(0x80FF0000, MDP_CC_REG, 0xE1FF0010);
5860 rmwreg(0x80FF0000, MDP_LUT_CC_REG, 0xE0FF0010);
5861 rmwreg(0x80FF0000, ROT_CC_REG, 0xE0FF0010);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005862 rmwreg(0x000004FF, TV_CC2_REG, 0x000007FF);
5863 rmwreg(0xC0FF0000, VCODEC_CC_REG, 0xE0FF0010);
5864 rmwreg(0x80FF0000, VFE_CC_REG, 0xE0FF4010);
Stephen Boyd94625ef2011-07-12 17:06:01 -07005865 rmwreg(0x800000FF, VFE_CC2_REG, 0xE00000FF);
Matt Wagantall53d968f2011-07-19 13:22:53 -07005866 rmwreg(0x80FF0000, VPE_CC_REG, 0xE0FF0010);
Tianyi Goue3d4f542012-03-15 17:06:45 -07005867 if (cpu_is_msm8960() || cpu_is_apq8064()) {
5868 rmwreg(0x80FF0000, DSI2_BYTE_CC_REG, 0xE0FF0010);
5869 rmwreg(0x80FF0000, DSI2_PIXEL_CC_REG, 0xE0FF0010);
5870 rmwreg(0x80FF0000, JPEGD_CC_REG, 0xE0FF0010);
5871 }
5872 if (cpu_is_msm8960() || cpu_is_msm8930())
5873 rmwreg(0x80FF0000, TV_CC_REG, 0xE1FFC010);
5874
5875 if (cpu_is_msm8960()) {
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005876 rmwreg(0x80FF0000, GFX2D0_CC_REG, 0xE0FF0010);
5877 rmwreg(0x80FF0000, GFX2D1_CC_REG, 0xE0FF0010);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005878 }
5879 if (cpu_is_apq8064()) {
5880 rmwreg(0x00000000, TV_CC_REG, 0x00004010);
Tianyi Gou621f8742011-09-01 21:45:01 -07005881 rmwreg(0x80FF0000, VCAP_CC_REG, 0xE0FF1010);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005882 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005883
Tianyi Gou41515e22011-09-01 19:37:43 -07005884 /*
5885 * Initialize USB_HS_HCLK_FS registers: Set FORCE_C_ON bits so that
5886 * core remain active during halt state of the clk. Also, set sleep
5887 * and wake-up value to max.
5888 */
5889 rmwreg(0x0000004F, USB_HS1_HCLK_FS_REG, 0x0000007F);
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005890 if (cpu_is_apq8064()) {
5891 rmwreg(0x0000004F, USB_HS3_HCLK_FS_REG, 0x0000007F);
5892 rmwreg(0x0000004F, USB_HS4_HCLK_FS_REG, 0x0000007F);
5893 }
Tianyi Gou41515e22011-09-01 19:37:43 -07005894
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005895 /* De-assert MM AXI resets to all hardware blocks. */
5896 writel_relaxed(0, SW_RESET_AXI_REG);
5897
5898 /* Deassert all MM core resets. */
5899 writel_relaxed(0, SW_RESET_CORE_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005900 writel_relaxed(0, SW_RESET_CORE2_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005901
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005902 /* Enable TSSC and PDM PXO sources. */
5903 writel_relaxed(BIT(11), TSSC_CLK_CTL_REG);
5904 writel_relaxed(BIT(15), PDM_CLK_NS_REG);
5905
5906 /* Source SLIMBus xo src from slimbus reference clock */
Tianyi Goue3d4f542012-03-15 17:06:45 -07005907 if (cpu_is_msm8960())
Tianyi Gou8c1a1182011-10-10 14:47:11 -07005908 writel_relaxed(0x3, SLIMBUS_XO_SRC_CLK_CTL_REG);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005909
5910 /* Source the dsi_byte_clks from the DSI PHY PLLs */
5911 rmwreg(0x1, DSI1_BYTE_NS_REG, 0x7);
Tianyi Goue3d4f542012-03-15 17:06:45 -07005912 if (cpu_is_msm8960() || cpu_is_apq8064())
5913 rmwreg(0x2, DSI2_BYTE_NS_REG, 0x7);
Tianyi Gou41515e22011-09-01 19:37:43 -07005914
5915 /* Source the sata_phy_ref_clk from PXO */
5916 if (cpu_is_apq8064())
5917 rmwreg(0, SATA_PHY_REF_CLK_CTL_REG, 0x1);
5918
5919 /*
Tianyi Gou05e01102012-02-08 22:15:49 -08005920 * TODO: Programming below PLLs and prng_clk is temporary and
5921 * needs to be removed after bootloaders program them.
Tianyi Gou41515e22011-09-01 19:37:43 -07005922 */
5923 if (cpu_is_apq8064()) {
Tianyi Gou317aa862012-02-06 14:31:07 -08005924 u32 is_pll_enabled;
Tianyi Gou41515e22011-09-01 19:37:43 -07005925
5926 /* Program pxo_src_clk to source from PXO */
5927 rmwreg(0x1, PXO_SRC_CLK_CTL_REG, 0x7);
5928
Tianyi Gou41515e22011-09-01 19:37:43 -07005929 /* Check if PLL14 is active */
5930 is_pll_enabled = readl_relaxed(BB_PLL14_STATUS_REG) & BIT(16);
5931 if (!is_pll_enabled) {
Tianyi Goudf71f2e2011-10-24 22:25:04 -07005932 /* Ref clk = 27MHz and program pll14 to 480MHz */
Tianyi Gou317aa862012-02-06 14:31:07 -08005933 writel_relaxed(0x00031011, BB_PLL14_L_VAL_REG);
Tianyi Goudf71f2e2011-10-24 22:25:04 -07005934 writel_relaxed(0x7, BB_PLL14_M_VAL_REG);
5935 writel_relaxed(0x9, BB_PLL14_N_VAL_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005936
Tianyi Gou317aa862012-02-06 14:31:07 -08005937 /*
5938 * Enable the main output and the MN accumulator
5939 * Set pre-divider and post-divider values to 1 and 1
5940 */
5941 writel_relaxed(0x00C00000, BB_PLL14_CONFIG_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005942
Tianyi Gou41515e22011-09-01 19:37:43 -07005943 set_fsm_mode(BB_PLL14_MODE_REG);
5944 }
Tianyi Gou621f8742011-09-01 21:45:01 -07005945
Tianyi Gou621f8742011-09-01 21:45:01 -07005946 /* Program PLL15 to 975MHz with ref clk = 27MHz */
Tianyi Gou317aa862012-02-06 14:31:07 -08005947 writel_relaxed(0x31024, MM_PLL3_L_VAL_REG);
5948 writel_relaxed(0x1, MM_PLL3_M_VAL_REG);
5949 writel_relaxed(0x9, MM_PLL3_N_VAL_REG);
Tianyi Gou621f8742011-09-01 21:45:01 -07005950
Tianyi Gou317aa862012-02-06 14:31:07 -08005951 writel_relaxed(0xC20000, MM_PLL3_CONFIG_REG);
Tianyi Gouc29c3242011-10-12 21:02:15 -07005952
5953 /* Check if PLL4 is active */
5954 is_pll_enabled = readl_relaxed(LCC_PLL0_STATUS_REG) & BIT(16);
5955 if (!is_pll_enabled) {
Tianyi Goudf71f2e2011-10-24 22:25:04 -07005956 /* Ref clk = 27MHz and program pll4 to 393.2160MHz */
5957 writel_relaxed(0xE, LCC_PLL0_L_VAL_REG);
5958 writel_relaxed(0x27A, LCC_PLL0_M_VAL_REG);
5959 writel_relaxed(0x465, LCC_PLL0_N_VAL_REG);
Tianyi Gouc29c3242011-10-12 21:02:15 -07005960
Tianyi Gou317aa862012-02-06 14:31:07 -08005961 writel_relaxed(0xC00000, LCC_PLL0_CONFIG_REG);
Tianyi Gouc29c3242011-10-12 21:02:15 -07005962
5963 set_fsm_mode(LCC_PLL0_MODE_REG);
5964 }
5965
5966 /* Enable PLL4 source on the LPASS Primary PLL Mux */
5967 writel_relaxed(0x1, LCC_PRI_PLL_CLK_CTL_REG);
Tianyi Gou05e01102012-02-08 22:15:49 -08005968
5969 /* Program prng_clk to 64MHz if it isn't configured */
5970 if (!readl_relaxed(PRNG_CLK_NS_REG))
5971 writel_relaxed(0x2B, PRNG_CLK_NS_REG);
Tianyi Gou41515e22011-09-01 19:37:43 -07005972 }
Tianyi Gou65c536a2012-03-20 23:20:29 -07005973
5974 /*
5975 * Program PLL15 to 900MHz with ref clk = 27MHz and
5976 * only enable PLL main output.
5977 */
5978 if (cpu_is_msm8930()) {
5979 writel_relaxed(0x30021, MM_PLL3_L_VAL_REG);
5980 writel_relaxed(0x1, MM_PLL3_M_VAL_REG);
5981 writel_relaxed(0x3, MM_PLL3_N_VAL_REG);
5982
5983 writel_relaxed(0xC20000, MM_PLL3_CONFIG_REG);
5984 writel_relaxed(0, MM_PLL3_TEST_CTL_REG);
5985 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005986}
5987
Matt Wagantallb64888f2012-04-02 21:35:07 -07005988static void __init msm8960_clock_pre_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005989{
Saravana Kannan298ec392012-02-08 19:21:47 -08005990 if (cpu_is_apq8064()) {
5991 vdd_sr2_pll.set_vdd = set_vdd_sr2_pll_8064;
Tianyi Goue1faaf22012-01-24 16:07:19 -08005992 } else if (cpu_is_msm8930() || cpu_is_msm8627()) {
Saravana Kannan298ec392012-02-08 19:21:47 -08005993 vdd_dig.set_vdd = set_vdd_dig_8930;
5994 vdd_sr2_pll.set_vdd = set_vdd_sr2_pll_8930;
Tianyi Goue1faaf22012-01-24 16:07:19 -08005995 }
Tianyi Goubf3d0b12012-01-23 14:37:28 -08005996
Tianyi Gou41515e22011-09-01 19:37:43 -07005997 /*
Matt Wagantalle18bbc82011-10-06 10:07:28 -07005998 * Change the freq tables for and voltage requirements for
5999 * clocks which differ between 8960 and 8064.
Tianyi Gou41515e22011-09-01 19:37:43 -07006000 */
6001 if (cpu_is_apq8064()) {
6002 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8064;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07006003
6004 memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8064,
6005 sizeof(gfx3d_clk.c.fmax));
6006 memcpy(ijpeg_clk.c.fmax, fmax_ijpeg_8064,
6007 sizeof(ijpeg_clk.c.fmax));
6008 memcpy(mdp_clk.c.fmax, fmax_mdp_8064,
6009 sizeof(ijpeg_clk.c.fmax));
6010 memcpy(tv_src_clk.c.fmax, fmax_tv_src_8064,
6011 sizeof(tv_src_clk.c.fmax));
6012 memcpy(vfe_clk.c.fmax, fmax_vfe_8064,
6013 sizeof(vfe_clk.c.fmax));
6014
Tianyi Goue3d4f542012-03-15 17:06:45 -07006015 gmem_axi_clk.c.depends = &gfx3d_axi_clk_8064.c;
6016 }
6017
6018 /*
6019 * Change the freq tables and voltage requirements for
6020 * clocks which differ between 8960 and 8930.
6021 */
6022 if (cpu_is_msm8930()) {
6023 gfx3d_clk.freq_tbl = clk_tbl_gfx3d_8930;
6024
6025 memcpy(gfx3d_clk.c.fmax, fmax_gfx3d_8930,
6026 sizeof(gfx3d_clk.c.fmax));
6027
6028 pll15_clk.c.rate = 900000000;
6029 gmem_axi_clk.c.depends = &gfx3d_axi_clk_8930.c;
Tianyi Gou41515e22011-09-01 19:37:43 -07006030 }
Stephen Boyd94625ef2011-07-12 17:06:01 -07006031
Matt Wagantalle18bbc82011-10-06 10:07:28 -07006032 vote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006033
Vikram Mulukutla489e39e2011-08-31 18:04:05 -07006034 clk_ops_pll.enable = sr_pll_clk_enable;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006035
6036 /* Initialize clock registers. */
6037 reg_init();
Matt Wagantallb64888f2012-04-02 21:35:07 -07006038}
6039
6040static void __init msm8960_clock_post_init(void)
6041{
6042 /* Keep PXO on whenever APPS cpu is active */
6043 clk_prepare_enable(&pxo_a_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006044
Matt Wagantalle655cd72012-04-09 10:15:03 -07006045 /* Reset 3D core while clocked to ensure it resets completely. */
6046 clk_set_rate(&gfx3d_clk.c, 27000000);
6047 clk_prepare_enable(&gfx3d_clk.c);
6048 clk_reset(&gfx3d_clk.c, CLK_RESET_ASSERT);
6049 udelay(5);
6050 clk_reset(&gfx3d_clk.c, CLK_RESET_DEASSERT);
6051 clk_disable_unprepare(&gfx3d_clk.c);
6052
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006053 /* Initialize rates for clocks that only support one. */
6054 clk_set_rate(&pdm_clk.c, 27000000);
6055 clk_set_rate(&prng_clk.c, 64000000);
6056 clk_set_rate(&mdp_vsync_clk.c, 27000000);
6057 clk_set_rate(&tsif_ref_clk.c, 105000);
6058 clk_set_rate(&tssc_clk.c, 27000000);
6059 clk_set_rate(&usb_hs1_xcvr_clk.c, 60000000);
Tianyi Gou41515e22011-09-01 19:37:43 -07006060 if (cpu_is_apq8064()) {
6061 clk_set_rate(&usb_hs3_xcvr_clk.c, 60000000);
6062 clk_set_rate(&usb_hs4_xcvr_clk.c, 60000000);
6063 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006064 clk_set_rate(&usb_fs1_src_clk.c, 60000000);
Stepan Moskovchenko2429f152011-10-25 14:42:35 -07006065 if (cpu_is_msm8960() || cpu_is_msm8930())
Tianyi Gou41515e22011-09-01 19:37:43 -07006066 clk_set_rate(&usb_fs2_src_clk.c, 60000000);
Stephen Boyd94625ef2011-07-12 17:06:01 -07006067 clk_set_rate(&usb_hsic_xcvr_fs_clk.c, 60000000);
6068 clk_set_rate(&usb_hsic_hsic_src_clk.c, 480000000);
6069 clk_set_rate(&usb_hsic_hsio_cal_clk.c, 9000000);
Lena Salman127823f2012-02-14 17:13:53 +02006070 clk_set_rate(&usb_hsic_system_clk.c, 60000000);
Stephen Boyd092fd182011-10-21 15:56:30 -07006071 /*
6072 * Set the CSI rates to a safe default to avoid warnings when
6073 * switching csi pix and rdi clocks.
6074 */
6075 clk_set_rate(&csi0_src_clk.c, 27000000);
6076 clk_set_rate(&csi1_src_clk.c, 27000000);
6077 clk_set_rate(&csi2_src_clk.c, 27000000);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006078
6079 /*
Stephen Boyd60496bb2011-10-17 13:51:37 -07006080 * The halt status bits for these clocks may be incorrect at boot.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006081 * Toggle these clocks on and off to refresh them.
6082 */
Matt Wagantall0625ea02011-07-13 18:51:56 -07006083 rcg_clk_enable(&pdm_clk.c);
6084 rcg_clk_disable(&pdm_clk.c);
6085 rcg_clk_enable(&tssc_clk.c);
6086 rcg_clk_disable(&tssc_clk.c);
Stephen Boyde334aeb2012-01-24 12:17:29 -08006087 clk_prepare_enable(&usb_hsic_hsic_clk.c);
6088 clk_disable_unprepare(&usb_hsic_hsic_clk.c);
Stephen Boydd7a143a2012-02-16 17:59:26 -08006089
6090 /*
6091 * Keep sfab floor @ 54MHz so that Krait AHB is at least 27MHz at all
6092 * times when Apps CPU is active. This ensures the timer's requirement
6093 * of Krait AHB running 4 times as fast as the timer itself.
6094 */
6095 clk_set_rate(&sfab_tmr_a_clk.c, 54000000);
Stephen Boyde334aeb2012-01-24 12:17:29 -08006096 clk_prepare_enable(&sfab_tmr_a_clk.c);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006097}
6098
Stephen Boydbb600ae2011-08-02 20:11:40 -07006099static int __init msm8960_clock_late_init(void)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006100{
Stephen Boyda3787f32011-09-16 18:55:13 -07006101 int rc;
6102 struct clk *mmfpb_a_clk = clk_get_sys("clock-8960", "mmfpb_a_clk");
Stephen Boyd85436132011-09-16 18:55:13 -07006103 struct clk *cfpb_a_clk = clk_get_sys("clock-8960", "cfpb_a_clk");
Stephen Boyda3787f32011-09-16 18:55:13 -07006104
6105 /* Vote for MMFPB to be at least 76.8MHz when an Apps CPU is active. */
6106 if (WARN(IS_ERR(mmfpb_a_clk), "mmfpb_a_clk not found (%ld)\n",
6107 PTR_ERR(mmfpb_a_clk)))
6108 return PTR_ERR(mmfpb_a_clk);
Matt Wagantallde555f562011-11-08 14:18:07 -08006109 rc = clk_set_rate(mmfpb_a_clk, 76800000);
Stephen Boyda3787f32011-09-16 18:55:13 -07006110 if (WARN(rc, "mmfpb_a_clk rate was not set (%d)\n", rc))
6111 return rc;
Stephen Boyde334aeb2012-01-24 12:17:29 -08006112 rc = clk_prepare_enable(mmfpb_a_clk);
Stephen Boyda3787f32011-09-16 18:55:13 -07006113 if (WARN(rc, "mmfpb_a_clk not enabled (%d)\n", rc))
6114 return rc;
6115
Stephen Boyd85436132011-09-16 18:55:13 -07006116 /* Vote for CFPB to be at least 64MHz when an Apps CPU is active. */
6117 if (WARN(IS_ERR(cfpb_a_clk), "cfpb_a_clk not found (%ld)\n",
6118 PTR_ERR(cfpb_a_clk)))
6119 return PTR_ERR(cfpb_a_clk);
Matt Wagantallde555f562011-11-08 14:18:07 -08006120 rc = clk_set_rate(cfpb_a_clk, 64000000);
Stephen Boyd85436132011-09-16 18:55:13 -07006121 if (WARN(rc, "cfpb_a_clk rate was not set (%d)\n", rc))
6122 return rc;
Stephen Boyde334aeb2012-01-24 12:17:29 -08006123 rc = clk_prepare_enable(cfpb_a_clk);
Stephen Boyd85436132011-09-16 18:55:13 -07006124 if (WARN(rc, "cfpb_a_clk not enabled (%d)\n", rc))
6125 return rc;
Matt Wagantalle18bbc82011-10-06 10:07:28 -07006126
6127 return unvote_vdd_level(&vdd_dig, VDD_DIG_HIGH);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006128}
Stephen Boydbb600ae2011-08-02 20:11:40 -07006129
6130struct clock_init_data msm8960_clock_init_data __initdata = {
6131 .table = msm_clocks_8960,
6132 .size = ARRAY_SIZE(msm_clocks_8960),
Matt Wagantallb64888f2012-04-02 21:35:07 -07006133 .pre_init = msm8960_clock_pre_init,
6134 .post_init = msm8960_clock_post_init,
Stephen Boydbb600ae2011-08-02 20:11:40 -07006135 .late_init = msm8960_clock_late_init,
6136};
Tianyi Gou41515e22011-09-01 19:37:43 -07006137
6138struct clock_init_data apq8064_clock_init_data __initdata = {
6139 .table = msm_clocks_8064,
6140 .size = ARRAY_SIZE(msm_clocks_8064),
Matt Wagantallb64888f2012-04-02 21:35:07 -07006141 .pre_init = msm8960_clock_pre_init,
6142 .post_init = msm8960_clock_post_init,
Tianyi Gou41515e22011-09-01 19:37:43 -07006143 .late_init = msm8960_clock_late_init,
6144};
Tianyi Goue3d4f542012-03-15 17:06:45 -07006145
6146struct clock_init_data msm8930_clock_init_data __initdata = {
6147 .table = msm_clocks_8930,
6148 .size = ARRAY_SIZE(msm_clocks_8930),
Matt Wagantallb64888f2012-04-02 21:35:07 -07006149 .pre_init = msm8960_clock_pre_init,
6150 .post_init = msm8960_clock_post_init,
Tianyi Goue3d4f542012-03-15 17:06:45 -07006151 .late_init = msm8960_clock_late_init,
6152};