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Linus Walleijb43d65f2009-06-09 08:11:42 +01001/*
2 * drivers/spi/amba-pl022.c
3 *
4 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
5 *
6 * Copyright (C) 2008-2009 ST-Ericsson AB
7 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
8 *
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 *
11 * Initial version inspired by:
12 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
13 * Initial adoption to PL022 by:
14 * Sachin Verma <sachin.verma@st.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 */
26
Linus Walleijb43d65f2009-06-09 08:11:42 +010027#include <linux/init.h>
28#include <linux/module.h>
29#include <linux/device.h>
30#include <linux/ioport.h>
31#include <linux/errno.h>
32#include <linux/interrupt.h>
33#include <linux/spi/spi.h>
34#include <linux/workqueue.h>
Linus Walleijb43d65f2009-06-09 08:11:42 +010035#include <linux/delay.h>
36#include <linux/clk.h>
37#include <linux/err.h>
38#include <linux/amba/bus.h>
39#include <linux/amba/pl022.h>
40#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090041#include <linux/slab.h>
Linus Walleijb1b6b9a2010-09-29 17:31:35 +090042#include <linux/dmaengine.h>
43#include <linux/dma-mapping.h>
44#include <linux/scatterlist.h>
Linus Walleijb43d65f2009-06-09 08:11:42 +010045
46/*
47 * This macro is used to define some register default values.
48 * reg is masked with mask, the OR:ed with an (again masked)
49 * val shifted sb steps to the left.
50 */
51#define SSP_WRITE_BITS(reg, val, mask, sb) \
52 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
53
54/*
55 * This macro is also used to define some default values.
56 * It will just shift val by sb steps to the left and mask
57 * the result with mask.
58 */
59#define GEN_MASK_BITS(val, mask, sb) \
60 (((val)<<(sb)) & (mask))
61
62#define DRIVE_TX 0
63#define DO_NOT_DRIVE_TX 1
64
65#define DO_NOT_QUEUE_DMA 0
66#define QUEUE_DMA 1
67
68#define RX_TRANSFER 1
69#define TX_TRANSFER 2
70
71/*
72 * Macros to access SSP Registers with their offsets
73 */
74#define SSP_CR0(r) (r + 0x000)
75#define SSP_CR1(r) (r + 0x004)
76#define SSP_DR(r) (r + 0x008)
77#define SSP_SR(r) (r + 0x00C)
78#define SSP_CPSR(r) (r + 0x010)
79#define SSP_IMSC(r) (r + 0x014)
80#define SSP_RIS(r) (r + 0x018)
81#define SSP_MIS(r) (r + 0x01C)
82#define SSP_ICR(r) (r + 0x020)
83#define SSP_DMACR(r) (r + 0x024)
84#define SSP_ITCR(r) (r + 0x080)
85#define SSP_ITIP(r) (r + 0x084)
86#define SSP_ITOP(r) (r + 0x088)
87#define SSP_TDR(r) (r + 0x08C)
88
89#define SSP_PID0(r) (r + 0xFE0)
90#define SSP_PID1(r) (r + 0xFE4)
91#define SSP_PID2(r) (r + 0xFE8)
92#define SSP_PID3(r) (r + 0xFEC)
93
94#define SSP_CID0(r) (r + 0xFF0)
95#define SSP_CID1(r) (r + 0xFF4)
96#define SSP_CID2(r) (r + 0xFF8)
97#define SSP_CID3(r) (r + 0xFFC)
98
99/*
100 * SSP Control Register 0 - SSP_CR0
101 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000102#define SSP_CR0_MASK_DSS (0x0FUL << 0)
103#define SSP_CR0_MASK_FRF (0x3UL << 4)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100104#define SSP_CR0_MASK_SPO (0x1UL << 6)
105#define SSP_CR0_MASK_SPH (0x1UL << 7)
106#define SSP_CR0_MASK_SCR (0xFFUL << 8)
Linus Walleij556f4ae2010-05-05 09:28:15 +0000107
108/*
109 * The ST version of this block moves som bits
110 * in SSP_CR0 and extends it to 32 bits
111 */
112#define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
113#define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
114#define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
115#define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
116
Linus Walleijb43d65f2009-06-09 08:11:42 +0100117
118/*
119 * SSP Control Register 0 - SSP_CR1
120 */
121#define SSP_CR1_MASK_LBM (0x1UL << 0)
122#define SSP_CR1_MASK_SSE (0x1UL << 1)
123#define SSP_CR1_MASK_MS (0x1UL << 2)
124#define SSP_CR1_MASK_SOD (0x1UL << 3)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100125
126/*
Linus Walleij556f4ae2010-05-05 09:28:15 +0000127 * The ST version of this block adds some bits
128 * in SSP_CR1
Linus Walleijb43d65f2009-06-09 08:11:42 +0100129 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000130#define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
131#define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
132#define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
133#define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
134#define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
Linus Walleij781c7b12010-05-07 08:40:53 +0000135/* This one is only in the PL023 variant */
136#define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100137
138/*
139 * SSP Status Register - SSP_SR
140 */
141#define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
142#define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
143#define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000144#define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
Linus Walleijb43d65f2009-06-09 08:11:42 +0100145#define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
146
147/*
148 * SSP Clock Prescale Register - SSP_CPSR
149 */
150#define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
151
152/*
153 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
154 */
155#define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
156#define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
157#define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
158#define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
159
160/*
161 * SSP Raw Interrupt Status Register - SSP_RIS
162 */
163/* Receive Overrun Raw Interrupt status */
164#define SSP_RIS_MASK_RORRIS (0x1UL << 0)
165/* Receive Timeout Raw Interrupt status */
166#define SSP_RIS_MASK_RTRIS (0x1UL << 1)
167/* Receive FIFO Raw Interrupt status */
168#define SSP_RIS_MASK_RXRIS (0x1UL << 2)
169/* Transmit FIFO Raw Interrupt status */
170#define SSP_RIS_MASK_TXRIS (0x1UL << 3)
171
172/*
173 * SSP Masked Interrupt Status Register - SSP_MIS
174 */
175/* Receive Overrun Masked Interrupt status */
176#define SSP_MIS_MASK_RORMIS (0x1UL << 0)
177/* Receive Timeout Masked Interrupt status */
178#define SSP_MIS_MASK_RTMIS (0x1UL << 1)
179/* Receive FIFO Masked Interrupt status */
180#define SSP_MIS_MASK_RXMIS (0x1UL << 2)
181/* Transmit FIFO Masked Interrupt status */
182#define SSP_MIS_MASK_TXMIS (0x1UL << 3)
183
184/*
185 * SSP Interrupt Clear Register - SSP_ICR
186 */
187/* Receive Overrun Raw Clear Interrupt bit */
188#define SSP_ICR_MASK_RORIC (0x1UL << 0)
189/* Receive Timeout Clear Interrupt bit */
190#define SSP_ICR_MASK_RTIC (0x1UL << 1)
191
192/*
193 * SSP DMA Control Register - SSP_DMACR
194 */
195/* Receive DMA Enable bit */
196#define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
197/* Transmit DMA Enable bit */
198#define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
199
200/*
201 * SSP Integration Test control Register - SSP_ITCR
202 */
203#define SSP_ITCR_MASK_ITEN (0x1UL << 0)
204#define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
205
206/*
207 * SSP Integration Test Input Register - SSP_ITIP
208 */
209#define ITIP_MASK_SSPRXD (0x1UL << 0)
210#define ITIP_MASK_SSPFSSIN (0x1UL << 1)
211#define ITIP_MASK_SSPCLKIN (0x1UL << 2)
212#define ITIP_MASK_RXDMAC (0x1UL << 3)
213#define ITIP_MASK_TXDMAC (0x1UL << 4)
214#define ITIP_MASK_SSPTXDIN (0x1UL << 5)
215
216/*
217 * SSP Integration Test output Register - SSP_ITOP
218 */
219#define ITOP_MASK_SSPTXD (0x1UL << 0)
220#define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
221#define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
222#define ITOP_MASK_SSPOEn (0x1UL << 3)
223#define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
224#define ITOP_MASK_RORINTR (0x1UL << 5)
225#define ITOP_MASK_RTINTR (0x1UL << 6)
226#define ITOP_MASK_RXINTR (0x1UL << 7)
227#define ITOP_MASK_TXINTR (0x1UL << 8)
228#define ITOP_MASK_INTR (0x1UL << 9)
229#define ITOP_MASK_RXDMABREQ (0x1UL << 10)
230#define ITOP_MASK_RXDMASREQ (0x1UL << 11)
231#define ITOP_MASK_TXDMABREQ (0x1UL << 12)
232#define ITOP_MASK_TXDMASREQ (0x1UL << 13)
233
234/*
235 * SSP Test Data Register - SSP_TDR
236 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000237#define TDR_MASK_TESTDATA (0xFFFFFFFF)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100238
239/*
240 * Message State
241 * we use the spi_message.state (void *) pointer to
242 * hold a single state value, that's why all this
243 * (void *) casting is done here.
244 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000245#define STATE_START ((void *) 0)
246#define STATE_RUNNING ((void *) 1)
247#define STATE_DONE ((void *) 2)
248#define STATE_ERROR ((void *) -1)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100249
250/*
Linus Walleijb43d65f2009-06-09 08:11:42 +0100251 * SSP State - Whether Enabled or Disabled
252 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000253#define SSP_DISABLED (0)
254#define SSP_ENABLED (1)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100255
256/*
257 * SSP DMA State - Whether DMA Enabled or Disabled
258 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000259#define SSP_DMA_DISABLED (0)
260#define SSP_DMA_ENABLED (1)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100261
262/*
263 * SSP Clock Defaults
264 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000265#define SSP_DEFAULT_CLKRATE 0x2
266#define SSP_DEFAULT_PRESCALE 0x40
Linus Walleijb43d65f2009-06-09 08:11:42 +0100267
268/*
269 * SSP Clock Parameter ranges
270 */
271#define CPSDVR_MIN 0x02
272#define CPSDVR_MAX 0xFE
273#define SCR_MIN 0x00
274#define SCR_MAX 0xFF
275
276/*
277 * SSP Interrupt related Macros
278 */
279#define DEFAULT_SSP_REG_IMSC 0x0UL
280#define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
281#define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)
282
283#define CLEAR_ALL_INTERRUPTS 0x3
284
Magnus Templinga18c2662011-05-19 18:05:34 +0200285#define SPI_POLLING_TIMEOUT 1000
286
Linus Walleijb43d65f2009-06-09 08:11:42 +0100287
288/*
289 * The type of reading going on on this chip
290 */
291enum ssp_reading {
292 READING_NULL,
293 READING_U8,
294 READING_U16,
295 READING_U32
296};
297
298/**
299 * The type of writing going on on this chip
300 */
301enum ssp_writing {
302 WRITING_NULL,
303 WRITING_U8,
304 WRITING_U16,
305 WRITING_U32
306};
307
308/**
309 * struct vendor_data - vendor-specific config parameters
310 * for PL022 derivates
311 * @fifodepth: depth of FIFOs (both)
312 * @max_bpw: maximum number of bits per word
313 * @unidir: supports unidirection transfers
Linus Walleij556f4ae2010-05-05 09:28:15 +0000314 * @extended_cr: 32 bit wide control register 0 with extra
315 * features and extra features in CR1 as found in the ST variants
Linus Walleij781c7b12010-05-07 08:40:53 +0000316 * @pl023: supports a subset of the ST extensions called "PL023"
Linus Walleijb43d65f2009-06-09 08:11:42 +0100317 */
318struct vendor_data {
319 int fifodepth;
320 int max_bpw;
321 bool unidir;
Linus Walleij556f4ae2010-05-05 09:28:15 +0000322 bool extended_cr;
Linus Walleij781c7b12010-05-07 08:40:53 +0000323 bool pl023;
Philippe Langlais06fb01f2011-03-23 11:05:16 +0100324 bool loopback;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100325};
326
327/**
328 * struct pl022 - This is the private SSP driver data structure
329 * @adev: AMBA device model hookup
Linus Walleij12e8b322011-02-08 13:03:55 +0100330 * @vendor: vendor data for the IP block
331 * @phybase: the physical memory where the SSP device resides
332 * @virtbase: the virtual memory where the SSP is mapped
333 * @clk: outgoing clock "SPICLK" for the SPI bus
Linus Walleijb43d65f2009-06-09 08:11:42 +0100334 * @master: SPI framework hookup
335 * @master_info: controller-specific data from machine setup
Linus Walleijb43d65f2009-06-09 08:11:42 +0100336 * @workqueue: a workqueue on which any spi_message request is queued
Linus Walleij12e8b322011-02-08 13:03:55 +0100337 * @pump_messages: work struct for scheduling work to the workqueue
338 * @queue_lock: spinlock to syncronise access to message queue
339 * @queue: message queue
Linus Walleijb43d65f2009-06-09 08:11:42 +0100340 * @busy: workqueue is busy
Linus Walleij5e8b8212010-12-22 23:13:59 +0100341 * @running: workqueue is running
Linus Walleijb43d65f2009-06-09 08:11:42 +0100342 * @pump_transfers: Tasklet used in Interrupt Transfer mode
343 * @cur_msg: Pointer to current spi_message being processed
344 * @cur_transfer: Pointer to current spi_transfer
345 * @cur_chip: pointer to current clients chip(assigned from controller_state)
346 * @tx: current position in TX buffer to be read
347 * @tx_end: end position in TX buffer to be read
348 * @rx: current position in RX buffer to be written
349 * @rx_end: end position in RX buffer to be written
Linus Walleij12e8b322011-02-08 13:03:55 +0100350 * @read: the type of read currently going on
351 * @write: the type of write currently going on
352 * @exp_fifo_level: expected FIFO level
353 * @dma_rx_channel: optional channel for RX DMA
354 * @dma_tx_channel: optional channel for TX DMA
355 * @sgt_rx: scattertable for the RX transfer
356 * @sgt_tx: scattertable for the TX transfer
357 * @dummypage: a dummy page used for driving data on the bus with DMA
Linus Walleijb43d65f2009-06-09 08:11:42 +0100358 */
359struct pl022 {
360 struct amba_device *adev;
361 struct vendor_data *vendor;
362 resource_size_t phybase;
363 void __iomem *virtbase;
364 struct clk *clk;
365 struct spi_master *master;
366 struct pl022_ssp_controller *master_info;
367 /* Driver message queue */
368 struct workqueue_struct *workqueue;
369 struct work_struct pump_messages;
370 spinlock_t queue_lock;
371 struct list_head queue;
Linus Walleijdec5a582010-12-22 23:13:48 +0100372 bool busy;
Linus Walleij5e8b8212010-12-22 23:13:59 +0100373 bool running;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100374 /* Message transfer pump */
375 struct tasklet_struct pump_transfers;
376 struct spi_message *cur_msg;
377 struct spi_transfer *cur_transfer;
378 struct chip_data *cur_chip;
379 void *tx;
380 void *tx_end;
381 void *rx;
382 void *rx_end;
383 enum ssp_reading read;
384 enum ssp_writing write;
Linus Walleijfc054752010-01-22 13:53:30 +0100385 u32 exp_fifo_level;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900386 /* DMA settings */
387#ifdef CONFIG_DMA_ENGINE
388 struct dma_chan *dma_rx_channel;
389 struct dma_chan *dma_tx_channel;
390 struct sg_table sgt_rx;
391 struct sg_table sgt_tx;
392 char *dummypage;
393#endif
Linus Walleijb43d65f2009-06-09 08:11:42 +0100394};
395
396/**
397 * struct chip_data - To maintain runtime state of SSP for each client chip
Linus Walleij556f4ae2010-05-05 09:28:15 +0000398 * @cr0: Value of control register CR0 of SSP - on later ST variants this
399 * register is 32 bits wide rather than just 16
Linus Walleijb43d65f2009-06-09 08:11:42 +0100400 * @cr1: Value of control register CR1 of SSP
401 * @dmacr: Value of DMA control Register of SSP
402 * @cpsr: Value of Clock prescale register
403 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
404 * @enable_dma: Whether to enable DMA or not
Linus Walleijb43d65f2009-06-09 08:11:42 +0100405 * @read: function ptr to be used to read when doing xfer for this chip
Linus Walleij12e8b322011-02-08 13:03:55 +0100406 * @write: function ptr to be used to write when doing xfer for this chip
Linus Walleijb43d65f2009-06-09 08:11:42 +0100407 * @cs_control: chip select callback provided by chip
408 * @xfer_type: polling/interrupt/DMA
409 *
410 * Runtime state of the SSP controller, maintained per chip,
411 * This would be set according to the current message that would be served
412 */
413struct chip_data {
Linus Walleij556f4ae2010-05-05 09:28:15 +0000414 u32 cr0;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100415 u16 cr1;
416 u16 dmacr;
417 u16 cpsr;
418 u8 n_bytes;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900419 bool enable_dma;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100420 enum ssp_reading read;
421 enum ssp_writing write;
422 void (*cs_control) (u32 command);
423 int xfer_type;
424};
425
426/**
427 * null_cs_control - Dummy chip select function
428 * @command: select/delect the chip
429 *
430 * If no chip select function is provided by client this is used as dummy
431 * chip select
432 */
433static void null_cs_control(u32 command)
434{
435 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
436}
437
438/**
439 * giveback - current spi_message is over, schedule next message and call
440 * callback of this message. Assumes that caller already
441 * set message->status; dma and pio irqs are blocked
442 * @pl022: SSP driver private data structure
443 */
444static void giveback(struct pl022 *pl022)
445{
446 struct spi_transfer *last_transfer;
447 unsigned long flags;
448 struct spi_message *msg;
449 void (*curr_cs_control) (u32 command);
450
451 /*
452 * This local reference to the chip select function
453 * is needed because we set curr_chip to NULL
454 * as a step toward termininating the message.
455 */
456 curr_cs_control = pl022->cur_chip->cs_control;
457 spin_lock_irqsave(&pl022->queue_lock, flags);
458 msg = pl022->cur_msg;
459 pl022->cur_msg = NULL;
460 pl022->cur_transfer = NULL;
461 pl022->cur_chip = NULL;
462 queue_work(pl022->workqueue, &pl022->pump_messages);
463 spin_unlock_irqrestore(&pl022->queue_lock, flags);
464
465 last_transfer = list_entry(msg->transfers.prev,
466 struct spi_transfer,
467 transfer_list);
468
469 /* Delay if requested before any change in chip select */
470 if (last_transfer->delay_usecs)
471 /*
472 * FIXME: This runs in interrupt context.
473 * Is this really smart?
474 */
475 udelay(last_transfer->delay_usecs);
476
477 /*
478 * Drop chip select UNLESS cs_change is true or we are returning
479 * a message with an error, or next message is for another chip
480 */
481 if (!last_transfer->cs_change)
482 curr_cs_control(SSP_CHIP_DESELECT);
483 else {
484 struct spi_message *next_msg;
485
486 /* Holding of cs was hinted, but we need to make sure
487 * the next message is for the same chip. Don't waste
488 * time with the following tests unless this was hinted.
489 *
490 * We cannot postpone this until pump_messages, because
491 * after calling msg->complete (below) the driver that
492 * sent the current message could be unloaded, which
493 * could invalidate the cs_control() callback...
494 */
495
496 /* get a pointer to the next message, if any */
497 spin_lock_irqsave(&pl022->queue_lock, flags);
498 if (list_empty(&pl022->queue))
499 next_msg = NULL;
500 else
501 next_msg = list_entry(pl022->queue.next,
502 struct spi_message, queue);
503 spin_unlock_irqrestore(&pl022->queue_lock, flags);
504
505 /* see if the next and current messages point
506 * to the same chip
507 */
508 if (next_msg && next_msg->spi != msg->spi)
509 next_msg = NULL;
510 if (!next_msg || msg->state == STATE_ERROR)
511 curr_cs_control(SSP_CHIP_DESELECT);
512 }
513 msg->state = NULL;
514 if (msg->complete)
515 msg->complete(msg->context);
Linus Walleij808f1032011-02-08 13:03:32 +0100516 /* This message is completed, so let's turn off the clocks & power */
Linus Walleijb43d65f2009-06-09 08:11:42 +0100517 clk_disable(pl022->clk);
Linus Walleij545074f2010-08-21 11:07:36 +0200518 amba_pclk_disable(pl022->adev);
Linus Walleij808f1032011-02-08 13:03:32 +0100519 amba_vcore_disable(pl022->adev);
Linus Walleijb43d65f2009-06-09 08:11:42 +0100520}
521
522/**
523 * flush - flush the FIFO to reach a clean state
524 * @pl022: SSP driver private data structure
525 */
526static int flush(struct pl022 *pl022)
527{
528 unsigned long limit = loops_per_jiffy << 1;
529
530 dev_dbg(&pl022->adev->dev, "flush\n");
531 do {
532 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
533 readw(SSP_DR(pl022->virtbase));
534 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
Linus Walleijfc054752010-01-22 13:53:30 +0100535
536 pl022->exp_fifo_level = 0;
537
Linus Walleijb43d65f2009-06-09 08:11:42 +0100538 return limit;
539}
540
541/**
542 * restore_state - Load configuration of current chip
543 * @pl022: SSP driver private data structure
544 */
545static void restore_state(struct pl022 *pl022)
546{
547 struct chip_data *chip = pl022->cur_chip;
548
Linus Walleij556f4ae2010-05-05 09:28:15 +0000549 if (pl022->vendor->extended_cr)
550 writel(chip->cr0, SSP_CR0(pl022->virtbase));
551 else
552 writew(chip->cr0, SSP_CR0(pl022->virtbase));
Linus Walleijb43d65f2009-06-09 08:11:42 +0100553 writew(chip->cr1, SSP_CR1(pl022->virtbase));
554 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
555 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
556 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
557 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
558}
559
Linus Walleijb43d65f2009-06-09 08:11:42 +0100560/*
561 * Default SSP Register Values
562 */
563#define DEFAULT_SSP_REG_CR0 ( \
564 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
Linus Walleij556f4ae2010-05-05 09:28:15 +0000565 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
Linus Walleijb43d65f2009-06-09 08:11:42 +0100566 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
Linus Walleijee2b8052009-08-15 15:12:05 +0100567 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
Linus Walleij556f4ae2010-05-05 09:28:15 +0000568 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
569)
570
571/* ST versions have slightly different bit layout */
572#define DEFAULT_SSP_REG_CR0_ST ( \
573 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
574 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
575 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
576 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
577 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
578 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
579 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
Linus Walleijb43d65f2009-06-09 08:11:42 +0100580)
581
Linus Walleij781c7b12010-05-07 08:40:53 +0000582/* The PL023 version is slightly different again */
583#define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
584 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
585 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
586 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
587 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
588)
589
Linus Walleijb43d65f2009-06-09 08:11:42 +0100590#define DEFAULT_SSP_REG_CR1 ( \
591 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
592 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
593 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
Linus Walleij556f4ae2010-05-05 09:28:15 +0000594 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
Linus Walleijb43d65f2009-06-09 08:11:42 +0100595)
596
Linus Walleij556f4ae2010-05-05 09:28:15 +0000597/* ST versions extend this register to use all 16 bits */
598#define DEFAULT_SSP_REG_CR1_ST ( \
599 DEFAULT_SSP_REG_CR1 | \
600 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
601 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
602 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
603 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
604 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
605)
606
Linus Walleij781c7b12010-05-07 08:40:53 +0000607/*
608 * The PL023 variant has further differences: no loopback mode, no microwire
609 * support, and a new clock feedback delay setting.
610 */
611#define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
612 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
613 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
614 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
615 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
616 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
617 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
618 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
619 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
620)
Linus Walleij556f4ae2010-05-05 09:28:15 +0000621
Linus Walleijb43d65f2009-06-09 08:11:42 +0100622#define DEFAULT_SSP_REG_CPSR ( \
Linus Walleij556f4ae2010-05-05 09:28:15 +0000623 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
Linus Walleijb43d65f2009-06-09 08:11:42 +0100624)
625
626#define DEFAULT_SSP_REG_DMACR (\
627 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
628 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
629)
630
Linus Walleij781c7b12010-05-07 08:40:53 +0000631/**
632 * load_ssp_default_config - Load default configuration for SSP
633 * @pl022: SSP driver private data structure
634 */
Linus Walleijb43d65f2009-06-09 08:11:42 +0100635static void load_ssp_default_config(struct pl022 *pl022)
636{
Linus Walleij781c7b12010-05-07 08:40:53 +0000637 if (pl022->vendor->pl023) {
638 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
639 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
640 } else if (pl022->vendor->extended_cr) {
Linus Walleij556f4ae2010-05-05 09:28:15 +0000641 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
642 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
643 } else {
644 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
645 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
646 }
Linus Walleijb43d65f2009-06-09 08:11:42 +0100647 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
648 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
649 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
650 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
651}
652
653/**
654 * This will write to TX and read from RX according to the parameters
655 * set in pl022.
656 */
657static void readwriter(struct pl022 *pl022)
658{
659
660 /*
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300661 * The FIFO depth is different between primecell variants.
Linus Walleijb43d65f2009-06-09 08:11:42 +0100662 * I believe filling in too much in the FIFO might cause
663 * errons in 8bit wide transfers on ARM variants (just 8 words
664 * FIFO, means only 8x8 = 64 bits in FIFO) at least.
665 *
Linus Walleijfc054752010-01-22 13:53:30 +0100666 * To prevent this issue, the TX FIFO is only filled to the
667 * unused RX FIFO fill length, regardless of what the TX
668 * FIFO status flag indicates.
Linus Walleijb43d65f2009-06-09 08:11:42 +0100669 */
670 dev_dbg(&pl022->adev->dev,
671 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
672 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
673
674 /* Read as much as you can */
675 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
676 && (pl022->rx < pl022->rx_end)) {
677 switch (pl022->read) {
678 case READING_NULL:
679 readw(SSP_DR(pl022->virtbase));
680 break;
681 case READING_U8:
682 *(u8 *) (pl022->rx) =
683 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
684 break;
685 case READING_U16:
686 *(u16 *) (pl022->rx) =
687 (u16) readw(SSP_DR(pl022->virtbase));
688 break;
689 case READING_U32:
690 *(u32 *) (pl022->rx) =
691 readl(SSP_DR(pl022->virtbase));
692 break;
693 }
694 pl022->rx += (pl022->cur_chip->n_bytes);
Linus Walleijfc054752010-01-22 13:53:30 +0100695 pl022->exp_fifo_level--;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100696 }
697 /*
Linus Walleijfc054752010-01-22 13:53:30 +0100698 * Write as much as possible up to the RX FIFO size
Linus Walleijb43d65f2009-06-09 08:11:42 +0100699 */
Linus Walleijfc054752010-01-22 13:53:30 +0100700 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100701 && (pl022->tx < pl022->tx_end)) {
702 switch (pl022->write) {
703 case WRITING_NULL:
704 writew(0x0, SSP_DR(pl022->virtbase));
705 break;
706 case WRITING_U8:
707 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
708 break;
709 case WRITING_U16:
710 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
711 break;
712 case WRITING_U32:
713 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
714 break;
715 }
716 pl022->tx += (pl022->cur_chip->n_bytes);
Linus Walleijfc054752010-01-22 13:53:30 +0100717 pl022->exp_fifo_level++;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100718 /*
719 * This inner reader takes care of things appearing in the RX
720 * FIFO as we're transmitting. This will happen a lot since the
721 * clock starts running when you put things into the TX FIFO,
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300722 * and then things are continuously clocked into the RX FIFO.
Linus Walleijb43d65f2009-06-09 08:11:42 +0100723 */
724 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
725 && (pl022->rx < pl022->rx_end)) {
726 switch (pl022->read) {
727 case READING_NULL:
728 readw(SSP_DR(pl022->virtbase));
729 break;
730 case READING_U8:
731 *(u8 *) (pl022->rx) =
732 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
733 break;
734 case READING_U16:
735 *(u16 *) (pl022->rx) =
736 (u16) readw(SSP_DR(pl022->virtbase));
737 break;
738 case READING_U32:
739 *(u32 *) (pl022->rx) =
740 readl(SSP_DR(pl022->virtbase));
741 break;
742 }
743 pl022->rx += (pl022->cur_chip->n_bytes);
Linus Walleijfc054752010-01-22 13:53:30 +0100744 pl022->exp_fifo_level--;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100745 }
746 }
747 /*
748 * When we exit here the TX FIFO should be full and the RX FIFO
749 * should be empty
750 */
751}
752
753
754/**
755 * next_transfer - Move to the Next transfer in the current spi message
756 * @pl022: SSP driver private data structure
757 *
758 * This function moves though the linked list of spi transfers in the
759 * current spi message and returns with the state of current spi
760 * message i.e whether its last transfer is done(STATE_DONE) or
761 * Next transfer is ready(STATE_RUNNING)
762 */
763static void *next_transfer(struct pl022 *pl022)
764{
765 struct spi_message *msg = pl022->cur_msg;
766 struct spi_transfer *trans = pl022->cur_transfer;
767
768 /* Move to next transfer */
769 if (trans->transfer_list.next != &msg->transfers) {
770 pl022->cur_transfer =
771 list_entry(trans->transfer_list.next,
772 struct spi_transfer, transfer_list);
773 return STATE_RUNNING;
774 }
775 return STATE_DONE;
776}
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900777
778/*
779 * This DMA functionality is only compiled in if we have
780 * access to the generic DMA devices/DMA engine.
781 */
782#ifdef CONFIG_DMA_ENGINE
783static void unmap_free_dma_scatter(struct pl022 *pl022)
784{
785 /* Unmap and free the SG tables */
Linus Walleijb7298892010-12-22 23:13:07 +0100786 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900787 pl022->sgt_tx.nents, DMA_TO_DEVICE);
Linus Walleijb7298892010-12-22 23:13:07 +0100788 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900789 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
790 sg_free_table(&pl022->sgt_rx);
791 sg_free_table(&pl022->sgt_tx);
792}
793
794static void dma_callback(void *data)
795{
796 struct pl022 *pl022 = data;
797 struct spi_message *msg = pl022->cur_msg;
798
799 BUG_ON(!pl022->sgt_rx.sgl);
800
801#ifdef VERBOSE_DEBUG
802 /*
803 * Optionally dump out buffers to inspect contents, this is
804 * good if you want to convince yourself that the loopback
805 * read/write contents are the same, when adopting to a new
806 * DMA engine.
807 */
808 {
809 struct scatterlist *sg;
810 unsigned int i;
811
812 dma_sync_sg_for_cpu(&pl022->adev->dev,
813 pl022->sgt_rx.sgl,
814 pl022->sgt_rx.nents,
815 DMA_FROM_DEVICE);
816
817 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
818 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
819 print_hex_dump(KERN_ERR, "SPI RX: ",
820 DUMP_PREFIX_OFFSET,
821 16,
822 1,
823 sg_virt(sg),
824 sg_dma_len(sg),
825 1);
826 }
827 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
828 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
829 print_hex_dump(KERN_ERR, "SPI TX: ",
830 DUMP_PREFIX_OFFSET,
831 16,
832 1,
833 sg_virt(sg),
834 sg_dma_len(sg),
835 1);
836 }
837 }
838#endif
839
840 unmap_free_dma_scatter(pl022);
841
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300842 /* Update total bytes transferred */
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900843 msg->actual_length += pl022->cur_transfer->len;
844 if (pl022->cur_transfer->cs_change)
845 pl022->cur_chip->
846 cs_control(SSP_CHIP_DESELECT);
847
848 /* Move to next transfer */
849 msg->state = next_transfer(pl022);
850 tasklet_schedule(&pl022->pump_transfers);
851}
852
853static void setup_dma_scatter(struct pl022 *pl022,
854 void *buffer,
855 unsigned int length,
856 struct sg_table *sgtab)
857{
858 struct scatterlist *sg;
859 int bytesleft = length;
860 void *bufp = buffer;
861 int mapbytes;
862 int i;
863
864 if (buffer) {
865 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
866 /*
867 * If there are less bytes left than what fits
868 * in the current page (plus page alignment offset)
869 * we just feed in this, else we stuff in as much
870 * as we can.
871 */
872 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
873 mapbytes = bytesleft;
874 else
875 mapbytes = PAGE_SIZE - offset_in_page(bufp);
876 sg_set_page(sg, virt_to_page(bufp),
877 mapbytes, offset_in_page(bufp));
878 bufp += mapbytes;
879 bytesleft -= mapbytes;
880 dev_dbg(&pl022->adev->dev,
881 "set RX/TX target page @ %p, %d bytes, %d left\n",
882 bufp, mapbytes, bytesleft);
883 }
884 } else {
885 /* Map the dummy buffer on every page */
886 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
887 if (bytesleft < PAGE_SIZE)
888 mapbytes = bytesleft;
889 else
890 mapbytes = PAGE_SIZE;
891 sg_set_page(sg, virt_to_page(pl022->dummypage),
892 mapbytes, 0);
893 bytesleft -= mapbytes;
894 dev_dbg(&pl022->adev->dev,
895 "set RX/TX to dummy page %d bytes, %d left\n",
896 mapbytes, bytesleft);
897
898 }
899 }
900 BUG_ON(bytesleft);
901}
902
903/**
904 * configure_dma - configures the channels for the next transfer
905 * @pl022: SSP driver's private data structure
906 */
907static int configure_dma(struct pl022 *pl022)
908{
909 struct dma_slave_config rx_conf = {
910 .src_addr = SSP_DR(pl022->phybase),
911 .direction = DMA_FROM_DEVICE,
912 .src_maxburst = pl022->vendor->fifodepth >> 1,
913 };
914 struct dma_slave_config tx_conf = {
915 .dst_addr = SSP_DR(pl022->phybase),
916 .direction = DMA_TO_DEVICE,
917 .dst_maxburst = pl022->vendor->fifodepth >> 1,
918 };
919 unsigned int pages;
920 int ret;
Linus Walleij082086f2010-12-22 23:13:37 +0100921 int rx_sglen, tx_sglen;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900922 struct dma_chan *rxchan = pl022->dma_rx_channel;
923 struct dma_chan *txchan = pl022->dma_tx_channel;
924 struct dma_async_tx_descriptor *rxdesc;
925 struct dma_async_tx_descriptor *txdesc;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900926
927 /* Check that the channels are available */
928 if (!rxchan || !txchan)
929 return -ENODEV;
930
931 switch (pl022->read) {
932 case READING_NULL:
933 /* Use the same as for writing */
934 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
935 break;
936 case READING_U8:
937 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
938 break;
939 case READING_U16:
940 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
941 break;
942 case READING_U32:
943 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
944 break;
945 }
946
947 switch (pl022->write) {
948 case WRITING_NULL:
949 /* Use the same as for reading */
950 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
951 break;
952 case WRITING_U8:
953 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
954 break;
955 case WRITING_U16:
956 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
957 break;
958 case WRITING_U32:
Joe Perchesbc3f67a2010-11-14 19:04:47 -0800959 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900960 break;
961 }
962
963 /* SPI pecularity: we need to read and write the same width */
964 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
965 rx_conf.src_addr_width = tx_conf.dst_addr_width;
966 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
967 tx_conf.dst_addr_width = rx_conf.src_addr_width;
968 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
969
Linus Walleijecd442f2011-02-08 13:03:12 +0100970 dmaengine_slave_config(rxchan, &rx_conf);
971 dmaengine_slave_config(txchan, &tx_conf);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900972
973 /* Create sglists for the transfers */
974 pages = (pl022->cur_transfer->len >> PAGE_SHIFT) + 1;
975 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
976
977 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_KERNEL);
978 if (ret)
979 goto err_alloc_rx_sg;
980
981 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_KERNEL);
982 if (ret)
983 goto err_alloc_tx_sg;
984
985 /* Fill in the scatterlists for the RX+TX buffers */
986 setup_dma_scatter(pl022, pl022->rx,
987 pl022->cur_transfer->len, &pl022->sgt_rx);
988 setup_dma_scatter(pl022, pl022->tx,
989 pl022->cur_transfer->len, &pl022->sgt_tx);
990
991 /* Map DMA buffers */
Linus Walleij082086f2010-12-22 23:13:37 +0100992 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900993 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
Linus Walleij082086f2010-12-22 23:13:37 +0100994 if (!rx_sglen)
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900995 goto err_rx_sgmap;
996
Linus Walleij082086f2010-12-22 23:13:37 +0100997 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900998 pl022->sgt_tx.nents, DMA_TO_DEVICE);
Linus Walleij082086f2010-12-22 23:13:37 +0100999 if (!tx_sglen)
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001000 goto err_tx_sgmap;
1001
1002 /* Send both scatterlists */
1003 rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
1004 pl022->sgt_rx.sgl,
Linus Walleij082086f2010-12-22 23:13:37 +01001005 rx_sglen,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001006 DMA_FROM_DEVICE,
1007 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1008 if (!rxdesc)
1009 goto err_rxdesc;
1010
1011 txdesc = txchan->device->device_prep_slave_sg(txchan,
1012 pl022->sgt_tx.sgl,
Linus Walleij082086f2010-12-22 23:13:37 +01001013 tx_sglen,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001014 DMA_TO_DEVICE,
1015 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1016 if (!txdesc)
1017 goto err_txdesc;
1018
1019 /* Put the callback on the RX transfer only, that should finish last */
1020 rxdesc->callback = dma_callback;
1021 rxdesc->callback_param = pl022;
1022
1023 /* Submit and fire RX and TX with TX last so we're ready to read! */
Linus Walleijecd442f2011-02-08 13:03:12 +01001024 dmaengine_submit(rxdesc);
1025 dmaengine_submit(txdesc);
1026 dma_async_issue_pending(rxchan);
1027 dma_async_issue_pending(txchan);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001028
1029 return 0;
1030
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001031err_txdesc:
Linus Walleijecd442f2011-02-08 13:03:12 +01001032 dmaengine_terminate_all(txchan);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001033err_rxdesc:
Linus Walleijecd442f2011-02-08 13:03:12 +01001034 dmaengine_terminate_all(rxchan);
Linus Walleijb7298892010-12-22 23:13:07 +01001035 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001036 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1037err_tx_sgmap:
Linus Walleijb7298892010-12-22 23:13:07 +01001038 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001039 pl022->sgt_tx.nents, DMA_FROM_DEVICE);
1040err_rx_sgmap:
1041 sg_free_table(&pl022->sgt_tx);
1042err_alloc_tx_sg:
1043 sg_free_table(&pl022->sgt_rx);
1044err_alloc_rx_sg:
1045 return -ENOMEM;
1046}
1047
1048static int __init pl022_dma_probe(struct pl022 *pl022)
1049{
1050 dma_cap_mask_t mask;
1051
1052 /* Try to acquire a generic DMA engine slave channel */
1053 dma_cap_zero(mask);
1054 dma_cap_set(DMA_SLAVE, mask);
1055 /*
1056 * We need both RX and TX channels to do DMA, else do none
1057 * of them.
1058 */
1059 pl022->dma_rx_channel = dma_request_channel(mask,
1060 pl022->master_info->dma_filter,
1061 pl022->master_info->dma_rx_param);
1062 if (!pl022->dma_rx_channel) {
Viresh Kumar43c64012011-05-16 09:40:10 +05301063 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001064 goto err_no_rxchan;
1065 }
1066
1067 pl022->dma_tx_channel = dma_request_channel(mask,
1068 pl022->master_info->dma_filter,
1069 pl022->master_info->dma_tx_param);
1070 if (!pl022->dma_tx_channel) {
Viresh Kumar43c64012011-05-16 09:40:10 +05301071 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001072 goto err_no_txchan;
1073 }
1074
1075 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1076 if (!pl022->dummypage) {
Viresh Kumar43c64012011-05-16 09:40:10 +05301077 dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n");
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001078 goto err_no_dummypage;
1079 }
1080
1081 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
1082 dma_chan_name(pl022->dma_rx_channel),
1083 dma_chan_name(pl022->dma_tx_channel));
1084
1085 return 0;
1086
1087err_no_dummypage:
1088 dma_release_channel(pl022->dma_tx_channel);
1089err_no_txchan:
1090 dma_release_channel(pl022->dma_rx_channel);
1091 pl022->dma_rx_channel = NULL;
1092err_no_rxchan:
Viresh Kumar43c64012011-05-16 09:40:10 +05301093 dev_err(&pl022->adev->dev,
1094 "Failed to work in dma mode, work without dma!\n");
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001095 return -ENODEV;
1096}
1097
1098static void terminate_dma(struct pl022 *pl022)
1099{
1100 struct dma_chan *rxchan = pl022->dma_rx_channel;
1101 struct dma_chan *txchan = pl022->dma_tx_channel;
1102
Linus Walleijecd442f2011-02-08 13:03:12 +01001103 dmaengine_terminate_all(rxchan);
1104 dmaengine_terminate_all(txchan);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001105 unmap_free_dma_scatter(pl022);
1106}
1107
1108static void pl022_dma_remove(struct pl022 *pl022)
1109{
1110 if (pl022->busy)
1111 terminate_dma(pl022);
1112 if (pl022->dma_tx_channel)
1113 dma_release_channel(pl022->dma_tx_channel);
1114 if (pl022->dma_rx_channel)
1115 dma_release_channel(pl022->dma_rx_channel);
1116 kfree(pl022->dummypage);
1117}
1118
1119#else
1120static inline int configure_dma(struct pl022 *pl022)
1121{
1122 return -ENODEV;
1123}
1124
1125static inline int pl022_dma_probe(struct pl022 *pl022)
1126{
1127 return 0;
1128}
1129
1130static inline void pl022_dma_remove(struct pl022 *pl022)
1131{
1132}
1133#endif
1134
Linus Walleijb43d65f2009-06-09 08:11:42 +01001135/**
1136 * pl022_interrupt_handler - Interrupt handler for SSP controller
1137 *
1138 * This function handles interrupts generated for an interrupt based transfer.
1139 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
1140 * current message's state as STATE_ERROR and schedule the tasklet
1141 * pump_transfers which will do the postprocessing of the current message by
1142 * calling giveback(). Otherwise it reads data from RX FIFO till there is no
1143 * more data, and writes data in TX FIFO till it is not full. If we complete
1144 * the transfer we move to the next transfer and schedule the tasklet.
1145 */
1146static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1147{
1148 struct pl022 *pl022 = dev_id;
1149 struct spi_message *msg = pl022->cur_msg;
1150 u16 irq_status = 0;
1151 u16 flag = 0;
1152
1153 if (unlikely(!msg)) {
1154 dev_err(&pl022->adev->dev,
1155 "bad message state in interrupt handler");
1156 /* Never fail */
1157 return IRQ_HANDLED;
1158 }
1159
1160 /* Read the Interrupt Status Register */
1161 irq_status = readw(SSP_MIS(pl022->virtbase));
1162
1163 if (unlikely(!irq_status))
1164 return IRQ_NONE;
1165
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001166 /*
1167 * This handles the FIFO interrupts, the timeout
1168 * interrupts are flatly ignored, they cannot be
1169 * trusted.
1170 */
Linus Walleijb43d65f2009-06-09 08:11:42 +01001171 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
1172 /*
1173 * Overrun interrupt - bail out since our Data has been
1174 * corrupted
1175 */
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001176 dev_err(&pl022->adev->dev, "FIFO overrun\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001177 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1178 dev_err(&pl022->adev->dev,
1179 "RXFIFO is full\n");
1180 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF)
1181 dev_err(&pl022->adev->dev,
1182 "TXFIFO is full\n");
1183
1184 /*
1185 * Disable and clear interrupts, disable SSP,
1186 * mark message with bad status so it can be
1187 * retried.
1188 */
1189 writew(DISABLE_ALL_INTERRUPTS,
1190 SSP_IMSC(pl022->virtbase));
1191 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1192 writew((readw(SSP_CR1(pl022->virtbase)) &
1193 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1194 msg->state = STATE_ERROR;
1195
1196 /* Schedule message queue handler */
1197 tasklet_schedule(&pl022->pump_transfers);
1198 return IRQ_HANDLED;
1199 }
1200
1201 readwriter(pl022);
1202
1203 if ((pl022->tx == pl022->tx_end) && (flag == 0)) {
1204 flag = 1;
1205 /* Disable Transmit interrupt */
1206 writew(readw(SSP_IMSC(pl022->virtbase)) &
1207 (~SSP_IMSC_MASK_TXIM),
1208 SSP_IMSC(pl022->virtbase));
1209 }
1210
1211 /*
1212 * Since all transactions must write as much as shall be read,
1213 * we can conclude the entire transaction once RX is complete.
1214 * At this point, all TX will always be finished.
1215 */
1216 if (pl022->rx >= pl022->rx_end) {
1217 writew(DISABLE_ALL_INTERRUPTS,
1218 SSP_IMSC(pl022->virtbase));
1219 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1220 if (unlikely(pl022->rx > pl022->rx_end)) {
1221 dev_warn(&pl022->adev->dev, "read %u surplus "
1222 "bytes (did you request an odd "
1223 "number of bytes on a 16bit bus?)\n",
1224 (u32) (pl022->rx - pl022->rx_end));
1225 }
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001226 /* Update total bytes transferred */
Linus Walleijb43d65f2009-06-09 08:11:42 +01001227 msg->actual_length += pl022->cur_transfer->len;
1228 if (pl022->cur_transfer->cs_change)
1229 pl022->cur_chip->
1230 cs_control(SSP_CHIP_DESELECT);
1231 /* Move to next transfer */
1232 msg->state = next_transfer(pl022);
1233 tasklet_schedule(&pl022->pump_transfers);
1234 return IRQ_HANDLED;
1235 }
1236
1237 return IRQ_HANDLED;
1238}
1239
1240/**
1241 * This sets up the pointers to memory for the next message to
1242 * send out on the SPI bus.
1243 */
1244static int set_up_next_transfer(struct pl022 *pl022,
1245 struct spi_transfer *transfer)
1246{
1247 int residue;
1248
1249 /* Sanity check the message for this bus width */
1250 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
1251 if (unlikely(residue != 0)) {
1252 dev_err(&pl022->adev->dev,
1253 "message of %u bytes to transmit but the current "
1254 "chip bus has a data width of %u bytes!\n",
1255 pl022->cur_transfer->len,
1256 pl022->cur_chip->n_bytes);
1257 dev_err(&pl022->adev->dev, "skipping this message\n");
1258 return -EIO;
1259 }
1260 pl022->tx = (void *)transfer->tx_buf;
1261 pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
1262 pl022->rx = (void *)transfer->rx_buf;
1263 pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
1264 pl022->write =
1265 pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
1266 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
1267 return 0;
1268}
1269
1270/**
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001271 * pump_transfers - Tasklet function which schedules next transfer
1272 * when running in interrupt or DMA transfer mode.
Linus Walleijb43d65f2009-06-09 08:11:42 +01001273 * @data: SSP driver private data structure
1274 *
1275 */
1276static void pump_transfers(unsigned long data)
1277{
1278 struct pl022 *pl022 = (struct pl022 *) data;
1279 struct spi_message *message = NULL;
1280 struct spi_transfer *transfer = NULL;
1281 struct spi_transfer *previous = NULL;
1282
1283 /* Get current state information */
1284 message = pl022->cur_msg;
1285 transfer = pl022->cur_transfer;
1286
1287 /* Handle for abort */
1288 if (message->state == STATE_ERROR) {
1289 message->status = -EIO;
1290 giveback(pl022);
1291 return;
1292 }
1293
1294 /* Handle end of message */
1295 if (message->state == STATE_DONE) {
1296 message->status = 0;
1297 giveback(pl022);
1298 return;
1299 }
1300
1301 /* Delay if requested at end of transfer before CS change */
1302 if (message->state == STATE_RUNNING) {
1303 previous = list_entry(transfer->transfer_list.prev,
1304 struct spi_transfer,
1305 transfer_list);
1306 if (previous->delay_usecs)
1307 /*
1308 * FIXME: This runs in interrupt context.
1309 * Is this really smart?
1310 */
1311 udelay(previous->delay_usecs);
1312
1313 /* Drop chip select only if cs_change is requested */
1314 if (previous->cs_change)
1315 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1316 } else {
1317 /* STATE_START */
1318 message->state = STATE_RUNNING;
1319 }
1320
1321 if (set_up_next_transfer(pl022, transfer)) {
1322 message->state = STATE_ERROR;
1323 message->status = -EIO;
1324 giveback(pl022);
1325 return;
1326 }
1327 /* Flush the FIFOs and let's go! */
1328 flush(pl022);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001329
1330 if (pl022->cur_chip->enable_dma) {
1331 if (configure_dma(pl022)) {
1332 dev_dbg(&pl022->adev->dev,
1333 "configuration of DMA failed, fall back to interrupt mode\n");
1334 goto err_config_dma;
1335 }
1336 return;
1337 }
1338
1339err_config_dma:
Linus Walleijb43d65f2009-06-09 08:11:42 +01001340 writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
1341}
1342
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001343static void do_interrupt_dma_transfer(struct pl022 *pl022)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001344{
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001345 u32 irqflags = ENABLE_ALL_INTERRUPTS;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001346
1347 /* Enable target chip */
1348 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1349 if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
1350 /* Error path */
1351 pl022->cur_msg->state = STATE_ERROR;
1352 pl022->cur_msg->status = -EIO;
1353 giveback(pl022);
1354 return;
1355 }
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001356 /* If we're using DMA, set up DMA here */
1357 if (pl022->cur_chip->enable_dma) {
1358 /* Configure DMA transfer */
1359 if (configure_dma(pl022)) {
1360 dev_dbg(&pl022->adev->dev,
1361 "configuration of DMA failed, fall back to interrupt mode\n");
1362 goto err_config_dma;
1363 }
1364 /* Disable interrupts in DMA mode, IRQ from DMA controller */
1365 irqflags = DISABLE_ALL_INTERRUPTS;
1366 }
1367err_config_dma:
Linus Walleijb43d65f2009-06-09 08:11:42 +01001368 /* Enable SSP, turn on interrupts */
1369 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1370 SSP_CR1(pl022->virtbase));
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001371 writew(irqflags, SSP_IMSC(pl022->virtbase));
Linus Walleijb43d65f2009-06-09 08:11:42 +01001372}
1373
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001374static void do_polling_transfer(struct pl022 *pl022)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001375{
Linus Walleijb43d65f2009-06-09 08:11:42 +01001376 struct spi_message *message = NULL;
1377 struct spi_transfer *transfer = NULL;
1378 struct spi_transfer *previous = NULL;
1379 struct chip_data *chip;
Magnus Templinga18c2662011-05-19 18:05:34 +02001380 unsigned long time, timeout;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001381
1382 chip = pl022->cur_chip;
1383 message = pl022->cur_msg;
1384
1385 while (message->state != STATE_DONE) {
1386 /* Handle for abort */
1387 if (message->state == STATE_ERROR)
1388 break;
1389 transfer = pl022->cur_transfer;
1390
1391 /* Delay if requested at end of transfer */
1392 if (message->state == STATE_RUNNING) {
1393 previous =
1394 list_entry(transfer->transfer_list.prev,
1395 struct spi_transfer, transfer_list);
1396 if (previous->delay_usecs)
1397 udelay(previous->delay_usecs);
1398 if (previous->cs_change)
1399 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1400 } else {
1401 /* STATE_START */
1402 message->state = STATE_RUNNING;
1403 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
1404 }
1405
1406 /* Configuration Changing Per Transfer */
1407 if (set_up_next_transfer(pl022, transfer)) {
1408 /* Error path */
1409 message->state = STATE_ERROR;
1410 break;
1411 }
1412 /* Flush FIFOs and enable SSP */
1413 flush(pl022);
1414 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1415 SSP_CR1(pl022->virtbase));
1416
Linus Walleij556f4ae2010-05-05 09:28:15 +00001417 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
Magnus Templinga18c2662011-05-19 18:05:34 +02001418
1419 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
1420 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
1421 time = jiffies;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001422 readwriter(pl022);
Magnus Templinga18c2662011-05-19 18:05:34 +02001423 if (time_after(time, timeout)) {
1424 dev_warn(&pl022->adev->dev,
1425 "%s: timeout!\n", __func__);
1426 message->state = STATE_ERROR;
1427 goto out;
1428 }
Linus Walleij521999b2011-05-19 20:01:25 +02001429 cpu_relax();
Magnus Templinga18c2662011-05-19 18:05:34 +02001430 }
Linus Walleijb43d65f2009-06-09 08:11:42 +01001431
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001432 /* Update total byte transferred */
Linus Walleijb43d65f2009-06-09 08:11:42 +01001433 message->actual_length += pl022->cur_transfer->len;
1434 if (pl022->cur_transfer->cs_change)
1435 pl022->cur_chip->cs_control(SSP_CHIP_DESELECT);
1436 /* Move to next transfer */
1437 message->state = next_transfer(pl022);
1438 }
Magnus Templinga18c2662011-05-19 18:05:34 +02001439out:
Linus Walleijb43d65f2009-06-09 08:11:42 +01001440 /* Handle end of message */
1441 if (message->state == STATE_DONE)
1442 message->status = 0;
1443 else
1444 message->status = -EIO;
1445
1446 giveback(pl022);
1447 return;
1448}
1449
1450/**
1451 * pump_messages - Workqueue function which processes spi message queue
1452 * @data: pointer to private data of SSP driver
1453 *
1454 * This function checks if there is any spi message in the queue that
1455 * needs processing and delegate control to appropriate function
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001456 * do_polling_transfer()/do_interrupt_dma_transfer()
Linus Walleijb43d65f2009-06-09 08:11:42 +01001457 * based on the kind of the transfer
1458 *
1459 */
1460static void pump_messages(struct work_struct *work)
1461{
1462 struct pl022 *pl022 =
1463 container_of(work, struct pl022, pump_messages);
1464 unsigned long flags;
1465
1466 /* Lock queue and check for queue work */
1467 spin_lock_irqsave(&pl022->queue_lock, flags);
Linus Walleij5e8b8212010-12-22 23:13:59 +01001468 if (list_empty(&pl022->queue) || !pl022->running) {
Linus Walleijdec5a582010-12-22 23:13:48 +01001469 pl022->busy = false;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001470 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1471 return;
1472 }
1473 /* Make sure we are not already running a message */
1474 if (pl022->cur_msg) {
1475 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1476 return;
1477 }
1478 /* Extract head of queue */
1479 pl022->cur_msg =
1480 list_entry(pl022->queue.next, struct spi_message, queue);
1481
1482 list_del_init(&pl022->cur_msg->queue);
Linus Walleijdec5a582010-12-22 23:13:48 +01001483 pl022->busy = true;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001484 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1485
1486 /* Initial message state */
1487 pl022->cur_msg->state = STATE_START;
1488 pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next,
1489 struct spi_transfer,
1490 transfer_list);
1491
1492 /* Setup the SPI using the per chip configuration */
1493 pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi);
1494 /*
Linus Walleij808f1032011-02-08 13:03:32 +01001495 * We enable the core voltage and clocks here, then the clocks
1496 * and core will be disabled when giveback() is called in each method
1497 * (poll/interrupt/DMA)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001498 */
Linus Walleij808f1032011-02-08 13:03:32 +01001499 amba_vcore_enable(pl022->adev);
Linus Walleij545074f2010-08-21 11:07:36 +02001500 amba_pclk_enable(pl022->adev);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001501 clk_enable(pl022->clk);
1502 restore_state(pl022);
1503 flush(pl022);
1504
1505 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1506 do_polling_transfer(pl022);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001507 else
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001508 do_interrupt_dma_transfer(pl022);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001509}
1510
1511
1512static int __init init_queue(struct pl022 *pl022)
1513{
1514 INIT_LIST_HEAD(&pl022->queue);
1515 spin_lock_init(&pl022->queue_lock);
1516
Linus Walleij5e8b8212010-12-22 23:13:59 +01001517 pl022->running = false;
Linus Walleijdec5a582010-12-22 23:13:48 +01001518 pl022->busy = false;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001519
1520 tasklet_init(&pl022->pump_transfers,
1521 pump_transfers, (unsigned long)pl022);
1522
1523 INIT_WORK(&pl022->pump_messages, pump_messages);
1524 pl022->workqueue = create_singlethread_workqueue(
1525 dev_name(pl022->master->dev.parent));
1526 if (pl022->workqueue == NULL)
1527 return -EBUSY;
1528
1529 return 0;
1530}
1531
1532
1533static int start_queue(struct pl022 *pl022)
1534{
1535 unsigned long flags;
1536
1537 spin_lock_irqsave(&pl022->queue_lock, flags);
1538
Linus Walleij5e8b8212010-12-22 23:13:59 +01001539 if (pl022->running || pl022->busy) {
Linus Walleijb43d65f2009-06-09 08:11:42 +01001540 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1541 return -EBUSY;
1542 }
1543
Linus Walleij5e8b8212010-12-22 23:13:59 +01001544 pl022->running = true;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001545 pl022->cur_msg = NULL;
1546 pl022->cur_transfer = NULL;
1547 pl022->cur_chip = NULL;
1548 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1549
1550 queue_work(pl022->workqueue, &pl022->pump_messages);
1551
1552 return 0;
1553}
1554
1555
1556static int stop_queue(struct pl022 *pl022)
1557{
1558 unsigned long flags;
1559 unsigned limit = 500;
1560 int status = 0;
1561
1562 spin_lock_irqsave(&pl022->queue_lock, flags);
1563
1564 /* This is a bit lame, but is optimized for the common execution path.
1565 * A wait_queue on the pl022->busy could be used, but then the common
1566 * execution path (pump_messages) would be required to call wake_up or
1567 * friends on every SPI message. Do this instead */
Vasily Khoruzhick850a28e2011-04-06 17:49:15 +03001568 while ((!list_empty(&pl022->queue) || pl022->busy) && limit--) {
Linus Walleijb43d65f2009-06-09 08:11:42 +01001569 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1570 msleep(10);
1571 spin_lock_irqsave(&pl022->queue_lock, flags);
1572 }
1573
1574 if (!list_empty(&pl022->queue) || pl022->busy)
1575 status = -EBUSY;
Linus Walleij5e8b8212010-12-22 23:13:59 +01001576 else
1577 pl022->running = false;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001578
1579 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1580
1581 return status;
1582}
1583
1584static int destroy_queue(struct pl022 *pl022)
1585{
1586 int status;
1587
1588 status = stop_queue(pl022);
1589 /* we are unloading the module or failing to load (only two calls
1590 * to this routine), and neither call can handle a return value.
1591 * However, destroy_workqueue calls flush_workqueue, and that will
1592 * block until all work is done. If the reason that stop_queue
1593 * timed out is that the work will never finish, then it does no
1594 * good to call destroy_workqueue, so return anyway. */
1595 if (status != 0)
1596 return status;
1597
1598 destroy_workqueue(pl022->workqueue);
1599
1600 return 0;
1601}
1602
1603static int verify_controller_parameters(struct pl022 *pl022,
Linus Walleijf9d629c2010-10-01 13:33:13 +02001604 struct pl022_config_chip const *chip_info)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001605{
Linus Walleijb43d65f2009-06-09 08:11:42 +01001606 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1607 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001608 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001609 "interface is configured incorrectly\n");
1610 return -EINVAL;
1611 }
1612 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1613 (!pl022->vendor->unidir)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001614 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001615 "unidirectional mode not supported in this "
1616 "hardware version\n");
1617 return -EINVAL;
1618 }
1619 if ((chip_info->hierarchy != SSP_MASTER)
1620 && (chip_info->hierarchy != SSP_SLAVE)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001621 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001622 "hierarchy is configured incorrectly\n");
1623 return -EINVAL;
1624 }
Linus Walleijb43d65f2009-06-09 08:11:42 +01001625 if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1626 && (chip_info->com_mode != DMA_TRANSFER)
1627 && (chip_info->com_mode != POLLING_TRANSFER)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001628 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001629 "Communication mode is configured incorrectly\n");
1630 return -EINVAL;
1631 }
1632 if ((chip_info->rx_lev_trig < SSP_RX_1_OR_MORE_ELEM)
1633 || (chip_info->rx_lev_trig > SSP_RX_32_OR_MORE_ELEM)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001634 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001635 "RX FIFO Trigger Level is configured incorrectly\n");
1636 return -EINVAL;
1637 }
1638 if ((chip_info->tx_lev_trig < SSP_TX_1_OR_MORE_EMPTY_LOC)
1639 || (chip_info->tx_lev_trig > SSP_TX_32_OR_MORE_EMPTY_LOC)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001640 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001641 "TX FIFO Trigger Level is configured incorrectly\n");
1642 return -EINVAL;
1643 }
Linus Walleijb43d65f2009-06-09 08:11:42 +01001644 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1645 if ((chip_info->ctrl_len < SSP_BITS_4)
1646 || (chip_info->ctrl_len > SSP_BITS_32)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001647 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001648 "CTRL LEN is configured incorrectly\n");
1649 return -EINVAL;
1650 }
1651 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1652 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001653 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001654 "Wait State is configured incorrectly\n");
1655 return -EINVAL;
1656 }
Linus Walleij556f4ae2010-05-05 09:28:15 +00001657 /* Half duplex is only available in the ST Micro version */
1658 if (pl022->vendor->extended_cr) {
1659 if ((chip_info->duplex !=
1660 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1661 && (chip_info->duplex !=
Julia Lawall4a4fd472010-09-29 17:31:30 +09001662 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001663 dev_err(&pl022->adev->dev,
Linus Walleij556f4ae2010-05-05 09:28:15 +00001664 "Microwire duplex mode is configured incorrectly\n");
1665 return -EINVAL;
Julia Lawall4a4fd472010-09-29 17:31:30 +09001666 }
Linus Walleij556f4ae2010-05-05 09:28:15 +00001667 } else {
1668 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001669 dev_err(&pl022->adev->dev,
Linus Walleij556f4ae2010-05-05 09:28:15 +00001670 "Microwire half duplex mode requested,"
1671 " but this is only available in the"
1672 " ST version of PL022\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001673 return -EINVAL;
1674 }
1675 }
Linus Walleijb43d65f2009-06-09 08:11:42 +01001676 return 0;
1677}
1678
1679/**
1680 * pl022_transfer - transfer function registered to SPI master framework
1681 * @spi: spi device which is requesting transfer
1682 * @msg: spi message which is to handled is queued to driver queue
1683 *
1684 * This function is registered to the SPI framework for this SPI master
1685 * controller. It will queue the spi_message in the queue of driver if
1686 * the queue is not stopped and return.
1687 */
1688static int pl022_transfer(struct spi_device *spi, struct spi_message *msg)
1689{
1690 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1691 unsigned long flags;
1692
1693 spin_lock_irqsave(&pl022->queue_lock, flags);
1694
Linus Walleij5e8b8212010-12-22 23:13:59 +01001695 if (!pl022->running) {
Linus Walleijb43d65f2009-06-09 08:11:42 +01001696 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1697 return -ESHUTDOWN;
1698 }
1699 msg->actual_length = 0;
1700 msg->status = -EINPROGRESS;
1701 msg->state = STATE_START;
1702
1703 list_add_tail(&msg->queue, &pl022->queue);
Linus Walleij5e8b8212010-12-22 23:13:59 +01001704 if (pl022->running && !pl022->busy)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001705 queue_work(pl022->workqueue, &pl022->pump_messages);
1706
1707 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1708 return 0;
1709}
1710
1711static int calculate_effective_freq(struct pl022 *pl022,
1712 int freq,
1713 struct ssp_clock_params *clk_freq)
1714{
1715 /* Lets calculate the frequency parameters */
1716 u16 cpsdvsr = 2;
1717 u16 scr = 0;
1718 bool freq_found = false;
1719 u32 rate;
1720 u32 max_tclk;
1721 u32 min_tclk;
1722
1723 rate = clk_get_rate(pl022->clk);
1724 /* cpsdvscr = 2 & scr 0 */
1725 max_tclk = (rate / (CPSDVR_MIN * (1 + SCR_MIN)));
1726 /* cpsdvsr = 254 & scr = 255 */
1727 min_tclk = (rate / (CPSDVR_MAX * (1 + SCR_MAX)));
1728
1729 if ((freq <= max_tclk) && (freq >= min_tclk)) {
1730 while (cpsdvsr <= CPSDVR_MAX && !freq_found) {
1731 while (scr <= SCR_MAX && !freq_found) {
1732 if ((rate /
1733 (cpsdvsr * (1 + scr))) > freq)
1734 scr += 1;
1735 else {
1736 /*
1737 * This bool is made true when
1738 * effective frequency >=
1739 * target frequency is found
1740 */
1741 freq_found = true;
1742 if ((rate /
1743 (cpsdvsr * (1 + scr))) != freq) {
1744 if (scr == SCR_MIN) {
1745 cpsdvsr -= 2;
1746 scr = SCR_MAX;
1747 } else
1748 scr -= 1;
1749 }
1750 }
1751 }
1752 if (!freq_found) {
1753 cpsdvsr += 2;
1754 scr = SCR_MIN;
1755 }
1756 }
1757 if (cpsdvsr != 0) {
1758 dev_dbg(&pl022->adev->dev,
1759 "SSP Effective Frequency is %u\n",
1760 (rate / (cpsdvsr * (1 + scr))));
1761 clk_freq->cpsdvsr = (u8) (cpsdvsr & 0xFF);
1762 clk_freq->scr = (u8) (scr & 0xFF);
1763 dev_dbg(&pl022->adev->dev,
1764 "SSP cpsdvsr = %d, scr = %d\n",
1765 clk_freq->cpsdvsr, clk_freq->scr);
1766 }
1767 } else {
1768 dev_err(&pl022->adev->dev,
1769 "controller data is incorrect: out of range frequency");
1770 return -EINVAL;
1771 }
1772 return 0;
1773}
1774
Linus Walleijf9d629c2010-10-01 13:33:13 +02001775
1776/*
1777 * A piece of default chip info unless the platform
1778 * supplies it.
1779 */
1780static const struct pl022_config_chip pl022_default_chip_info = {
1781 .com_mode = POLLING_TRANSFER,
1782 .iface = SSP_INTERFACE_MOTOROLA_SPI,
1783 .hierarchy = SSP_SLAVE,
1784 .slave_tx_disable = DO_NOT_DRIVE_TX,
1785 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
1786 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
1787 .ctrl_len = SSP_BITS_8,
1788 .wait_state = SSP_MWIRE_WAIT_ZERO,
1789 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
1790 .cs_control = null_cs_control,
1791};
1792
1793
Linus Walleijb43d65f2009-06-09 08:11:42 +01001794/**
Linus Walleijb43d65f2009-06-09 08:11:42 +01001795 * pl022_setup - setup function registered to SPI master framework
1796 * @spi: spi device which is requesting setup
1797 *
1798 * This function is registered to the SPI framework for this SPI master
1799 * controller. If it is the first time when setup is called by this device,
1800 * this function will initialize the runtime state for this chip and save
1801 * the same in the device structure. Else it will update the runtime info
1802 * with the updated chip info. Nothing is really being written to the
1803 * controller hardware here, that is not done until the actual transfer
1804 * commence.
1805 */
Linus Walleijb43d65f2009-06-09 08:11:42 +01001806static int pl022_setup(struct spi_device *spi)
1807{
Linus Walleijf9d629c2010-10-01 13:33:13 +02001808 struct pl022_config_chip const *chip_info;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001809 struct chip_data *chip;
Viresh Kumar94a1b6d2011-01-13 17:24:22 +05301810 struct ssp_clock_params clk_freq = {0, };
Linus Walleijb43d65f2009-06-09 08:11:42 +01001811 int status = 0;
1812 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
Kevin Wellsbde435a2010-09-16 06:18:50 -07001813 unsigned int bits = spi->bits_per_word;
1814 u32 tmp;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001815
1816 if (!spi->max_speed_hz)
1817 return -EINVAL;
1818
1819 /* Get controller_state if one is supplied */
1820 chip = spi_get_ctldata(spi);
1821
1822 if (chip == NULL) {
1823 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1824 if (!chip) {
1825 dev_err(&spi->dev,
1826 "cannot allocate controller state\n");
1827 return -ENOMEM;
1828 }
1829 dev_dbg(&spi->dev,
1830 "allocated memory for controller's runtime state\n");
1831 }
1832
1833 /* Get controller data if one is supplied */
1834 chip_info = spi->controller_data;
1835
1836 if (chip_info == NULL) {
Linus Walleijf9d629c2010-10-01 13:33:13 +02001837 chip_info = &pl022_default_chip_info;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001838 /* spi_board_info.controller_data not is supplied */
1839 dev_dbg(&spi->dev,
1840 "using default controller_data settings\n");
Linus Walleijf9d629c2010-10-01 13:33:13 +02001841 } else
Linus Walleijb43d65f2009-06-09 08:11:42 +01001842 dev_dbg(&spi->dev,
1843 "using user supplied controller_data settings\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001844
1845 /*
1846 * We can override with custom divisors, else we use the board
1847 * frequency setting
1848 */
1849 if ((0 == chip_info->clk_freq.cpsdvsr)
1850 && (0 == chip_info->clk_freq.scr)) {
1851 status = calculate_effective_freq(pl022,
1852 spi->max_speed_hz,
Linus Walleijf9d629c2010-10-01 13:33:13 +02001853 &clk_freq);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001854 if (status < 0)
1855 goto err_config_params;
1856 } else {
Linus Walleijf9d629c2010-10-01 13:33:13 +02001857 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
1858 if ((clk_freq.cpsdvsr % 2) != 0)
1859 clk_freq.cpsdvsr =
1860 clk_freq.cpsdvsr - 1;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001861 }
Linus Walleijf9d629c2010-10-01 13:33:13 +02001862 if ((clk_freq.cpsdvsr < CPSDVR_MIN)
1863 || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
Virupax Sadashivpetimathe3f88ae2011-06-13 16:23:46 +05301864 status = -EINVAL;
Linus Walleijf9d629c2010-10-01 13:33:13 +02001865 dev_err(&spi->dev,
1866 "cpsdvsr is configured incorrectly\n");
1867 goto err_config_params;
1868 }
1869
1870
Linus Walleijb43d65f2009-06-09 08:11:42 +01001871 status = verify_controller_parameters(pl022, chip_info);
1872 if (status) {
1873 dev_err(&spi->dev, "controller data is incorrect");
1874 goto err_config_params;
1875 }
Linus Walleijf9d629c2010-10-01 13:33:13 +02001876
Linus Walleijb43d65f2009-06-09 08:11:42 +01001877 /* Now set controller state based on controller data */
1878 chip->xfer_type = chip_info->com_mode;
Linus Walleijf9d629c2010-10-01 13:33:13 +02001879 if (!chip_info->cs_control) {
1880 chip->cs_control = null_cs_control;
1881 dev_warn(&spi->dev,
1882 "chip select function is NULL for this chip\n");
1883 } else
1884 chip->cs_control = chip_info->cs_control;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001885
Kevin Wellsbde435a2010-09-16 06:18:50 -07001886 if (bits <= 3) {
1887 /* PL022 doesn't support less than 4-bits */
1888 status = -ENOTSUPP;
1889 goto err_config_params;
1890 } else if (bits <= 8) {
1891 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001892 chip->n_bytes = 1;
1893 chip->read = READING_U8;
1894 chip->write = WRITING_U8;
Kevin Wellsbde435a2010-09-16 06:18:50 -07001895 } else if (bits <= 16) {
Linus Walleijb43d65f2009-06-09 08:11:42 +01001896 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
1897 chip->n_bytes = 2;
1898 chip->read = READING_U16;
1899 chip->write = WRITING_U16;
1900 } else {
1901 if (pl022->vendor->max_bpw >= 32) {
1902 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
1903 chip->n_bytes = 4;
1904 chip->read = READING_U32;
1905 chip->write = WRITING_U32;
1906 } else {
1907 dev_err(&spi->dev,
1908 "illegal data size for this controller!\n");
1909 dev_err(&spi->dev,
1910 "a standard pl022 can only handle "
1911 "1 <= n <= 16 bit words\n");
Kevin Wellsbde435a2010-09-16 06:18:50 -07001912 status = -ENOTSUPP;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001913 goto err_config_params;
1914 }
1915 }
1916
1917 /* Now Initialize all register settings required for this chip */
1918 chip->cr0 = 0;
1919 chip->cr1 = 0;
1920 chip->dmacr = 0;
1921 chip->cpsr = 0;
1922 if ((chip_info->com_mode == DMA_TRANSFER)
1923 && ((pl022->master_info)->enable_dma)) {
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001924 chip->enable_dma = true;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001925 dev_dbg(&spi->dev, "DMA mode set in controller state\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001926 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1927 SSP_DMACR_MASK_RXDMAE, 0);
1928 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1929 SSP_DMACR_MASK_TXDMAE, 1);
1930 } else {
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001931 chip->enable_dma = false;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001932 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
1933 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1934 SSP_DMACR_MASK_RXDMAE, 0);
1935 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1936 SSP_DMACR_MASK_TXDMAE, 1);
1937 }
1938
Linus Walleijf9d629c2010-10-01 13:33:13 +02001939 chip->cpsr = clk_freq.cpsdvsr;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001940
Linus Walleij556f4ae2010-05-05 09:28:15 +00001941 /* Special setup for the ST micro extended control registers */
1942 if (pl022->vendor->extended_cr) {
Kevin Wellsbde435a2010-09-16 06:18:50 -07001943 u32 etx;
1944
Linus Walleij781c7b12010-05-07 08:40:53 +00001945 if (pl022->vendor->pl023) {
1946 /* These bits are only in the PL023 */
1947 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
1948 SSP_CR1_MASK_FBCLKDEL_ST, 13);
1949 } else {
1950 /* These bits are in the PL022 but not PL023 */
1951 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
1952 SSP_CR0_MASK_HALFDUP_ST, 5);
1953 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
1954 SSP_CR0_MASK_CSS_ST, 16);
1955 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1956 SSP_CR0_MASK_FRF_ST, 21);
1957 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
1958 SSP_CR1_MASK_MWAIT_ST, 6);
1959 }
Kevin Wellsbde435a2010-09-16 06:18:50 -07001960 SSP_WRITE_BITS(chip->cr0, bits - 1,
Linus Walleij556f4ae2010-05-05 09:28:15 +00001961 SSP_CR0_MASK_DSS_ST, 0);
Kevin Wellsbde435a2010-09-16 06:18:50 -07001962
1963 if (spi->mode & SPI_LSB_FIRST) {
1964 tmp = SSP_RX_LSB;
1965 etx = SSP_TX_LSB;
1966 } else {
1967 tmp = SSP_RX_MSB;
1968 etx = SSP_TX_MSB;
1969 }
1970 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
1971 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
Linus Walleij556f4ae2010-05-05 09:28:15 +00001972 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
1973 SSP_CR1_MASK_RXIFLSEL_ST, 7);
1974 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
1975 SSP_CR1_MASK_TXIFLSEL_ST, 10);
1976 } else {
Kevin Wellsbde435a2010-09-16 06:18:50 -07001977 SSP_WRITE_BITS(chip->cr0, bits - 1,
Linus Walleij556f4ae2010-05-05 09:28:15 +00001978 SSP_CR0_MASK_DSS, 0);
1979 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1980 SSP_CR0_MASK_FRF, 4);
1981 }
Kevin Wellsbde435a2010-09-16 06:18:50 -07001982
Linus Walleij556f4ae2010-05-05 09:28:15 +00001983 /* Stuff that is common for all versions */
Kevin Wellsbde435a2010-09-16 06:18:50 -07001984 if (spi->mode & SPI_CPOL)
1985 tmp = SSP_CLK_POL_IDLE_HIGH;
1986 else
1987 tmp = SSP_CLK_POL_IDLE_LOW;
1988 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
1989
1990 if (spi->mode & SPI_CPHA)
1991 tmp = SSP_CLK_SECOND_EDGE;
1992 else
1993 tmp = SSP_CLK_FIRST_EDGE;
1994 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
1995
Linus Walleijf9d629c2010-10-01 13:33:13 +02001996 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
Linus Walleij781c7b12010-05-07 08:40:53 +00001997 /* Loopback is available on all versions except PL023 */
Philippe Langlais06fb01f2011-03-23 11:05:16 +01001998 if (pl022->vendor->loopback) {
Kevin Wellsbde435a2010-09-16 06:18:50 -07001999 if (spi->mode & SPI_LOOP)
2000 tmp = LOOPBACK_ENABLED;
2001 else
2002 tmp = LOOPBACK_DISABLED;
2003 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
2004 }
Linus Walleijb43d65f2009-06-09 08:11:42 +01002005 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
2006 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
2007 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 3);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002008
2009 /* Save controller_state */
2010 spi_set_ctldata(spi, chip);
2011 return status;
2012 err_config_params:
Kevin Wellsbde435a2010-09-16 06:18:50 -07002013 spi_set_ctldata(spi, NULL);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002014 kfree(chip);
2015 return status;
2016}
2017
2018/**
2019 * pl022_cleanup - cleanup function registered to SPI master framework
2020 * @spi: spi device which is requesting cleanup
2021 *
2022 * This function is registered to the SPI framework for this SPI master
2023 * controller. It will free the runtime state of chip.
2024 */
2025static void pl022_cleanup(struct spi_device *spi)
2026{
2027 struct chip_data *chip = spi_get_ctldata(spi);
2028
2029 spi_set_ctldata(spi, NULL);
2030 kfree(chip);
2031}
2032
2033
Kevin Wellsb4225882010-07-27 16:39:30 +00002034static int __devinit
Russell Kingaa25afa2011-02-19 15:55:00 +00002035pl022_probe(struct amba_device *adev, const struct amba_id *id)
Linus Walleijb43d65f2009-06-09 08:11:42 +01002036{
2037 struct device *dev = &adev->dev;
2038 struct pl022_ssp_controller *platform_info = adev->dev.platform_data;
2039 struct spi_master *master;
2040 struct pl022 *pl022 = NULL; /*Data for this driver */
2041 int status = 0;
2042
2043 dev_info(&adev->dev,
2044 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
2045 if (platform_info == NULL) {
2046 dev_err(&adev->dev, "probe - no platform data supplied\n");
2047 status = -ENODEV;
2048 goto err_no_pdata;
2049 }
2050
2051 /* Allocate master with space for data */
2052 master = spi_alloc_master(dev, sizeof(struct pl022));
2053 if (master == NULL) {
2054 dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
2055 status = -ENOMEM;
2056 goto err_no_master;
2057 }
2058
2059 pl022 = spi_master_get_devdata(master);
2060 pl022->master = master;
2061 pl022->master_info = platform_info;
2062 pl022->adev = adev;
2063 pl022->vendor = id->data;
2064
2065 /*
2066 * Bus Number Which has been Assigned to this SSP controller
2067 * on this board
2068 */
2069 master->bus_num = platform_info->bus_id;
2070 master->num_chipselect = platform_info->num_chipselect;
2071 master->cleanup = pl022_cleanup;
2072 master->setup = pl022_setup;
2073 master->transfer = pl022_transfer;
2074
Kevin Wellsbde435a2010-09-16 06:18:50 -07002075 /*
2076 * Supports mode 0-3, loopback, and active low CS. Transfers are
2077 * always MS bit first on the original pl022.
2078 */
2079 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
2080 if (pl022->vendor->extended_cr)
2081 master->mode_bits |= SPI_LSB_FIRST;
2082
Linus Walleijb43d65f2009-06-09 08:11:42 +01002083 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
2084
2085 status = amba_request_regions(adev, NULL);
2086 if (status)
2087 goto err_no_ioregion;
2088
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09002089 pl022->phybase = adev->res.start;
Linus Walleijb43d65f2009-06-09 08:11:42 +01002090 pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res));
2091 if (pl022->virtbase == NULL) {
2092 status = -ENOMEM;
2093 goto err_no_ioremap;
2094 }
2095 printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n",
2096 adev->res.start, pl022->virtbase);
2097
2098 pl022->clk = clk_get(&adev->dev, NULL);
2099 if (IS_ERR(pl022->clk)) {
2100 status = PTR_ERR(pl022->clk);
2101 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
2102 goto err_no_clk;
2103 }
2104
2105 /* Disable SSP */
Linus Walleijb43d65f2009-06-09 08:11:42 +01002106 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
2107 SSP_CR1(pl022->virtbase));
2108 load_ssp_default_config(pl022);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002109
2110 status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022",
2111 pl022);
2112 if (status < 0) {
2113 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
2114 goto err_no_irq;
2115 }
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09002116
2117 /* Get DMA channels */
2118 if (platform_info->enable_dma) {
2119 status = pl022_dma_probe(pl022);
2120 if (status != 0)
Viresh Kumar43c64012011-05-16 09:40:10 +05302121 platform_info->enable_dma = 0;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09002122 }
2123
Linus Walleijb43d65f2009-06-09 08:11:42 +01002124 /* Initialize and start queue */
2125 status = init_queue(pl022);
2126 if (status != 0) {
2127 dev_err(&adev->dev, "probe - problem initializing queue\n");
2128 goto err_init_queue;
2129 }
2130 status = start_queue(pl022);
2131 if (status != 0) {
2132 dev_err(&adev->dev, "probe - problem starting queue\n");
2133 goto err_start_queue;
2134 }
2135 /* Register with the SPI framework */
2136 amba_set_drvdata(adev, pl022);
2137 status = spi_register_master(master);
2138 if (status != 0) {
2139 dev_err(&adev->dev,
2140 "probe - problem registering spi master\n");
2141 goto err_spi_register;
2142 }
Lucas De Marchi25985ed2011-03-30 22:57:33 -03002143 dev_dbg(dev, "probe succeeded\n");
Linus Walleij808f1032011-02-08 13:03:32 +01002144 /*
2145 * Disable the silicon block pclk and any voltage domain and just
2146 * power it up and clock it when it's needed
2147 */
Linus Walleij545074f2010-08-21 11:07:36 +02002148 amba_pclk_disable(adev);
Linus Walleij808f1032011-02-08 13:03:32 +01002149 amba_vcore_disable(adev);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002150 return 0;
2151
2152 err_spi_register:
2153 err_start_queue:
2154 err_init_queue:
2155 destroy_queue(pl022);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09002156 pl022_dma_remove(pl022);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002157 free_irq(adev->irq[0], pl022);
2158 err_no_irq:
2159 clk_put(pl022->clk);
2160 err_no_clk:
2161 iounmap(pl022->virtbase);
2162 err_no_ioremap:
2163 amba_release_regions(adev);
2164 err_no_ioregion:
2165 spi_master_put(master);
2166 err_no_master:
2167 err_no_pdata:
2168 return status;
2169}
2170
Kevin Wellsb4225882010-07-27 16:39:30 +00002171static int __devexit
Linus Walleijb43d65f2009-06-09 08:11:42 +01002172pl022_remove(struct amba_device *adev)
2173{
2174 struct pl022 *pl022 = amba_get_drvdata(adev);
2175 int status = 0;
2176 if (!pl022)
2177 return 0;
2178
2179 /* Remove the queue */
2180 status = destroy_queue(pl022);
2181 if (status != 0) {
2182 dev_err(&adev->dev,
2183 "queue remove failed (%d)\n", status);
2184 return status;
2185 }
2186 load_ssp_default_config(pl022);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09002187 pl022_dma_remove(pl022);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002188 free_irq(adev->irq[0], pl022);
2189 clk_disable(pl022->clk);
2190 clk_put(pl022->clk);
2191 iounmap(pl022->virtbase);
2192 amba_release_regions(adev);
2193 tasklet_disable(&pl022->pump_transfers);
2194 spi_unregister_master(pl022->master);
2195 spi_master_put(pl022->master);
2196 amba_set_drvdata(adev, NULL);
Lucas De Marchi25985ed2011-03-30 22:57:33 -03002197 dev_dbg(&adev->dev, "remove succeeded\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01002198 return 0;
2199}
2200
2201#ifdef CONFIG_PM
2202static int pl022_suspend(struct amba_device *adev, pm_message_t state)
2203{
2204 struct pl022 *pl022 = amba_get_drvdata(adev);
2205 int status = 0;
2206
2207 status = stop_queue(pl022);
2208 if (status) {
2209 dev_warn(&adev->dev, "suspend cannot stop queue\n");
2210 return status;
2211 }
2212
Linus Walleij808f1032011-02-08 13:03:32 +01002213 amba_vcore_enable(adev);
Linus Walleij545074f2010-08-21 11:07:36 +02002214 amba_pclk_enable(adev);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002215 load_ssp_default_config(pl022);
Linus Walleij545074f2010-08-21 11:07:36 +02002216 amba_pclk_disable(adev);
Linus Walleij808f1032011-02-08 13:03:32 +01002217 amba_vcore_disable(adev);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002218 dev_dbg(&adev->dev, "suspended\n");
2219 return 0;
2220}
2221
2222static int pl022_resume(struct amba_device *adev)
2223{
2224 struct pl022 *pl022 = amba_get_drvdata(adev);
2225 int status = 0;
2226
2227 /* Start the queue running */
2228 status = start_queue(pl022);
2229 if (status)
2230 dev_err(&adev->dev, "problem starting queue (%d)\n", status);
2231 else
2232 dev_dbg(&adev->dev, "resumed\n");
2233
2234 return status;
2235}
2236#else
2237#define pl022_suspend NULL
2238#define pl022_resume NULL
2239#endif /* CONFIG_PM */
2240
2241static struct vendor_data vendor_arm = {
2242 .fifodepth = 8,
2243 .max_bpw = 16,
2244 .unidir = false,
Linus Walleij556f4ae2010-05-05 09:28:15 +00002245 .extended_cr = false,
Linus Walleij781c7b12010-05-07 08:40:53 +00002246 .pl023 = false,
Philippe Langlais06fb01f2011-03-23 11:05:16 +01002247 .loopback = true,
Linus Walleijb43d65f2009-06-09 08:11:42 +01002248};
2249
2250
2251static struct vendor_data vendor_st = {
2252 .fifodepth = 32,
2253 .max_bpw = 32,
2254 .unidir = false,
Linus Walleij556f4ae2010-05-05 09:28:15 +00002255 .extended_cr = true,
Linus Walleij781c7b12010-05-07 08:40:53 +00002256 .pl023 = false,
Philippe Langlais06fb01f2011-03-23 11:05:16 +01002257 .loopback = true,
Linus Walleij781c7b12010-05-07 08:40:53 +00002258};
2259
2260static struct vendor_data vendor_st_pl023 = {
2261 .fifodepth = 32,
2262 .max_bpw = 32,
2263 .unidir = false,
2264 .extended_cr = true,
2265 .pl023 = true,
Philippe Langlais06fb01f2011-03-23 11:05:16 +01002266 .loopback = false,
2267};
2268
2269static struct vendor_data vendor_db5500_pl023 = {
2270 .fifodepth = 32,
2271 .max_bpw = 32,
2272 .unidir = false,
2273 .extended_cr = true,
2274 .pl023 = true,
2275 .loopback = true,
Linus Walleijb43d65f2009-06-09 08:11:42 +01002276};
2277
2278static struct amba_id pl022_ids[] = {
2279 {
2280 /*
2281 * ARM PL022 variant, this has a 16bit wide
2282 * and 8 locations deep TX/RX FIFO
2283 */
2284 .id = 0x00041022,
2285 .mask = 0x000fffff,
2286 .data = &vendor_arm,
2287 },
2288 {
2289 /*
2290 * ST Micro derivative, this has 32bit wide
2291 * and 32 locations deep TX/RX FIFO
2292 */
Srinidhi Kasagare89e04f2009-10-05 06:13:53 +01002293 .id = 0x01080022,
Linus Walleijb43d65f2009-06-09 08:11:42 +01002294 .mask = 0xffffffff,
2295 .data = &vendor_st,
2296 },
Linus Walleij781c7b12010-05-07 08:40:53 +00002297 {
2298 /*
2299 * ST-Ericsson derivative "PL023" (this is not
2300 * an official ARM number), this is a PL022 SSP block
2301 * stripped to SPI mode only, it has 32bit wide
2302 * and 32 locations deep TX/RX FIFO but no extended
2303 * CR0/CR1 register
2304 */
2305 .id = 0x00080023,
2306 .mask = 0xffffffff,
2307 .data = &vendor_st_pl023,
2308 },
Philippe Langlais06fb01f2011-03-23 11:05:16 +01002309 {
2310 .id = 0x10080023,
2311 .mask = 0xffffffff,
2312 .data = &vendor_db5500_pl023,
2313 },
Linus Walleijb43d65f2009-06-09 08:11:42 +01002314 { 0, 0 },
2315};
2316
2317static struct amba_driver pl022_driver = {
2318 .drv = {
2319 .name = "ssp-pl022",
2320 },
2321 .id_table = pl022_ids,
2322 .probe = pl022_probe,
Kevin Wellsb4225882010-07-27 16:39:30 +00002323 .remove = __devexit_p(pl022_remove),
Linus Walleijb43d65f2009-06-09 08:11:42 +01002324 .suspend = pl022_suspend,
2325 .resume = pl022_resume,
2326};
2327
2328
2329static int __init pl022_init(void)
2330{
2331 return amba_driver_register(&pl022_driver);
2332}
2333
Linus Walleij25c8e032010-09-06 11:02:12 +02002334subsys_initcall(pl022_init);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002335
2336static void __exit pl022_exit(void)
2337{
2338 amba_driver_unregister(&pl022_driver);
2339}
2340
2341module_exit(pl022_exit);
2342
2343MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
2344MODULE_DESCRIPTION("PL022 SSP Controller Driver");
2345MODULE_LICENSE("GPL");