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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaa7e16d2005-08-29 15:12:56 -04008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
Linus Torvalds1da177e2005-04-16 15:20:36 -070021 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040022 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
30 * hotplug info, etc.
31 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 */
33
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/pci.h>
37#include <linux/init.h>
38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050041#include <linux/device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070042#include <scsi/scsi_host.h>
43#include <linux/libata.h>
44
45#define DRV_NAME "sata_nv"
Jeff Garzik8676ce02006-06-26 20:41:33 -040046#define DRV_VERSION "2.0"
Linus Torvalds1da177e2005-04-16 15:20:36 -070047
Jeff Garzik10ad05d2006-03-22 23:50:50 -050048enum {
49 NV_PORTS = 2,
50 NV_PIO_MASK = 0x1f,
51 NV_MWDMA_MASK = 0x07,
52 NV_UDMA_MASK = 0x7f,
53 NV_PORT0_SCR_REG_OFFSET = 0x00,
54 NV_PORT1_SCR_REG_OFFSET = 0x40,
Linus Torvalds1da177e2005-04-16 15:20:36 -070055
Tejun Heo27e4b272006-06-17 15:49:55 +090056 /* INT_STATUS/ENABLE */
Jeff Garzik10ad05d2006-03-22 23:50:50 -050057 NV_INT_STATUS = 0x10,
Jeff Garzik10ad05d2006-03-22 23:50:50 -050058 NV_INT_ENABLE = 0x11,
Tejun Heo27e4b272006-06-17 15:49:55 +090059 NV_INT_STATUS_CK804 = 0x440,
Jeff Garzik10ad05d2006-03-22 23:50:50 -050060 NV_INT_ENABLE_CK804 = 0x441,
Linus Torvalds1da177e2005-04-16 15:20:36 -070061
Tejun Heo27e4b272006-06-17 15:49:55 +090062 /* INT_STATUS/ENABLE bits */
63 NV_INT_DEV = 0x01,
64 NV_INT_PM = 0x02,
65 NV_INT_ADDED = 0x04,
66 NV_INT_REMOVED = 0x08,
67
68 NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */
69
Tejun Heo39f87582006-06-17 15:49:56 +090070 NV_INT_ALL = 0x0f,
Tejun Heo5a44eff2006-06-17 15:49:56 +090071 NV_INT_MASK = NV_INT_DEV |
72 NV_INT_ADDED | NV_INT_REMOVED,
Tejun Heo39f87582006-06-17 15:49:56 +090073
Tejun Heo27e4b272006-06-17 15:49:55 +090074 /* INT_CONFIG */
Jeff Garzik10ad05d2006-03-22 23:50:50 -050075 NV_INT_CONFIG = 0x12,
76 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
Linus Torvalds1da177e2005-04-16 15:20:36 -070077
Jeff Garzik10ad05d2006-03-22 23:50:50 -050078 // For PCI config register 20
79 NV_MCP_SATA_CFG_20 = 0x50,
80 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
81};
Linus Torvalds1da177e2005-04-16 15:20:36 -070082
83static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
Jeff Garzikcca39742006-08-24 03:19:22 -040084static void nv_ck804_host_stop(struct ata_host *host);
Tejun Heoada364e2006-06-17 15:49:56 +090085static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance,
86 struct pt_regs *regs);
87static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance,
88 struct pt_regs *regs);
89static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance,
90 struct pt_regs *regs);
Linus Torvalds1da177e2005-04-16 15:20:36 -070091static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
92static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
Linus Torvalds1da177e2005-04-16 15:20:36 -070093
Tejun Heo39f87582006-06-17 15:49:56 +090094static void nv_nf2_freeze(struct ata_port *ap);
95static void nv_nf2_thaw(struct ata_port *ap);
96static void nv_ck804_freeze(struct ata_port *ap);
97static void nv_ck804_thaw(struct ata_port *ap);
98static void nv_error_handler(struct ata_port *ap);
99
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100enum nv_host_type
101{
102 GENERIC,
103 NFORCE2,
Tejun Heo27e4b272006-06-17 15:49:55 +0900104 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
Andy Curride7102452005-10-07 08:53:39 -0700105 CK804
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106};
107
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500108static const struct pci_device_id nv_pci_tbl[] = {
Jeff Garzik54bb3a92006-09-27 22:20:11 -0400109 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 },
110 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 },
111 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 },
112 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 },
113 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 },
114 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 },
115 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 },
116 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), GENERIC },
117 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), GENERIC },
118 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), GENERIC },
119 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), GENERIC },
120 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC },
121 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC },
122 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC },
123 { PCI_VDEVICE(NVIDIA, 0x045c), GENERIC },
124 { PCI_VDEVICE(NVIDIA, 0x045d), GENERIC },
125 { PCI_VDEVICE(NVIDIA, 0x045e), GENERIC },
126 { PCI_VDEVICE(NVIDIA, 0x045f), GENERIC },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
128 PCI_ANY_ID, PCI_ANY_ID,
129 PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
Daniel Drake541134c2005-07-03 13:44:39 +0100130 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
131 PCI_ANY_ID, PCI_ANY_ID,
132 PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700133 { 0, } /* terminate list */
134};
135
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136static struct pci_driver nv_pci_driver = {
137 .name = DRV_NAME,
138 .id_table = nv_pci_tbl,
139 .probe = nv_init_one,
140 .remove = ata_pci_remove_one,
141};
142
Jeff Garzik193515d2005-11-07 00:59:37 -0500143static struct scsi_host_template nv_sht = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144 .module = THIS_MODULE,
145 .name = DRV_NAME,
146 .ioctl = ata_scsi_ioctl,
147 .queuecommand = ata_scsi_queuecmd,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700148 .can_queue = ATA_DEF_QUEUE,
149 .this_id = ATA_SHT_THIS_ID,
150 .sg_tablesize = LIBATA_MAX_PRD,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
152 .emulated = ATA_SHT_EMULATED,
153 .use_clustering = ATA_SHT_USE_CLUSTERING,
154 .proc_name = DRV_NAME,
155 .dma_boundary = ATA_DMA_BOUNDARY,
156 .slave_configure = ata_scsi_slave_config,
Tejun Heoccf68c32006-05-31 18:28:09 +0900157 .slave_destroy = ata_scsi_slave_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158 .bios_param = ata_std_bios_param,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159};
160
Tejun Heoada364e2006-06-17 15:49:56 +0900161static const struct ata_port_operations nv_generic_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700162 .port_disable = ata_port_disable,
163 .tf_load = ata_tf_load,
164 .tf_read = ata_tf_read,
165 .exec_command = ata_exec_command,
166 .check_status = ata_check_status,
167 .dev_select = ata_std_dev_select,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168 .bmdma_setup = ata_bmdma_setup,
169 .bmdma_start = ata_bmdma_start,
170 .bmdma_stop = ata_bmdma_stop,
171 .bmdma_status = ata_bmdma_status,
172 .qc_prep = ata_qc_prep,
173 .qc_issue = ata_qc_issue_prot,
Tejun Heo39f87582006-06-17 15:49:56 +0900174 .freeze = ata_bmdma_freeze,
175 .thaw = ata_bmdma_thaw,
176 .error_handler = nv_error_handler,
177 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Alan Coxa6b2c5d2006-05-22 16:59:59 +0100178 .data_xfer = ata_pio_data_xfer,
Tejun Heoada364e2006-06-17 15:49:56 +0900179 .irq_handler = nv_generic_interrupt,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180 .irq_clear = ata_bmdma_irq_clear,
181 .scr_read = nv_scr_read,
182 .scr_write = nv_scr_write,
183 .port_start = ata_port_start,
184 .port_stop = ata_port_stop,
Tejun Heoe6faf082006-06-17 15:49:55 +0900185 .host_stop = ata_pci_host_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186};
187
Tejun Heoada364e2006-06-17 15:49:56 +0900188static const struct ata_port_operations nv_nf2_ops = {
189 .port_disable = ata_port_disable,
190 .tf_load = ata_tf_load,
191 .tf_read = ata_tf_read,
192 .exec_command = ata_exec_command,
193 .check_status = ata_check_status,
194 .dev_select = ata_std_dev_select,
Tejun Heoada364e2006-06-17 15:49:56 +0900195 .bmdma_setup = ata_bmdma_setup,
196 .bmdma_start = ata_bmdma_start,
197 .bmdma_stop = ata_bmdma_stop,
198 .bmdma_status = ata_bmdma_status,
199 .qc_prep = ata_qc_prep,
200 .qc_issue = ata_qc_issue_prot,
Tejun Heo39f87582006-06-17 15:49:56 +0900201 .freeze = nv_nf2_freeze,
202 .thaw = nv_nf2_thaw,
203 .error_handler = nv_error_handler,
204 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Tejun Heoada364e2006-06-17 15:49:56 +0900205 .data_xfer = ata_pio_data_xfer,
206 .irq_handler = nv_nf2_interrupt,
207 .irq_clear = ata_bmdma_irq_clear,
208 .scr_read = nv_scr_read,
209 .scr_write = nv_scr_write,
210 .port_start = ata_port_start,
211 .port_stop = ata_port_stop,
212 .host_stop = ata_pci_host_stop,
213};
214
215static const struct ata_port_operations nv_ck804_ops = {
216 .port_disable = ata_port_disable,
217 .tf_load = ata_tf_load,
218 .tf_read = ata_tf_read,
219 .exec_command = ata_exec_command,
220 .check_status = ata_check_status,
221 .dev_select = ata_std_dev_select,
Tejun Heoada364e2006-06-17 15:49:56 +0900222 .bmdma_setup = ata_bmdma_setup,
223 .bmdma_start = ata_bmdma_start,
224 .bmdma_stop = ata_bmdma_stop,
225 .bmdma_status = ata_bmdma_status,
226 .qc_prep = ata_qc_prep,
227 .qc_issue = ata_qc_issue_prot,
Tejun Heo39f87582006-06-17 15:49:56 +0900228 .freeze = nv_ck804_freeze,
229 .thaw = nv_ck804_thaw,
230 .error_handler = nv_error_handler,
231 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Tejun Heoada364e2006-06-17 15:49:56 +0900232 .data_xfer = ata_pio_data_xfer,
233 .irq_handler = nv_ck804_interrupt,
234 .irq_clear = ata_bmdma_irq_clear,
235 .scr_read = nv_scr_read,
236 .scr_write = nv_scr_write,
237 .port_start = ata_port_start,
238 .port_stop = ata_port_stop,
239 .host_stop = nv_ck804_host_stop,
240};
241
Tejun Heoada364e2006-06-17 15:49:56 +0900242static struct ata_port_info nv_port_info[] = {
243 /* generic */
244 {
245 .sht = &nv_sht,
Jeff Garzikcca39742006-08-24 03:19:22 -0400246 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
Tejun Heoada364e2006-06-17 15:49:56 +0900247 .pio_mask = NV_PIO_MASK,
248 .mwdma_mask = NV_MWDMA_MASK,
249 .udma_mask = NV_UDMA_MASK,
250 .port_ops = &nv_generic_ops,
251 },
252 /* nforce2/3 */
253 {
254 .sht = &nv_sht,
Jeff Garzikcca39742006-08-24 03:19:22 -0400255 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
Tejun Heoada364e2006-06-17 15:49:56 +0900256 .pio_mask = NV_PIO_MASK,
257 .mwdma_mask = NV_MWDMA_MASK,
258 .udma_mask = NV_UDMA_MASK,
259 .port_ops = &nv_nf2_ops,
260 },
261 /* ck804 */
262 {
263 .sht = &nv_sht,
Jeff Garzikcca39742006-08-24 03:19:22 -0400264 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
Tejun Heoada364e2006-06-17 15:49:56 +0900265 .pio_mask = NV_PIO_MASK,
266 .mwdma_mask = NV_MWDMA_MASK,
267 .udma_mask = NV_UDMA_MASK,
268 .port_ops = &nv_ck804_ops,
269 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270};
271
272MODULE_AUTHOR("NVIDIA");
273MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
274MODULE_LICENSE("GPL");
275MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
276MODULE_VERSION(DRV_VERSION);
277
Tejun Heoada364e2006-06-17 15:49:56 +0900278static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance,
279 struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280{
Jeff Garzikcca39742006-08-24 03:19:22 -0400281 struct ata_host *host = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282 unsigned int i;
283 unsigned int handled = 0;
284 unsigned long flags;
285
Jeff Garzikcca39742006-08-24 03:19:22 -0400286 spin_lock_irqsave(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700287
Jeff Garzikcca39742006-08-24 03:19:22 -0400288 for (i = 0; i < host->n_ports; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289 struct ata_port *ap;
290
Jeff Garzikcca39742006-08-24 03:19:22 -0400291 ap = host->ports[i];
Tejun Heoc1389502005-08-22 14:59:24 +0900292 if (ap &&
Jeff Garzik029f5462006-04-02 10:30:40 -0400293 !(ap->flags & ATA_FLAG_DISABLED)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294 struct ata_queued_cmd *qc;
295
296 qc = ata_qc_from_tag(ap, ap->active_tag);
Albert Leee50362e2005-09-27 17:39:50 +0800297 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298 handled += ata_host_intr(ap, qc);
Andrew Chewb8870302006-01-04 19:13:04 -0800299 else
300 // No request pending? Clear interrupt status
301 // anyway, in case there's one pending.
302 ap->ops->check_status(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303 }
304
305 }
306
Jeff Garzikcca39742006-08-24 03:19:22 -0400307 spin_unlock_irqrestore(&host->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308
309 return IRQ_RETVAL(handled);
310}
311
Tejun Heoada364e2006-06-17 15:49:56 +0900312static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
313{
314 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
315 int handled;
316
Tejun Heo5a44eff2006-06-17 15:49:56 +0900317 /* freeze if hotplugged */
318 if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) {
319 ata_port_freeze(ap);
320 return 1;
321 }
322
Tejun Heoada364e2006-06-17 15:49:56 +0900323 /* bail out if not our interrupt */
324 if (!(irq_stat & NV_INT_DEV))
325 return 0;
326
327 /* DEV interrupt w/ no active qc? */
328 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
329 ata_check_status(ap);
330 return 1;
331 }
332
333 /* handle interrupt */
334 handled = ata_host_intr(ap, qc);
335 if (unlikely(!handled)) {
336 /* spurious, clear it */
337 ata_check_status(ap);
338 }
339
340 return 1;
341}
342
Jeff Garzikcca39742006-08-24 03:19:22 -0400343static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat)
Tejun Heoada364e2006-06-17 15:49:56 +0900344{
345 int i, handled = 0;
346
Jeff Garzikcca39742006-08-24 03:19:22 -0400347 for (i = 0; i < host->n_ports; i++) {
348 struct ata_port *ap = host->ports[i];
Tejun Heoada364e2006-06-17 15:49:56 +0900349
350 if (ap && !(ap->flags & ATA_FLAG_DISABLED))
351 handled += nv_host_intr(ap, irq_stat);
352
353 irq_stat >>= NV_INT_PORT_SHIFT;
354 }
355
356 return IRQ_RETVAL(handled);
357}
358
359static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance,
360 struct pt_regs *regs)
361{
Jeff Garzikcca39742006-08-24 03:19:22 -0400362 struct ata_host *host = dev_instance;
Tejun Heoada364e2006-06-17 15:49:56 +0900363 u8 irq_stat;
364 irqreturn_t ret;
365
Jeff Garzikcca39742006-08-24 03:19:22 -0400366 spin_lock(&host->lock);
367 irq_stat = inb(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
368 ret = nv_do_interrupt(host, irq_stat);
369 spin_unlock(&host->lock);
Tejun Heoada364e2006-06-17 15:49:56 +0900370
371 return ret;
372}
373
374static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance,
375 struct pt_regs *regs)
376{
Jeff Garzikcca39742006-08-24 03:19:22 -0400377 struct ata_host *host = dev_instance;
Tejun Heoada364e2006-06-17 15:49:56 +0900378 u8 irq_stat;
379 irqreturn_t ret;
380
Jeff Garzikcca39742006-08-24 03:19:22 -0400381 spin_lock(&host->lock);
382 irq_stat = readb(host->mmio_base + NV_INT_STATUS_CK804);
383 ret = nv_do_interrupt(host, irq_stat);
384 spin_unlock(&host->lock);
Tejun Heoada364e2006-06-17 15:49:56 +0900385
386 return ret;
387}
388
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
390{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391 if (sc_reg > SCR_CONTROL)
392 return 0xffffffffU;
393
Jeff Garzik02cbd922006-03-22 23:59:46 -0500394 return ioread32((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395}
396
397static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
398{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399 if (sc_reg > SCR_CONTROL)
400 return;
401
Jeff Garzik02cbd922006-03-22 23:59:46 -0500402 iowrite32(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403}
404
Tejun Heo39f87582006-06-17 15:49:56 +0900405static void nv_nf2_freeze(struct ata_port *ap)
406{
Jeff Garzikcca39742006-08-24 03:19:22 -0400407 unsigned long scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
Tejun Heo39f87582006-06-17 15:49:56 +0900408 int shift = ap->port_no * NV_INT_PORT_SHIFT;
409 u8 mask;
410
411 mask = inb(scr_addr + NV_INT_ENABLE);
412 mask &= ~(NV_INT_ALL << shift);
413 outb(mask, scr_addr + NV_INT_ENABLE);
414}
415
416static void nv_nf2_thaw(struct ata_port *ap)
417{
Jeff Garzikcca39742006-08-24 03:19:22 -0400418 unsigned long scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
Tejun Heo39f87582006-06-17 15:49:56 +0900419 int shift = ap->port_no * NV_INT_PORT_SHIFT;
420 u8 mask;
421
422 outb(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS);
423
424 mask = inb(scr_addr + NV_INT_ENABLE);
425 mask |= (NV_INT_MASK << shift);
426 outb(mask, scr_addr + NV_INT_ENABLE);
427}
428
429static void nv_ck804_freeze(struct ata_port *ap)
430{
Jeff Garzikcca39742006-08-24 03:19:22 -0400431 void __iomem *mmio_base = ap->host->mmio_base;
Tejun Heo39f87582006-06-17 15:49:56 +0900432 int shift = ap->port_no * NV_INT_PORT_SHIFT;
433 u8 mask;
434
435 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
436 mask &= ~(NV_INT_ALL << shift);
437 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
438}
439
440static void nv_ck804_thaw(struct ata_port *ap)
441{
Jeff Garzikcca39742006-08-24 03:19:22 -0400442 void __iomem *mmio_base = ap->host->mmio_base;
Tejun Heo39f87582006-06-17 15:49:56 +0900443 int shift = ap->port_no * NV_INT_PORT_SHIFT;
444 u8 mask;
445
446 writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);
447
448 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
449 mask |= (NV_INT_MASK << shift);
450 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
451}
452
453static int nv_hardreset(struct ata_port *ap, unsigned int *class)
454{
455 unsigned int dummy;
456
457 /* SATA hardreset fails to retrieve proper device signature on
458 * some controllers. Don't classify on hardreset. For more
459 * info, see http://bugme.osdl.org/show_bug.cgi?id=3352
460 */
461 return sata_std_hardreset(ap, &dummy);
462}
463
464static void nv_error_handler(struct ata_port *ap)
465{
466 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
467 nv_hardreset, ata_std_postreset);
468}
469
Linus Torvalds1da177e2005-04-16 15:20:36 -0700470static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
471{
472 static int printed_version = 0;
Jeff Garzik29da9f62006-09-25 21:56:33 -0400473 struct ata_port_info *ppi[2];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474 struct ata_probe_ent *probe_ent;
475 int pci_dev_busy = 0;
476 int rc;
477 u32 bar;
Jeff Garzik02cbd922006-03-22 23:59:46 -0500478 unsigned long base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700479
480 // Make sure this is a SATA controller by counting the number of bars
481 // (NVIDIA SATA controllers will always have six bars). Otherwise,
482 // it's an IDE controller and we ignore it.
483 for (bar=0; bar<6; bar++)
484 if (pci_resource_start(pdev, bar) == 0)
485 return -ENODEV;
486
487 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -0500488 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489
490 rc = pci_enable_device(pdev);
491 if (rc)
492 goto err_out;
493
494 rc = pci_request_regions(pdev, DRV_NAME);
495 if (rc) {
496 pci_dev_busy = 1;
497 goto err_out_disable;
498 }
499
500 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
501 if (rc)
502 goto err_out_regions;
503 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
504 if (rc)
505 goto err_out_regions;
506
507 rc = -ENOMEM;
508
Jeff Garzik29da9f62006-09-25 21:56:33 -0400509 ppi[0] = ppi[1] = &nv_port_info[ent->driver_data];
510 probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700511 if (!probe_ent)
512 goto err_out_regions;
513
Jeff Garzik02cbd922006-03-22 23:59:46 -0500514 probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
515 if (!probe_ent->mmio_base) {
516 rc = -EIO;
Tejun Heoe6faf082006-06-17 15:49:55 +0900517 goto err_out_free_ent;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700518 }
519
Jeff Garzik02cbd922006-03-22 23:59:46 -0500520 base = (unsigned long)probe_ent->mmio_base;
521
522 probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
523 probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
524
Tejun Heoada364e2006-06-17 15:49:56 +0900525 /* enable SATA space for CK804 */
526 if (ent->driver_data == CK804) {
527 u8 regval;
528
529 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
530 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
531 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
532 }
533
Linus Torvalds1da177e2005-04-16 15:20:36 -0700534 pci_set_master(pdev);
535
536 rc = ata_device_add(probe_ent);
537 if (rc != NV_PORTS)
538 goto err_out_iounmap;
539
Linus Torvalds1da177e2005-04-16 15:20:36 -0700540 kfree(probe_ent);
541
542 return 0;
543
544err_out_iounmap:
Jeff Garzik02cbd922006-03-22 23:59:46 -0500545 pci_iounmap(pdev, probe_ent->mmio_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700546err_out_free_ent:
547 kfree(probe_ent);
548err_out_regions:
549 pci_release_regions(pdev);
550err_out_disable:
551 if (!pci_dev_busy)
552 pci_disable_device(pdev);
553err_out:
554 return rc;
555}
556
Jeff Garzikcca39742006-08-24 03:19:22 -0400557static void nv_ck804_host_stop(struct ata_host *host)
Tejun Heoada364e2006-06-17 15:49:56 +0900558{
Jeff Garzikcca39742006-08-24 03:19:22 -0400559 struct pci_dev *pdev = to_pci_dev(host->dev);
Tejun Heoada364e2006-06-17 15:49:56 +0900560 u8 regval;
561
562 /* disable SATA space for CK804 */
563 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
564 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
565 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
566
Jeff Garzikcca39742006-08-24 03:19:22 -0400567 ata_pci_host_stop(host);
Tejun Heoada364e2006-06-17 15:49:56 +0900568}
569
Linus Torvalds1da177e2005-04-16 15:20:36 -0700570static int __init nv_init(void)
571{
Pavel Roskinb7887192006-08-10 18:13:18 +0900572 return pci_register_driver(&nv_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700573}
574
575static void __exit nv_exit(void)
576{
577 pci_unregister_driver(&nv_pci_driver);
578}
579
580module_init(nv_init);
581module_exit(nv_exit);