Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; version 2 of the License. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program; if not, write to the Free Software |
| 15 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. |
| 16 | */ |
| 17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 18 | #include <linux/kernel.h> |
| 19 | #include <linux/module.h> |
| 20 | #include <linux/pci.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/errno.h> |
| 23 | #include <linux/list.h> |
| 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/usb/ch9.h> |
| 26 | #include <linux/usb/gadget.h> |
| 27 | |
| 28 | /* Address offset of Registers */ |
| 29 | #define UDC_EP_REG_SHIFT 0x20 /* Offset to next EP */ |
| 30 | |
| 31 | #define UDC_EPCTL_ADDR 0x00 /* Endpoint control */ |
| 32 | #define UDC_EPSTS_ADDR 0x04 /* Endpoint status */ |
| 33 | #define UDC_BUFIN_FRAMENUM_ADDR 0x08 /* buffer size in / frame number out */ |
| 34 | #define UDC_BUFOUT_MAXPKT_ADDR 0x0C /* buffer size out / maxpkt in */ |
| 35 | #define UDC_SUBPTR_ADDR 0x10 /* setup buffer pointer */ |
| 36 | #define UDC_DESPTR_ADDR 0x14 /* Data descriptor pointer */ |
| 37 | #define UDC_CONFIRM_ADDR 0x18 /* Write/Read confirmation */ |
| 38 | |
| 39 | #define UDC_DEVCFG_ADDR 0x400 /* Device configuration */ |
| 40 | #define UDC_DEVCTL_ADDR 0x404 /* Device control */ |
| 41 | #define UDC_DEVSTS_ADDR 0x408 /* Device status */ |
| 42 | #define UDC_DEVIRQSTS_ADDR 0x40C /* Device irq status */ |
| 43 | #define UDC_DEVIRQMSK_ADDR 0x410 /* Device irq mask */ |
| 44 | #define UDC_EPIRQSTS_ADDR 0x414 /* Endpoint irq status */ |
| 45 | #define UDC_EPIRQMSK_ADDR 0x418 /* Endpoint irq mask */ |
| 46 | #define UDC_DEVLPM_ADDR 0x41C /* LPM control / status */ |
| 47 | #define UDC_CSR_BUSY_ADDR 0x4f0 /* UDC_CSR_BUSY Status register */ |
| 48 | #define UDC_SRST_ADDR 0x4fc /* SOFT RESET register */ |
| 49 | #define UDC_CSR_ADDR 0x500 /* USB_DEVICE endpoint register */ |
| 50 | |
| 51 | /* Endpoint control register */ |
| 52 | /* Bit position */ |
| 53 | #define UDC_EPCTL_MRXFLUSH (1 << 12) |
| 54 | #define UDC_EPCTL_RRDY (1 << 9) |
| 55 | #define UDC_EPCTL_CNAK (1 << 8) |
| 56 | #define UDC_EPCTL_SNAK (1 << 7) |
| 57 | #define UDC_EPCTL_NAK (1 << 6) |
| 58 | #define UDC_EPCTL_P (1 << 3) |
| 59 | #define UDC_EPCTL_F (1 << 1) |
| 60 | #define UDC_EPCTL_S (1 << 0) |
| 61 | #define UDC_EPCTL_ET_SHIFT 4 |
| 62 | /* Mask patern */ |
| 63 | #define UDC_EPCTL_ET_MASK 0x00000030 |
| 64 | /* Value for ET field */ |
| 65 | #define UDC_EPCTL_ET_CONTROL 0 |
| 66 | #define UDC_EPCTL_ET_ISO 1 |
| 67 | #define UDC_EPCTL_ET_BULK 2 |
| 68 | #define UDC_EPCTL_ET_INTERRUPT 3 |
| 69 | |
| 70 | /* Endpoint status register */ |
| 71 | /* Bit position */ |
| 72 | #define UDC_EPSTS_XFERDONE (1 << 27) |
| 73 | #define UDC_EPSTS_RSS (1 << 26) |
| 74 | #define UDC_EPSTS_RCS (1 << 25) |
| 75 | #define UDC_EPSTS_TXEMPTY (1 << 24) |
| 76 | #define UDC_EPSTS_TDC (1 << 10) |
| 77 | #define UDC_EPSTS_HE (1 << 9) |
| 78 | #define UDC_EPSTS_MRXFIFO_EMP (1 << 8) |
| 79 | #define UDC_EPSTS_BNA (1 << 7) |
| 80 | #define UDC_EPSTS_IN (1 << 6) |
| 81 | #define UDC_EPSTS_OUT_SHIFT 4 |
| 82 | /* Mask patern */ |
| 83 | #define UDC_EPSTS_OUT_MASK 0x00000030 |
| 84 | #define UDC_EPSTS_ALL_CLR_MASK 0x1F0006F0 |
| 85 | /* Value for OUT field */ |
| 86 | #define UDC_EPSTS_OUT_SETUP 2 |
| 87 | #define UDC_EPSTS_OUT_DATA 1 |
| 88 | |
| 89 | /* Device configuration register */ |
| 90 | /* Bit position */ |
| 91 | #define UDC_DEVCFG_CSR_PRG (1 << 17) |
| 92 | #define UDC_DEVCFG_SP (1 << 3) |
| 93 | /* SPD Valee */ |
| 94 | #define UDC_DEVCFG_SPD_HS 0x0 |
| 95 | #define UDC_DEVCFG_SPD_FS 0x1 |
| 96 | #define UDC_DEVCFG_SPD_LS 0x2 |
| 97 | |
| 98 | /* Device control register */ |
| 99 | /* Bit position */ |
| 100 | #define UDC_DEVCTL_THLEN_SHIFT 24 |
| 101 | #define UDC_DEVCTL_BRLEN_SHIFT 16 |
| 102 | #define UDC_DEVCTL_CSR_DONE (1 << 13) |
| 103 | #define UDC_DEVCTL_SD (1 << 10) |
| 104 | #define UDC_DEVCTL_MODE (1 << 9) |
| 105 | #define UDC_DEVCTL_BREN (1 << 8) |
| 106 | #define UDC_DEVCTL_THE (1 << 7) |
| 107 | #define UDC_DEVCTL_DU (1 << 4) |
| 108 | #define UDC_DEVCTL_TDE (1 << 3) |
| 109 | #define UDC_DEVCTL_RDE (1 << 2) |
| 110 | #define UDC_DEVCTL_RES (1 << 0) |
| 111 | |
| 112 | /* Device status register */ |
| 113 | /* Bit position */ |
| 114 | #define UDC_DEVSTS_TS_SHIFT 18 |
| 115 | #define UDC_DEVSTS_ENUM_SPEED_SHIFT 13 |
| 116 | #define UDC_DEVSTS_ALT_SHIFT 8 |
| 117 | #define UDC_DEVSTS_INTF_SHIFT 4 |
| 118 | #define UDC_DEVSTS_CFG_SHIFT 0 |
| 119 | /* Mask patern */ |
| 120 | #define UDC_DEVSTS_TS_MASK 0xfffc0000 |
| 121 | #define UDC_DEVSTS_ENUM_SPEED_MASK 0x00006000 |
| 122 | #define UDC_DEVSTS_ALT_MASK 0x00000f00 |
| 123 | #define UDC_DEVSTS_INTF_MASK 0x000000f0 |
| 124 | #define UDC_DEVSTS_CFG_MASK 0x0000000f |
| 125 | /* value for maximum speed for SPEED field */ |
| 126 | #define UDC_DEVSTS_ENUM_SPEED_FULL 1 |
| 127 | #define UDC_DEVSTS_ENUM_SPEED_HIGH 0 |
| 128 | #define UDC_DEVSTS_ENUM_SPEED_LOW 2 |
| 129 | #define UDC_DEVSTS_ENUM_SPEED_FULLX 3 |
| 130 | |
| 131 | /* Device irq register */ |
| 132 | /* Bit position */ |
| 133 | #define UDC_DEVINT_RWKP (1 << 7) |
| 134 | #define UDC_DEVINT_ENUM (1 << 6) |
| 135 | #define UDC_DEVINT_SOF (1 << 5) |
| 136 | #define UDC_DEVINT_US (1 << 4) |
| 137 | #define UDC_DEVINT_UR (1 << 3) |
| 138 | #define UDC_DEVINT_ES (1 << 2) |
| 139 | #define UDC_DEVINT_SI (1 << 1) |
| 140 | #define UDC_DEVINT_SC (1 << 0) |
| 141 | /* Mask patern */ |
| 142 | #define UDC_DEVINT_MSK 0x7f |
| 143 | |
| 144 | /* Endpoint irq register */ |
| 145 | /* Bit position */ |
| 146 | #define UDC_EPINT_IN_SHIFT 0 |
| 147 | #define UDC_EPINT_OUT_SHIFT 16 |
| 148 | #define UDC_EPINT_IN_EP0 (1 << 0) |
| 149 | #define UDC_EPINT_OUT_EP0 (1 << 16) |
| 150 | /* Mask patern */ |
| 151 | #define UDC_EPINT_MSK_DISABLE_ALL 0xffffffff |
| 152 | |
| 153 | /* UDC_CSR_BUSY Status register */ |
| 154 | /* Bit position */ |
| 155 | #define UDC_CSR_BUSY (1 << 0) |
| 156 | |
| 157 | /* SOFT RESET register */ |
| 158 | /* Bit position */ |
| 159 | #define UDC_PSRST (1 << 1) |
| 160 | #define UDC_SRST (1 << 0) |
| 161 | |
| 162 | /* USB_DEVICE endpoint register */ |
| 163 | /* Bit position */ |
| 164 | #define UDC_CSR_NE_NUM_SHIFT 0 |
| 165 | #define UDC_CSR_NE_DIR_SHIFT 4 |
| 166 | #define UDC_CSR_NE_TYPE_SHIFT 5 |
| 167 | #define UDC_CSR_NE_CFG_SHIFT 7 |
| 168 | #define UDC_CSR_NE_INTF_SHIFT 11 |
| 169 | #define UDC_CSR_NE_ALT_SHIFT 15 |
| 170 | #define UDC_CSR_NE_MAX_PKT_SHIFT 19 |
| 171 | /* Mask patern */ |
| 172 | #define UDC_CSR_NE_NUM_MASK 0x0000000f |
| 173 | #define UDC_CSR_NE_DIR_MASK 0x00000010 |
| 174 | #define UDC_CSR_NE_TYPE_MASK 0x00000060 |
| 175 | #define UDC_CSR_NE_CFG_MASK 0x00000780 |
| 176 | #define UDC_CSR_NE_INTF_MASK 0x00007800 |
| 177 | #define UDC_CSR_NE_ALT_MASK 0x00078000 |
| 178 | #define UDC_CSR_NE_MAX_PKT_MASK 0x3ff80000 |
| 179 | |
| 180 | #define PCH_UDC_CSR(ep) (UDC_CSR_ADDR + ep*4) |
| 181 | #define PCH_UDC_EPINT(in, num)\ |
| 182 | (1 << (num + (in ? UDC_EPINT_IN_SHIFT : UDC_EPINT_OUT_SHIFT))) |
| 183 | |
| 184 | /* Index of endpoint */ |
| 185 | #define UDC_EP0IN_IDX 0 |
| 186 | #define UDC_EP0OUT_IDX 1 |
| 187 | #define UDC_EPIN_IDX(ep) (ep * 2) |
| 188 | #define UDC_EPOUT_IDX(ep) (ep * 2 + 1) |
| 189 | #define PCH_UDC_EP0 0 |
| 190 | #define PCH_UDC_EP1 1 |
| 191 | #define PCH_UDC_EP2 2 |
| 192 | #define PCH_UDC_EP3 3 |
| 193 | |
| 194 | /* Number of endpoint */ |
| 195 | #define PCH_UDC_EP_NUM 32 /* Total number of EPs (16 IN,16 OUT) */ |
| 196 | #define PCH_UDC_USED_EP_NUM 4 /* EP number of EP's really used */ |
| 197 | /* Length Value */ |
| 198 | #define PCH_UDC_BRLEN 0x0F /* Burst length */ |
| 199 | #define PCH_UDC_THLEN 0x1F /* Threshold length */ |
| 200 | /* Value of EP Buffer Size */ |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 201 | #define UDC_EP0IN_BUFF_SIZE 16 |
| 202 | #define UDC_EPIN_BUFF_SIZE 256 |
| 203 | #define UDC_EP0OUT_BUFF_SIZE 16 |
| 204 | #define UDC_EPOUT_BUFF_SIZE 256 |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 205 | /* Value of EP maximum packet size */ |
| 206 | #define UDC_EP0IN_MAX_PKT_SIZE 64 |
| 207 | #define UDC_EP0OUT_MAX_PKT_SIZE 64 |
| 208 | #define UDC_BULK_MAX_PKT_SIZE 512 |
| 209 | |
| 210 | /* DMA */ |
| 211 | #define DMA_DIR_RX 1 /* DMA for data receive */ |
| 212 | #define DMA_DIR_TX 2 /* DMA for data transmit */ |
| 213 | #define DMA_ADDR_INVALID (~(dma_addr_t)0) |
| 214 | #define UDC_DMA_MAXPACKET 65536 /* maximum packet size for DMA */ |
| 215 | |
| 216 | /** |
| 217 | * struct pch_udc_data_dma_desc - Structure to hold DMA descriptor information |
| 218 | * for data |
| 219 | * @status: Status quadlet |
| 220 | * @reserved: Reserved |
| 221 | * @dataptr: Buffer descriptor |
| 222 | * @next: Next descriptor |
| 223 | */ |
| 224 | struct pch_udc_data_dma_desc { |
| 225 | u32 status; |
| 226 | u32 reserved; |
| 227 | u32 dataptr; |
| 228 | u32 next; |
| 229 | }; |
| 230 | |
| 231 | /** |
| 232 | * struct pch_udc_stp_dma_desc - Structure to hold DMA descriptor information |
| 233 | * for control data |
| 234 | * @status: Status |
| 235 | * @reserved: Reserved |
| 236 | * @data12: First setup word |
| 237 | * @data34: Second setup word |
| 238 | */ |
| 239 | struct pch_udc_stp_dma_desc { |
| 240 | u32 status; |
| 241 | u32 reserved; |
| 242 | struct usb_ctrlrequest request; |
| 243 | } __attribute((packed)); |
| 244 | |
| 245 | /* DMA status definitions */ |
| 246 | /* Buffer status */ |
| 247 | #define PCH_UDC_BUFF_STS 0xC0000000 |
| 248 | #define PCH_UDC_BS_HST_RDY 0x00000000 |
| 249 | #define PCH_UDC_BS_DMA_BSY 0x40000000 |
| 250 | #define PCH_UDC_BS_DMA_DONE 0x80000000 |
| 251 | #define PCH_UDC_BS_HST_BSY 0xC0000000 |
| 252 | /* Rx/Tx Status */ |
| 253 | #define PCH_UDC_RXTX_STS 0x30000000 |
| 254 | #define PCH_UDC_RTS_SUCC 0x00000000 |
| 255 | #define PCH_UDC_RTS_DESERR 0x10000000 |
| 256 | #define PCH_UDC_RTS_BUFERR 0x30000000 |
| 257 | /* Last Descriptor Indication */ |
| 258 | #define PCH_UDC_DMA_LAST 0x08000000 |
| 259 | /* Number of Rx/Tx Bytes Mask */ |
| 260 | #define PCH_UDC_RXTX_BYTES 0x0000ffff |
| 261 | |
| 262 | /** |
| 263 | * struct pch_udc_cfg_data - Structure to hold current configuration |
| 264 | * and interface information |
| 265 | * @cur_cfg: current configuration in use |
| 266 | * @cur_intf: current interface in use |
| 267 | * @cur_alt: current alt interface in use |
| 268 | */ |
| 269 | struct pch_udc_cfg_data { |
| 270 | u16 cur_cfg; |
| 271 | u16 cur_intf; |
| 272 | u16 cur_alt; |
| 273 | }; |
| 274 | |
| 275 | /** |
| 276 | * struct pch_udc_ep - Structure holding a PCH USB device Endpoint information |
| 277 | * @ep: embedded ep request |
| 278 | * @td_stp_phys: for setup request |
| 279 | * @td_data_phys: for data request |
| 280 | * @td_stp: for setup request |
| 281 | * @td_data: for data request |
| 282 | * @dev: reference to device struct |
| 283 | * @offset_addr: offset address of ep register |
| 284 | * @desc: for this ep |
| 285 | * @queue: queue for requests |
| 286 | * @num: endpoint number |
| 287 | * @in: endpoint is IN |
| 288 | * @halted: endpoint halted? |
| 289 | * @epsts: Endpoint status |
| 290 | */ |
| 291 | struct pch_udc_ep { |
| 292 | struct usb_ep ep; |
| 293 | dma_addr_t td_stp_phys; |
| 294 | dma_addr_t td_data_phys; |
| 295 | struct pch_udc_stp_dma_desc *td_stp; |
| 296 | struct pch_udc_data_dma_desc *td_data; |
| 297 | struct pch_udc_dev *dev; |
| 298 | unsigned long offset_addr; |
| 299 | const struct usb_endpoint_descriptor *desc; |
| 300 | struct list_head queue; |
| 301 | unsigned num:5, |
| 302 | in:1, |
| 303 | halted:1; |
| 304 | unsigned long epsts; |
| 305 | }; |
| 306 | |
| 307 | /** |
| 308 | * struct pch_udc_dev - Structure holding complete information |
| 309 | * of the PCH USB device |
| 310 | * @gadget: gadget driver data |
| 311 | * @driver: reference to gadget driver bound |
| 312 | * @pdev: reference to the PCI device |
| 313 | * @ep: array of endpoints |
| 314 | * @lock: protects all state |
| 315 | * @active: enabled the PCI device |
| 316 | * @stall: stall requested |
| 317 | * @prot_stall: protcol stall requested |
| 318 | * @irq_registered: irq registered with system |
| 319 | * @mem_region: device memory mapped |
| 320 | * @registered: driver regsitered with system |
| 321 | * @suspended: driver in suspended state |
| 322 | * @connected: gadget driver associated |
| 323 | * @set_cfg_not_acked: pending acknowledgement 4 setup |
| 324 | * @waiting_zlp_ack: pending acknowledgement 4 ZLP |
| 325 | * @data_requests: DMA pool for data requests |
| 326 | * @stp_requests: DMA pool for setup requests |
| 327 | * @dma_addr: DMA pool for received |
| 328 | * @ep0out_buf: Buffer for DMA |
| 329 | * @setup_data: Received setup data |
| 330 | * @phys_addr: of device memory |
| 331 | * @base_addr: for mapped device memory |
| 332 | * @irq: IRQ line for the device |
| 333 | * @cfg_data: current cfg, intf, and alt in use |
| 334 | */ |
| 335 | struct pch_udc_dev { |
| 336 | struct usb_gadget gadget; |
| 337 | struct usb_gadget_driver *driver; |
| 338 | struct pci_dev *pdev; |
| 339 | struct pch_udc_ep ep[PCH_UDC_EP_NUM]; |
Richard Röjfors | 49e2083 | 2010-12-07 17:28:30 +0100 | [diff] [blame] | 340 | spinlock_t lock; /* protects all state */ |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 341 | unsigned active:1, |
| 342 | stall:1, |
| 343 | prot_stall:1, |
| 344 | irq_registered:1, |
| 345 | mem_region:1, |
| 346 | registered:1, |
| 347 | suspended:1, |
| 348 | connected:1, |
| 349 | set_cfg_not_acked:1, |
| 350 | waiting_zlp_ack:1; |
| 351 | struct pci_pool *data_requests; |
| 352 | struct pci_pool *stp_requests; |
| 353 | dma_addr_t dma_addr; |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 354 | void *ep0out_buf; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 355 | struct usb_ctrlrequest setup_data; |
| 356 | unsigned long phys_addr; |
| 357 | void __iomem *base_addr; |
| 358 | unsigned irq; |
| 359 | struct pch_udc_cfg_data cfg_data; |
| 360 | }; |
| 361 | |
| 362 | #define PCH_UDC_PCI_BAR 1 |
| 363 | #define PCI_DEVICE_ID_INTEL_EG20T_UDC 0x8808 |
Tomoya MORINAGA | 06f1b97 | 2011-01-06 09:16:31 +0900 | [diff] [blame] | 364 | #define PCI_VENDOR_ID_ROHM 0x10DB |
| 365 | #define PCI_DEVICE_ID_ML7213_IOH_UDC 0x801D |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 366 | |
| 367 | static const char ep0_string[] = "ep0in"; |
| 368 | static DEFINE_SPINLOCK(udc_stall_spinlock); /* stall spin lock */ |
| 369 | struct pch_udc_dev *pch_udc; /* pointer to device object */ |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 370 | static int speed_fs; |
| 371 | module_param_named(speed_fs, speed_fs, bool, S_IRUGO); |
| 372 | MODULE_PARM_DESC(speed_fs, "true for Full speed operation"); |
| 373 | |
| 374 | /** |
| 375 | * struct pch_udc_request - Structure holding a PCH USB device request packet |
| 376 | * @req: embedded ep request |
| 377 | * @td_data_phys: phys. address |
| 378 | * @td_data: first dma desc. of chain |
| 379 | * @td_data_last: last dma desc. of chain |
| 380 | * @queue: associated queue |
| 381 | * @dma_going: DMA in progress for request |
| 382 | * @dma_mapped: DMA memory mapped for request |
| 383 | * @dma_done: DMA completed for request |
| 384 | * @chain_len: chain length |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 385 | * @buf: Buffer memory for align adjustment |
| 386 | * @dma: DMA memory for align adjustment |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 387 | */ |
| 388 | struct pch_udc_request { |
| 389 | struct usb_request req; |
| 390 | dma_addr_t td_data_phys; |
| 391 | struct pch_udc_data_dma_desc *td_data; |
| 392 | struct pch_udc_data_dma_desc *td_data_last; |
| 393 | struct list_head queue; |
| 394 | unsigned dma_going:1, |
| 395 | dma_mapped:1, |
| 396 | dma_done:1; |
| 397 | unsigned chain_len; |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 398 | void *buf; |
| 399 | dma_addr_t dma; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 400 | }; |
| 401 | |
| 402 | static inline u32 pch_udc_readl(struct pch_udc_dev *dev, unsigned long reg) |
| 403 | { |
| 404 | return ioread32(dev->base_addr + reg); |
| 405 | } |
| 406 | |
| 407 | static inline void pch_udc_writel(struct pch_udc_dev *dev, |
| 408 | unsigned long val, unsigned long reg) |
| 409 | { |
| 410 | iowrite32(val, dev->base_addr + reg); |
| 411 | } |
| 412 | |
| 413 | static inline void pch_udc_bit_set(struct pch_udc_dev *dev, |
| 414 | unsigned long reg, |
| 415 | unsigned long bitmask) |
| 416 | { |
| 417 | pch_udc_writel(dev, pch_udc_readl(dev, reg) | bitmask, reg); |
| 418 | } |
| 419 | |
| 420 | static inline void pch_udc_bit_clr(struct pch_udc_dev *dev, |
| 421 | unsigned long reg, |
| 422 | unsigned long bitmask) |
| 423 | { |
| 424 | pch_udc_writel(dev, pch_udc_readl(dev, reg) & ~(bitmask), reg); |
| 425 | } |
| 426 | |
| 427 | static inline u32 pch_udc_ep_readl(struct pch_udc_ep *ep, unsigned long reg) |
| 428 | { |
| 429 | return ioread32(ep->dev->base_addr + ep->offset_addr + reg); |
| 430 | } |
| 431 | |
| 432 | static inline void pch_udc_ep_writel(struct pch_udc_ep *ep, |
| 433 | unsigned long val, unsigned long reg) |
| 434 | { |
| 435 | iowrite32(val, ep->dev->base_addr + ep->offset_addr + reg); |
| 436 | } |
| 437 | |
| 438 | static inline void pch_udc_ep_bit_set(struct pch_udc_ep *ep, |
| 439 | unsigned long reg, |
| 440 | unsigned long bitmask) |
| 441 | { |
| 442 | pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) | bitmask, reg); |
| 443 | } |
| 444 | |
| 445 | static inline void pch_udc_ep_bit_clr(struct pch_udc_ep *ep, |
| 446 | unsigned long reg, |
| 447 | unsigned long bitmask) |
| 448 | { |
| 449 | pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) & ~(bitmask), reg); |
| 450 | } |
| 451 | |
| 452 | /** |
| 453 | * pch_udc_csr_busy() - Wait till idle. |
| 454 | * @dev: Reference to pch_udc_dev structure |
| 455 | */ |
| 456 | static void pch_udc_csr_busy(struct pch_udc_dev *dev) |
| 457 | { |
| 458 | unsigned int count = 200; |
| 459 | |
| 460 | /* Wait till idle */ |
| 461 | while ((pch_udc_readl(dev, UDC_CSR_BUSY_ADDR) & UDC_CSR_BUSY) |
| 462 | && --count) |
| 463 | cpu_relax(); |
| 464 | if (!count) |
| 465 | dev_err(&dev->pdev->dev, "%s: wait error\n", __func__); |
| 466 | } |
| 467 | |
| 468 | /** |
| 469 | * pch_udc_write_csr() - Write the command and status registers. |
| 470 | * @dev: Reference to pch_udc_dev structure |
| 471 | * @val: value to be written to CSR register |
| 472 | * @addr: address of CSR register |
| 473 | */ |
| 474 | static void pch_udc_write_csr(struct pch_udc_dev *dev, unsigned long val, |
| 475 | unsigned int ep) |
| 476 | { |
| 477 | unsigned long reg = PCH_UDC_CSR(ep); |
| 478 | |
| 479 | pch_udc_csr_busy(dev); /* Wait till idle */ |
| 480 | pch_udc_writel(dev, val, reg); |
| 481 | pch_udc_csr_busy(dev); /* Wait till idle */ |
| 482 | } |
| 483 | |
| 484 | /** |
| 485 | * pch_udc_read_csr() - Read the command and status registers. |
| 486 | * @dev: Reference to pch_udc_dev structure |
| 487 | * @addr: address of CSR register |
| 488 | * |
| 489 | * Return codes: content of CSR register |
| 490 | */ |
| 491 | static u32 pch_udc_read_csr(struct pch_udc_dev *dev, unsigned int ep) |
| 492 | { |
| 493 | unsigned long reg = PCH_UDC_CSR(ep); |
| 494 | |
| 495 | pch_udc_csr_busy(dev); /* Wait till idle */ |
| 496 | pch_udc_readl(dev, reg); /* Dummy read */ |
| 497 | pch_udc_csr_busy(dev); /* Wait till idle */ |
| 498 | return pch_udc_readl(dev, reg); |
| 499 | } |
| 500 | |
| 501 | /** |
| 502 | * pch_udc_rmt_wakeup() - Initiate for remote wakeup |
| 503 | * @dev: Reference to pch_udc_dev structure |
| 504 | */ |
| 505 | static inline void pch_udc_rmt_wakeup(struct pch_udc_dev *dev) |
| 506 | { |
| 507 | pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES); |
| 508 | mdelay(1); |
| 509 | pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES); |
| 510 | } |
| 511 | |
| 512 | /** |
| 513 | * pch_udc_get_frame() - Get the current frame from device status register |
| 514 | * @dev: Reference to pch_udc_dev structure |
| 515 | * Retern current frame |
| 516 | */ |
| 517 | static inline int pch_udc_get_frame(struct pch_udc_dev *dev) |
| 518 | { |
| 519 | u32 frame = pch_udc_readl(dev, UDC_DEVSTS_ADDR); |
| 520 | return (frame & UDC_DEVSTS_TS_MASK) >> UDC_DEVSTS_TS_SHIFT; |
| 521 | } |
| 522 | |
| 523 | /** |
| 524 | * pch_udc_clear_selfpowered() - Clear the self power control |
| 525 | * @dev: Reference to pch_udc_regs structure |
| 526 | */ |
| 527 | static inline void pch_udc_clear_selfpowered(struct pch_udc_dev *dev) |
| 528 | { |
| 529 | pch_udc_bit_clr(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP); |
| 530 | } |
| 531 | |
| 532 | /** |
| 533 | * pch_udc_set_selfpowered() - Set the self power control |
| 534 | * @dev: Reference to pch_udc_regs structure |
| 535 | */ |
| 536 | static inline void pch_udc_set_selfpowered(struct pch_udc_dev *dev) |
| 537 | { |
| 538 | pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP); |
| 539 | } |
| 540 | |
| 541 | /** |
| 542 | * pch_udc_set_disconnect() - Set the disconnect status. |
| 543 | * @dev: Reference to pch_udc_regs structure |
| 544 | */ |
| 545 | static inline void pch_udc_set_disconnect(struct pch_udc_dev *dev) |
| 546 | { |
| 547 | pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD); |
| 548 | } |
| 549 | |
| 550 | /** |
| 551 | * pch_udc_clear_disconnect() - Clear the disconnect status. |
| 552 | * @dev: Reference to pch_udc_regs structure |
| 553 | */ |
| 554 | static void pch_udc_clear_disconnect(struct pch_udc_dev *dev) |
| 555 | { |
| 556 | /* Clear the disconnect */ |
| 557 | pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES); |
| 558 | pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD); |
| 559 | mdelay(1); |
| 560 | /* Resume USB signalling */ |
| 561 | pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES); |
| 562 | } |
| 563 | |
| 564 | /** |
| 565 | * pch_udc_vbus_session() - set or clearr the disconnect status. |
| 566 | * @dev: Reference to pch_udc_regs structure |
| 567 | * @is_active: Parameter specifying the action |
| 568 | * 0: indicating VBUS power is ending |
| 569 | * !0: indicating VBUS power is starting |
| 570 | */ |
| 571 | static inline void pch_udc_vbus_session(struct pch_udc_dev *dev, |
| 572 | int is_active) |
| 573 | { |
| 574 | if (is_active) |
| 575 | pch_udc_clear_disconnect(dev); |
| 576 | else |
| 577 | pch_udc_set_disconnect(dev); |
| 578 | } |
| 579 | |
| 580 | /** |
| 581 | * pch_udc_ep_set_stall() - Set the stall of endpoint |
| 582 | * @ep: Reference to structure of type pch_udc_ep_regs |
| 583 | */ |
| 584 | static void pch_udc_ep_set_stall(struct pch_udc_ep *ep) |
| 585 | { |
| 586 | if (ep->in) { |
| 587 | pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F); |
| 588 | pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S); |
| 589 | } else { |
| 590 | pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S); |
| 591 | } |
| 592 | } |
| 593 | |
| 594 | /** |
| 595 | * pch_udc_ep_clear_stall() - Clear the stall of endpoint |
| 596 | * @ep: Reference to structure of type pch_udc_ep_regs |
| 597 | */ |
| 598 | static inline void pch_udc_ep_clear_stall(struct pch_udc_ep *ep) |
| 599 | { |
| 600 | /* Clear the stall */ |
| 601 | pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S); |
| 602 | /* Clear NAK by writing CNAK */ |
| 603 | pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK); |
| 604 | } |
| 605 | |
| 606 | /** |
| 607 | * pch_udc_ep_set_trfr_type() - Set the transfer type of endpoint |
| 608 | * @ep: Reference to structure of type pch_udc_ep_regs |
| 609 | * @type: Type of endpoint |
| 610 | */ |
| 611 | static inline void pch_udc_ep_set_trfr_type(struct pch_udc_ep *ep, |
| 612 | u8 type) |
| 613 | { |
| 614 | pch_udc_ep_writel(ep, ((type << UDC_EPCTL_ET_SHIFT) & |
| 615 | UDC_EPCTL_ET_MASK), UDC_EPCTL_ADDR); |
| 616 | } |
| 617 | |
| 618 | /** |
| 619 | * pch_udc_ep_set_bufsz() - Set the maximum packet size for the endpoint |
| 620 | * @ep: Reference to structure of type pch_udc_ep_regs |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 621 | * @buf_size: The buffer word size |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 622 | */ |
| 623 | static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep, |
| 624 | u32 buf_size, u32 ep_in) |
| 625 | { |
| 626 | u32 data; |
| 627 | if (ep_in) { |
| 628 | data = pch_udc_ep_readl(ep, UDC_BUFIN_FRAMENUM_ADDR); |
| 629 | data = (data & 0xffff0000) | (buf_size & 0xffff); |
| 630 | pch_udc_ep_writel(ep, data, UDC_BUFIN_FRAMENUM_ADDR); |
| 631 | } else { |
| 632 | data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR); |
| 633 | data = (buf_size << 16) | (data & 0xffff); |
| 634 | pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR); |
| 635 | } |
| 636 | } |
| 637 | |
| 638 | /** |
| 639 | * pch_udc_ep_set_maxpkt() - Set the Max packet size for the endpoint |
| 640 | * @ep: Reference to structure of type pch_udc_ep_regs |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 641 | * @pkt_size: The packet byte size |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 642 | */ |
| 643 | static void pch_udc_ep_set_maxpkt(struct pch_udc_ep *ep, u32 pkt_size) |
| 644 | { |
| 645 | u32 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR); |
| 646 | data = (data & 0xffff0000) | (pkt_size & 0xffff); |
| 647 | pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR); |
| 648 | } |
| 649 | |
| 650 | /** |
| 651 | * pch_udc_ep_set_subptr() - Set the Setup buffer pointer for the endpoint |
| 652 | * @ep: Reference to structure of type pch_udc_ep_regs |
| 653 | * @addr: Address of the register |
| 654 | */ |
| 655 | static inline void pch_udc_ep_set_subptr(struct pch_udc_ep *ep, u32 addr) |
| 656 | { |
| 657 | pch_udc_ep_writel(ep, addr, UDC_SUBPTR_ADDR); |
| 658 | } |
| 659 | |
| 660 | /** |
| 661 | * pch_udc_ep_set_ddptr() - Set the Data descriptor pointer for the endpoint |
| 662 | * @ep: Reference to structure of type pch_udc_ep_regs |
| 663 | * @addr: Address of the register |
| 664 | */ |
| 665 | static inline void pch_udc_ep_set_ddptr(struct pch_udc_ep *ep, u32 addr) |
| 666 | { |
| 667 | pch_udc_ep_writel(ep, addr, UDC_DESPTR_ADDR); |
| 668 | } |
| 669 | |
| 670 | /** |
| 671 | * pch_udc_ep_set_pd() - Set the poll demand bit for the endpoint |
| 672 | * @ep: Reference to structure of type pch_udc_ep_regs |
| 673 | */ |
| 674 | static inline void pch_udc_ep_set_pd(struct pch_udc_ep *ep) |
| 675 | { |
| 676 | pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P); |
| 677 | } |
| 678 | |
| 679 | /** |
| 680 | * pch_udc_ep_set_rrdy() - Set the receive ready bit for the endpoint |
| 681 | * @ep: Reference to structure of type pch_udc_ep_regs |
| 682 | */ |
| 683 | static inline void pch_udc_ep_set_rrdy(struct pch_udc_ep *ep) |
| 684 | { |
| 685 | pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY); |
| 686 | } |
| 687 | |
| 688 | /** |
| 689 | * pch_udc_ep_clear_rrdy() - Clear the receive ready bit for the endpoint |
| 690 | * @ep: Reference to structure of type pch_udc_ep_regs |
| 691 | */ |
| 692 | static inline void pch_udc_ep_clear_rrdy(struct pch_udc_ep *ep) |
| 693 | { |
| 694 | pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY); |
| 695 | } |
| 696 | |
| 697 | /** |
| 698 | * pch_udc_set_dma() - Set the 'TDE' or RDE bit of device control |
| 699 | * register depending on the direction specified |
| 700 | * @dev: Reference to structure of type pch_udc_regs |
| 701 | * @dir: whether Tx or Rx |
| 702 | * DMA_DIR_RX: Receive |
| 703 | * DMA_DIR_TX: Transmit |
| 704 | */ |
| 705 | static inline void pch_udc_set_dma(struct pch_udc_dev *dev, int dir) |
| 706 | { |
| 707 | if (dir == DMA_DIR_RX) |
| 708 | pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE); |
| 709 | else if (dir == DMA_DIR_TX) |
| 710 | pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE); |
| 711 | } |
| 712 | |
| 713 | /** |
| 714 | * pch_udc_clear_dma() - Clear the 'TDE' or RDE bit of device control |
| 715 | * register depending on the direction specified |
| 716 | * @dev: Reference to structure of type pch_udc_regs |
| 717 | * @dir: Whether Tx or Rx |
| 718 | * DMA_DIR_RX: Receive |
| 719 | * DMA_DIR_TX: Transmit |
| 720 | */ |
| 721 | static inline void pch_udc_clear_dma(struct pch_udc_dev *dev, int dir) |
| 722 | { |
| 723 | if (dir == DMA_DIR_RX) |
| 724 | pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE); |
| 725 | else if (dir == DMA_DIR_TX) |
| 726 | pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE); |
| 727 | } |
| 728 | |
| 729 | /** |
| 730 | * pch_udc_set_csr_done() - Set the device control register |
| 731 | * CSR done field (bit 13) |
| 732 | * @dev: reference to structure of type pch_udc_regs |
| 733 | */ |
| 734 | static inline void pch_udc_set_csr_done(struct pch_udc_dev *dev) |
| 735 | { |
| 736 | pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_CSR_DONE); |
| 737 | } |
| 738 | |
| 739 | /** |
| 740 | * pch_udc_disable_interrupts() - Disables the specified interrupts |
| 741 | * @dev: Reference to structure of type pch_udc_regs |
| 742 | * @mask: Mask to disable interrupts |
| 743 | */ |
| 744 | static inline void pch_udc_disable_interrupts(struct pch_udc_dev *dev, |
| 745 | u32 mask) |
| 746 | { |
| 747 | pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, mask); |
| 748 | } |
| 749 | |
| 750 | /** |
| 751 | * pch_udc_enable_interrupts() - Enable the specified interrupts |
| 752 | * @dev: Reference to structure of type pch_udc_regs |
| 753 | * @mask: Mask to enable interrupts |
| 754 | */ |
| 755 | static inline void pch_udc_enable_interrupts(struct pch_udc_dev *dev, |
| 756 | u32 mask) |
| 757 | { |
| 758 | pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR, mask); |
| 759 | } |
| 760 | |
| 761 | /** |
| 762 | * pch_udc_disable_ep_interrupts() - Disable endpoint interrupts |
| 763 | * @dev: Reference to structure of type pch_udc_regs |
| 764 | * @mask: Mask to disable interrupts |
| 765 | */ |
| 766 | static inline void pch_udc_disable_ep_interrupts(struct pch_udc_dev *dev, |
| 767 | u32 mask) |
| 768 | { |
| 769 | pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, mask); |
| 770 | } |
| 771 | |
| 772 | /** |
| 773 | * pch_udc_enable_ep_interrupts() - Enable endpoint interrupts |
| 774 | * @dev: Reference to structure of type pch_udc_regs |
| 775 | * @mask: Mask to enable interrupts |
| 776 | */ |
| 777 | static inline void pch_udc_enable_ep_interrupts(struct pch_udc_dev *dev, |
| 778 | u32 mask) |
| 779 | { |
| 780 | pch_udc_bit_clr(dev, UDC_EPIRQMSK_ADDR, mask); |
| 781 | } |
| 782 | |
| 783 | /** |
| 784 | * pch_udc_read_device_interrupts() - Read the device interrupts |
| 785 | * @dev: Reference to structure of type pch_udc_regs |
| 786 | * Retern The device interrupts |
| 787 | */ |
| 788 | static inline u32 pch_udc_read_device_interrupts(struct pch_udc_dev *dev) |
| 789 | { |
| 790 | return pch_udc_readl(dev, UDC_DEVIRQSTS_ADDR); |
| 791 | } |
| 792 | |
| 793 | /** |
| 794 | * pch_udc_write_device_interrupts() - Write device interrupts |
| 795 | * @dev: Reference to structure of type pch_udc_regs |
| 796 | * @val: The value to be written to interrupt register |
| 797 | */ |
| 798 | static inline void pch_udc_write_device_interrupts(struct pch_udc_dev *dev, |
| 799 | u32 val) |
| 800 | { |
| 801 | pch_udc_writel(dev, val, UDC_DEVIRQSTS_ADDR); |
| 802 | } |
| 803 | |
| 804 | /** |
| 805 | * pch_udc_read_ep_interrupts() - Read the endpoint interrupts |
| 806 | * @dev: Reference to structure of type pch_udc_regs |
| 807 | * Retern The endpoint interrupt |
| 808 | */ |
| 809 | static inline u32 pch_udc_read_ep_interrupts(struct pch_udc_dev *dev) |
| 810 | { |
| 811 | return pch_udc_readl(dev, UDC_EPIRQSTS_ADDR); |
| 812 | } |
| 813 | |
| 814 | /** |
| 815 | * pch_udc_write_ep_interrupts() - Clear endpoint interupts |
| 816 | * @dev: Reference to structure of type pch_udc_regs |
| 817 | * @val: The value to be written to interrupt register |
| 818 | */ |
| 819 | static inline void pch_udc_write_ep_interrupts(struct pch_udc_dev *dev, |
| 820 | u32 val) |
| 821 | { |
| 822 | pch_udc_writel(dev, val, UDC_EPIRQSTS_ADDR); |
| 823 | } |
| 824 | |
| 825 | /** |
| 826 | * pch_udc_read_device_status() - Read the device status |
| 827 | * @dev: Reference to structure of type pch_udc_regs |
| 828 | * Retern The device status |
| 829 | */ |
| 830 | static inline u32 pch_udc_read_device_status(struct pch_udc_dev *dev) |
| 831 | { |
| 832 | return pch_udc_readl(dev, UDC_DEVSTS_ADDR); |
| 833 | } |
| 834 | |
| 835 | /** |
| 836 | * pch_udc_read_ep_control() - Read the endpoint control |
| 837 | * @ep: Reference to structure of type pch_udc_ep_regs |
| 838 | * Retern The endpoint control register value |
| 839 | */ |
| 840 | static inline u32 pch_udc_read_ep_control(struct pch_udc_ep *ep) |
| 841 | { |
| 842 | return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR); |
| 843 | } |
| 844 | |
| 845 | /** |
| 846 | * pch_udc_clear_ep_control() - Clear the endpoint control register |
| 847 | * @ep: Reference to structure of type pch_udc_ep_regs |
| 848 | * Retern The endpoint control register value |
| 849 | */ |
| 850 | static inline void pch_udc_clear_ep_control(struct pch_udc_ep *ep) |
| 851 | { |
| 852 | return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR); |
| 853 | } |
| 854 | |
| 855 | /** |
| 856 | * pch_udc_read_ep_status() - Read the endpoint status |
| 857 | * @ep: Reference to structure of type pch_udc_ep_regs |
| 858 | * Retern The endpoint status |
| 859 | */ |
| 860 | static inline u32 pch_udc_read_ep_status(struct pch_udc_ep *ep) |
| 861 | { |
| 862 | return pch_udc_ep_readl(ep, UDC_EPSTS_ADDR); |
| 863 | } |
| 864 | |
| 865 | /** |
| 866 | * pch_udc_clear_ep_status() - Clear the endpoint status |
| 867 | * @ep: Reference to structure of type pch_udc_ep_regs |
| 868 | * @stat: Endpoint status |
| 869 | */ |
| 870 | static inline void pch_udc_clear_ep_status(struct pch_udc_ep *ep, |
| 871 | u32 stat) |
| 872 | { |
| 873 | return pch_udc_ep_writel(ep, stat, UDC_EPSTS_ADDR); |
| 874 | } |
| 875 | |
| 876 | /** |
| 877 | * pch_udc_ep_set_nak() - Set the bit 7 (SNAK field) |
| 878 | * of the endpoint control register |
| 879 | * @ep: Reference to structure of type pch_udc_ep_regs |
| 880 | */ |
| 881 | static inline void pch_udc_ep_set_nak(struct pch_udc_ep *ep) |
| 882 | { |
| 883 | pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK); |
| 884 | } |
| 885 | |
| 886 | /** |
| 887 | * pch_udc_ep_clear_nak() - Set the bit 8 (CNAK field) |
| 888 | * of the endpoint control register |
| 889 | * @ep: reference to structure of type pch_udc_ep_regs |
| 890 | */ |
| 891 | static void pch_udc_ep_clear_nak(struct pch_udc_ep *ep) |
| 892 | { |
| 893 | unsigned int loopcnt = 0; |
| 894 | struct pch_udc_dev *dev = ep->dev; |
| 895 | |
| 896 | if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK)) |
| 897 | return; |
| 898 | if (!ep->in) { |
| 899 | loopcnt = 10000; |
| 900 | while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) && |
| 901 | --loopcnt) |
| 902 | udelay(5); |
| 903 | if (!loopcnt) |
| 904 | dev_err(&dev->pdev->dev, "%s: RxFIFO not Empty\n", |
| 905 | __func__); |
| 906 | } |
| 907 | loopcnt = 10000; |
| 908 | while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_NAK) && --loopcnt) { |
| 909 | pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK); |
| 910 | udelay(5); |
| 911 | } |
| 912 | if (!loopcnt) |
| 913 | dev_err(&dev->pdev->dev, "%s: Clear NAK not set for ep%d%s\n", |
| 914 | __func__, ep->num, (ep->in ? "in" : "out")); |
| 915 | } |
| 916 | |
| 917 | /** |
| 918 | * pch_udc_ep_fifo_flush() - Flush the endpoint fifo |
| 919 | * @ep: reference to structure of type pch_udc_ep_regs |
| 920 | * @dir: direction of endpoint |
| 921 | * 0: endpoint is OUT |
| 922 | * !0: endpoint is IN |
| 923 | */ |
| 924 | static void pch_udc_ep_fifo_flush(struct pch_udc_ep *ep, int dir) |
| 925 | { |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 926 | if (dir) { /* IN ep */ |
| 927 | pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F); |
| 928 | return; |
| 929 | } |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 930 | } |
| 931 | |
| 932 | /** |
| 933 | * pch_udc_ep_enable() - This api enables endpoint |
| 934 | * @regs: Reference to structure pch_udc_ep_regs |
| 935 | * @desc: endpoint descriptor |
| 936 | */ |
| 937 | static void pch_udc_ep_enable(struct pch_udc_ep *ep, |
| 938 | struct pch_udc_cfg_data *cfg, |
| 939 | const struct usb_endpoint_descriptor *desc) |
| 940 | { |
| 941 | u32 val = 0; |
| 942 | u32 buff_size = 0; |
| 943 | |
| 944 | pch_udc_ep_set_trfr_type(ep, desc->bmAttributes); |
| 945 | if (ep->in) |
| 946 | buff_size = UDC_EPIN_BUFF_SIZE; |
| 947 | else |
| 948 | buff_size = UDC_EPOUT_BUFF_SIZE; |
| 949 | pch_udc_ep_set_bufsz(ep, buff_size, ep->in); |
| 950 | pch_udc_ep_set_maxpkt(ep, le16_to_cpu(desc->wMaxPacketSize)); |
| 951 | pch_udc_ep_set_nak(ep); |
| 952 | pch_udc_ep_fifo_flush(ep, ep->in); |
| 953 | /* Configure the endpoint */ |
| 954 | val = ep->num << UDC_CSR_NE_NUM_SHIFT | ep->in << UDC_CSR_NE_DIR_SHIFT | |
| 955 | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) << |
| 956 | UDC_CSR_NE_TYPE_SHIFT) | |
| 957 | (cfg->cur_cfg << UDC_CSR_NE_CFG_SHIFT) | |
| 958 | (cfg->cur_intf << UDC_CSR_NE_INTF_SHIFT) | |
| 959 | (cfg->cur_alt << UDC_CSR_NE_ALT_SHIFT) | |
| 960 | le16_to_cpu(desc->wMaxPacketSize) << UDC_CSR_NE_MAX_PKT_SHIFT; |
| 961 | |
| 962 | if (ep->in) |
| 963 | pch_udc_write_csr(ep->dev, val, UDC_EPIN_IDX(ep->num)); |
| 964 | else |
| 965 | pch_udc_write_csr(ep->dev, val, UDC_EPOUT_IDX(ep->num)); |
| 966 | } |
| 967 | |
| 968 | /** |
| 969 | * pch_udc_ep_disable() - This api disables endpoint |
| 970 | * @regs: Reference to structure pch_udc_ep_regs |
| 971 | */ |
| 972 | static void pch_udc_ep_disable(struct pch_udc_ep *ep) |
| 973 | { |
| 974 | if (ep->in) { |
| 975 | /* flush the fifo */ |
| 976 | pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR); |
| 977 | /* set NAK */ |
| 978 | pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR); |
| 979 | pch_udc_ep_bit_set(ep, UDC_EPSTS_ADDR, UDC_EPSTS_IN); |
| 980 | } else { |
| 981 | /* set NAK */ |
| 982 | pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR); |
| 983 | } |
| 984 | /* reset desc pointer */ |
| 985 | pch_udc_ep_writel(ep, 0, UDC_DESPTR_ADDR); |
| 986 | } |
| 987 | |
| 988 | /** |
| 989 | * pch_udc_wait_ep_stall() - Wait EP stall. |
| 990 | * @dev: Reference to pch_udc_dev structure |
| 991 | */ |
| 992 | static void pch_udc_wait_ep_stall(struct pch_udc_ep *ep) |
| 993 | { |
| 994 | unsigned int count = 10000; |
| 995 | |
| 996 | /* Wait till idle */ |
| 997 | while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_S) && --count) |
| 998 | udelay(5); |
| 999 | if (!count) |
| 1000 | dev_err(&ep->dev->pdev->dev, "%s: wait error\n", __func__); |
| 1001 | } |
| 1002 | |
| 1003 | /** |
| 1004 | * pch_udc_init() - This API initializes usb device controller |
| 1005 | * @dev: Rreference to pch_udc_regs structure |
| 1006 | */ |
| 1007 | static void pch_udc_init(struct pch_udc_dev *dev) |
| 1008 | { |
| 1009 | if (NULL == dev) { |
| 1010 | pr_err("%s: Invalid address\n", __func__); |
| 1011 | return; |
| 1012 | } |
| 1013 | /* Soft Reset and Reset PHY */ |
| 1014 | pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR); |
| 1015 | pch_udc_writel(dev, UDC_SRST | UDC_PSRST, UDC_SRST_ADDR); |
| 1016 | mdelay(1); |
| 1017 | pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR); |
| 1018 | pch_udc_writel(dev, 0x00, UDC_SRST_ADDR); |
| 1019 | mdelay(1); |
| 1020 | /* mask and clear all device interrupts */ |
| 1021 | pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK); |
| 1022 | pch_udc_bit_set(dev, UDC_DEVIRQSTS_ADDR, UDC_DEVINT_MSK); |
| 1023 | |
| 1024 | /* mask and clear all ep interrupts */ |
| 1025 | pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL); |
| 1026 | pch_udc_bit_set(dev, UDC_EPIRQSTS_ADDR, UDC_EPINT_MSK_DISABLE_ALL); |
| 1027 | |
| 1028 | /* enable dynamic CSR programmingi, self powered and device speed */ |
| 1029 | if (speed_fs) |
| 1030 | pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG | |
| 1031 | UDC_DEVCFG_SP | UDC_DEVCFG_SPD_FS); |
| 1032 | else /* defaul high speed */ |
| 1033 | pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG | |
| 1034 | UDC_DEVCFG_SP | UDC_DEVCFG_SPD_HS); |
| 1035 | pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, |
| 1036 | (PCH_UDC_THLEN << UDC_DEVCTL_THLEN_SHIFT) | |
| 1037 | (PCH_UDC_BRLEN << UDC_DEVCTL_BRLEN_SHIFT) | |
| 1038 | UDC_DEVCTL_MODE | UDC_DEVCTL_BREN | |
| 1039 | UDC_DEVCTL_THE); |
| 1040 | } |
| 1041 | |
| 1042 | /** |
| 1043 | * pch_udc_exit() - This API exit usb device controller |
| 1044 | * @dev: Reference to pch_udc_regs structure |
| 1045 | */ |
| 1046 | static void pch_udc_exit(struct pch_udc_dev *dev) |
| 1047 | { |
| 1048 | /* mask all device interrupts */ |
| 1049 | pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK); |
| 1050 | /* mask all ep interrupts */ |
| 1051 | pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL); |
| 1052 | /* put device in disconnected state */ |
| 1053 | pch_udc_set_disconnect(dev); |
| 1054 | } |
| 1055 | |
| 1056 | /** |
| 1057 | * pch_udc_pcd_get_frame() - This API is invoked to get the current frame number |
| 1058 | * @gadget: Reference to the gadget driver |
| 1059 | * |
| 1060 | * Return codes: |
| 1061 | * 0: Success |
| 1062 | * -EINVAL: If the gadget passed is NULL |
| 1063 | */ |
| 1064 | static int pch_udc_pcd_get_frame(struct usb_gadget *gadget) |
| 1065 | { |
| 1066 | struct pch_udc_dev *dev; |
| 1067 | |
| 1068 | if (!gadget) |
| 1069 | return -EINVAL; |
| 1070 | dev = container_of(gadget, struct pch_udc_dev, gadget); |
| 1071 | return pch_udc_get_frame(dev); |
| 1072 | } |
| 1073 | |
| 1074 | /** |
| 1075 | * pch_udc_pcd_wakeup() - This API is invoked to initiate a remote wakeup |
| 1076 | * @gadget: Reference to the gadget driver |
| 1077 | * |
| 1078 | * Return codes: |
| 1079 | * 0: Success |
| 1080 | * -EINVAL: If the gadget passed is NULL |
| 1081 | */ |
| 1082 | static int pch_udc_pcd_wakeup(struct usb_gadget *gadget) |
| 1083 | { |
| 1084 | struct pch_udc_dev *dev; |
| 1085 | unsigned long flags; |
| 1086 | |
| 1087 | if (!gadget) |
| 1088 | return -EINVAL; |
| 1089 | dev = container_of(gadget, struct pch_udc_dev, gadget); |
| 1090 | spin_lock_irqsave(&dev->lock, flags); |
| 1091 | pch_udc_rmt_wakeup(dev); |
| 1092 | spin_unlock_irqrestore(&dev->lock, flags); |
| 1093 | return 0; |
| 1094 | } |
| 1095 | |
| 1096 | /** |
| 1097 | * pch_udc_pcd_selfpowered() - This API is invoked to specify whether the device |
| 1098 | * is self powered or not |
| 1099 | * @gadget: Reference to the gadget driver |
| 1100 | * @value: Specifies self powered or not |
| 1101 | * |
| 1102 | * Return codes: |
| 1103 | * 0: Success |
| 1104 | * -EINVAL: If the gadget passed is NULL |
| 1105 | */ |
| 1106 | static int pch_udc_pcd_selfpowered(struct usb_gadget *gadget, int value) |
| 1107 | { |
| 1108 | struct pch_udc_dev *dev; |
| 1109 | |
| 1110 | if (!gadget) |
| 1111 | return -EINVAL; |
| 1112 | dev = container_of(gadget, struct pch_udc_dev, gadget); |
| 1113 | if (value) |
| 1114 | pch_udc_set_selfpowered(dev); |
| 1115 | else |
| 1116 | pch_udc_clear_selfpowered(dev); |
| 1117 | return 0; |
| 1118 | } |
| 1119 | |
| 1120 | /** |
| 1121 | * pch_udc_pcd_pullup() - This API is invoked to make the device |
| 1122 | * visible/invisible to the host |
| 1123 | * @gadget: Reference to the gadget driver |
| 1124 | * @is_on: Specifies whether the pull up is made active or inactive |
| 1125 | * |
| 1126 | * Return codes: |
| 1127 | * 0: Success |
| 1128 | * -EINVAL: If the gadget passed is NULL |
| 1129 | */ |
| 1130 | static int pch_udc_pcd_pullup(struct usb_gadget *gadget, int is_on) |
| 1131 | { |
| 1132 | struct pch_udc_dev *dev; |
| 1133 | |
| 1134 | if (!gadget) |
| 1135 | return -EINVAL; |
| 1136 | dev = container_of(gadget, struct pch_udc_dev, gadget); |
| 1137 | pch_udc_vbus_session(dev, is_on); |
| 1138 | return 0; |
| 1139 | } |
| 1140 | |
| 1141 | /** |
| 1142 | * pch_udc_pcd_vbus_session() - This API is used by a driver for an external |
| 1143 | * transceiver (or GPIO) that |
| 1144 | * detects a VBUS power session starting/ending |
| 1145 | * @gadget: Reference to the gadget driver |
| 1146 | * @is_active: specifies whether the session is starting or ending |
| 1147 | * |
| 1148 | * Return codes: |
| 1149 | * 0: Success |
| 1150 | * -EINVAL: If the gadget passed is NULL |
| 1151 | */ |
| 1152 | static int pch_udc_pcd_vbus_session(struct usb_gadget *gadget, int is_active) |
| 1153 | { |
| 1154 | struct pch_udc_dev *dev; |
| 1155 | |
| 1156 | if (!gadget) |
| 1157 | return -EINVAL; |
| 1158 | dev = container_of(gadget, struct pch_udc_dev, gadget); |
| 1159 | pch_udc_vbus_session(dev, is_active); |
| 1160 | return 0; |
| 1161 | } |
| 1162 | |
| 1163 | /** |
| 1164 | * pch_udc_pcd_vbus_draw() - This API is used by gadget drivers during |
| 1165 | * SET_CONFIGURATION calls to |
| 1166 | * specify how much power the device can consume |
| 1167 | * @gadget: Reference to the gadget driver |
| 1168 | * @mA: specifies the current limit in 2mA unit |
| 1169 | * |
| 1170 | * Return codes: |
| 1171 | * -EINVAL: If the gadget passed is NULL |
| 1172 | * -EOPNOTSUPP: |
| 1173 | */ |
| 1174 | static int pch_udc_pcd_vbus_draw(struct usb_gadget *gadget, unsigned int mA) |
| 1175 | { |
| 1176 | return -EOPNOTSUPP; |
| 1177 | } |
| 1178 | |
| 1179 | static const struct usb_gadget_ops pch_udc_ops = { |
| 1180 | .get_frame = pch_udc_pcd_get_frame, |
| 1181 | .wakeup = pch_udc_pcd_wakeup, |
| 1182 | .set_selfpowered = pch_udc_pcd_selfpowered, |
| 1183 | .pullup = pch_udc_pcd_pullup, |
| 1184 | .vbus_session = pch_udc_pcd_vbus_session, |
| 1185 | .vbus_draw = pch_udc_pcd_vbus_draw, |
| 1186 | }; |
| 1187 | |
| 1188 | /** |
| 1189 | * complete_req() - This API is invoked from the driver when processing |
| 1190 | * of a request is complete |
| 1191 | * @ep: Reference to the endpoint structure |
| 1192 | * @req: Reference to the request structure |
| 1193 | * @status: Indicates the success/failure of completion |
| 1194 | */ |
| 1195 | static void complete_req(struct pch_udc_ep *ep, struct pch_udc_request *req, |
| 1196 | int status) |
| 1197 | { |
| 1198 | struct pch_udc_dev *dev; |
| 1199 | unsigned halted = ep->halted; |
| 1200 | |
| 1201 | list_del_init(&req->queue); |
| 1202 | |
| 1203 | /* set new status if pending */ |
| 1204 | if (req->req.status == -EINPROGRESS) |
| 1205 | req->req.status = status; |
| 1206 | else |
| 1207 | status = req->req.status; |
| 1208 | |
| 1209 | dev = ep->dev; |
| 1210 | if (req->dma_mapped) { |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 1211 | if (req->dma == DMA_ADDR_INVALID) { |
| 1212 | if (ep->in) |
| 1213 | dma_unmap_single(&dev->pdev->dev, req->req.dma, |
| 1214 | req->req.length, |
| 1215 | DMA_TO_DEVICE); |
| 1216 | else |
| 1217 | dma_unmap_single(&dev->pdev->dev, req->req.dma, |
| 1218 | req->req.length, |
| 1219 | DMA_FROM_DEVICE); |
| 1220 | req->req.dma = DMA_ADDR_INVALID; |
| 1221 | } else { |
| 1222 | if (ep->in) |
| 1223 | dma_unmap_single(&dev->pdev->dev, req->dma, |
| 1224 | req->req.length, |
| 1225 | DMA_TO_DEVICE); |
| 1226 | else { |
| 1227 | dma_unmap_single(&dev->pdev->dev, req->dma, |
| 1228 | req->req.length, |
| 1229 | DMA_FROM_DEVICE); |
| 1230 | memcpy(req->req.buf, req->buf, req->req.length); |
| 1231 | } |
| 1232 | kfree(req->buf); |
| 1233 | req->dma = DMA_ADDR_INVALID; |
| 1234 | } |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1235 | req->dma_mapped = 0; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1236 | } |
| 1237 | ep->halted = 1; |
| 1238 | spin_unlock(&dev->lock); |
| 1239 | if (!ep->in) |
| 1240 | pch_udc_ep_clear_rrdy(ep); |
| 1241 | req->req.complete(&ep->ep, &req->req); |
| 1242 | spin_lock(&dev->lock); |
| 1243 | ep->halted = halted; |
| 1244 | } |
| 1245 | |
| 1246 | /** |
| 1247 | * empty_req_queue() - This API empties the request queue of an endpoint |
| 1248 | * @ep: Reference to the endpoint structure |
| 1249 | */ |
| 1250 | static void empty_req_queue(struct pch_udc_ep *ep) |
| 1251 | { |
| 1252 | struct pch_udc_request *req; |
| 1253 | |
| 1254 | ep->halted = 1; |
| 1255 | while (!list_empty(&ep->queue)) { |
| 1256 | req = list_entry(ep->queue.next, struct pch_udc_request, queue); |
| 1257 | complete_req(ep, req, -ESHUTDOWN); /* Remove from list */ |
| 1258 | } |
| 1259 | } |
| 1260 | |
| 1261 | /** |
| 1262 | * pch_udc_free_dma_chain() - This function frees the DMA chain created |
| 1263 | * for the request |
| 1264 | * @dev Reference to the driver structure |
| 1265 | * @req Reference to the request to be freed |
| 1266 | * |
| 1267 | * Return codes: |
| 1268 | * 0: Success |
| 1269 | */ |
| 1270 | static void pch_udc_free_dma_chain(struct pch_udc_dev *dev, |
| 1271 | struct pch_udc_request *req) |
| 1272 | { |
| 1273 | struct pch_udc_data_dma_desc *td = req->td_data; |
| 1274 | unsigned i = req->chain_len; |
| 1275 | |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 1276 | dma_addr_t addr2; |
| 1277 | dma_addr_t addr = (dma_addr_t)td->next; |
| 1278 | td->next = 0x00; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1279 | for (; i > 1; --i) { |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1280 | /* do not free first desc., will be done by free for request */ |
| 1281 | td = phys_to_virt(addr); |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 1282 | addr2 = (dma_addr_t)td->next; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1283 | pci_pool_free(dev->data_requests, td, addr); |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 1284 | td->next = 0x00; |
| 1285 | addr = addr2; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1286 | } |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 1287 | req->chain_len = 1; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1288 | } |
| 1289 | |
| 1290 | /** |
| 1291 | * pch_udc_create_dma_chain() - This function creates or reinitializes |
| 1292 | * a DMA chain |
| 1293 | * @ep: Reference to the endpoint structure |
| 1294 | * @req: Reference to the request |
| 1295 | * @buf_len: The buffer length |
| 1296 | * @gfp_flags: Flags to be used while mapping the data buffer |
| 1297 | * |
| 1298 | * Return codes: |
| 1299 | * 0: success, |
| 1300 | * -ENOMEM: pci_pool_alloc invocation fails |
| 1301 | */ |
| 1302 | static int pch_udc_create_dma_chain(struct pch_udc_ep *ep, |
| 1303 | struct pch_udc_request *req, |
| 1304 | unsigned long buf_len, |
| 1305 | gfp_t gfp_flags) |
| 1306 | { |
| 1307 | struct pch_udc_data_dma_desc *td = req->td_data, *last; |
| 1308 | unsigned long bytes = req->req.length, i = 0; |
| 1309 | dma_addr_t dma_addr; |
| 1310 | unsigned len = 1; |
| 1311 | |
| 1312 | if (req->chain_len > 1) |
| 1313 | pch_udc_free_dma_chain(ep->dev, req); |
| 1314 | |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 1315 | if (req->dma == DMA_ADDR_INVALID) |
| 1316 | td->dataptr = req->req.dma; |
| 1317 | else |
| 1318 | td->dataptr = req->dma; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1319 | |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 1320 | td->status = PCH_UDC_BS_HST_BSY; |
| 1321 | for (; ; bytes -= buf_len, ++len) { |
| 1322 | td->status = PCH_UDC_BS_HST_BSY | min(buf_len, bytes); |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1323 | if (bytes <= buf_len) |
| 1324 | break; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1325 | last = td; |
| 1326 | td = pci_pool_alloc(ep->dev->data_requests, gfp_flags, |
| 1327 | &dma_addr); |
| 1328 | if (!td) |
| 1329 | goto nomem; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1330 | i += buf_len; |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 1331 | td->dataptr = req->td_data->dataptr + i; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1332 | last->next = dma_addr; |
| 1333 | } |
| 1334 | |
| 1335 | req->td_data_last = td; |
| 1336 | td->status |= PCH_UDC_DMA_LAST; |
| 1337 | td->next = req->td_data_phys; |
| 1338 | req->chain_len = len; |
| 1339 | return 0; |
| 1340 | |
| 1341 | nomem: |
| 1342 | if (len > 1) { |
| 1343 | req->chain_len = len; |
| 1344 | pch_udc_free_dma_chain(ep->dev, req); |
| 1345 | } |
| 1346 | req->chain_len = 1; |
| 1347 | return -ENOMEM; |
| 1348 | } |
| 1349 | |
| 1350 | /** |
| 1351 | * prepare_dma() - This function creates and initializes the DMA chain |
| 1352 | * for the request |
| 1353 | * @ep: Reference to the endpoint structure |
| 1354 | * @req: Reference to the request |
| 1355 | * @gfp: Flag to be used while mapping the data buffer |
| 1356 | * |
| 1357 | * Return codes: |
| 1358 | * 0: Success |
| 1359 | * Other 0: linux error number on failure |
| 1360 | */ |
| 1361 | static int prepare_dma(struct pch_udc_ep *ep, struct pch_udc_request *req, |
| 1362 | gfp_t gfp) |
| 1363 | { |
| 1364 | int retval; |
| 1365 | |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1366 | /* Allocate and create a DMA chain */ |
| 1367 | retval = pch_udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp); |
| 1368 | if (retval) { |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 1369 | pr_err("%s: could not create DMA chain:%d\n", __func__, retval); |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1370 | return retval; |
| 1371 | } |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 1372 | if (ep->in) |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1373 | req->td_data->status = (req->td_data->status & |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 1374 | ~PCH_UDC_BUFF_STS) | PCH_UDC_BS_HST_RDY; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1375 | return 0; |
| 1376 | } |
| 1377 | |
| 1378 | /** |
| 1379 | * process_zlp() - This function process zero length packets |
| 1380 | * from the gadget driver |
| 1381 | * @ep: Reference to the endpoint structure |
| 1382 | * @req: Reference to the request |
| 1383 | */ |
| 1384 | static void process_zlp(struct pch_udc_ep *ep, struct pch_udc_request *req) |
| 1385 | { |
| 1386 | struct pch_udc_dev *dev = ep->dev; |
| 1387 | |
| 1388 | /* IN zlp's are handled by hardware */ |
| 1389 | complete_req(ep, req, 0); |
| 1390 | |
| 1391 | /* if set_config or set_intf is waiting for ack by zlp |
| 1392 | * then set CSR_DONE |
| 1393 | */ |
| 1394 | if (dev->set_cfg_not_acked) { |
| 1395 | pch_udc_set_csr_done(dev); |
| 1396 | dev->set_cfg_not_acked = 0; |
| 1397 | } |
| 1398 | /* setup command is ACK'ed now by zlp */ |
| 1399 | if (!dev->stall && dev->waiting_zlp_ack) { |
| 1400 | pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX])); |
| 1401 | dev->waiting_zlp_ack = 0; |
| 1402 | } |
| 1403 | } |
| 1404 | |
| 1405 | /** |
| 1406 | * pch_udc_start_rxrequest() - This function starts the receive requirement. |
| 1407 | * @ep: Reference to the endpoint structure |
| 1408 | * @req: Reference to the request structure |
| 1409 | */ |
| 1410 | static void pch_udc_start_rxrequest(struct pch_udc_ep *ep, |
| 1411 | struct pch_udc_request *req) |
| 1412 | { |
| 1413 | struct pch_udc_data_dma_desc *td_data; |
| 1414 | |
| 1415 | pch_udc_clear_dma(ep->dev, DMA_DIR_RX); |
| 1416 | td_data = req->td_data; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1417 | /* Set the status bits for all descriptors */ |
| 1418 | while (1) { |
| 1419 | td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) | |
| 1420 | PCH_UDC_BS_HST_RDY; |
| 1421 | if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST) |
| 1422 | break; |
| 1423 | td_data = phys_to_virt(td_data->next); |
| 1424 | } |
| 1425 | /* Write the descriptor pointer */ |
| 1426 | pch_udc_ep_set_ddptr(ep, req->td_data_phys); |
| 1427 | req->dma_going = 1; |
| 1428 | pch_udc_enable_ep_interrupts(ep->dev, UDC_EPINT_OUT_EP0 << ep->num); |
| 1429 | pch_udc_set_dma(ep->dev, DMA_DIR_RX); |
| 1430 | pch_udc_ep_clear_nak(ep); |
| 1431 | pch_udc_ep_set_rrdy(ep); |
| 1432 | } |
| 1433 | |
| 1434 | /** |
| 1435 | * pch_udc_pcd_ep_enable() - This API enables the endpoint. It is called |
| 1436 | * from gadget driver |
| 1437 | * @usbep: Reference to the USB endpoint structure |
| 1438 | * @desc: Reference to the USB endpoint descriptor structure |
| 1439 | * |
| 1440 | * Return codes: |
| 1441 | * 0: Success |
| 1442 | * -EINVAL: |
| 1443 | * -ESHUTDOWN: |
| 1444 | */ |
| 1445 | static int pch_udc_pcd_ep_enable(struct usb_ep *usbep, |
| 1446 | const struct usb_endpoint_descriptor *desc) |
| 1447 | { |
| 1448 | struct pch_udc_ep *ep; |
| 1449 | struct pch_udc_dev *dev; |
| 1450 | unsigned long iflags; |
| 1451 | |
| 1452 | if (!usbep || (usbep->name == ep0_string) || !desc || |
| 1453 | (desc->bDescriptorType != USB_DT_ENDPOINT) || !desc->wMaxPacketSize) |
| 1454 | return -EINVAL; |
| 1455 | |
| 1456 | ep = container_of(usbep, struct pch_udc_ep, ep); |
| 1457 | dev = ep->dev; |
| 1458 | if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN)) |
| 1459 | return -ESHUTDOWN; |
| 1460 | spin_lock_irqsave(&dev->lock, iflags); |
| 1461 | ep->desc = desc; |
| 1462 | ep->halted = 0; |
| 1463 | pch_udc_ep_enable(ep, &ep->dev->cfg_data, desc); |
| 1464 | ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize); |
| 1465 | pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num)); |
| 1466 | spin_unlock_irqrestore(&dev->lock, iflags); |
| 1467 | return 0; |
| 1468 | } |
| 1469 | |
| 1470 | /** |
| 1471 | * pch_udc_pcd_ep_disable() - This API disables endpoint and is called |
| 1472 | * from gadget driver |
| 1473 | * @usbep Reference to the USB endpoint structure |
| 1474 | * |
| 1475 | * Return codes: |
| 1476 | * 0: Success |
| 1477 | * -EINVAL: |
| 1478 | */ |
| 1479 | static int pch_udc_pcd_ep_disable(struct usb_ep *usbep) |
| 1480 | { |
| 1481 | struct pch_udc_ep *ep; |
| 1482 | struct pch_udc_dev *dev; |
| 1483 | unsigned long iflags; |
| 1484 | |
| 1485 | if (!usbep) |
| 1486 | return -EINVAL; |
| 1487 | |
| 1488 | ep = container_of(usbep, struct pch_udc_ep, ep); |
| 1489 | dev = ep->dev; |
| 1490 | if ((usbep->name == ep0_string) || !ep->desc) |
| 1491 | return -EINVAL; |
| 1492 | |
| 1493 | spin_lock_irqsave(&ep->dev->lock, iflags); |
| 1494 | empty_req_queue(ep); |
| 1495 | ep->halted = 1; |
| 1496 | pch_udc_ep_disable(ep); |
| 1497 | pch_udc_disable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num)); |
| 1498 | ep->desc = NULL; |
| 1499 | INIT_LIST_HEAD(&ep->queue); |
| 1500 | spin_unlock_irqrestore(&ep->dev->lock, iflags); |
| 1501 | return 0; |
| 1502 | } |
| 1503 | |
| 1504 | /** |
| 1505 | * pch_udc_alloc_request() - This function allocates request structure. |
| 1506 | * It is called by gadget driver |
| 1507 | * @usbep: Reference to the USB endpoint structure |
| 1508 | * @gfp: Flag to be used while allocating memory |
| 1509 | * |
| 1510 | * Return codes: |
| 1511 | * NULL: Failure |
| 1512 | * Allocated address: Success |
| 1513 | */ |
| 1514 | static struct usb_request *pch_udc_alloc_request(struct usb_ep *usbep, |
| 1515 | gfp_t gfp) |
| 1516 | { |
| 1517 | struct pch_udc_request *req; |
| 1518 | struct pch_udc_ep *ep; |
| 1519 | struct pch_udc_data_dma_desc *dma_desc; |
| 1520 | struct pch_udc_dev *dev; |
| 1521 | |
| 1522 | if (!usbep) |
| 1523 | return NULL; |
| 1524 | ep = container_of(usbep, struct pch_udc_ep, ep); |
| 1525 | dev = ep->dev; |
| 1526 | req = kzalloc(sizeof *req, gfp); |
| 1527 | if (!req) |
| 1528 | return NULL; |
| 1529 | req->req.dma = DMA_ADDR_INVALID; |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 1530 | req->dma = DMA_ADDR_INVALID; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1531 | INIT_LIST_HEAD(&req->queue); |
| 1532 | if (!ep->dev->dma_addr) |
| 1533 | return &req->req; |
| 1534 | /* ep0 in requests are allocated from data pool here */ |
| 1535 | dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp, |
| 1536 | &req->td_data_phys); |
| 1537 | if (NULL == dma_desc) { |
| 1538 | kfree(req); |
| 1539 | return NULL; |
| 1540 | } |
| 1541 | /* prevent from using desc. - set HOST BUSY */ |
| 1542 | dma_desc->status |= PCH_UDC_BS_HST_BSY; |
| 1543 | dma_desc->dataptr = __constant_cpu_to_le32(DMA_ADDR_INVALID); |
| 1544 | req->td_data = dma_desc; |
| 1545 | req->td_data_last = dma_desc; |
| 1546 | req->chain_len = 1; |
| 1547 | return &req->req; |
| 1548 | } |
| 1549 | |
| 1550 | /** |
| 1551 | * pch_udc_free_request() - This function frees request structure. |
| 1552 | * It is called by gadget driver |
| 1553 | * @usbep: Reference to the USB endpoint structure |
| 1554 | * @usbreq: Reference to the USB request |
| 1555 | */ |
| 1556 | static void pch_udc_free_request(struct usb_ep *usbep, |
| 1557 | struct usb_request *usbreq) |
| 1558 | { |
| 1559 | struct pch_udc_ep *ep; |
| 1560 | struct pch_udc_request *req; |
| 1561 | struct pch_udc_dev *dev; |
| 1562 | |
| 1563 | if (!usbep || !usbreq) |
| 1564 | return; |
| 1565 | ep = container_of(usbep, struct pch_udc_ep, ep); |
| 1566 | req = container_of(usbreq, struct pch_udc_request, req); |
| 1567 | dev = ep->dev; |
| 1568 | if (!list_empty(&req->queue)) |
| 1569 | dev_err(&dev->pdev->dev, "%s: %s req=0x%p queue not empty\n", |
| 1570 | __func__, usbep->name, req); |
| 1571 | if (req->td_data != NULL) { |
| 1572 | if (req->chain_len > 1) |
| 1573 | pch_udc_free_dma_chain(ep->dev, req); |
| 1574 | pci_pool_free(ep->dev->data_requests, req->td_data, |
| 1575 | req->td_data_phys); |
| 1576 | } |
| 1577 | kfree(req); |
| 1578 | } |
| 1579 | |
| 1580 | /** |
| 1581 | * pch_udc_pcd_queue() - This function queues a request packet. It is called |
| 1582 | * by gadget driver |
| 1583 | * @usbep: Reference to the USB endpoint structure |
| 1584 | * @usbreq: Reference to the USB request |
| 1585 | * @gfp: Flag to be used while mapping the data buffer |
| 1586 | * |
| 1587 | * Return codes: |
| 1588 | * 0: Success |
| 1589 | * linux error number: Failure |
| 1590 | */ |
| 1591 | static int pch_udc_pcd_queue(struct usb_ep *usbep, struct usb_request *usbreq, |
| 1592 | gfp_t gfp) |
| 1593 | { |
| 1594 | int retval = 0; |
| 1595 | struct pch_udc_ep *ep; |
| 1596 | struct pch_udc_dev *dev; |
| 1597 | struct pch_udc_request *req; |
| 1598 | unsigned long iflags; |
| 1599 | |
| 1600 | if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf) |
| 1601 | return -EINVAL; |
| 1602 | ep = container_of(usbep, struct pch_udc_ep, ep); |
| 1603 | dev = ep->dev; |
| 1604 | if (!ep->desc && ep->num) |
| 1605 | return -EINVAL; |
| 1606 | req = container_of(usbreq, struct pch_udc_request, req); |
| 1607 | if (!list_empty(&req->queue)) |
| 1608 | return -EINVAL; |
| 1609 | if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN)) |
| 1610 | return -ESHUTDOWN; |
Dan Carpenter | 4857071 | 2011-03-20 14:09:50 +0300 | [diff] [blame] | 1611 | spin_lock_irqsave(&dev->lock, iflags); |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1612 | /* map the buffer for dma */ |
| 1613 | if (usbreq->length && |
| 1614 | ((usbreq->dma == DMA_ADDR_INVALID) || !usbreq->dma)) { |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 1615 | if (!((unsigned long)(usbreq->buf) & 0x03)) { |
| 1616 | if (ep->in) |
| 1617 | usbreq->dma = dma_map_single(&dev->pdev->dev, |
| 1618 | usbreq->buf, |
| 1619 | usbreq->length, |
| 1620 | DMA_TO_DEVICE); |
| 1621 | else |
| 1622 | usbreq->dma = dma_map_single(&dev->pdev->dev, |
| 1623 | usbreq->buf, |
| 1624 | usbreq->length, |
| 1625 | DMA_FROM_DEVICE); |
| 1626 | } else { |
| 1627 | req->buf = kzalloc(usbreq->length, GFP_ATOMIC); |
Dan Carpenter | 4857071 | 2011-03-20 14:09:50 +0300 | [diff] [blame] | 1628 | if (!req->buf) { |
| 1629 | retval = -ENOMEM; |
| 1630 | goto probe_end; |
| 1631 | } |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 1632 | if (ep->in) { |
| 1633 | memcpy(req->buf, usbreq->buf, usbreq->length); |
| 1634 | req->dma = dma_map_single(&dev->pdev->dev, |
| 1635 | req->buf, |
| 1636 | usbreq->length, |
| 1637 | DMA_TO_DEVICE); |
| 1638 | } else |
| 1639 | req->dma = dma_map_single(&dev->pdev->dev, |
| 1640 | req->buf, |
| 1641 | usbreq->length, |
| 1642 | DMA_FROM_DEVICE); |
| 1643 | } |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1644 | req->dma_mapped = 1; |
| 1645 | } |
| 1646 | if (usbreq->length > 0) { |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 1647 | retval = prepare_dma(ep, req, GFP_ATOMIC); |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1648 | if (retval) |
| 1649 | goto probe_end; |
| 1650 | } |
| 1651 | usbreq->actual = 0; |
| 1652 | usbreq->status = -EINPROGRESS; |
| 1653 | req->dma_done = 0; |
| 1654 | if (list_empty(&ep->queue) && !ep->halted) { |
| 1655 | /* no pending transfer, so start this req */ |
| 1656 | if (!usbreq->length) { |
| 1657 | process_zlp(ep, req); |
| 1658 | retval = 0; |
| 1659 | goto probe_end; |
| 1660 | } |
| 1661 | if (!ep->in) { |
| 1662 | pch_udc_start_rxrequest(ep, req); |
| 1663 | } else { |
| 1664 | /* |
| 1665 | * For IN trfr the descriptors will be programmed and |
| 1666 | * P bit will be set when |
| 1667 | * we get an IN token |
| 1668 | */ |
| 1669 | pch_udc_wait_ep_stall(ep); |
| 1670 | pch_udc_ep_clear_nak(ep); |
| 1671 | pch_udc_enable_ep_interrupts(ep->dev, (1 << ep->num)); |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1672 | } |
| 1673 | } |
| 1674 | /* Now add this request to the ep's pending requests */ |
| 1675 | if (req != NULL) |
| 1676 | list_add_tail(&req->queue, &ep->queue); |
| 1677 | |
| 1678 | probe_end: |
| 1679 | spin_unlock_irqrestore(&dev->lock, iflags); |
| 1680 | return retval; |
| 1681 | } |
| 1682 | |
| 1683 | /** |
| 1684 | * pch_udc_pcd_dequeue() - This function de-queues a request packet. |
| 1685 | * It is called by gadget driver |
| 1686 | * @usbep: Reference to the USB endpoint structure |
| 1687 | * @usbreq: Reference to the USB request |
| 1688 | * |
| 1689 | * Return codes: |
| 1690 | * 0: Success |
| 1691 | * linux error number: Failure |
| 1692 | */ |
| 1693 | static int pch_udc_pcd_dequeue(struct usb_ep *usbep, |
| 1694 | struct usb_request *usbreq) |
| 1695 | { |
| 1696 | struct pch_udc_ep *ep; |
| 1697 | struct pch_udc_request *req; |
| 1698 | struct pch_udc_dev *dev; |
| 1699 | unsigned long flags; |
| 1700 | int ret = -EINVAL; |
| 1701 | |
| 1702 | ep = container_of(usbep, struct pch_udc_ep, ep); |
| 1703 | dev = ep->dev; |
| 1704 | if (!usbep || !usbreq || (!ep->desc && ep->num)) |
| 1705 | return ret; |
| 1706 | req = container_of(usbreq, struct pch_udc_request, req); |
| 1707 | spin_lock_irqsave(&ep->dev->lock, flags); |
| 1708 | /* make sure it's still queued on this endpoint */ |
| 1709 | list_for_each_entry(req, &ep->queue, queue) { |
| 1710 | if (&req->req == usbreq) { |
| 1711 | pch_udc_ep_set_nak(ep); |
| 1712 | if (!list_empty(&req->queue)) |
| 1713 | complete_req(ep, req, -ECONNRESET); |
| 1714 | ret = 0; |
| 1715 | break; |
| 1716 | } |
| 1717 | } |
| 1718 | spin_unlock_irqrestore(&ep->dev->lock, flags); |
| 1719 | return ret; |
| 1720 | } |
| 1721 | |
| 1722 | /** |
| 1723 | * pch_udc_pcd_set_halt() - This function Sets or clear the endpoint halt |
| 1724 | * feature |
| 1725 | * @usbep: Reference to the USB endpoint structure |
| 1726 | * @halt: Specifies whether to set or clear the feature |
| 1727 | * |
| 1728 | * Return codes: |
| 1729 | * 0: Success |
| 1730 | * linux error number: Failure |
| 1731 | */ |
| 1732 | static int pch_udc_pcd_set_halt(struct usb_ep *usbep, int halt) |
| 1733 | { |
| 1734 | struct pch_udc_ep *ep; |
| 1735 | struct pch_udc_dev *dev; |
| 1736 | unsigned long iflags; |
| 1737 | int ret; |
| 1738 | |
| 1739 | if (!usbep) |
| 1740 | return -EINVAL; |
| 1741 | ep = container_of(usbep, struct pch_udc_ep, ep); |
| 1742 | dev = ep->dev; |
| 1743 | if (!ep->desc && !ep->num) |
| 1744 | return -EINVAL; |
| 1745 | if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN)) |
| 1746 | return -ESHUTDOWN; |
| 1747 | spin_lock_irqsave(&udc_stall_spinlock, iflags); |
| 1748 | if (list_empty(&ep->queue)) { |
| 1749 | if (halt) { |
| 1750 | if (ep->num == PCH_UDC_EP0) |
| 1751 | ep->dev->stall = 1; |
| 1752 | pch_udc_ep_set_stall(ep); |
| 1753 | pch_udc_enable_ep_interrupts(ep->dev, |
| 1754 | PCH_UDC_EPINT(ep->in, |
| 1755 | ep->num)); |
| 1756 | } else { |
| 1757 | pch_udc_ep_clear_stall(ep); |
| 1758 | } |
| 1759 | ret = 0; |
| 1760 | } else { |
| 1761 | ret = -EAGAIN; |
| 1762 | } |
| 1763 | spin_unlock_irqrestore(&udc_stall_spinlock, iflags); |
| 1764 | return ret; |
| 1765 | } |
| 1766 | |
| 1767 | /** |
| 1768 | * pch_udc_pcd_set_wedge() - This function Sets or clear the endpoint |
| 1769 | * halt feature |
| 1770 | * @usbep: Reference to the USB endpoint structure |
| 1771 | * @halt: Specifies whether to set or clear the feature |
| 1772 | * |
| 1773 | * Return codes: |
| 1774 | * 0: Success |
| 1775 | * linux error number: Failure |
| 1776 | */ |
| 1777 | static int pch_udc_pcd_set_wedge(struct usb_ep *usbep) |
| 1778 | { |
| 1779 | struct pch_udc_ep *ep; |
| 1780 | struct pch_udc_dev *dev; |
| 1781 | unsigned long iflags; |
| 1782 | int ret; |
| 1783 | |
| 1784 | if (!usbep) |
| 1785 | return -EINVAL; |
| 1786 | ep = container_of(usbep, struct pch_udc_ep, ep); |
| 1787 | dev = ep->dev; |
| 1788 | if (!ep->desc && !ep->num) |
| 1789 | return -EINVAL; |
| 1790 | if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN)) |
| 1791 | return -ESHUTDOWN; |
| 1792 | spin_lock_irqsave(&udc_stall_spinlock, iflags); |
| 1793 | if (!list_empty(&ep->queue)) { |
| 1794 | ret = -EAGAIN; |
| 1795 | } else { |
| 1796 | if (ep->num == PCH_UDC_EP0) |
| 1797 | ep->dev->stall = 1; |
| 1798 | pch_udc_ep_set_stall(ep); |
| 1799 | pch_udc_enable_ep_interrupts(ep->dev, |
| 1800 | PCH_UDC_EPINT(ep->in, ep->num)); |
| 1801 | ep->dev->prot_stall = 1; |
| 1802 | ret = 0; |
| 1803 | } |
| 1804 | spin_unlock_irqrestore(&udc_stall_spinlock, iflags); |
| 1805 | return ret; |
| 1806 | } |
| 1807 | |
| 1808 | /** |
| 1809 | * pch_udc_pcd_fifo_flush() - This function Flush the FIFO of specified endpoint |
| 1810 | * @usbep: Reference to the USB endpoint structure |
| 1811 | */ |
| 1812 | static void pch_udc_pcd_fifo_flush(struct usb_ep *usbep) |
| 1813 | { |
| 1814 | struct pch_udc_ep *ep; |
| 1815 | |
| 1816 | if (!usbep) |
| 1817 | return; |
| 1818 | |
| 1819 | ep = container_of(usbep, struct pch_udc_ep, ep); |
| 1820 | if (ep->desc || !ep->num) |
| 1821 | pch_udc_ep_fifo_flush(ep, ep->in); |
| 1822 | } |
| 1823 | |
| 1824 | static const struct usb_ep_ops pch_udc_ep_ops = { |
| 1825 | .enable = pch_udc_pcd_ep_enable, |
| 1826 | .disable = pch_udc_pcd_ep_disable, |
| 1827 | .alloc_request = pch_udc_alloc_request, |
| 1828 | .free_request = pch_udc_free_request, |
| 1829 | .queue = pch_udc_pcd_queue, |
| 1830 | .dequeue = pch_udc_pcd_dequeue, |
| 1831 | .set_halt = pch_udc_pcd_set_halt, |
| 1832 | .set_wedge = pch_udc_pcd_set_wedge, |
| 1833 | .fifo_status = NULL, |
| 1834 | .fifo_flush = pch_udc_pcd_fifo_flush, |
| 1835 | }; |
| 1836 | |
| 1837 | /** |
| 1838 | * pch_udc_init_setup_buff() - This function initializes the SETUP buffer |
| 1839 | * @td_stp: Reference to the SETP buffer structure |
| 1840 | */ |
| 1841 | static void pch_udc_init_setup_buff(struct pch_udc_stp_dma_desc *td_stp) |
| 1842 | { |
| 1843 | static u32 pky_marker; |
| 1844 | |
| 1845 | if (!td_stp) |
| 1846 | return; |
| 1847 | td_stp->reserved = ++pky_marker; |
| 1848 | memset(&td_stp->request, 0xFF, sizeof td_stp->request); |
| 1849 | td_stp->status = PCH_UDC_BS_HST_RDY; |
| 1850 | } |
| 1851 | |
| 1852 | /** |
| 1853 | * pch_udc_start_next_txrequest() - This function starts |
| 1854 | * the next transmission requirement |
| 1855 | * @ep: Reference to the endpoint structure |
| 1856 | */ |
| 1857 | static void pch_udc_start_next_txrequest(struct pch_udc_ep *ep) |
| 1858 | { |
| 1859 | struct pch_udc_request *req; |
| 1860 | struct pch_udc_data_dma_desc *td_data; |
| 1861 | |
| 1862 | if (pch_udc_read_ep_control(ep) & UDC_EPCTL_P) |
| 1863 | return; |
| 1864 | |
| 1865 | if (list_empty(&ep->queue)) |
| 1866 | return; |
| 1867 | |
| 1868 | /* next request */ |
| 1869 | req = list_entry(ep->queue.next, struct pch_udc_request, queue); |
| 1870 | if (req->dma_going) |
| 1871 | return; |
| 1872 | if (!req->td_data) |
| 1873 | return; |
| 1874 | pch_udc_wait_ep_stall(ep); |
| 1875 | req->dma_going = 1; |
| 1876 | pch_udc_ep_set_ddptr(ep, 0); |
| 1877 | td_data = req->td_data; |
| 1878 | while (1) { |
| 1879 | td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) | |
| 1880 | PCH_UDC_BS_HST_RDY; |
| 1881 | if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST) |
| 1882 | break; |
| 1883 | td_data = phys_to_virt(td_data->next); |
| 1884 | } |
| 1885 | pch_udc_ep_set_ddptr(ep, req->td_data_phys); |
| 1886 | pch_udc_set_dma(ep->dev, DMA_DIR_TX); |
| 1887 | pch_udc_ep_set_pd(ep); |
| 1888 | pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num)); |
| 1889 | pch_udc_ep_clear_nak(ep); |
| 1890 | } |
| 1891 | |
| 1892 | /** |
| 1893 | * pch_udc_complete_transfer() - This function completes a transfer |
| 1894 | * @ep: Reference to the endpoint structure |
| 1895 | */ |
| 1896 | static void pch_udc_complete_transfer(struct pch_udc_ep *ep) |
| 1897 | { |
| 1898 | struct pch_udc_request *req; |
| 1899 | struct pch_udc_dev *dev = ep->dev; |
| 1900 | |
| 1901 | if (list_empty(&ep->queue)) |
| 1902 | return; |
| 1903 | req = list_entry(ep->queue.next, struct pch_udc_request, queue); |
| 1904 | if ((req->td_data_last->status & PCH_UDC_BUFF_STS) != |
| 1905 | PCH_UDC_BS_DMA_DONE) |
| 1906 | return; |
| 1907 | if ((req->td_data_last->status & PCH_UDC_RXTX_STS) != |
| 1908 | PCH_UDC_RTS_SUCC) { |
| 1909 | dev_err(&dev->pdev->dev, "Invalid RXTX status (0x%08x) " |
| 1910 | "epstatus=0x%08x\n", |
| 1911 | (req->td_data_last->status & PCH_UDC_RXTX_STS), |
| 1912 | (int)(ep->epsts)); |
| 1913 | return; |
| 1914 | } |
| 1915 | |
| 1916 | req->req.actual = req->req.length; |
| 1917 | req->td_data_last->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST; |
| 1918 | req->td_data->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST; |
| 1919 | complete_req(ep, req, 0); |
| 1920 | req->dma_going = 0; |
| 1921 | if (!list_empty(&ep->queue)) { |
| 1922 | pch_udc_wait_ep_stall(ep); |
| 1923 | pch_udc_ep_clear_nak(ep); |
| 1924 | pch_udc_enable_ep_interrupts(ep->dev, |
| 1925 | PCH_UDC_EPINT(ep->in, ep->num)); |
| 1926 | } else { |
| 1927 | pch_udc_disable_ep_interrupts(ep->dev, |
| 1928 | PCH_UDC_EPINT(ep->in, ep->num)); |
| 1929 | } |
| 1930 | } |
| 1931 | |
| 1932 | /** |
| 1933 | * pch_udc_complete_receiver() - This function completes a receiver |
| 1934 | * @ep: Reference to the endpoint structure |
| 1935 | */ |
| 1936 | static void pch_udc_complete_receiver(struct pch_udc_ep *ep) |
| 1937 | { |
| 1938 | struct pch_udc_request *req; |
| 1939 | struct pch_udc_dev *dev = ep->dev; |
| 1940 | unsigned int count; |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 1941 | struct pch_udc_data_dma_desc *td; |
| 1942 | dma_addr_t addr; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1943 | |
| 1944 | if (list_empty(&ep->queue)) |
| 1945 | return; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1946 | /* next request */ |
| 1947 | req = list_entry(ep->queue.next, struct pch_udc_request, queue); |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1948 | pch_udc_clear_dma(ep->dev, DMA_DIR_RX); |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 1949 | pch_udc_ep_set_ddptr(ep, 0); |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 1950 | if ((req->td_data_last->status & PCH_UDC_BUFF_STS) == |
| 1951 | PCH_UDC_BS_DMA_DONE) |
| 1952 | td = req->td_data_last; |
| 1953 | else |
| 1954 | td = req->td_data; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1955 | |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 1956 | while (1) { |
| 1957 | if ((td->status & PCH_UDC_RXTX_STS) != PCH_UDC_RTS_SUCC) { |
| 1958 | dev_err(&dev->pdev->dev, "Invalid RXTX status=0x%08x " |
| 1959 | "epstatus=0x%08x\n", |
| 1960 | (req->td_data->status & PCH_UDC_RXTX_STS), |
| 1961 | (int)(ep->epsts)); |
| 1962 | return; |
| 1963 | } |
| 1964 | if ((td->status & PCH_UDC_BUFF_STS) == PCH_UDC_BS_DMA_DONE) |
| 1965 | if (td->status | PCH_UDC_DMA_LAST) { |
| 1966 | count = td->status & PCH_UDC_RXTX_BYTES; |
| 1967 | break; |
| 1968 | } |
| 1969 | if (td == req->td_data_last) { |
| 1970 | dev_err(&dev->pdev->dev, "Not complete RX descriptor"); |
| 1971 | return; |
| 1972 | } |
| 1973 | addr = (dma_addr_t)td->next; |
| 1974 | td = phys_to_virt(addr); |
| 1975 | } |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1976 | /* on 64k packets the RXBYTES field is zero */ |
| 1977 | if (!count && (req->req.length == UDC_DMA_MAXPACKET)) |
| 1978 | count = UDC_DMA_MAXPACKET; |
| 1979 | req->td_data->status |= PCH_UDC_DMA_LAST; |
Toshiharu Okada | c17f459 | 2011-02-07 17:01:26 +0900 | [diff] [blame] | 1980 | td->status |= PCH_UDC_BS_HST_BSY; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 1981 | |
| 1982 | req->dma_going = 0; |
| 1983 | req->req.actual = count; |
| 1984 | complete_req(ep, req, 0); |
| 1985 | /* If there is a new/failed requests try that now */ |
| 1986 | if (!list_empty(&ep->queue)) { |
| 1987 | req = list_entry(ep->queue.next, struct pch_udc_request, queue); |
| 1988 | pch_udc_start_rxrequest(ep, req); |
| 1989 | } |
| 1990 | } |
| 1991 | |
| 1992 | /** |
| 1993 | * pch_udc_svc_data_in() - This function process endpoint interrupts |
| 1994 | * for IN endpoints |
| 1995 | * @dev: Reference to the device structure |
| 1996 | * @ep_num: Endpoint that generated the interrupt |
| 1997 | */ |
| 1998 | static void pch_udc_svc_data_in(struct pch_udc_dev *dev, int ep_num) |
| 1999 | { |
| 2000 | u32 epsts; |
| 2001 | struct pch_udc_ep *ep; |
| 2002 | |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 2003 | ep = &dev->ep[UDC_EPIN_IDX(ep_num)]; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2004 | epsts = ep->epsts; |
| 2005 | ep->epsts = 0; |
| 2006 | |
| 2007 | if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE | |
| 2008 | UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY | |
| 2009 | UDC_EPSTS_RSS | UDC_EPSTS_XFERDONE))) |
| 2010 | return; |
| 2011 | if ((epsts & UDC_EPSTS_BNA)) |
| 2012 | return; |
| 2013 | if (epsts & UDC_EPSTS_HE) |
| 2014 | return; |
| 2015 | if (epsts & UDC_EPSTS_RSS) { |
| 2016 | pch_udc_ep_set_stall(ep); |
| 2017 | pch_udc_enable_ep_interrupts(ep->dev, |
| 2018 | PCH_UDC_EPINT(ep->in, ep->num)); |
| 2019 | } |
Richard Röjfors | 49e2083 | 2010-12-07 17:28:30 +0100 | [diff] [blame] | 2020 | if (epsts & UDC_EPSTS_RCS) { |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2021 | if (!dev->prot_stall) { |
| 2022 | pch_udc_ep_clear_stall(ep); |
| 2023 | } else { |
| 2024 | pch_udc_ep_set_stall(ep); |
| 2025 | pch_udc_enable_ep_interrupts(ep->dev, |
| 2026 | PCH_UDC_EPINT(ep->in, ep->num)); |
| 2027 | } |
Richard Röjfors | 49e2083 | 2010-12-07 17:28:30 +0100 | [diff] [blame] | 2028 | } |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2029 | if (epsts & UDC_EPSTS_TDC) |
| 2030 | pch_udc_complete_transfer(ep); |
| 2031 | /* On IN interrupt, provide data if we have any */ |
| 2032 | if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_RSS) && |
| 2033 | !(epsts & UDC_EPSTS_TDC) && !(epsts & UDC_EPSTS_TXEMPTY)) |
| 2034 | pch_udc_start_next_txrequest(ep); |
| 2035 | } |
| 2036 | |
| 2037 | /** |
| 2038 | * pch_udc_svc_data_out() - Handles interrupts from OUT endpoint |
| 2039 | * @dev: Reference to the device structure |
| 2040 | * @ep_num: Endpoint that generated the interrupt |
| 2041 | */ |
| 2042 | static void pch_udc_svc_data_out(struct pch_udc_dev *dev, int ep_num) |
| 2043 | { |
| 2044 | u32 epsts; |
| 2045 | struct pch_udc_ep *ep; |
| 2046 | struct pch_udc_request *req = NULL; |
| 2047 | |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 2048 | ep = &dev->ep[UDC_EPOUT_IDX(ep_num)]; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2049 | epsts = ep->epsts; |
| 2050 | ep->epsts = 0; |
| 2051 | |
| 2052 | if ((epsts & UDC_EPSTS_BNA) && (!list_empty(&ep->queue))) { |
| 2053 | /* next request */ |
| 2054 | req = list_entry(ep->queue.next, struct pch_udc_request, |
| 2055 | queue); |
| 2056 | if ((req->td_data_last->status & PCH_UDC_BUFF_STS) != |
| 2057 | PCH_UDC_BS_DMA_DONE) { |
| 2058 | if (!req->dma_going) |
| 2059 | pch_udc_start_rxrequest(ep, req); |
| 2060 | return; |
| 2061 | } |
| 2062 | } |
| 2063 | if (epsts & UDC_EPSTS_HE) |
| 2064 | return; |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 2065 | if (epsts & UDC_EPSTS_RSS) { |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2066 | pch_udc_ep_set_stall(ep); |
| 2067 | pch_udc_enable_ep_interrupts(ep->dev, |
| 2068 | PCH_UDC_EPINT(ep->in, ep->num)); |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 2069 | } |
Richard Röjfors | 49e2083 | 2010-12-07 17:28:30 +0100 | [diff] [blame] | 2070 | if (epsts & UDC_EPSTS_RCS) { |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2071 | if (!dev->prot_stall) { |
| 2072 | pch_udc_ep_clear_stall(ep); |
| 2073 | } else { |
| 2074 | pch_udc_ep_set_stall(ep); |
| 2075 | pch_udc_enable_ep_interrupts(ep->dev, |
| 2076 | PCH_UDC_EPINT(ep->in, ep->num)); |
| 2077 | } |
Richard Röjfors | 49e2083 | 2010-12-07 17:28:30 +0100 | [diff] [blame] | 2078 | } |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2079 | if (((epsts & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) == |
| 2080 | UDC_EPSTS_OUT_DATA) { |
| 2081 | if (ep->dev->prot_stall == 1) { |
| 2082 | pch_udc_ep_set_stall(ep); |
| 2083 | pch_udc_enable_ep_interrupts(ep->dev, |
| 2084 | PCH_UDC_EPINT(ep->in, ep->num)); |
| 2085 | } else { |
| 2086 | pch_udc_complete_receiver(ep); |
| 2087 | } |
| 2088 | } |
| 2089 | if (list_empty(&ep->queue)) |
| 2090 | pch_udc_set_dma(dev, DMA_DIR_RX); |
| 2091 | } |
| 2092 | |
| 2093 | /** |
| 2094 | * pch_udc_svc_control_in() - Handle Control IN endpoint interrupts |
| 2095 | * @dev: Reference to the device structure |
| 2096 | */ |
| 2097 | static void pch_udc_svc_control_in(struct pch_udc_dev *dev) |
| 2098 | { |
| 2099 | u32 epsts; |
| 2100 | struct pch_udc_ep *ep; |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 2101 | struct pch_udc_ep *ep_out; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2102 | |
| 2103 | ep = &dev->ep[UDC_EP0IN_IDX]; |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 2104 | ep_out = &dev->ep[UDC_EP0OUT_IDX]; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2105 | epsts = ep->epsts; |
| 2106 | ep->epsts = 0; |
| 2107 | |
| 2108 | if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE | |
| 2109 | UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY | |
| 2110 | UDC_EPSTS_XFERDONE))) |
| 2111 | return; |
| 2112 | if ((epsts & UDC_EPSTS_BNA)) |
| 2113 | return; |
| 2114 | if (epsts & UDC_EPSTS_HE) |
| 2115 | return; |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 2116 | if ((epsts & UDC_EPSTS_TDC) && (!dev->stall)) { |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2117 | pch_udc_complete_transfer(ep); |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 2118 | pch_udc_clear_dma(dev, DMA_DIR_RX); |
| 2119 | ep_out->td_data->status = (ep_out->td_data->status & |
| 2120 | ~PCH_UDC_BUFF_STS) | |
| 2121 | PCH_UDC_BS_HST_RDY; |
| 2122 | pch_udc_ep_clear_nak(ep_out); |
| 2123 | pch_udc_set_dma(dev, DMA_DIR_RX); |
| 2124 | pch_udc_ep_set_rrdy(ep_out); |
| 2125 | } |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2126 | /* On IN interrupt, provide data if we have any */ |
| 2127 | if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_TDC) && |
| 2128 | !(epsts & UDC_EPSTS_TXEMPTY)) |
| 2129 | pch_udc_start_next_txrequest(ep); |
| 2130 | } |
| 2131 | |
| 2132 | /** |
| 2133 | * pch_udc_svc_control_out() - Routine that handle Control |
| 2134 | * OUT endpoint interrupts |
| 2135 | * @dev: Reference to the device structure |
| 2136 | */ |
| 2137 | static void pch_udc_svc_control_out(struct pch_udc_dev *dev) |
| 2138 | { |
| 2139 | u32 stat; |
| 2140 | int setup_supported; |
| 2141 | struct pch_udc_ep *ep; |
| 2142 | |
| 2143 | ep = &dev->ep[UDC_EP0OUT_IDX]; |
| 2144 | stat = ep->epsts; |
| 2145 | ep->epsts = 0; |
| 2146 | |
| 2147 | /* If setup data */ |
| 2148 | if (((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) == |
| 2149 | UDC_EPSTS_OUT_SETUP) { |
| 2150 | dev->stall = 0; |
| 2151 | dev->ep[UDC_EP0IN_IDX].halted = 0; |
| 2152 | dev->ep[UDC_EP0OUT_IDX].halted = 0; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2153 | dev->setup_data = ep->td_stp->request; |
| 2154 | pch_udc_init_setup_buff(ep->td_stp); |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 2155 | pch_udc_clear_dma(dev, DMA_DIR_RX); |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2156 | pch_udc_ep_fifo_flush(&(dev->ep[UDC_EP0IN_IDX]), |
| 2157 | dev->ep[UDC_EP0IN_IDX].in); |
| 2158 | if ((dev->setup_data.bRequestType & USB_DIR_IN)) |
| 2159 | dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep; |
| 2160 | else /* OUT */ |
| 2161 | dev->gadget.ep0 = &ep->ep; |
| 2162 | spin_unlock(&dev->lock); |
| 2163 | /* If Mass storage Reset */ |
| 2164 | if ((dev->setup_data.bRequestType == 0x21) && |
| 2165 | (dev->setup_data.bRequest == 0xFF)) |
| 2166 | dev->prot_stall = 0; |
| 2167 | /* call gadget with setup data received */ |
| 2168 | setup_supported = dev->driver->setup(&dev->gadget, |
| 2169 | &dev->setup_data); |
| 2170 | spin_lock(&dev->lock); |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 2171 | |
| 2172 | if (dev->setup_data.bRequestType & USB_DIR_IN) { |
| 2173 | ep->td_data->status = (ep->td_data->status & |
| 2174 | ~PCH_UDC_BUFF_STS) | |
| 2175 | PCH_UDC_BS_HST_RDY; |
| 2176 | pch_udc_ep_set_ddptr(ep, ep->td_data_phys); |
| 2177 | } |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2178 | /* ep0 in returns data on IN phase */ |
| 2179 | if (setup_supported >= 0 && setup_supported < |
| 2180 | UDC_EP0IN_MAX_PKT_SIZE) { |
| 2181 | pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX])); |
| 2182 | /* Gadget would have queued a request when |
| 2183 | * we called the setup */ |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 2184 | if (!(dev->setup_data.bRequestType & USB_DIR_IN)) { |
| 2185 | pch_udc_set_dma(dev, DMA_DIR_RX); |
| 2186 | pch_udc_ep_clear_nak(ep); |
| 2187 | } |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2188 | } else if (setup_supported < 0) { |
| 2189 | /* if unsupported request, then stall */ |
| 2190 | pch_udc_ep_set_stall(&(dev->ep[UDC_EP0IN_IDX])); |
| 2191 | pch_udc_enable_ep_interrupts(ep->dev, |
| 2192 | PCH_UDC_EPINT(ep->in, ep->num)); |
| 2193 | dev->stall = 0; |
| 2194 | pch_udc_set_dma(dev, DMA_DIR_RX); |
| 2195 | } else { |
| 2196 | dev->waiting_zlp_ack = 1; |
| 2197 | } |
| 2198 | } else if ((((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) == |
| 2199 | UDC_EPSTS_OUT_DATA) && !dev->stall) { |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 2200 | pch_udc_clear_dma(dev, DMA_DIR_RX); |
| 2201 | pch_udc_ep_set_ddptr(ep, 0); |
| 2202 | if (!list_empty(&ep->queue)) { |
Richard Röjfors | ff176a4 | 2010-12-07 17:28:33 +0100 | [diff] [blame] | 2203 | ep->epsts = stat; |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 2204 | pch_udc_svc_data_out(dev, PCH_UDC_EP0); |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2205 | } |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 2206 | pch_udc_set_dma(dev, DMA_DIR_RX); |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2207 | } |
| 2208 | pch_udc_ep_set_rrdy(ep); |
| 2209 | } |
| 2210 | |
| 2211 | |
| 2212 | /** |
| 2213 | * pch_udc_postsvc_epinters() - This function enables end point interrupts |
| 2214 | * and clears NAK status |
| 2215 | * @dev: Reference to the device structure |
| 2216 | * @ep_num: End point number |
| 2217 | */ |
| 2218 | static void pch_udc_postsvc_epinters(struct pch_udc_dev *dev, int ep_num) |
| 2219 | { |
| 2220 | struct pch_udc_ep *ep; |
| 2221 | struct pch_udc_request *req; |
| 2222 | |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 2223 | ep = &dev->ep[UDC_EPIN_IDX(ep_num)]; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2224 | if (!list_empty(&ep->queue)) { |
| 2225 | req = list_entry(ep->queue.next, struct pch_udc_request, queue); |
| 2226 | pch_udc_enable_ep_interrupts(ep->dev, |
| 2227 | PCH_UDC_EPINT(ep->in, ep->num)); |
| 2228 | pch_udc_ep_clear_nak(ep); |
| 2229 | } |
| 2230 | } |
| 2231 | |
| 2232 | /** |
| 2233 | * pch_udc_read_all_epstatus() - This function read all endpoint status |
| 2234 | * @dev: Reference to the device structure |
| 2235 | * @ep_intr: Status of endpoint interrupt |
| 2236 | */ |
| 2237 | static void pch_udc_read_all_epstatus(struct pch_udc_dev *dev, u32 ep_intr) |
| 2238 | { |
| 2239 | int i; |
| 2240 | struct pch_udc_ep *ep; |
| 2241 | |
| 2242 | for (i = 0; i < PCH_UDC_USED_EP_NUM; i++) { |
| 2243 | /* IN */ |
| 2244 | if (ep_intr & (0x1 << i)) { |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 2245 | ep = &dev->ep[UDC_EPIN_IDX(i)]; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2246 | ep->epsts = pch_udc_read_ep_status(ep); |
| 2247 | pch_udc_clear_ep_status(ep, ep->epsts); |
| 2248 | } |
| 2249 | /* OUT */ |
| 2250 | if (ep_intr & (0x10000 << i)) { |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 2251 | ep = &dev->ep[UDC_EPOUT_IDX(i)]; |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2252 | ep->epsts = pch_udc_read_ep_status(ep); |
| 2253 | pch_udc_clear_ep_status(ep, ep->epsts); |
| 2254 | } |
| 2255 | } |
| 2256 | } |
| 2257 | |
| 2258 | /** |
| 2259 | * pch_udc_activate_control_ep() - This function enables the control endpoints |
| 2260 | * for traffic after a reset |
| 2261 | * @dev: Reference to the device structure |
| 2262 | */ |
| 2263 | static void pch_udc_activate_control_ep(struct pch_udc_dev *dev) |
| 2264 | { |
| 2265 | struct pch_udc_ep *ep; |
| 2266 | u32 val; |
| 2267 | |
| 2268 | /* Setup the IN endpoint */ |
| 2269 | ep = &dev->ep[UDC_EP0IN_IDX]; |
| 2270 | pch_udc_clear_ep_control(ep); |
| 2271 | pch_udc_ep_fifo_flush(ep, ep->in); |
| 2272 | pch_udc_ep_set_bufsz(ep, UDC_EP0IN_BUFF_SIZE, ep->in); |
| 2273 | pch_udc_ep_set_maxpkt(ep, UDC_EP0IN_MAX_PKT_SIZE); |
| 2274 | /* Initialize the IN EP Descriptor */ |
| 2275 | ep->td_data = NULL; |
| 2276 | ep->td_stp = NULL; |
| 2277 | ep->td_data_phys = 0; |
| 2278 | ep->td_stp_phys = 0; |
| 2279 | |
| 2280 | /* Setup the OUT endpoint */ |
| 2281 | ep = &dev->ep[UDC_EP0OUT_IDX]; |
| 2282 | pch_udc_clear_ep_control(ep); |
| 2283 | pch_udc_ep_fifo_flush(ep, ep->in); |
| 2284 | pch_udc_ep_set_bufsz(ep, UDC_EP0OUT_BUFF_SIZE, ep->in); |
| 2285 | pch_udc_ep_set_maxpkt(ep, UDC_EP0OUT_MAX_PKT_SIZE); |
| 2286 | val = UDC_EP0OUT_MAX_PKT_SIZE << UDC_CSR_NE_MAX_PKT_SHIFT; |
| 2287 | pch_udc_write_csr(ep->dev, val, UDC_EP0OUT_IDX); |
| 2288 | |
| 2289 | /* Initialize the SETUP buffer */ |
| 2290 | pch_udc_init_setup_buff(ep->td_stp); |
| 2291 | /* Write the pointer address of dma descriptor */ |
| 2292 | pch_udc_ep_set_subptr(ep, ep->td_stp_phys); |
| 2293 | /* Write the pointer address of Setup descriptor */ |
| 2294 | pch_udc_ep_set_ddptr(ep, ep->td_data_phys); |
| 2295 | |
| 2296 | /* Initialize the dma descriptor */ |
| 2297 | ep->td_data->status = PCH_UDC_DMA_LAST; |
| 2298 | ep->td_data->dataptr = dev->dma_addr; |
| 2299 | ep->td_data->next = ep->td_data_phys; |
| 2300 | |
| 2301 | pch_udc_ep_clear_nak(ep); |
| 2302 | } |
| 2303 | |
| 2304 | |
| 2305 | /** |
| 2306 | * pch_udc_svc_ur_interrupt() - This function handles a USB reset interrupt |
| 2307 | * @dev: Reference to driver structure |
| 2308 | */ |
| 2309 | static void pch_udc_svc_ur_interrupt(struct pch_udc_dev *dev) |
| 2310 | { |
| 2311 | struct pch_udc_ep *ep; |
| 2312 | int i; |
| 2313 | |
| 2314 | pch_udc_clear_dma(dev, DMA_DIR_TX); |
| 2315 | pch_udc_clear_dma(dev, DMA_DIR_RX); |
| 2316 | /* Mask all endpoint interrupts */ |
| 2317 | pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL); |
| 2318 | /* clear all endpoint interrupts */ |
| 2319 | pch_udc_write_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL); |
| 2320 | |
| 2321 | for (i = 0; i < PCH_UDC_EP_NUM; i++) { |
| 2322 | ep = &dev->ep[i]; |
| 2323 | pch_udc_clear_ep_status(ep, UDC_EPSTS_ALL_CLR_MASK); |
| 2324 | pch_udc_clear_ep_control(ep); |
| 2325 | pch_udc_ep_set_ddptr(ep, 0); |
| 2326 | pch_udc_write_csr(ep->dev, 0x00, i); |
| 2327 | } |
| 2328 | dev->stall = 0; |
| 2329 | dev->prot_stall = 0; |
| 2330 | dev->waiting_zlp_ack = 0; |
| 2331 | dev->set_cfg_not_acked = 0; |
| 2332 | |
| 2333 | /* disable ep to empty req queue. Skip the control EP's */ |
| 2334 | for (i = 0; i < (PCH_UDC_USED_EP_NUM*2); i++) { |
| 2335 | ep = &dev->ep[i]; |
| 2336 | pch_udc_ep_set_nak(ep); |
| 2337 | pch_udc_ep_fifo_flush(ep, ep->in); |
| 2338 | /* Complete request queue */ |
| 2339 | empty_req_queue(ep); |
| 2340 | } |
| 2341 | if (dev->driver && dev->driver->disconnect) |
| 2342 | dev->driver->disconnect(&dev->gadget); |
| 2343 | } |
| 2344 | |
| 2345 | /** |
| 2346 | * pch_udc_svc_enum_interrupt() - This function handles a USB speed enumeration |
| 2347 | * done interrupt |
| 2348 | * @dev: Reference to driver structure |
| 2349 | */ |
| 2350 | static void pch_udc_svc_enum_interrupt(struct pch_udc_dev *dev) |
| 2351 | { |
| 2352 | u32 dev_stat, dev_speed; |
| 2353 | u32 speed = USB_SPEED_FULL; |
| 2354 | |
| 2355 | dev_stat = pch_udc_read_device_status(dev); |
| 2356 | dev_speed = (dev_stat & UDC_DEVSTS_ENUM_SPEED_MASK) >> |
| 2357 | UDC_DEVSTS_ENUM_SPEED_SHIFT; |
| 2358 | switch (dev_speed) { |
| 2359 | case UDC_DEVSTS_ENUM_SPEED_HIGH: |
| 2360 | speed = USB_SPEED_HIGH; |
| 2361 | break; |
| 2362 | case UDC_DEVSTS_ENUM_SPEED_FULL: |
| 2363 | speed = USB_SPEED_FULL; |
| 2364 | break; |
| 2365 | case UDC_DEVSTS_ENUM_SPEED_LOW: |
| 2366 | speed = USB_SPEED_LOW; |
| 2367 | break; |
| 2368 | default: |
| 2369 | BUG(); |
| 2370 | } |
| 2371 | dev->gadget.speed = speed; |
| 2372 | pch_udc_activate_control_ep(dev); |
| 2373 | pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 | UDC_EPINT_OUT_EP0); |
| 2374 | pch_udc_set_dma(dev, DMA_DIR_TX); |
| 2375 | pch_udc_set_dma(dev, DMA_DIR_RX); |
| 2376 | pch_udc_ep_set_rrdy(&(dev->ep[UDC_EP0OUT_IDX])); |
| 2377 | } |
| 2378 | |
| 2379 | /** |
| 2380 | * pch_udc_svc_intf_interrupt() - This function handles a set interface |
| 2381 | * interrupt |
| 2382 | * @dev: Reference to driver structure |
| 2383 | */ |
| 2384 | static void pch_udc_svc_intf_interrupt(struct pch_udc_dev *dev) |
| 2385 | { |
| 2386 | u32 reg, dev_stat = 0; |
| 2387 | int i, ret; |
| 2388 | |
| 2389 | dev_stat = pch_udc_read_device_status(dev); |
| 2390 | dev->cfg_data.cur_intf = (dev_stat & UDC_DEVSTS_INTF_MASK) >> |
| 2391 | UDC_DEVSTS_INTF_SHIFT; |
| 2392 | dev->cfg_data.cur_alt = (dev_stat & UDC_DEVSTS_ALT_MASK) >> |
| 2393 | UDC_DEVSTS_ALT_SHIFT; |
| 2394 | dev->set_cfg_not_acked = 1; |
| 2395 | /* Construct the usb request for gadget driver and inform it */ |
| 2396 | memset(&dev->setup_data, 0 , sizeof dev->setup_data); |
| 2397 | dev->setup_data.bRequest = USB_REQ_SET_INTERFACE; |
| 2398 | dev->setup_data.bRequestType = USB_RECIP_INTERFACE; |
| 2399 | dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_alt); |
| 2400 | dev->setup_data.wIndex = cpu_to_le16(dev->cfg_data.cur_intf); |
| 2401 | /* programm the Endpoint Cfg registers */ |
| 2402 | /* Only one end point cfg register */ |
| 2403 | reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX); |
| 2404 | reg = (reg & ~UDC_CSR_NE_INTF_MASK) | |
| 2405 | (dev->cfg_data.cur_intf << UDC_CSR_NE_INTF_SHIFT); |
| 2406 | reg = (reg & ~UDC_CSR_NE_ALT_MASK) | |
| 2407 | (dev->cfg_data.cur_alt << UDC_CSR_NE_ALT_SHIFT); |
| 2408 | pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX); |
| 2409 | for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) { |
| 2410 | /* clear stall bits */ |
| 2411 | pch_udc_ep_clear_stall(&(dev->ep[i])); |
| 2412 | dev->ep[i].halted = 0; |
| 2413 | } |
| 2414 | dev->stall = 0; |
| 2415 | spin_unlock(&dev->lock); |
| 2416 | ret = dev->driver->setup(&dev->gadget, &dev->setup_data); |
| 2417 | spin_lock(&dev->lock); |
| 2418 | } |
| 2419 | |
| 2420 | /** |
| 2421 | * pch_udc_svc_cfg_interrupt() - This function handles a set configuration |
| 2422 | * interrupt |
| 2423 | * @dev: Reference to driver structure |
| 2424 | */ |
| 2425 | static void pch_udc_svc_cfg_interrupt(struct pch_udc_dev *dev) |
| 2426 | { |
| 2427 | int i, ret; |
| 2428 | u32 reg, dev_stat = 0; |
| 2429 | |
| 2430 | dev_stat = pch_udc_read_device_status(dev); |
| 2431 | dev->set_cfg_not_acked = 1; |
| 2432 | dev->cfg_data.cur_cfg = (dev_stat & UDC_DEVSTS_CFG_MASK) >> |
| 2433 | UDC_DEVSTS_CFG_SHIFT; |
| 2434 | /* make usb request for gadget driver */ |
| 2435 | memset(&dev->setup_data, 0 , sizeof dev->setup_data); |
| 2436 | dev->setup_data.bRequest = USB_REQ_SET_CONFIGURATION; |
| 2437 | dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_cfg); |
| 2438 | /* program the NE registers */ |
| 2439 | /* Only one end point cfg register */ |
| 2440 | reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX); |
| 2441 | reg = (reg & ~UDC_CSR_NE_CFG_MASK) | |
| 2442 | (dev->cfg_data.cur_cfg << UDC_CSR_NE_CFG_SHIFT); |
| 2443 | pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX); |
| 2444 | for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) { |
| 2445 | /* clear stall bits */ |
| 2446 | pch_udc_ep_clear_stall(&(dev->ep[i])); |
| 2447 | dev->ep[i].halted = 0; |
| 2448 | } |
| 2449 | dev->stall = 0; |
| 2450 | |
| 2451 | /* call gadget zero with setup data received */ |
| 2452 | spin_unlock(&dev->lock); |
| 2453 | ret = dev->driver->setup(&dev->gadget, &dev->setup_data); |
| 2454 | spin_lock(&dev->lock); |
| 2455 | } |
| 2456 | |
| 2457 | /** |
| 2458 | * pch_udc_dev_isr() - This function services device interrupts |
| 2459 | * by invoking appropriate routines. |
| 2460 | * @dev: Reference to the device structure |
| 2461 | * @dev_intr: The Device interrupt status. |
| 2462 | */ |
| 2463 | static void pch_udc_dev_isr(struct pch_udc_dev *dev, u32 dev_intr) |
| 2464 | { |
| 2465 | /* USB Reset Interrupt */ |
| 2466 | if (dev_intr & UDC_DEVINT_UR) |
| 2467 | pch_udc_svc_ur_interrupt(dev); |
| 2468 | /* Enumeration Done Interrupt */ |
| 2469 | if (dev_intr & UDC_DEVINT_ENUM) |
| 2470 | pch_udc_svc_enum_interrupt(dev); |
| 2471 | /* Set Interface Interrupt */ |
| 2472 | if (dev_intr & UDC_DEVINT_SI) |
| 2473 | pch_udc_svc_intf_interrupt(dev); |
| 2474 | /* Set Config Interrupt */ |
| 2475 | if (dev_intr & UDC_DEVINT_SC) |
| 2476 | pch_udc_svc_cfg_interrupt(dev); |
| 2477 | /* USB Suspend interrupt */ |
| 2478 | if (dev_intr & UDC_DEVINT_US) |
| 2479 | dev_dbg(&dev->pdev->dev, "USB_SUSPEND\n"); |
| 2480 | /* Clear the SOF interrupt, if enabled */ |
| 2481 | if (dev_intr & UDC_DEVINT_SOF) |
| 2482 | dev_dbg(&dev->pdev->dev, "SOF\n"); |
| 2483 | /* ES interrupt, IDLE > 3ms on the USB */ |
| 2484 | if (dev_intr & UDC_DEVINT_ES) |
| 2485 | dev_dbg(&dev->pdev->dev, "ES\n"); |
| 2486 | /* RWKP interrupt */ |
| 2487 | if (dev_intr & UDC_DEVINT_RWKP) |
| 2488 | dev_dbg(&dev->pdev->dev, "RWKP\n"); |
| 2489 | } |
| 2490 | |
| 2491 | /** |
| 2492 | * pch_udc_isr() - This function handles interrupts from the PCH USB Device |
| 2493 | * @irq: Interrupt request number |
| 2494 | * @dev: Reference to the device structure |
| 2495 | */ |
| 2496 | static irqreturn_t pch_udc_isr(int irq, void *pdev) |
| 2497 | { |
| 2498 | struct pch_udc_dev *dev = (struct pch_udc_dev *) pdev; |
| 2499 | u32 dev_intr, ep_intr; |
| 2500 | int i; |
| 2501 | |
| 2502 | dev_intr = pch_udc_read_device_interrupts(dev); |
| 2503 | ep_intr = pch_udc_read_ep_interrupts(dev); |
| 2504 | |
| 2505 | if (dev_intr) |
| 2506 | /* Clear device interrupts */ |
| 2507 | pch_udc_write_device_interrupts(dev, dev_intr); |
| 2508 | if (ep_intr) |
| 2509 | /* Clear ep interrupts */ |
| 2510 | pch_udc_write_ep_interrupts(dev, ep_intr); |
| 2511 | if (!dev_intr && !ep_intr) |
| 2512 | return IRQ_NONE; |
| 2513 | spin_lock(&dev->lock); |
| 2514 | if (dev_intr) |
| 2515 | pch_udc_dev_isr(dev, dev_intr); |
| 2516 | if (ep_intr) { |
| 2517 | pch_udc_read_all_epstatus(dev, ep_intr); |
| 2518 | /* Process Control In interrupts, if present */ |
| 2519 | if (ep_intr & UDC_EPINT_IN_EP0) { |
| 2520 | pch_udc_svc_control_in(dev); |
| 2521 | pch_udc_postsvc_epinters(dev, 0); |
| 2522 | } |
| 2523 | /* Process Control Out interrupts, if present */ |
| 2524 | if (ep_intr & UDC_EPINT_OUT_EP0) |
| 2525 | pch_udc_svc_control_out(dev); |
| 2526 | /* Process data in end point interrupts */ |
| 2527 | for (i = 1; i < PCH_UDC_USED_EP_NUM; i++) { |
| 2528 | if (ep_intr & (1 << i)) { |
| 2529 | pch_udc_svc_data_in(dev, i); |
| 2530 | pch_udc_postsvc_epinters(dev, i); |
| 2531 | } |
| 2532 | } |
| 2533 | /* Process data out end point interrupts */ |
| 2534 | for (i = UDC_EPINT_OUT_SHIFT + 1; i < (UDC_EPINT_OUT_SHIFT + |
| 2535 | PCH_UDC_USED_EP_NUM); i++) |
| 2536 | if (ep_intr & (1 << i)) |
| 2537 | pch_udc_svc_data_out(dev, i - |
| 2538 | UDC_EPINT_OUT_SHIFT); |
| 2539 | } |
| 2540 | spin_unlock(&dev->lock); |
| 2541 | return IRQ_HANDLED; |
| 2542 | } |
| 2543 | |
| 2544 | /** |
| 2545 | * pch_udc_setup_ep0() - This function enables control endpoint for traffic |
| 2546 | * @dev: Reference to the device structure |
| 2547 | */ |
| 2548 | static void pch_udc_setup_ep0(struct pch_udc_dev *dev) |
| 2549 | { |
| 2550 | /* enable ep0 interrupts */ |
| 2551 | pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 | |
| 2552 | UDC_EPINT_OUT_EP0); |
| 2553 | /* enable device interrupts */ |
| 2554 | pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US | |
| 2555 | UDC_DEVINT_ES | UDC_DEVINT_ENUM | |
| 2556 | UDC_DEVINT_SI | UDC_DEVINT_SC); |
| 2557 | } |
| 2558 | |
| 2559 | /** |
| 2560 | * gadget_release() - Free the gadget driver private data |
| 2561 | * @pdev reference to struct pci_dev |
| 2562 | */ |
| 2563 | static void gadget_release(struct device *pdev) |
| 2564 | { |
| 2565 | struct pch_udc_dev *dev = dev_get_drvdata(pdev); |
| 2566 | |
| 2567 | kfree(dev); |
| 2568 | } |
| 2569 | |
| 2570 | /** |
| 2571 | * pch_udc_pcd_reinit() - This API initializes the endpoint structures |
| 2572 | * @dev: Reference to the driver structure |
| 2573 | */ |
| 2574 | static void pch_udc_pcd_reinit(struct pch_udc_dev *dev) |
| 2575 | { |
| 2576 | const char *const ep_string[] = { |
| 2577 | ep0_string, "ep0out", "ep1in", "ep1out", "ep2in", "ep2out", |
| 2578 | "ep3in", "ep3out", "ep4in", "ep4out", "ep5in", "ep5out", |
| 2579 | "ep6in", "ep6out", "ep7in", "ep7out", "ep8in", "ep8out", |
| 2580 | "ep9in", "ep9out", "ep10in", "ep10out", "ep11in", "ep11out", |
| 2581 | "ep12in", "ep12out", "ep13in", "ep13out", "ep14in", "ep14out", |
| 2582 | "ep15in", "ep15out", |
| 2583 | }; |
| 2584 | int i; |
| 2585 | |
| 2586 | dev->gadget.speed = USB_SPEED_UNKNOWN; |
| 2587 | INIT_LIST_HEAD(&dev->gadget.ep_list); |
| 2588 | |
| 2589 | /* Initialize the endpoints structures */ |
| 2590 | memset(dev->ep, 0, sizeof dev->ep); |
| 2591 | for (i = 0; i < PCH_UDC_EP_NUM; i++) { |
| 2592 | struct pch_udc_ep *ep = &dev->ep[i]; |
| 2593 | ep->dev = dev; |
| 2594 | ep->halted = 1; |
| 2595 | ep->num = i / 2; |
| 2596 | ep->in = ~i & 1; |
| 2597 | ep->ep.name = ep_string[i]; |
| 2598 | ep->ep.ops = &pch_udc_ep_ops; |
| 2599 | if (ep->in) |
| 2600 | ep->offset_addr = ep->num * UDC_EP_REG_SHIFT; |
| 2601 | else |
| 2602 | ep->offset_addr = (UDC_EPINT_OUT_SHIFT + ep->num) * |
| 2603 | UDC_EP_REG_SHIFT; |
| 2604 | /* need to set ep->ep.maxpacket and set Default Configuration?*/ |
| 2605 | ep->ep.maxpacket = UDC_BULK_MAX_PKT_SIZE; |
| 2606 | list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list); |
| 2607 | INIT_LIST_HEAD(&ep->queue); |
| 2608 | } |
| 2609 | dev->ep[UDC_EP0IN_IDX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE; |
| 2610 | dev->ep[UDC_EP0OUT_IDX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE; |
| 2611 | |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2612 | /* remove ep0 in and out from the list. They have own pointer */ |
| 2613 | list_del_init(&dev->ep[UDC_EP0IN_IDX].ep.ep_list); |
| 2614 | list_del_init(&dev->ep[UDC_EP0OUT_IDX].ep.ep_list); |
| 2615 | |
| 2616 | dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep; |
| 2617 | INIT_LIST_HEAD(&dev->gadget.ep0->ep_list); |
| 2618 | } |
| 2619 | |
| 2620 | /** |
| 2621 | * pch_udc_pcd_init() - This API initializes the driver structure |
| 2622 | * @dev: Reference to the driver structure |
| 2623 | * |
| 2624 | * Return codes: |
| 2625 | * 0: Success |
| 2626 | */ |
| 2627 | static int pch_udc_pcd_init(struct pch_udc_dev *dev) |
| 2628 | { |
| 2629 | pch_udc_init(dev); |
| 2630 | pch_udc_pcd_reinit(dev); |
| 2631 | return 0; |
| 2632 | } |
| 2633 | |
| 2634 | /** |
| 2635 | * init_dma_pools() - create dma pools during initialization |
| 2636 | * @pdev: reference to struct pci_dev |
| 2637 | */ |
| 2638 | static int init_dma_pools(struct pch_udc_dev *dev) |
| 2639 | { |
| 2640 | struct pch_udc_stp_dma_desc *td_stp; |
| 2641 | struct pch_udc_data_dma_desc *td_data; |
| 2642 | |
| 2643 | /* DMA setup */ |
| 2644 | dev->data_requests = pci_pool_create("data_requests", dev->pdev, |
| 2645 | sizeof(struct pch_udc_data_dma_desc), 0, 0); |
| 2646 | if (!dev->data_requests) { |
| 2647 | dev_err(&dev->pdev->dev, "%s: can't get request data pool\n", |
| 2648 | __func__); |
| 2649 | return -ENOMEM; |
| 2650 | } |
| 2651 | |
| 2652 | /* dma desc for setup data */ |
| 2653 | dev->stp_requests = pci_pool_create("setup requests", dev->pdev, |
| 2654 | sizeof(struct pch_udc_stp_dma_desc), 0, 0); |
| 2655 | if (!dev->stp_requests) { |
| 2656 | dev_err(&dev->pdev->dev, "%s: can't get setup request pool\n", |
| 2657 | __func__); |
| 2658 | return -ENOMEM; |
| 2659 | } |
| 2660 | /* setup */ |
| 2661 | td_stp = pci_pool_alloc(dev->stp_requests, GFP_KERNEL, |
| 2662 | &dev->ep[UDC_EP0OUT_IDX].td_stp_phys); |
| 2663 | if (!td_stp) { |
| 2664 | dev_err(&dev->pdev->dev, |
| 2665 | "%s: can't allocate setup dma descriptor\n", __func__); |
| 2666 | return -ENOMEM; |
| 2667 | } |
| 2668 | dev->ep[UDC_EP0OUT_IDX].td_stp = td_stp; |
| 2669 | |
| 2670 | /* data: 0 packets !? */ |
| 2671 | td_data = pci_pool_alloc(dev->data_requests, GFP_KERNEL, |
| 2672 | &dev->ep[UDC_EP0OUT_IDX].td_data_phys); |
| 2673 | if (!td_data) { |
| 2674 | dev_err(&dev->pdev->dev, |
| 2675 | "%s: can't allocate data dma descriptor\n", __func__); |
| 2676 | return -ENOMEM; |
| 2677 | } |
| 2678 | dev->ep[UDC_EP0OUT_IDX].td_data = td_data; |
| 2679 | dev->ep[UDC_EP0IN_IDX].td_stp = NULL; |
| 2680 | dev->ep[UDC_EP0IN_IDX].td_stp_phys = 0; |
| 2681 | dev->ep[UDC_EP0IN_IDX].td_data = NULL; |
| 2682 | dev->ep[UDC_EP0IN_IDX].td_data_phys = 0; |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 2683 | |
| 2684 | dev->ep0out_buf = kzalloc(UDC_EP0OUT_BUFF_SIZE * 4, GFP_KERNEL); |
| 2685 | if (!dev->ep0out_buf) |
| 2686 | return -ENOMEM; |
| 2687 | dev->dma_addr = dma_map_single(&dev->pdev->dev, dev->ep0out_buf, |
| 2688 | UDC_EP0OUT_BUFF_SIZE * 4, |
| 2689 | DMA_FROM_DEVICE); |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2690 | return 0; |
| 2691 | } |
| 2692 | |
Richard Röjfors | 49e2083 | 2010-12-07 17:28:30 +0100 | [diff] [blame] | 2693 | int usb_gadget_probe_driver(struct usb_gadget_driver *driver, |
| 2694 | int (*bind)(struct usb_gadget *)) |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2695 | { |
| 2696 | struct pch_udc_dev *dev = pch_udc; |
| 2697 | int retval; |
| 2698 | |
Richard Röjfors | 49e2083 | 2010-12-07 17:28:30 +0100 | [diff] [blame] | 2699 | if (!driver || (driver->speed == USB_SPEED_UNKNOWN) || !bind || |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2700 | !driver->setup || !driver->unbind || !driver->disconnect) { |
| 2701 | dev_err(&dev->pdev->dev, |
| 2702 | "%s: invalid driver parameter\n", __func__); |
| 2703 | return -EINVAL; |
| 2704 | } |
| 2705 | |
| 2706 | if (!dev) |
| 2707 | return -ENODEV; |
| 2708 | |
| 2709 | if (dev->driver) { |
| 2710 | dev_err(&dev->pdev->dev, "%s: already bound\n", __func__); |
| 2711 | return -EBUSY; |
| 2712 | } |
| 2713 | driver->driver.bus = NULL; |
| 2714 | dev->driver = driver; |
| 2715 | dev->gadget.dev.driver = &driver->driver; |
| 2716 | |
| 2717 | /* Invoke the bind routine of the gadget driver */ |
Richard Röjfors | 49e2083 | 2010-12-07 17:28:30 +0100 | [diff] [blame] | 2718 | retval = bind(&dev->gadget); |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2719 | |
| 2720 | if (retval) { |
| 2721 | dev_err(&dev->pdev->dev, "%s: binding to %s returning %d\n", |
| 2722 | __func__, driver->driver.name, retval); |
| 2723 | dev->driver = NULL; |
| 2724 | dev->gadget.dev.driver = NULL; |
| 2725 | return retval; |
| 2726 | } |
| 2727 | /* get ready for ep0 traffic */ |
| 2728 | pch_udc_setup_ep0(dev); |
| 2729 | |
| 2730 | /* clear SD */ |
| 2731 | pch_udc_clear_disconnect(dev); |
| 2732 | |
| 2733 | dev->connected = 1; |
| 2734 | return 0; |
| 2735 | } |
Richard Röjfors | 49e2083 | 2010-12-07 17:28:30 +0100 | [diff] [blame] | 2736 | EXPORT_SYMBOL(usb_gadget_probe_driver); |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2737 | |
| 2738 | int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) |
| 2739 | { |
| 2740 | struct pch_udc_dev *dev = pch_udc; |
| 2741 | |
| 2742 | if (!dev) |
| 2743 | return -ENODEV; |
| 2744 | |
| 2745 | if (!driver || (driver != dev->driver)) { |
| 2746 | dev_err(&dev->pdev->dev, |
| 2747 | "%s: invalid driver parameter\n", __func__); |
| 2748 | return -EINVAL; |
| 2749 | } |
| 2750 | |
| 2751 | pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK); |
| 2752 | |
Toshiharu Okada | 15680cd | 2011-01-18 20:26:27 +0900 | [diff] [blame] | 2753 | /* Assures that there are no pending requests with this driver */ |
| 2754 | driver->disconnect(&dev->gadget); |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2755 | driver->unbind(&dev->gadget); |
| 2756 | dev->gadget.dev.driver = NULL; |
| 2757 | dev->driver = NULL; |
| 2758 | dev->connected = 0; |
| 2759 | |
| 2760 | /* set SD */ |
| 2761 | pch_udc_set_disconnect(dev); |
| 2762 | return 0; |
| 2763 | } |
| 2764 | EXPORT_SYMBOL(usb_gadget_unregister_driver); |
| 2765 | |
| 2766 | static void pch_udc_shutdown(struct pci_dev *pdev) |
| 2767 | { |
| 2768 | struct pch_udc_dev *dev = pci_get_drvdata(pdev); |
| 2769 | |
| 2770 | pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK); |
| 2771 | pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL); |
| 2772 | |
| 2773 | /* disable the pullup so the host will think we're gone */ |
| 2774 | pch_udc_set_disconnect(dev); |
| 2775 | } |
| 2776 | |
| 2777 | static void pch_udc_remove(struct pci_dev *pdev) |
| 2778 | { |
| 2779 | struct pch_udc_dev *dev = pci_get_drvdata(pdev); |
| 2780 | |
| 2781 | /* gadget driver must not be registered */ |
| 2782 | if (dev->driver) |
| 2783 | dev_err(&pdev->dev, |
| 2784 | "%s: gadget driver still bound!!!\n", __func__); |
| 2785 | /* dma pool cleanup */ |
| 2786 | if (dev->data_requests) |
| 2787 | pci_pool_destroy(dev->data_requests); |
| 2788 | |
| 2789 | if (dev->stp_requests) { |
| 2790 | /* cleanup DMA desc's for ep0in */ |
| 2791 | if (dev->ep[UDC_EP0OUT_IDX].td_stp) { |
| 2792 | pci_pool_free(dev->stp_requests, |
| 2793 | dev->ep[UDC_EP0OUT_IDX].td_stp, |
| 2794 | dev->ep[UDC_EP0OUT_IDX].td_stp_phys); |
| 2795 | } |
| 2796 | if (dev->ep[UDC_EP0OUT_IDX].td_data) { |
| 2797 | pci_pool_free(dev->stp_requests, |
| 2798 | dev->ep[UDC_EP0OUT_IDX].td_data, |
| 2799 | dev->ep[UDC_EP0OUT_IDX].td_data_phys); |
| 2800 | } |
| 2801 | pci_pool_destroy(dev->stp_requests); |
| 2802 | } |
| 2803 | |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 2804 | if (dev->dma_addr) |
| 2805 | dma_unmap_single(&dev->pdev->dev, dev->dma_addr, |
| 2806 | UDC_EP0OUT_BUFF_SIZE * 4, DMA_FROM_DEVICE); |
| 2807 | kfree(dev->ep0out_buf); |
| 2808 | |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2809 | pch_udc_exit(dev); |
| 2810 | |
| 2811 | if (dev->irq_registered) |
| 2812 | free_irq(pdev->irq, dev); |
| 2813 | if (dev->base_addr) |
| 2814 | iounmap(dev->base_addr); |
| 2815 | if (dev->mem_region) |
| 2816 | release_mem_region(dev->phys_addr, |
| 2817 | pci_resource_len(pdev, PCH_UDC_PCI_BAR)); |
| 2818 | if (dev->active) |
| 2819 | pci_disable_device(pdev); |
| 2820 | if (dev->registered) |
| 2821 | device_unregister(&dev->gadget.dev); |
| 2822 | kfree(dev); |
| 2823 | pci_set_drvdata(pdev, NULL); |
| 2824 | } |
| 2825 | |
| 2826 | #ifdef CONFIG_PM |
| 2827 | static int pch_udc_suspend(struct pci_dev *pdev, pm_message_t state) |
| 2828 | { |
| 2829 | struct pch_udc_dev *dev = pci_get_drvdata(pdev); |
| 2830 | |
| 2831 | pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK); |
| 2832 | pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL); |
| 2833 | |
| 2834 | pci_disable_device(pdev); |
| 2835 | pci_enable_wake(pdev, PCI_D3hot, 0); |
| 2836 | |
| 2837 | if (pci_save_state(pdev)) { |
| 2838 | dev_err(&pdev->dev, |
| 2839 | "%s: could not save PCI config state\n", __func__); |
| 2840 | return -ENOMEM; |
| 2841 | } |
| 2842 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
| 2843 | return 0; |
| 2844 | } |
| 2845 | |
| 2846 | static int pch_udc_resume(struct pci_dev *pdev) |
| 2847 | { |
| 2848 | int ret; |
| 2849 | |
| 2850 | pci_set_power_state(pdev, PCI_D0); |
Toshiharu Okada | abab0c6 | 2010-12-29 10:07:33 +0900 | [diff] [blame] | 2851 | pci_restore_state(pdev); |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2852 | ret = pci_enable_device(pdev); |
| 2853 | if (ret) { |
| 2854 | dev_err(&pdev->dev, "%s: pci_enable_device failed\n", __func__); |
| 2855 | return ret; |
| 2856 | } |
| 2857 | pci_enable_wake(pdev, PCI_D3hot, 0); |
| 2858 | return 0; |
| 2859 | } |
| 2860 | #else |
| 2861 | #define pch_udc_suspend NULL |
| 2862 | #define pch_udc_resume NULL |
| 2863 | #endif /* CONFIG_PM */ |
| 2864 | |
| 2865 | static int pch_udc_probe(struct pci_dev *pdev, |
| 2866 | const struct pci_device_id *id) |
| 2867 | { |
| 2868 | unsigned long resource; |
| 2869 | unsigned long len; |
| 2870 | int retval; |
| 2871 | struct pch_udc_dev *dev; |
| 2872 | |
| 2873 | /* one udc only */ |
| 2874 | if (pch_udc) { |
| 2875 | pr_err("%s: already probed\n", __func__); |
| 2876 | return -EBUSY; |
| 2877 | } |
| 2878 | /* init */ |
| 2879 | dev = kzalloc(sizeof *dev, GFP_KERNEL); |
| 2880 | if (!dev) { |
| 2881 | pr_err("%s: no memory for device structure\n", __func__); |
| 2882 | return -ENOMEM; |
| 2883 | } |
| 2884 | /* pci setup */ |
| 2885 | if (pci_enable_device(pdev) < 0) { |
| 2886 | kfree(dev); |
| 2887 | pr_err("%s: pci_enable_device failed\n", __func__); |
| 2888 | return -ENODEV; |
| 2889 | } |
| 2890 | dev->active = 1; |
| 2891 | pci_set_drvdata(pdev, dev); |
| 2892 | |
| 2893 | /* PCI resource allocation */ |
| 2894 | resource = pci_resource_start(pdev, 1); |
| 2895 | len = pci_resource_len(pdev, 1); |
| 2896 | |
| 2897 | if (!request_mem_region(resource, len, KBUILD_MODNAME)) { |
| 2898 | dev_err(&pdev->dev, "%s: pci device used already\n", __func__); |
| 2899 | retval = -EBUSY; |
| 2900 | goto finished; |
| 2901 | } |
| 2902 | dev->phys_addr = resource; |
| 2903 | dev->mem_region = 1; |
| 2904 | |
| 2905 | dev->base_addr = ioremap_nocache(resource, len); |
| 2906 | if (!dev->base_addr) { |
| 2907 | pr_err("%s: device memory cannot be mapped\n", __func__); |
| 2908 | retval = -ENOMEM; |
| 2909 | goto finished; |
| 2910 | } |
| 2911 | if (!pdev->irq) { |
| 2912 | dev_err(&pdev->dev, "%s: irq not set\n", __func__); |
| 2913 | retval = -ENODEV; |
| 2914 | goto finished; |
| 2915 | } |
| 2916 | pch_udc = dev; |
| 2917 | /* initialize the hardware */ |
| 2918 | if (pch_udc_pcd_init(dev)) |
| 2919 | goto finished; |
| 2920 | if (request_irq(pdev->irq, pch_udc_isr, IRQF_SHARED, KBUILD_MODNAME, |
| 2921 | dev)) { |
| 2922 | dev_err(&pdev->dev, "%s: request_irq(%d) fail\n", __func__, |
| 2923 | pdev->irq); |
| 2924 | retval = -ENODEV; |
| 2925 | goto finished; |
| 2926 | } |
| 2927 | dev->irq = pdev->irq; |
| 2928 | dev->irq_registered = 1; |
| 2929 | |
| 2930 | pci_set_master(pdev); |
| 2931 | pci_try_set_mwi(pdev); |
| 2932 | |
| 2933 | /* device struct setup */ |
| 2934 | spin_lock_init(&dev->lock); |
| 2935 | dev->pdev = pdev; |
| 2936 | dev->gadget.ops = &pch_udc_ops; |
| 2937 | |
| 2938 | retval = init_dma_pools(dev); |
| 2939 | if (retval) |
| 2940 | goto finished; |
| 2941 | |
| 2942 | dev_set_name(&dev->gadget.dev, "gadget"); |
| 2943 | dev->gadget.dev.parent = &pdev->dev; |
| 2944 | dev->gadget.dev.dma_mask = pdev->dev.dma_mask; |
| 2945 | dev->gadget.dev.release = gadget_release; |
| 2946 | dev->gadget.name = KBUILD_MODNAME; |
| 2947 | dev->gadget.is_dualspeed = 1; |
| 2948 | |
| 2949 | retval = device_register(&dev->gadget.dev); |
| 2950 | if (retval) |
| 2951 | goto finished; |
| 2952 | dev->registered = 1; |
| 2953 | |
| 2954 | /* Put the device in disconnected state till a driver is bound */ |
| 2955 | pch_udc_set_disconnect(dev); |
| 2956 | return 0; |
| 2957 | |
| 2958 | finished: |
| 2959 | pch_udc_remove(pdev); |
| 2960 | return retval; |
| 2961 | } |
| 2962 | |
Richard Röjfors | 49e2083 | 2010-12-07 17:28:30 +0100 | [diff] [blame] | 2963 | static DEFINE_PCI_DEVICE_TABLE(pch_udc_pcidev_id) = { |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2964 | { |
| 2965 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EG20T_UDC), |
| 2966 | .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe, |
| 2967 | .class_mask = 0xffffffff, |
| 2968 | }, |
Tomoya MORINAGA | 06f1b97 | 2011-01-06 09:16:31 +0900 | [diff] [blame] | 2969 | { |
| 2970 | PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7213_IOH_UDC), |
| 2971 | .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe, |
| 2972 | .class_mask = 0xffffffff, |
| 2973 | }, |
Toshiharu Okada | f646cf9 | 2010-11-11 18:27:57 +0900 | [diff] [blame] | 2974 | { 0 }, |
| 2975 | }; |
| 2976 | |
| 2977 | MODULE_DEVICE_TABLE(pci, pch_udc_pcidev_id); |
| 2978 | |
| 2979 | |
| 2980 | static struct pci_driver pch_udc_driver = { |
| 2981 | .name = KBUILD_MODNAME, |
| 2982 | .id_table = pch_udc_pcidev_id, |
| 2983 | .probe = pch_udc_probe, |
| 2984 | .remove = pch_udc_remove, |
| 2985 | .suspend = pch_udc_suspend, |
| 2986 | .resume = pch_udc_resume, |
| 2987 | .shutdown = pch_udc_shutdown, |
| 2988 | }; |
| 2989 | |
| 2990 | static int __init pch_udc_pci_init(void) |
| 2991 | { |
| 2992 | return pci_register_driver(&pch_udc_driver); |
| 2993 | } |
| 2994 | module_init(pch_udc_pci_init); |
| 2995 | |
| 2996 | static void __exit pch_udc_pci_exit(void) |
| 2997 | { |
| 2998 | pci_unregister_driver(&pch_udc_driver); |
| 2999 | } |
| 3000 | module_exit(pch_udc_pci_exit); |
| 3001 | |
| 3002 | MODULE_DESCRIPTION("Intel EG20T USB Device Controller"); |
| 3003 | MODULE_AUTHOR("OKI SEMICONDUCTOR, <toshiharu-linux@dsn.okisemi.com>"); |
| 3004 | MODULE_LICENSE("GPL"); |