blob: 486bd3fd01a14669e8ce9140d8729db10c95dcf0 [file] [log] [blame]
Wu Zhangjin363c55c2009-06-04 20:27:10 +08001/*
2 * Hibernation support specific for mips - temporary page tables
3 *
4 * Licensed under the GPLv2
5 *
6 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
7 * Author: Hu Hongbing <huhb@lemote.com>
8 * Wu Zhangjin <wuzj@lemote.com>
9 */
10#include <asm/asm-offsets.h>
11#include <asm/regdef.h>
12#include <asm/asm.h>
13
14.text
15LEAF(swsusp_arch_suspend)
16 PTR_LA t0, saved_regs
17 PTR_S ra, PT_R31(t0)
18 PTR_S sp, PT_R29(t0)
19 PTR_S fp, PT_R30(t0)
20 PTR_S gp, PT_R28(t0)
21 PTR_S s0, PT_R16(t0)
22 PTR_S s1, PT_R17(t0)
23 PTR_S s2, PT_R18(t0)
24 PTR_S s3, PT_R19(t0)
25 PTR_S s4, PT_R20(t0)
26 PTR_S s5, PT_R21(t0)
27 PTR_S s6, PT_R22(t0)
28 PTR_S s7, PT_R23(t0)
29 j swsusp_save
30END(swsusp_arch_suspend)
31
32LEAF(swsusp_arch_resume)
33 PTR_L t0, restore_pblist
340:
35 PTR_L t1, PBE_ADDRESS(t0) /* source */
36 PTR_L t2, PBE_ORIG_ADDRESS(t0) /* destination */
37 PTR_ADDIU t3, t1, _PAGE_SIZE
381:
39 REG_L t8, (t1)
40 REG_S t8, (t2)
41 PTR_ADDIU t1, t1, SZREG
42 PTR_ADDIU t2, t2, SZREG
43 bne t1, t3, 1b
44 PTR_L t0, PBE_NEXT(t0)
45 bnez t0, 0b
46 /* flush caches to make sure context is in memory */
47 PTR_L t0, __flush_cache_all
48 jalr t0
49 /* flush tlb entries */
50#ifdef CONFIG_SMP
51 jal flush_tlb_all
52#else
53 jal local_flush_tlb_all
54#endif
55 PTR_LA t0, saved_regs
56 PTR_L ra, PT_R31(t0)
57 PTR_L sp, PT_R29(t0)
58 PTR_L fp, PT_R30(t0)
59 PTR_L gp, PT_R28(t0)
60 PTR_L s0, PT_R16(t0)
61 PTR_L s1, PT_R17(t0)
62 PTR_L s2, PT_R18(t0)
63 PTR_L s3, PT_R19(t0)
64 PTR_L s4, PT_R20(t0)
65 PTR_L s5, PT_R21(t0)
66 PTR_L s6, PT_R22(t0)
67 PTR_L s7, PT_R23(t0)
68 PTR_LI v0, 0x0
69 jr ra
70END(swsusp_arch_resume)