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Mauro Carvalho Chehab52707f92010-05-18 20:43:52 -03001/* Intel i7 core/Nehalem Memory Controller kernel module
2 *
David Sterbae7bf0682010-12-27 16:51:15 +01003 * This driver supports the memory controllers found on the Intel
Mauro Carvalho Chehab52707f92010-05-18 20:43:52 -03004 * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx,
5 * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
6 * and Westmere-EP.
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03007 *
8 * This file may be distributed under the terms of the
9 * GNU General Public License version 2 only.
10 *
Mauro Carvalho Chehab52707f92010-05-18 20:43:52 -030011 * Copyright (c) 2009-2010 by:
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030012 * Mauro Carvalho Chehab <mchehab@redhat.com>
13 *
14 * Red Hat Inc. http://www.redhat.com
15 *
16 * Forked and adapted from the i5400_edac driver
17 *
18 * Based on the following public Intel datasheets:
19 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
20 * Datasheet, Volume 2:
21 * http://download.intel.com/design/processor/datashts/320835.pdf
22 * Intel Xeon Processor 5500 Series Datasheet Volume 2
23 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
24 * also available at:
25 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
26 */
27
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030028#include <linux/module.h>
29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/pci_ids.h>
32#include <linux/slab.h>
Randy Dunlap3b918c12009-11-08 01:36:40 -020033#include <linux/delay.h>
Nils Carlson535e9c72011-08-08 06:21:26 -030034#include <linux/dmi.h>
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030035#include <linux/edac.h>
36#include <linux/mmzone.h>
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -030037#include <linux/smp.h>
Borislav Petkov4140c542011-07-18 11:24:46 -030038#include <asm/mce.h>
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -030039#include <asm/processor.h>
Sedat Dilek4fad8092011-09-21 23:44:52 -030040#include <asm/div64.h>
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030041
42#include "edac_core.h"
43
Mauro Carvalho Chehab18c29002010-08-10 18:33:27 -030044/* Static vars */
45static LIST_HEAD(i7core_edac_list);
46static DEFINE_MUTEX(i7core_edac_lock);
47static int probed;
48
Mauro Carvalho Chehab54a08ab2010-08-19 15:51:00 -030049static int use_pci_fixup;
50module_param(use_pci_fixup, int, 0444);
51MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices");
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030052/*
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -030053 * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
54 * registers start at bus 255, and are not reported by BIOS.
55 * We currently find devices with only 2 sockets. In order to support more QPI
56 * Quick Path Interconnect, just increment this number.
57 */
58#define MAX_SOCKET_BUSES 2
59
60
61/*
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030062 * Alter this version for the module when modifications are made
63 */
Michal Marek152ba392011-04-01 12:41:20 +020064#define I7CORE_REVISION " Ver: 1.0.0"
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030065#define EDAC_MOD_STR "i7core_edac"
66
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030067/*
68 * Debug macros
69 */
70#define i7core_printk(level, fmt, arg...) \
71 edac_printk(level, "i7core", fmt, ##arg)
72
73#define i7core_mc_printk(mci, level, fmt, arg...) \
74 edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)
75
76/*
77 * i7core Memory Controller Registers
78 */
79
Mauro Carvalho Chehabe9bd2e72009-07-09 22:14:35 -030080 /* OFFSETS for Device 0 Function 0 */
81
82#define MC_CFG_CONTROL 0x90
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -030083 #define MC_CFG_UNLOCK 0x02
84 #define MC_CFG_LOCK 0x00
Mauro Carvalho Chehabe9bd2e72009-07-09 22:14:35 -030085
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030086 /* OFFSETS for Device 3 Function 0 */
87
88#define MC_CONTROL 0x48
89#define MC_STATUS 0x4c
90#define MC_MAX_DOD 0x64
91
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -030092/*
93 * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet:
94 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
95 */
96
97#define MC_TEST_ERR_RCV1 0x60
98 #define DIMM2_COR_ERR(r) ((r) & 0x7fff)
99
100#define MC_TEST_ERR_RCV0 0x64
101 #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff)
102 #define DIMM0_COR_ERR(r) ((r) & 0x7fff)
103
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300104/* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -0300105#define MC_SSRCONTROL 0x48
106 #define SSR_MODE_DISABLE 0x00
107 #define SSR_MODE_ENABLE 0x01
108 #define SSR_MODE_MASK 0x03
109
110#define MC_SCRUB_CONTROL 0x4c
111 #define STARTSCRUB (1 << 24)
Nils Carlson535e9c72011-08-08 06:21:26 -0300112 #define SCRUBINTERVAL_MASK 0xffffff
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -0300113
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300114#define MC_COR_ECC_CNT_0 0x80
115#define MC_COR_ECC_CNT_1 0x84
116#define MC_COR_ECC_CNT_2 0x88
117#define MC_COR_ECC_CNT_3 0x8c
118#define MC_COR_ECC_CNT_4 0x90
119#define MC_COR_ECC_CNT_5 0x94
120
121#define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff)
122#define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff)
123
124
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300125 /* OFFSETS for Devices 4,5 and 6 Function 0 */
126
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300127#define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
128 #define THREE_DIMMS_PRESENT (1 << 24)
129 #define SINGLE_QUAD_RANK_PRESENT (1 << 23)
130 #define QUAD_RANK_PRESENT (1 << 22)
131 #define REGISTERED_DIMM (1 << 15)
132
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300133#define MC_CHANNEL_MAPPER 0x60
134 #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1)
135 #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1)
136
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300137#define MC_CHANNEL_RANK_PRESENT 0x7c
138 #define RANK_PRESENT_MASK 0xffff
139
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300140#define MC_CHANNEL_ADDR_MATCH 0xf0
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300141#define MC_CHANNEL_ERROR_MASK 0xf8
142#define MC_CHANNEL_ERROR_INJECT 0xfc
143 #define INJECT_ADDR_PARITY 0x10
144 #define INJECT_ECC 0x08
145 #define MASK_CACHELINE 0x06
146 #define MASK_FULL_CACHELINE 0x06
147 #define MASK_MSB32_CACHELINE 0x04
148 #define MASK_LSB32_CACHELINE 0x02
149 #define NO_MASK_CACHELINE 0x00
150 #define REPEAT_EN 0x01
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300151
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300152 /* OFFSETS for Devices 4,5 and 6 Function 1 */
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -0300153
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300154#define MC_DOD_CH_DIMM0 0x48
155#define MC_DOD_CH_DIMM1 0x4c
156#define MC_DOD_CH_DIMM2 0x50
157 #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10))
158 #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10)
159 #define DIMM_PRESENT_MASK (1 << 9)
160 #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9)
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300161 #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7))
162 #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7)
163 #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5))
164 #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300165 #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2))
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300166 #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2)
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300167 #define MC_DOD_NUMCOL_MASK 3
168 #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK)
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300169
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300170#define MC_RANK_PRESENT 0x7c
171
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300172#define MC_SAG_CH_0 0x80
173#define MC_SAG_CH_1 0x84
174#define MC_SAG_CH_2 0x88
175#define MC_SAG_CH_3 0x8c
176#define MC_SAG_CH_4 0x90
177#define MC_SAG_CH_5 0x94
178#define MC_SAG_CH_6 0x98
179#define MC_SAG_CH_7 0x9c
180
181#define MC_RIR_LIMIT_CH_0 0x40
182#define MC_RIR_LIMIT_CH_1 0x44
183#define MC_RIR_LIMIT_CH_2 0x48
184#define MC_RIR_LIMIT_CH_3 0x4C
185#define MC_RIR_LIMIT_CH_4 0x50
186#define MC_RIR_LIMIT_CH_5 0x54
187#define MC_RIR_LIMIT_CH_6 0x58
188#define MC_RIR_LIMIT_CH_7 0x5C
189#define MC_RIR_LIMIT_MASK ((1 << 10) - 1)
190
191#define MC_RIR_WAY_CH 0x80
192 #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7)
193 #define MC_RIR_WAY_RANK_MASK 0x7
194
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300195/*
196 * i7core structs
197 */
198
199#define NUM_CHANS 3
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -0300200#define MAX_DIMMS 3 /* Max DIMMS per channel */
201#define MAX_MCR_FUNC 4
202#define MAX_CHAN_FUNC 3
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300203
204struct i7core_info {
205 u32 mc_control;
206 u32 mc_status;
207 u32 max_dod;
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300208 u32 ch_map;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300209};
210
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300211
212struct i7core_inject {
213 int enable;
214
215 u32 section;
216 u32 type;
217 u32 eccmask;
218
219 /* Error address mask */
220 int channel, dimm, rank, bank, page, col;
221};
222
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300223struct i7core_channel {
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -0300224 u32 ranks;
225 u32 dimms;
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300226};
227
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300228struct pci_id_descr {
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300229 int dev;
230 int func;
231 int dev_id;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300232 int optional;
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300233};
234
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300235struct pci_id_table {
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300236 const struct pci_id_descr *descr;
237 int n_devs;
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300238};
239
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300240struct i7core_dev {
241 struct list_head list;
242 u8 socket;
243 struct pci_dev **pdev;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300244 int n_devs;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300245 struct mem_ctl_info *mci;
246};
247
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300248struct i7core_pvt {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300249 struct pci_dev *pci_noncore;
250 struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1];
251 struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];
252
253 struct i7core_dev *i7core_dev;
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300254
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300255 struct i7core_info info;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300256 struct i7core_inject inject;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300257 struct i7core_channel channel[NUM_CHANS];
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300258
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300259 int ce_count_available;
260 int csrow_map[NUM_CHANS][MAX_DIMMS];
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300261
262 /* ECC corrected errors counts per udimm */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300263 unsigned long udimm_ce_count[MAX_DIMMS];
264 int udimm_last_ce_count[MAX_DIMMS];
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300265 /* ECC corrected errors counts per rdimm */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300266 unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
267 int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -0300268
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -0300269 bool is_registered, enable_scrub;
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -0300270
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -0300271 /* Fifo double buffers */
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -0300272 struct mce mce_entry[MCE_LOG_LEN];
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -0300273 struct mce mce_outentry[MCE_LOG_LEN];
274
275 /* Fifo in/out counters */
276 unsigned mce_in, mce_out;
277
278 /* Count indicator to show errors not got */
279 unsigned mce_overrun;
Mauro Carvalho Chehab939747bd2010-08-10 11:22:01 -0300280
Nils Carlson535e9c72011-08-08 06:21:26 -0300281 /* DCLK Frequency used for computing scrub rate */
282 int dclk_freq;
283
Mauro Carvalho Chehab939747bd2010-08-10 11:22:01 -0300284 /* Struct to control EDAC polling */
285 struct edac_pci_ctl_info *i7core_pci;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300286};
287
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300288#define PCI_DESCR(device, function, device_id) \
289 .dev = (device), \
290 .func = (function), \
291 .dev_id = (device_id)
292
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300293static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300294 /* Memory controller */
295 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
296 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -0300297 /* Exists only for RDIMM */
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300298 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1 },
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300299 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
300
301 /* Channel 0 */
302 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
303 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
304 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
305 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) },
306
307 /* Channel 1 */
308 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
309 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
310 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
311 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) },
312
313 /* Channel 2 */
314 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
315 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
316 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
317 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -0300318
319 /* Generic Non-core registers */
320 /*
321 * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
322 * On Xeon 55xx, however, it has a different id (8086:2c40). So,
323 * the probing code needs to test for the other address in case of
324 * failure of this one
325 */
326 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE) },
327
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300328};
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300329
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300330static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
Mauro Carvalho Chehab52a2e4f2009-10-14 11:21:58 -0300331 { PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR) },
332 { PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD) },
333 { PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST) },
334
335 { PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) },
336 { PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) },
337 { PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) },
338 { PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC) },
339
Mauro Carvalho Chehab508fa172009-10-14 13:44:37 -0300340 { PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) },
341 { PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
342 { PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
343 { PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC) },
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -0300344
345 /*
346 * This is the PCI device has an alternate address on some
347 * processors like Core i7 860
348 */
349 { PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE) },
Mauro Carvalho Chehab52a2e4f2009-10-14 11:21:58 -0300350};
351
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300352static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300353 /* Memory controller */
354 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2) },
355 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2) },
356 /* Exists only for RDIMM */
357 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1 },
358 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) },
359
360 /* Channel 0 */
361 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) },
362 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) },
363 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) },
364 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2) },
365
366 /* Channel 1 */
367 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) },
368 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) },
369 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) },
370 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2) },
371
372 /* Channel 2 */
373 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) },
374 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
375 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
376 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) },
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -0300377
378 /* Generic Non-core registers */
379 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2) },
380
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300381};
382
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300383#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
384static const struct pci_id_table pci_dev_table[] = {
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300385 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
386 PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
387 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -0200388 {0,} /* 0 terminated list. */
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300389};
390
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300391/*
392 * pci_device_id table for which devices we are looking for
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300393 */
394static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
Mauro Carvalho Chehabd1fd4fb2009-07-10 18:39:53 -0300395 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
Mauro Carvalho Chehabf05da2f2009-10-14 13:31:06 -0300396 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300397 {0,} /* 0 terminated list. */
398};
399
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300400/****************************************************************************
401 Anciliary status routines
402 ****************************************************************************/
403
404 /* MC_CONTROL bits */
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300405#define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch)))
406#define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300407
408 /* MC_STATUS bits */
Keith Mannthey61053fd2009-09-02 23:46:59 -0300409#define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300410#define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300411
412 /* MC_MAX_DOD read functions */
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300413static inline int numdimms(u32 dimms)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300414{
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300415 return (dimms & 0x3) + 1;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300416}
417
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300418static inline int numrank(u32 rank)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300419{
420 static int ranks[4] = { 1, 2, 4, -EINVAL };
421
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300422 return ranks[rank & 0x3];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300423}
424
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300425static inline int numbank(u32 bank)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300426{
427 static int banks[4] = { 4, 8, 16, -EINVAL };
428
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300429 return banks[bank & 0x3];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300430}
431
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300432static inline int numrow(u32 row)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300433{
434 static int rows[8] = {
435 1 << 12, 1 << 13, 1 << 14, 1 << 15,
436 1 << 16, -EINVAL, -EINVAL, -EINVAL,
437 };
438
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300439 return rows[row & 0x7];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300440}
441
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300442static inline int numcol(u32 col)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300443{
444 static int cols[8] = {
445 1 << 10, 1 << 11, 1 << 12, -EINVAL,
446 };
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300447 return cols[col & 0x3];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300448}
449
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300450static struct i7core_dev *get_i7core_dev(u8 socket)
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300451{
452 struct i7core_dev *i7core_dev;
453
454 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
455 if (i7core_dev->socket == socket)
456 return i7core_dev;
457 }
458
459 return NULL;
460}
461
Hidetoshi Seto848b2f72010-08-20 04:24:44 -0300462static struct i7core_dev *alloc_i7core_dev(u8 socket,
463 const struct pci_id_table *table)
464{
465 struct i7core_dev *i7core_dev;
466
467 i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
468 if (!i7core_dev)
469 return NULL;
470
471 i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * table->n_devs,
472 GFP_KERNEL);
473 if (!i7core_dev->pdev) {
474 kfree(i7core_dev);
475 return NULL;
476 }
477
478 i7core_dev->socket = socket;
479 i7core_dev->n_devs = table->n_devs;
480 list_add_tail(&i7core_dev->list, &i7core_edac_list);
481
482 return i7core_dev;
483}
484
Hidetoshi Seto2aa9be42010-08-20 04:25:00 -0300485static void free_i7core_dev(struct i7core_dev *i7core_dev)
486{
487 list_del(&i7core_dev->list);
488 kfree(i7core_dev->pdev);
489 kfree(i7core_dev);
490}
491
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300492/****************************************************************************
493 Memory check routines
494 ****************************************************************************/
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300495static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot,
496 unsigned func)
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300497{
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300498 struct i7core_dev *i7core_dev = get_i7core_dev(socket);
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300499 int i;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300500
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300501 if (!i7core_dev)
502 return NULL;
503
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300504 for (i = 0; i < i7core_dev->n_devs; i++) {
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300505 if (!i7core_dev->pdev[i])
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300506 continue;
507
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300508 if (PCI_SLOT(i7core_dev->pdev[i]->devfn) == slot &&
509 PCI_FUNC(i7core_dev->pdev[i]->devfn) == func) {
510 return i7core_dev->pdev[i];
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300511 }
512 }
513
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300514 return NULL;
515}
516
Mauro Carvalho Chehabec6df242009-07-18 10:44:30 -0300517/**
518 * i7core_get_active_channels() - gets the number of channels and csrows
519 * @socket: Quick Path Interconnect socket
520 * @channels: Number of channels that will be returned
521 * @csrows: Number of csrows found
522 *
523 * Since EDAC core needs to know in advance the number of available channels
524 * and csrows, in order to allocate memory for csrows/channels, it is needed
525 * to run two similar steps. At the first step, implemented on this function,
526 * it checks the number of csrows/channels present at one socket.
527 * this is used in order to properly allocate the size of mci components.
528 *
529 * It should be noticed that none of the current available datasheets explain
530 * or even mention how csrows are seen by the memory controller. So, we need
531 * to add a fake description for csrows.
532 * So, this driver is attributing one DIMM memory for one csrow.
533 */
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300534static int i7core_get_active_channels(const u8 socket, unsigned *channels,
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300535 unsigned *csrows)
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300536{
537 struct pci_dev *pdev = NULL;
538 int i, j;
539 u32 status, control;
540
541 *channels = 0;
542 *csrows = 0;
543
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300544 pdev = get_pdev_slot_func(socket, 3, 0);
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -0300545 if (!pdev) {
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300546 i7core_printk(KERN_ERR, "Couldn't find socket %d fn 3.0!!!\n",
547 socket);
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300548 return -ENODEV;
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -0300549 }
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300550
551 /* Device 3 function 0 reads */
552 pci_read_config_dword(pdev, MC_STATUS, &status);
553 pci_read_config_dword(pdev, MC_CONTROL, &control);
554
555 for (i = 0; i < NUM_CHANS; i++) {
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300556 u32 dimm_dod[3];
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300557 /* Check if the channel is active */
558 if (!(control & (1 << (8 + i))))
559 continue;
560
561 /* Check if the channel is disabled */
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300562 if (status & (1 << i))
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300563 continue;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300564
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300565 pdev = get_pdev_slot_func(socket, i + 4, 1);
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300566 if (!pdev) {
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300567 i7core_printk(KERN_ERR, "Couldn't find socket %d "
568 "fn %d.%d!!!\n",
569 socket, i + 4, 1);
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300570 return -ENODEV;
571 }
572 /* Devices 4-6 function 1 */
573 pci_read_config_dword(pdev,
574 MC_DOD_CH_DIMM0, &dimm_dod[0]);
575 pci_read_config_dword(pdev,
576 MC_DOD_CH_DIMM1, &dimm_dod[1]);
577 pci_read_config_dword(pdev,
578 MC_DOD_CH_DIMM2, &dimm_dod[2]);
579
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300580 (*channels)++;
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300581
582 for (j = 0; j < 3; j++) {
583 if (!DIMM_PRESENT(dimm_dod[j]))
584 continue;
585 (*csrows)++;
586 }
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300587 }
588
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -0300589 debugf0("Number of active channels on socket %d: %d\n",
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300590 socket, *channels);
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300591
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300592 return 0;
593}
594
Hidetoshi Seto2e5185f2010-08-20 04:32:56 -0300595static int get_dimm_config(const struct mem_ctl_info *mci)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300596{
597 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300598 struct csrow_info *csr;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300599 struct pci_dev *pdev;
Mauro Carvalho Chehabba6c5c62009-07-15 09:02:32 -0300600 int i, j;
Hidetoshi Seto2e5185f2010-08-20 04:32:56 -0300601 int csrow = 0;
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300602 unsigned long last_page = 0;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300603 enum edac_type mode;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300604 enum mem_type mtype;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300605
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300606 /* Get data from the MC register, function 0 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300607 pdev = pvt->pci_mcr[0];
Mauro Carvalho Chehab7dd69532009-06-22 22:48:30 -0300608 if (!pdev)
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300609 return -ENODEV;
610
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300611 /* Device 3 function 0 reads */
Mauro Carvalho Chehab7dd69532009-06-22 22:48:30 -0300612 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
613 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
614 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
615 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300616
Mauro Carvalho Chehab17cb7b02009-07-20 18:48:18 -0300617 debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
Mauro Carvalho Chehab4af91882009-09-24 09:58:26 -0300618 pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status,
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300619 pvt->info.max_dod, pvt->info.ch_map);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300620
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300621 if (ECC_ENABLED(pvt)) {
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300622 debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300623 if (ECCx8(pvt))
624 mode = EDAC_S8ECD8ED;
625 else
626 mode = EDAC_S4ECD4ED;
627 } else {
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300628 debugf0("ECC disabled\n");
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300629 mode = EDAC_NONE;
630 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300631
632 /* FIXME: need to handle the error codes */
Mauro Carvalho Chehab17cb7b02009-07-20 18:48:18 -0300633 debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked "
634 "x%x x 0x%x\n",
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300635 numdimms(pvt->info.max_dod),
636 numrank(pvt->info.max_dod >> 2),
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300637 numbank(pvt->info.max_dod >> 4),
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300638 numrow(pvt->info.max_dod >> 6),
639 numcol(pvt->info.max_dod >> 9));
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300640
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300641 for (i = 0; i < NUM_CHANS; i++) {
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300642 u32 data, dimm_dod[3], value[8];
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300643
Mauro Carvalho Chehab52a2e4f2009-10-14 11:21:58 -0300644 if (!pvt->pci_ch[i][0])
645 continue;
646
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300647 if (!CH_ACTIVE(pvt, i)) {
648 debugf0("Channel %i is not active\n", i);
649 continue;
650 }
651 if (CH_DISABLED(pvt, i)) {
652 debugf0("Channel %i is disabled\n", i);
653 continue;
654 }
655
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300656 /* Devices 4-6 function 0 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300657 pci_read_config_dword(pvt->pci_ch[i][0],
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300658 MC_CHANNEL_DIMM_INIT_PARAMS, &data);
659
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300660 pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ?
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300661 4 : 2;
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300662
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300663 if (data & REGISTERED_DIMM)
664 mtype = MEM_RDDR3;
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -0300665 else
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300666 mtype = MEM_DDR3;
667#if 0
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300668 if (data & THREE_DIMMS_PRESENT)
669 pvt->channel[i].dimms = 3;
670 else if (data & SINGLE_QUAD_RANK_PRESENT)
671 pvt->channel[i].dimms = 1;
672 else
673 pvt->channel[i].dimms = 2;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300674#endif
675
676 /* Devices 4-6 function 1 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300677 pci_read_config_dword(pvt->pci_ch[i][1],
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300678 MC_DOD_CH_DIMM0, &dimm_dod[0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300679 pci_read_config_dword(pvt->pci_ch[i][1],
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300680 MC_DOD_CH_DIMM1, &dimm_dod[1]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300681 pci_read_config_dword(pvt->pci_ch[i][1],
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300682 MC_DOD_CH_DIMM2, &dimm_dod[2]);
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300683
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300684 debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300685 "%d ranks, %cDIMMs\n",
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300686 i,
687 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
688 data,
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300689 pvt->channel[i].ranks,
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300690 (data & REGISTERED_DIMM) ? 'R' : 'U');
Mauro Carvalho Chehab7dd69532009-06-22 22:48:30 -0300691
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300692 for (j = 0; j < 3; j++) {
693 u32 banks, ranks, rows, cols;
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300694 u32 size, npages;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300695
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300696 if (!DIMM_PRESENT(dimm_dod[j]))
697 continue;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300698
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300699 banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
700 ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
701 rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
702 cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300703
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300704 /* DDR3 has 8 I/O banks */
705 size = (rows * cols * banks * ranks) >> (20 - 3);
706
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300707 pvt->channel[i].dimms++;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300708
Mauro Carvalho Chehab17cb7b02009-07-20 18:48:18 -0300709 debugf0("\tdimm %d %d Mb offset: %x, "
710 "bank: %d, rank: %d, row: %#x, col: %#x\n",
711 j, size,
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300712 RANKOFFSET(dimm_dod[j]),
713 banks, ranks, rows, cols);
714
Mauro Carvalho Chehabe9144602010-08-10 20:26:35 -0300715 npages = MiB_TO_PAGES(size);
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300716
Hidetoshi Seto2e5185f2010-08-20 04:32:56 -0300717 csr = &mci->csrows[csrow];
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300718 csr->first_page = last_page + 1;
719 last_page += npages;
720 csr->last_page = last_page;
721 csr->nr_pages = npages;
722
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300723 csr->page_mask = 0;
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300724 csr->grain = 8;
Hidetoshi Seto2e5185f2010-08-20 04:32:56 -0300725 csr->csrow_idx = csrow;
Mauro Carvalho Chehabeb94fc42009-06-22 22:48:31 -0300726 csr->nr_channels = 1;
727
728 csr->channels[0].chan_idx = i;
729 csr->channels[0].ce_count = 0;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300730
Hidetoshi Seto2e5185f2010-08-20 04:32:56 -0300731 pvt->csrow_map[i][j] = csrow;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300732
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300733 switch (banks) {
734 case 4:
735 csr->dtype = DEV_X4;
736 break;
737 case 8:
738 csr->dtype = DEV_X8;
739 break;
740 case 16:
741 csr->dtype = DEV_X16;
742 break;
743 default:
744 csr->dtype = DEV_UNKNOWN;
745 }
746
747 csr->edac_mode = mode;
748 csr->mtype = mtype;
Mauro Carvalho Chehab767ba4a2011-09-16 13:37:29 -0300749 snprintf(csr->channels[0].label,
750 sizeof(csr->channels[0].label),
751 "CPU#%uChannel#%u_DIMM#%u",
752 pvt->i7core_dev->socket, i, j);
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300753
Hidetoshi Seto2e5185f2010-08-20 04:32:56 -0300754 csrow++;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300755 }
756
757 pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
758 pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
759 pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
760 pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
761 pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
762 pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
763 pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
764 pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
Mauro Carvalho Chehab17cb7b02009-07-20 18:48:18 -0300765 debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300766 for (j = 0; j < 8; j++)
Mauro Carvalho Chehab17cb7b02009-07-20 18:48:18 -0300767 debugf1("\t\t%#x\t%#x\t%#x\n",
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300768 (value[j] >> 27) & 0x1,
769 (value[j] >> 24) & 0x7,
David Sterba80b8ce82010-12-27 15:39:12 +0000770 (value[j] & ((1 << 24) - 1)));
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300771 }
772
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300773 return 0;
774}
775
776/****************************************************************************
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300777 Error insertion routines
778 ****************************************************************************/
779
780/* The i7core has independent error injection features per channel.
781 However, to have a simpler code, we don't allow enabling error injection
782 on more than one channel.
783 Also, since a change at an inject parameter will be applied only at enable,
784 we're disabling error injection on all write calls to the sysfs nodes that
785 controls the error code injection.
786 */
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300787static int disable_inject(const struct mem_ctl_info *mci)
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300788{
789 struct i7core_pvt *pvt = mci->pvt_info;
790
791 pvt->inject.enable = 0;
792
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300793 if (!pvt->pci_ch[pvt->inject.channel][0])
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300794 return -ENODEV;
795
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300796 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -0300797 MC_CHANNEL_ERROR_INJECT, 0);
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300798
799 return 0;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300800}
801
802/*
803 * i7core inject inject.section
804 *
805 * accept and store error injection inject.section value
806 * bit 0 - refers to the lower 32-byte half cacheline
807 * bit 1 - refers to the upper 32-byte half cacheline
808 */
809static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci,
810 const char *data, size_t count)
811{
812 struct i7core_pvt *pvt = mci->pvt_info;
813 unsigned long value;
814 int rc;
815
816 if (pvt->inject.enable)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300817 disable_inject(mci);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300818
819 rc = strict_strtoul(data, 10, &value);
820 if ((rc < 0) || (value > 3))
Mauro Carvalho Chehab2068def2009-08-05 19:28:27 -0300821 return -EIO;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300822
823 pvt->inject.section = (u32) value;
824 return count;
825}
826
827static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci,
828 char *data)
829{
830 struct i7core_pvt *pvt = mci->pvt_info;
831 return sprintf(data, "0x%08x\n", pvt->inject.section);
832}
833
834/*
835 * i7core inject.type
836 *
837 * accept and store error injection inject.section value
838 * bit 0 - repeat enable - Enable error repetition
839 * bit 1 - inject ECC error
840 * bit 2 - inject parity error
841 */
842static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci,
843 const char *data, size_t count)
844{
845 struct i7core_pvt *pvt = mci->pvt_info;
846 unsigned long value;
847 int rc;
848
849 if (pvt->inject.enable)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300850 disable_inject(mci);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300851
852 rc = strict_strtoul(data, 10, &value);
853 if ((rc < 0) || (value > 7))
Mauro Carvalho Chehab2068def2009-08-05 19:28:27 -0300854 return -EIO;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300855
856 pvt->inject.type = (u32) value;
857 return count;
858}
859
860static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci,
861 char *data)
862{
863 struct i7core_pvt *pvt = mci->pvt_info;
864 return sprintf(data, "0x%08x\n", pvt->inject.type);
865}
866
867/*
868 * i7core_inject_inject.eccmask_store
869 *
870 * The type of error (UE/CE) will depend on the inject.eccmask value:
871 * Any bits set to a 1 will flip the corresponding ECC bit
872 * Correctable errors can be injected by flipping 1 bit or the bits within
873 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
874 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
875 * uncorrectable error to be injected.
876 */
877static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci,
878 const char *data, size_t count)
879{
880 struct i7core_pvt *pvt = mci->pvt_info;
881 unsigned long value;
882 int rc;
883
884 if (pvt->inject.enable)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300885 disable_inject(mci);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300886
887 rc = strict_strtoul(data, 10, &value);
888 if (rc < 0)
Mauro Carvalho Chehab2068def2009-08-05 19:28:27 -0300889 return -EIO;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300890
891 pvt->inject.eccmask = (u32) value;
892 return count;
893}
894
895static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci,
896 char *data)
897{
898 struct i7core_pvt *pvt = mci->pvt_info;
899 return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
900}
901
902/*
903 * i7core_addrmatch
904 *
905 * The type of error (UE/CE) will depend on the inject.eccmask value:
906 * Any bits set to a 1 will flip the corresponding ECC bit
907 * Correctable errors can be injected by flipping 1 bit or the bits within
908 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
909 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
910 * uncorrectable error to be injected.
911 */
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300912
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300913#define DECLARE_ADDR_MATCH(param, limit) \
914static ssize_t i7core_inject_store_##param( \
915 struct mem_ctl_info *mci, \
916 const char *data, size_t count) \
917{ \
Mauro Carvalho Chehabcc301b32009-09-24 16:23:42 -0300918 struct i7core_pvt *pvt; \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300919 long value; \
920 int rc; \
921 \
Mauro Carvalho Chehabcc301b32009-09-24 16:23:42 -0300922 debugf1("%s()\n", __func__); \
923 pvt = mci->pvt_info; \
924 \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300925 if (pvt->inject.enable) \
926 disable_inject(mci); \
927 \
Mauro Carvalho Chehab4f87fad2009-10-04 11:54:56 -0300928 if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300929 value = -1; \
930 else { \
931 rc = strict_strtoul(data, 10, &value); \
932 if ((rc < 0) || (value >= limit)) \
933 return -EIO; \
934 } \
935 \
936 pvt->inject.param = value; \
937 \
938 return count; \
939} \
940 \
941static ssize_t i7core_inject_show_##param( \
942 struct mem_ctl_info *mci, \
943 char *data) \
944{ \
Mauro Carvalho Chehabcc301b32009-09-24 16:23:42 -0300945 struct i7core_pvt *pvt; \
946 \
947 pvt = mci->pvt_info; \
948 debugf1("%s() pvt=%p\n", __func__, pvt); \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300949 if (pvt->inject.param < 0) \
950 return sprintf(data, "any\n"); \
951 else \
952 return sprintf(data, "%d\n", pvt->inject.param);\
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300953}
954
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300955#define ATTR_ADDR_MATCH(param) \
956 { \
957 .attr = { \
958 .name = #param, \
959 .mode = (S_IRUGO | S_IWUSR) \
960 }, \
961 .show = i7core_inject_show_##param, \
962 .store = i7core_inject_store_##param, \
963 }
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300964
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300965DECLARE_ADDR_MATCH(channel, 3);
966DECLARE_ADDR_MATCH(dimm, 3);
967DECLARE_ADDR_MATCH(rank, 4);
968DECLARE_ADDR_MATCH(bank, 32);
969DECLARE_ADDR_MATCH(page, 0x10000);
970DECLARE_ADDR_MATCH(col, 0x4000);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300971
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300972static int write_and_test(struct pci_dev *dev, const int where, const u32 val)
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300973{
974 u32 read;
975 int count;
976
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -0300977 debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n",
978 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
979 where, val);
980
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300981 for (count = 0; count < 10; count++) {
982 if (count)
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -0300983 msleep(100);
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300984 pci_write_config_dword(dev, where, val);
985 pci_read_config_dword(dev, where, &read);
986
987 if (read == val)
988 return 0;
989 }
990
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -0300991 i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
992 "write=%08x. Read=%08x\n",
993 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
994 where, val, read);
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300995
996 return -EINVAL;
997}
998
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300999/*
1000 * This routine prepares the Memory Controller for error injection.
1001 * The error will be injected when some process tries to write to the
1002 * memory that matches the given criteria.
1003 * The criteria can be set in terms of a mask where dimm, rank, bank, page
1004 * and col can be specified.
1005 * A -1 value for any of the mask items will make the MCU to ignore
1006 * that matching criteria for error injection.
1007 *
1008 * It should be noticed that the error will only happen after a write operation
1009 * on a memory that matches the condition. if REPEAT_EN is not enabled at
1010 * inject mask, then it will produce just one error. Otherwise, it will repeat
1011 * until the injectmask would be cleaned.
1012 *
1013 * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
1014 * is reliable enough to check if the MC is using the
1015 * three channels. However, this is not clear at the datasheet.
1016 */
1017static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
1018 const char *data, size_t count)
1019{
1020 struct i7core_pvt *pvt = mci->pvt_info;
1021 u32 injectmask;
1022 u64 mask = 0;
1023 int rc;
1024 long enable;
1025
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001026 if (!pvt->pci_ch[pvt->inject.channel][0])
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03001027 return 0;
1028
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001029 rc = strict_strtoul(data, 10, &enable);
1030 if ((rc < 0))
1031 return 0;
1032
1033 if (enable) {
1034 pvt->inject.enable = 1;
1035 } else {
1036 disable_inject(mci);
1037 return count;
1038 }
1039
1040 /* Sets pvt->inject.dimm mask */
1041 if (pvt->inject.dimm < 0)
Alan Cox486dd092009-11-08 01:34:27 -02001042 mask |= 1LL << 41;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001043 else {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001044 if (pvt->channel[pvt->inject.channel].dimms > 2)
Alan Cox486dd092009-11-08 01:34:27 -02001045 mask |= (pvt->inject.dimm & 0x3LL) << 35;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001046 else
Alan Cox486dd092009-11-08 01:34:27 -02001047 mask |= (pvt->inject.dimm & 0x1LL) << 36;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001048 }
1049
1050 /* Sets pvt->inject.rank mask */
1051 if (pvt->inject.rank < 0)
Alan Cox486dd092009-11-08 01:34:27 -02001052 mask |= 1LL << 40;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001053 else {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001054 if (pvt->channel[pvt->inject.channel].dimms > 2)
Alan Cox486dd092009-11-08 01:34:27 -02001055 mask |= (pvt->inject.rank & 0x1LL) << 34;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001056 else
Alan Cox486dd092009-11-08 01:34:27 -02001057 mask |= (pvt->inject.rank & 0x3LL) << 34;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001058 }
1059
1060 /* Sets pvt->inject.bank mask */
1061 if (pvt->inject.bank < 0)
Alan Cox486dd092009-11-08 01:34:27 -02001062 mask |= 1LL << 39;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001063 else
Alan Cox486dd092009-11-08 01:34:27 -02001064 mask |= (pvt->inject.bank & 0x15LL) << 30;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001065
1066 /* Sets pvt->inject.page mask */
1067 if (pvt->inject.page < 0)
Alan Cox486dd092009-11-08 01:34:27 -02001068 mask |= 1LL << 38;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001069 else
Alan Cox486dd092009-11-08 01:34:27 -02001070 mask |= (pvt->inject.page & 0xffff) << 14;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001071
1072 /* Sets pvt->inject.column mask */
1073 if (pvt->inject.col < 0)
Alan Cox486dd092009-11-08 01:34:27 -02001074 mask |= 1LL << 37;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001075 else
Alan Cox486dd092009-11-08 01:34:27 -02001076 mask |= (pvt->inject.col & 0x3fff);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001077
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001078 /*
1079 * bit 0: REPEAT_EN
1080 * bits 1-2: MASK_HALF_CACHELINE
1081 * bit 3: INJECT_ECC
1082 * bit 4: INJECT_ADDR_PARITY
1083 */
1084
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001085 injectmask = (pvt->inject.type & 1) |
1086 (pvt->inject.section & 0x3) << 1 |
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001087 (pvt->inject.type & 0x6) << (3 - 1);
1088
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001089 /* Unlock writes to registers - this register is write only */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001090 pci_write_config_dword(pvt->pci_noncore,
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001091 MC_CFG_CONTROL, 0x2);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001092
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001093 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001094 MC_CHANNEL_ADDR_MATCH, mask);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001095 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001096 MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);
1097
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001098 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001099 MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
1100
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001101 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -03001102 MC_CHANNEL_ERROR_INJECT, injectmask);
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001103
1104 /*
1105 * This is something undocumented, based on my tests
1106 * Without writing 8 to this register, errors aren't injected. Not sure
1107 * why.
1108 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001109 pci_write_config_dword(pvt->pci_noncore,
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001110 MC_CFG_CONTROL, 8);
1111
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -03001112 debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
1113 " inject 0x%08x\n",
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001114 mask, pvt->inject.eccmask, injectmask);
1115
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001116
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001117 return count;
1118}
1119
1120static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
1121 char *data)
1122{
1123 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001124 u32 injectmask;
1125
Mauro Carvalho Chehab52a2e4f2009-10-14 11:21:58 -03001126 if (!pvt->pci_ch[pvt->inject.channel][0])
1127 return 0;
1128
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001129 pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -03001130 MC_CHANNEL_ERROR_INJECT, &injectmask);
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001131
1132 debugf0("Inject error read: 0x%018x\n", injectmask);
1133
1134 if (injectmask & 0x0c)
1135 pvt->inject.enable = 1;
1136
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001137 return sprintf(data, "%d\n", pvt->inject.enable);
1138}
1139
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001140#define DECLARE_COUNTER(param) \
1141static ssize_t i7core_show_counter_##param( \
1142 struct mem_ctl_info *mci, \
1143 char *data) \
1144{ \
1145 struct i7core_pvt *pvt = mci->pvt_info; \
1146 \
1147 debugf1("%s() \n", __func__); \
1148 if (!pvt->ce_count_available || (pvt->is_registered)) \
1149 return sprintf(data, "data unavailable\n"); \
1150 return sprintf(data, "%lu\n", \
1151 pvt->udimm_ce_count[param]); \
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001152}
1153
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001154#define ATTR_COUNTER(param) \
1155 { \
1156 .attr = { \
1157 .name = __stringify(udimm##param), \
1158 .mode = (S_IRUGO | S_IWUSR) \
1159 }, \
1160 .show = i7core_show_counter_##param \
1161 }
1162
1163DECLARE_COUNTER(0);
1164DECLARE_COUNTER(1);
1165DECLARE_COUNTER(2);
1166
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001167/*
1168 * Sysfs struct
1169 */
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001170
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001171static const struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = {
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001172 ATTR_ADDR_MATCH(channel),
1173 ATTR_ADDR_MATCH(dimm),
1174 ATTR_ADDR_MATCH(rank),
1175 ATTR_ADDR_MATCH(bank),
1176 ATTR_ADDR_MATCH(page),
1177 ATTR_ADDR_MATCH(col),
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001178 { } /* End of list */
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001179};
1180
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001181static const struct mcidev_sysfs_group i7core_inject_addrmatch = {
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001182 .name = "inject_addrmatch",
1183 .mcidev_attr = i7core_addrmatch_attrs,
1184};
1185
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001186static const struct mcidev_sysfs_attribute i7core_udimm_counters_attrs[] = {
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001187 ATTR_COUNTER(0),
1188 ATTR_COUNTER(1),
1189 ATTR_COUNTER(2),
Marcin Slusarz64aab722010-09-30 15:15:30 -07001190 { .attr = { .name = NULL } }
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001191};
1192
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001193static const struct mcidev_sysfs_group i7core_udimm_counters = {
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001194 .name = "all_channel_counts",
1195 .mcidev_attr = i7core_udimm_counters_attrs,
1196};
1197
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001198static const struct mcidev_sysfs_attribute i7core_sysfs_rdimm_attrs[] = {
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001199 {
1200 .attr = {
1201 .name = "inject_section",
1202 .mode = (S_IRUGO | S_IWUSR)
1203 },
1204 .show = i7core_inject_section_show,
1205 .store = i7core_inject_section_store,
1206 }, {
1207 .attr = {
1208 .name = "inject_type",
1209 .mode = (S_IRUGO | S_IWUSR)
1210 },
1211 .show = i7core_inject_type_show,
1212 .store = i7core_inject_type_store,
1213 }, {
1214 .attr = {
1215 .name = "inject_eccmask",
1216 .mode = (S_IRUGO | S_IWUSR)
1217 },
1218 .show = i7core_inject_eccmask_show,
1219 .store = i7core_inject_eccmask_store,
1220 }, {
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001221 .grp = &i7core_inject_addrmatch,
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001222 }, {
1223 .attr = {
1224 .name = "inject_enable",
1225 .mode = (S_IRUGO | S_IWUSR)
1226 },
1227 .show = i7core_inject_enable_show,
1228 .store = i7core_inject_enable_store,
1229 },
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001230 { } /* End of list */
1231};
1232
1233static const struct mcidev_sysfs_attribute i7core_sysfs_udimm_attrs[] = {
1234 {
1235 .attr = {
1236 .name = "inject_section",
1237 .mode = (S_IRUGO | S_IWUSR)
1238 },
1239 .show = i7core_inject_section_show,
1240 .store = i7core_inject_section_store,
1241 }, {
1242 .attr = {
1243 .name = "inject_type",
1244 .mode = (S_IRUGO | S_IWUSR)
1245 },
1246 .show = i7core_inject_type_show,
1247 .store = i7core_inject_type_store,
1248 }, {
1249 .attr = {
1250 .name = "inject_eccmask",
1251 .mode = (S_IRUGO | S_IWUSR)
1252 },
1253 .show = i7core_inject_eccmask_show,
1254 .store = i7core_inject_eccmask_store,
1255 }, {
1256 .grp = &i7core_inject_addrmatch,
1257 }, {
1258 .attr = {
1259 .name = "inject_enable",
1260 .mode = (S_IRUGO | S_IWUSR)
1261 },
1262 .show = i7core_inject_enable_show,
1263 .store = i7core_inject_enable_store,
1264 }, {
1265 .grp = &i7core_udimm_counters,
1266 },
1267 { } /* End of list */
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001268};
1269
1270/****************************************************************************
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001271 Device initialization routines: put/get, init/exit
1272 ****************************************************************************/
1273
1274/*
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03001275 * i7core_put_all_devices 'put' all the devices that we have
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001276 * reserved via 'get'
1277 */
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001278static void i7core_put_devices(struct i7core_dev *i7core_dev)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001279{
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001280 int i;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001281
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03001282 debugf0(__FILE__ ": %s()\n", __func__);
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001283 for (i = 0; i < i7core_dev->n_devs; i++) {
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03001284 struct pci_dev *pdev = i7core_dev->pdev[i];
1285 if (!pdev)
1286 continue;
1287 debugf0("Removing dev %02x:%02x.%d\n",
1288 pdev->bus->number,
1289 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1290 pci_dev_put(pdev);
1291 }
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001292}
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001293
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001294static void i7core_put_all_devices(void)
1295{
Mauro Carvalho Chehab42538682009-09-24 09:59:13 -03001296 struct i7core_dev *i7core_dev, *tmp;
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001297
Mauro Carvalho Chehab39300e72010-08-11 23:40:15 -03001298 list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001299 i7core_put_devices(i7core_dev);
Hidetoshi Seto2aa9be42010-08-20 04:25:00 -03001300 free_i7core_dev(i7core_dev);
Mauro Carvalho Chehab39300e72010-08-11 23:40:15 -03001301 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001302}
1303
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001304static void __init i7core_xeon_pci_fixup(const struct pci_id_table *table)
Keith Manntheybc2d7242009-09-03 00:05:05 -03001305{
1306 struct pci_dev *pdev = NULL;
1307 int i;
Mauro Carvalho Chehab54a08ab2010-08-19 15:51:00 -03001308
Keith Manntheybc2d7242009-09-03 00:05:05 -03001309 /*
David Sterbae7bf0682010-12-27 16:51:15 +01001310 * On Xeon 55xx, the Intel Quick Path Arch Generic Non-core pci buses
Keith Manntheybc2d7242009-09-03 00:05:05 -03001311 * aren't announced by acpi. So, we need to use a legacy scan probing
1312 * to detect them
1313 */
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001314 while (table && table->descr) {
1315 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL);
1316 if (unlikely(!pdev)) {
1317 for (i = 0; i < MAX_SOCKET_BUSES; i++)
1318 pcibios_scan_specific_bus(255-i);
1319 }
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001320 pci_dev_put(pdev);
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001321 table++;
Keith Manntheybc2d7242009-09-03 00:05:05 -03001322 }
1323}
1324
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001325static unsigned i7core_pci_lastbus(void)
1326{
1327 int last_bus = 0, bus;
1328 struct pci_bus *b = NULL;
1329
1330 while ((b = pci_find_next_bus(b)) != NULL) {
1331 bus = b->number;
1332 debugf0("Found bus %d\n", bus);
1333 if (bus > last_bus)
1334 last_bus = bus;
1335 }
1336
1337 debugf0("Last bus %d\n", last_bus);
1338
1339 return last_bus;
1340}
1341
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001342/*
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03001343 * i7core_get_all_devices Find and perform 'get' operation on the MCH's
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001344 * device/functions we want to reference for this driver
1345 *
1346 * Need to 'get' device 16 func 1 and func 2
1347 */
Hidetoshi Setob197cba2010-08-20 04:24:31 -03001348static int i7core_get_onedevice(struct pci_dev **prev,
1349 const struct pci_id_table *table,
1350 const unsigned devno,
1351 const unsigned last_bus)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001352{
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001353 struct i7core_dev *i7core_dev;
Hidetoshi Setob197cba2010-08-20 04:24:31 -03001354 const struct pci_id_descr *dev_descr = &table->descr[devno];
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001355
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03001356 struct pci_dev *pdev = NULL;
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -03001357 u8 bus = 0;
1358 u8 socket = 0;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001359
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001360 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001361 dev_descr->dev_id, *prev);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001362
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -03001363 /*
1364 * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
1365 * is at addr 8086:2c40, instead of 8086:2c41. So, we need
1366 * to probe for the alternate address in case of failure
1367 */
1368 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev)
1369 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1370 PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev);
1371
1372 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && !pdev)
1373 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1374 PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT,
1375 *prev);
1376
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001377 if (!pdev) {
1378 if (*prev) {
1379 *prev = pdev;
1380 return 0;
Mauro Carvalho Chehabd1fd4fb2009-07-10 18:39:53 -03001381 }
1382
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001383 if (dev_descr->optional)
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001384 return 0;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001385
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001386 if (devno == 0)
1387 return -ENODEV;
1388
Daniel J Bluemanab089372010-07-23 23:16:52 +01001389 i7core_printk(KERN_INFO,
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001390 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001391 dev_descr->dev, dev_descr->func,
1392 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001393
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001394 /* End of list, leave */
1395 return -ENODEV;
1396 }
1397 bus = pdev->bus->number;
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03001398
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001399 socket = last_bus - bus;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001400
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001401 i7core_dev = get_i7core_dev(socket);
1402 if (!i7core_dev) {
Hidetoshi Seto848b2f72010-08-20 04:24:44 -03001403 i7core_dev = alloc_i7core_dev(socket, table);
Hidetoshi Seto28966372010-08-20 04:28:51 -03001404 if (!i7core_dev) {
1405 pci_dev_put(pdev);
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001406 return -ENOMEM;
Hidetoshi Seto28966372010-08-20 04:28:51 -03001407 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001408 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001409
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001410 if (i7core_dev->pdev[devno]) {
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001411 i7core_printk(KERN_ERR,
1412 "Duplicated device for "
1413 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001414 bus, dev_descr->dev, dev_descr->func,
1415 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001416 pci_dev_put(pdev);
1417 return -ENODEV;
1418 }
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001419
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001420 i7core_dev->pdev[devno] = pdev;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001421
1422 /* Sanity check */
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001423 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
1424 PCI_FUNC(pdev->devfn) != dev_descr->func)) {
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001425 i7core_printk(KERN_ERR,
1426 "Device PCI ID %04x:%04x "
1427 "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001428 PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001429 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001430 bus, dev_descr->dev, dev_descr->func);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001431 return -ENODEV;
1432 }
1433
1434 /* Be sure that the device is enabled */
1435 if (unlikely(pci_enable_device(pdev) < 0)) {
1436 i7core_printk(KERN_ERR,
1437 "Couldn't enable "
1438 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001439 bus, dev_descr->dev, dev_descr->func,
1440 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001441 return -ENODEV;
1442 }
1443
Mauro Carvalho Chehabd4c27792009-09-05 04:12:02 -03001444 debugf0("Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001445 socket, bus, dev_descr->dev,
1446 dev_descr->func,
1447 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001448
Mauro Carvalho Chehaba3e15412010-08-21 08:52:41 -03001449 /*
1450 * As stated on drivers/pci/search.c, the reference count for
1451 * @from is always decremented if it is not %NULL. So, as we need
1452 * to get all devices up to null, we need to do a get for the device
1453 */
1454 pci_dev_get(pdev);
1455
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001456 *prev = pdev;
1457
1458 return 0;
1459}
1460
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03001461static int i7core_get_all_devices(void)
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001462{
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -02001463 int i, rc, last_bus;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001464 struct pci_dev *pdev = NULL;
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -02001465 const struct pci_id_table *table = pci_dev_table;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001466
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001467 last_bus = i7core_pci_lastbus();
1468
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -02001469 while (table && table->descr) {
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001470 for (i = 0; i < table->n_devs; i++) {
1471 pdev = NULL;
1472 do {
Hidetoshi Setob197cba2010-08-20 04:24:31 -03001473 rc = i7core_get_onedevice(&pdev, table, i,
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001474 last_bus);
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001475 if (rc < 0) {
1476 if (i == 0) {
1477 i = table->n_devs;
1478 break;
1479 }
1480 i7core_put_all_devices();
1481 return -ENODEV;
1482 }
1483 } while (pdev);
1484 }
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -02001485 table++;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001486 }
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001487
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001488 return 0;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001489}
1490
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001491static int mci_bind_devs(struct mem_ctl_info *mci,
1492 struct i7core_dev *i7core_dev)
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001493{
1494 struct i7core_pvt *pvt = mci->pvt_info;
1495 struct pci_dev *pdev;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001496 int i, func, slot;
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001497 char *family;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001498
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001499 pvt->is_registered = false;
1500 pvt->enable_scrub = false;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001501 for (i = 0; i < i7core_dev->n_devs; i++) {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001502 pdev = i7core_dev->pdev[i];
1503 if (!pdev)
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001504 continue;
1505
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001506 func = PCI_FUNC(pdev->devfn);
1507 slot = PCI_SLOT(pdev->devfn);
1508 if (slot == 3) {
1509 if (unlikely(func > MAX_MCR_FUNC))
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001510 goto error;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001511 pvt->pci_mcr[func] = pdev;
1512 } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
1513 if (unlikely(func > MAX_CHAN_FUNC))
1514 goto error;
1515 pvt->pci_ch[slot - 4][func] = pdev;
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001516 } else if (!slot && !func) {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001517 pvt->pci_noncore = pdev;
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001518
1519 /* Detect the processor family */
1520 switch (pdev->device) {
1521 case PCI_DEVICE_ID_INTEL_I7_NONCORE:
1522 family = "Xeon 35xx/ i7core";
1523 pvt->enable_scrub = false;
1524 break;
1525 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT:
1526 family = "i7-800/i5-700";
1527 pvt->enable_scrub = false;
1528 break;
1529 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE:
1530 family = "Xeon 34xx";
1531 pvt->enable_scrub = false;
1532 break;
1533 case PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT:
1534 family = "Xeon 55xx";
1535 pvt->enable_scrub = true;
1536 break;
1537 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2:
1538 family = "Xeon 56xx / i7-900";
1539 pvt->enable_scrub = true;
1540 break;
1541 default:
1542 family = "unknown";
1543 pvt->enable_scrub = false;
1544 }
1545 debugf0("Detected a processor type %s\n", family);
1546 } else
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001547 goto error;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001548
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001549 debugf0("Associated fn %d.%d, dev = %p, socket %d\n",
1550 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1551 pdev, i7core_dev->socket);
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -03001552
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001553 if (PCI_SLOT(pdev->devfn) == 3 &&
1554 PCI_FUNC(pdev->devfn) == 2)
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001555 pvt->is_registered = true;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001556 }
Mauro Carvalho Chehabe9bd2e72009-07-09 22:14:35 -03001557
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001558 return 0;
1559
1560error:
1561 i7core_printk(KERN_ERR, "Device %d, function %d "
1562 "is out of the expected range\n",
1563 slot, func);
1564 return -EINVAL;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001565}
1566
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001567/****************************************************************************
1568 Error check routines
1569 ****************************************************************************/
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001570static void i7core_rdimm_update_csrow(struct mem_ctl_info *mci,
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001571 const int chan,
1572 const int dimm,
1573 const int add)
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001574{
1575 char *msg;
1576 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001577 int row = pvt->csrow_map[chan][dimm], i;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001578
1579 for (i = 0; i < add; i++) {
1580 msg = kasprintf(GFP_KERNEL, "Corrected error "
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001581 "(Socket=%d channel=%d dimm=%d)",
1582 pvt->i7core_dev->socket, chan, dimm);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001583
1584 edac_mc_handle_fbd_ce(mci, row, 0, msg);
1585 kfree (msg);
1586 }
1587}
1588
1589static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001590 const int chan,
1591 const int new0,
1592 const int new1,
1593 const int new2)
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001594{
1595 struct i7core_pvt *pvt = mci->pvt_info;
1596 int add0 = 0, add1 = 0, add2 = 0;
1597 /* Updates CE counters if it is not the first time here */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001598 if (pvt->ce_count_available) {
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001599 /* Updates CE counters */
1600
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001601 add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
1602 add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
1603 add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001604
1605 if (add2 < 0)
1606 add2 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001607 pvt->rdimm_ce_count[chan][2] += add2;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001608
1609 if (add1 < 0)
1610 add1 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001611 pvt->rdimm_ce_count[chan][1] += add1;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001612
1613 if (add0 < 0)
1614 add0 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001615 pvt->rdimm_ce_count[chan][0] += add0;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001616 } else
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001617 pvt->ce_count_available = 1;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001618
1619 /* Store the new values */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001620 pvt->rdimm_last_ce_count[chan][2] = new2;
1621 pvt->rdimm_last_ce_count[chan][1] = new1;
1622 pvt->rdimm_last_ce_count[chan][0] = new0;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001623
1624 /*updated the edac core */
1625 if (add0 != 0)
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001626 i7core_rdimm_update_csrow(mci, chan, 0, add0);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001627 if (add1 != 0)
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001628 i7core_rdimm_update_csrow(mci, chan, 1, add1);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001629 if (add2 != 0)
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001630 i7core_rdimm_update_csrow(mci, chan, 2, add2);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001631
1632}
1633
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001634static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci)
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001635{
1636 struct i7core_pvt *pvt = mci->pvt_info;
1637 u32 rcv[3][2];
1638 int i, new0, new1, new2;
1639
1640 /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001641 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001642 &rcv[0][0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001643 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001644 &rcv[0][1]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001645 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001646 &rcv[1][0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001647 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001648 &rcv[1][1]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001649 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001650 &rcv[2][0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001651 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001652 &rcv[2][1]);
1653 for (i = 0 ; i < 3; i++) {
1654 debugf3("MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n",
1655 (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]);
1656 /*if the channel has 3 dimms*/
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001657 if (pvt->channel[i].dimms > 2) {
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001658 new0 = DIMM_BOT_COR_ERR(rcv[i][0]);
1659 new1 = DIMM_TOP_COR_ERR(rcv[i][0]);
1660 new2 = DIMM_BOT_COR_ERR(rcv[i][1]);
1661 } else {
1662 new0 = DIMM_TOP_COR_ERR(rcv[i][0]) +
1663 DIMM_BOT_COR_ERR(rcv[i][0]);
1664 new1 = DIMM_TOP_COR_ERR(rcv[i][1]) +
1665 DIMM_BOT_COR_ERR(rcv[i][1]);
1666 new2 = 0;
1667 }
1668
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001669 i7core_rdimm_update_ce_count(mci, i, new0, new1, new2);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001670 }
1671}
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001672
1673/* This function is based on the device 3 function 4 registers as described on:
1674 * Intel Xeon Processor 5500 Series Datasheet Volume 2
1675 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
1676 * also available at:
1677 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
1678 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001679static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci)
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001680{
1681 struct i7core_pvt *pvt = mci->pvt_info;
1682 u32 rcv1, rcv0;
1683 int new0, new1, new2;
1684
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001685 if (!pvt->pci_mcr[4]) {
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -03001686 debugf0("%s MCR registers not found\n", __func__);
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001687 return;
1688 }
1689
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001690 /* Corrected test errors */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001691 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
1692 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001693
1694 /* Store the new values */
1695 new2 = DIMM2_COR_ERR(rcv1);
1696 new1 = DIMM1_COR_ERR(rcv0);
1697 new0 = DIMM0_COR_ERR(rcv0);
1698
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001699 /* Updates CE counters if it is not the first time here */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001700 if (pvt->ce_count_available) {
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001701 /* Updates CE counters */
1702 int add0, add1, add2;
1703
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001704 add2 = new2 - pvt->udimm_last_ce_count[2];
1705 add1 = new1 - pvt->udimm_last_ce_count[1];
1706 add0 = new0 - pvt->udimm_last_ce_count[0];
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001707
1708 if (add2 < 0)
1709 add2 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001710 pvt->udimm_ce_count[2] += add2;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001711
1712 if (add1 < 0)
1713 add1 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001714 pvt->udimm_ce_count[1] += add1;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001715
1716 if (add0 < 0)
1717 add0 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001718 pvt->udimm_ce_count[0] += add0;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001719
1720 if (add0 | add1 | add2)
1721 i7core_printk(KERN_ERR, "New Corrected error(s): "
1722 "dimm0: +%d, dimm1: +%d, dimm2 +%d\n",
1723 add0, add1, add2);
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001724 } else
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001725 pvt->ce_count_available = 1;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001726
1727 /* Store the new values */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001728 pvt->udimm_last_ce_count[2] = new2;
1729 pvt->udimm_last_ce_count[1] = new1;
1730 pvt->udimm_last_ce_count[0] = new0;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001731}
1732
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001733/*
1734 * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32
1735 * Architectures Software Developer’s Manual Volume 3B.
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001736 * Nehalem are defined as family 0x06, model 0x1a
1737 *
1738 * The MCA registers used here are the following ones:
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001739 * struct mce field MCA Register
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001740 * m->status MSR_IA32_MC8_STATUS
1741 * m->addr MSR_IA32_MC8_ADDR
1742 * m->misc MSR_IA32_MC8_MISC
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001743 * In the case of Nehalem, the error information is masked at .status and .misc
1744 * fields
1745 */
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001746static void i7core_mce_output_error(struct mem_ctl_info *mci,
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001747 const struct mce *m)
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001748{
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001749 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001750 char *type, *optype, *err, *msg;
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001751 unsigned long error = m->status & 0x1ff0000l;
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001752 u32 optypenum = (m->status >> 4) & 0x07;
Mathias Krause8cf2d232011-08-18 09:17:00 +02001753 u32 core_err_cnt = (m->status >> 38) & 0x7fff;
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001754 u32 dimm = (m->misc >> 16) & 0x3;
1755 u32 channel = (m->misc >> 18) & 0x3;
1756 u32 syndrome = m->misc >> 32;
1757 u32 errnum = find_first_bit(&error, 32);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001758 int csrow;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001759
Mauro Carvalho Chehabc5d34522009-07-17 10:28:15 -03001760 if (m->mcgstatus & 1)
1761 type = "FATAL";
1762 else
1763 type = "NON_FATAL";
1764
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001765 switch (optypenum) {
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -03001766 case 0:
1767 optype = "generic undef request";
1768 break;
1769 case 1:
1770 optype = "read error";
1771 break;
1772 case 2:
1773 optype = "write error";
1774 break;
1775 case 3:
1776 optype = "addr/cmd error";
1777 break;
1778 case 4:
1779 optype = "scrubbing error";
1780 break;
1781 default:
1782 optype = "reserved";
1783 break;
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001784 }
1785
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001786 switch (errnum) {
1787 case 16:
1788 err = "read ECC error";
1789 break;
1790 case 17:
1791 err = "RAS ECC error";
1792 break;
1793 case 18:
1794 err = "write parity error";
1795 break;
1796 case 19:
1797 err = "redundacy loss";
1798 break;
1799 case 20:
1800 err = "reserved";
1801 break;
1802 case 21:
1803 err = "memory range error";
1804 break;
1805 case 22:
1806 err = "RTID out of range";
1807 break;
1808 case 23:
1809 err = "address parity error";
1810 break;
1811 case 24:
1812 err = "byte enable parity error";
1813 break;
1814 default:
1815 err = "unknown";
1816 }
1817
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001818 /* FIXME: should convert addr into bank and rank information */
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001819 msg = kasprintf(GFP_ATOMIC,
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001820 "%s (addr = 0x%08llx, cpu=%d, Dimm=%d, Channel=%d, "
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001821 "syndrome=0x%08x, count=%d, Err=%08llx:%08llx (%s: %s))\n",
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001822 type, (long long) m->addr, m->cpu, dimm, channel,
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001823 syndrome, core_err_cnt, (long long)m->status,
1824 (long long)m->misc, optype, err);
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001825
1826 debugf0("%s", msg);
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001827
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001828 csrow = pvt->csrow_map[channel][dimm];
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001829
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001830 /* Call the helper to output message */
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001831 if (m->mcgstatus & 1)
1832 edac_mc_handle_fbd_ue(mci, csrow, 0,
1833 0 /* FIXME: should be channel here */, msg);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001834 else if (!pvt->is_registered)
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001835 edac_mc_handle_fbd_ce(mci, csrow,
1836 0 /* FIXME: should be channel here */, msg);
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001837
1838 kfree(msg);
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001839}
1840
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001841/*
Mauro Carvalho Chehab87d1d272009-06-22 22:48:29 -03001842 * i7core_check_error Retrieve and process errors reported by the
1843 * hardware. Called by the Core module.
1844 */
1845static void i7core_check_error(struct mem_ctl_info *mci)
1846{
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001847 struct i7core_pvt *pvt = mci->pvt_info;
1848 int i;
1849 unsigned count = 0;
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001850 struct mce *m;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001851
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001852 /*
1853 * MCE first step: Copy all mce errors into a temporary buffer
1854 * We use a double buffering here, to reduce the risk of
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001855 * losing an error.
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001856 */
1857 smp_rmb();
Mauro Carvalho Chehab321ece42009-10-08 13:11:08 -03001858 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1859 % MCE_LOG_LEN;
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001860 if (!count)
Vernon Mauery8a311e12010-04-16 19:40:19 -03001861 goto check_ce_error;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001862
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001863 m = pvt->mce_outentry;
Mauro Carvalho Chehab321ece42009-10-08 13:11:08 -03001864 if (pvt->mce_in + count > MCE_LOG_LEN) {
1865 unsigned l = MCE_LOG_LEN - pvt->mce_in;
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001866
1867 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1868 smp_wmb();
1869 pvt->mce_in = 0;
1870 count -= l;
1871 m += l;
1872 }
1873 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1874 smp_wmb();
1875 pvt->mce_in += count;
1876
1877 smp_rmb();
1878 if (pvt->mce_overrun) {
1879 i7core_printk(KERN_ERR, "Lost %d memory errors\n",
1880 pvt->mce_overrun);
1881 smp_wmb();
1882 pvt->mce_overrun = 0;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001883 }
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001884
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001885 /*
1886 * MCE second step: parse errors and display
1887 */
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001888 for (i = 0; i < count; i++)
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001889 i7core_mce_output_error(mci, &pvt->mce_outentry[i]);
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001890
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001891 /*
1892 * Now, let's increment CE error counts
1893 */
Vernon Mauery8a311e12010-04-16 19:40:19 -03001894check_ce_error:
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001895 if (!pvt->is_registered)
1896 i7core_udimm_check_mc_ecc_err(mci);
1897 else
1898 i7core_rdimm_check_mc_ecc_err(mci);
Mauro Carvalho Chehab87d1d272009-06-22 22:48:29 -03001899}
1900
1901/*
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001902 * i7core_mce_check_error Replicates mcelog routine to get errors
1903 * This routine simply queues mcelog errors, and
1904 * return. The error itself should be handled later
1905 * by i7core_check_error.
Mauro Carvalho Chehab6e103be2009-10-05 09:40:09 -03001906 * WARNING: As this routine should be called at NMI time, extra care should
1907 * be taken to avoid deadlocks, and to be as fast as possible.
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001908 */
Borislav Petkov4140c542011-07-18 11:24:46 -03001909static int i7core_mce_check_error(struct notifier_block *nb, unsigned long val,
1910 void *data)
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001911{
Borislav Petkov4140c542011-07-18 11:24:46 -03001912 struct mce *mce = (struct mce *)data;
1913 struct i7core_dev *i7_dev;
1914 struct mem_ctl_info *mci;
1915 struct i7core_pvt *pvt;
1916
1917 i7_dev = get_i7core_dev(mce->socketid);
1918 if (!i7_dev)
1919 return NOTIFY_BAD;
1920
1921 mci = i7_dev->mci;
1922 pvt = mci->pvt_info;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001923
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001924 /*
1925 * Just let mcelog handle it if the error is
1926 * outside the memory controller
1927 */
1928 if (((mce->status & 0xffff) >> 7) != 1)
Borislav Petkov4140c542011-07-18 11:24:46 -03001929 return NOTIFY_DONE;
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001930
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001931 /* Bank 8 registers are the only ones that we know how to handle */
1932 if (mce->bank != 8)
Borislav Petkov4140c542011-07-18 11:24:46 -03001933 return NOTIFY_DONE;
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001934
Randy Dunlap3b918c12009-11-08 01:36:40 -02001935#ifdef CONFIG_SMP
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001936 /* Only handle if it is the right mc controller */
Thomas Renninger50340862011-06-22 05:40:06 -03001937 if (mce->socketid != pvt->i7core_dev->socket)
Borislav Petkov4140c542011-07-18 11:24:46 -03001938 return NOTIFY_DONE;
Randy Dunlap3b918c12009-11-08 01:36:40 -02001939#endif
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001940
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001941 smp_rmb();
Mauro Carvalho Chehab321ece42009-10-08 13:11:08 -03001942 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001943 smp_wmb();
1944 pvt->mce_overrun++;
Borislav Petkov4140c542011-07-18 11:24:46 -03001945 return NOTIFY_DONE;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001946 }
Mauro Carvalho Chehab6e103be2009-10-05 09:40:09 -03001947
1948 /* Copy memory error at the ringbuffer */
1949 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001950 smp_wmb();
Mauro Carvalho Chehab321ece42009-10-08 13:11:08 -03001951 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001952
Mauro Carvalho Chehabc5d34522009-07-17 10:28:15 -03001953 /* Handle fatal errors immediately */
1954 if (mce->mcgstatus & 1)
1955 i7core_check_error(mci);
1956
David Sterbae7bf0682010-12-27 16:51:15 +01001957 /* Advise mcelog that the errors were handled */
Borislav Petkov4140c542011-07-18 11:24:46 -03001958 return NOTIFY_STOP;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001959}
1960
Borislav Petkov4140c542011-07-18 11:24:46 -03001961static struct notifier_block i7_mce_dec = {
1962 .notifier_call = i7core_mce_check_error,
1963};
1964
Nils Carlson535e9c72011-08-08 06:21:26 -03001965struct memdev_dmi_entry {
1966 u8 type;
1967 u8 length;
1968 u16 handle;
1969 u16 phys_mem_array_handle;
1970 u16 mem_err_info_handle;
1971 u16 total_width;
1972 u16 data_width;
1973 u16 size;
1974 u8 form;
1975 u8 device_set;
1976 u8 device_locator;
1977 u8 bank_locator;
1978 u8 memory_type;
1979 u16 type_detail;
1980 u16 speed;
1981 u8 manufacturer;
1982 u8 serial_number;
1983 u8 asset_tag;
1984 u8 part_number;
1985 u8 attributes;
1986 u32 extended_size;
1987 u16 conf_mem_clk_speed;
1988} __attribute__((__packed__));
1989
1990
1991/*
1992 * Decode the DRAM Clock Frequency, be paranoid, make sure that all
1993 * memory devices show the same speed, and if they don't then consider
1994 * all speeds to be invalid.
1995 */
1996static void decode_dclk(const struct dmi_header *dh, void *_dclk_freq)
1997{
1998 int *dclk_freq = _dclk_freq;
1999 u16 dmi_mem_clk_speed;
2000
2001 if (*dclk_freq == -1)
2002 return;
2003
2004 if (dh->type == DMI_ENTRY_MEM_DEVICE) {
2005 struct memdev_dmi_entry *memdev_dmi_entry =
2006 (struct memdev_dmi_entry *)dh;
2007 unsigned long conf_mem_clk_speed_offset =
2008 (unsigned long)&memdev_dmi_entry->conf_mem_clk_speed -
2009 (unsigned long)&memdev_dmi_entry->type;
2010 unsigned long speed_offset =
2011 (unsigned long)&memdev_dmi_entry->speed -
2012 (unsigned long)&memdev_dmi_entry->type;
2013
2014 /* Check that a DIMM is present */
2015 if (memdev_dmi_entry->size == 0)
2016 return;
2017
2018 /*
2019 * Pick the configured speed if it's available, otherwise
2020 * pick the DIMM speed, or we don't have a speed.
2021 */
2022 if (memdev_dmi_entry->length > conf_mem_clk_speed_offset) {
2023 dmi_mem_clk_speed =
2024 memdev_dmi_entry->conf_mem_clk_speed;
2025 } else if (memdev_dmi_entry->length > speed_offset) {
2026 dmi_mem_clk_speed = memdev_dmi_entry->speed;
2027 } else {
2028 *dclk_freq = -1;
2029 return;
2030 }
2031
2032 if (*dclk_freq == 0) {
2033 /* First pass, speed was 0 */
2034 if (dmi_mem_clk_speed > 0) {
2035 /* Set speed if a valid speed is read */
2036 *dclk_freq = dmi_mem_clk_speed;
2037 } else {
2038 /* Otherwise we don't have a valid speed */
2039 *dclk_freq = -1;
2040 }
2041 } else if (*dclk_freq > 0 &&
2042 *dclk_freq != dmi_mem_clk_speed) {
2043 /*
2044 * If we have a speed, check that all DIMMS are the same
2045 * speed, otherwise set the speed as invalid.
2046 */
2047 *dclk_freq = -1;
2048 }
2049 }
2050}
2051
2052/*
2053 * The default DCLK frequency is used as a fallback if we
2054 * fail to find anything reliable in the DMI. The value
2055 * is taken straight from the datasheet.
2056 */
2057#define DEFAULT_DCLK_FREQ 800
2058
2059static int get_dclk_freq(void)
2060{
2061 int dclk_freq = 0;
2062
2063 dmi_walk(decode_dclk, (void *)&dclk_freq);
2064
2065 if (dclk_freq < 1)
2066 return DEFAULT_DCLK_FREQ;
2067
2068 return dclk_freq;
2069}
2070
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002071/*
2072 * set_sdram_scrub_rate This routine sets byte/sec bandwidth scrub rate
2073 * to hardware according to SCRUBINTERVAL formula
2074 * found in datasheet.
2075 */
2076static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 new_bw)
2077{
2078 struct i7core_pvt *pvt = mci->pvt_info;
2079 struct pci_dev *pdev;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002080 u32 dw_scrub;
2081 u32 dw_ssr;
2082
2083 /* Get data from the MC register, function 2 */
2084 pdev = pvt->pci_mcr[2];
2085 if (!pdev)
2086 return -ENODEV;
2087
2088 pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &dw_scrub);
2089
2090 if (new_bw == 0) {
2091 /* Prepare to disable petrol scrub */
2092 dw_scrub &= ~STARTSCRUB;
2093 /* Stop the patrol scrub engine */
Nils Carlson535e9c72011-08-08 06:21:26 -03002094 write_and_test(pdev, MC_SCRUB_CONTROL,
2095 dw_scrub & ~SCRUBINTERVAL_MASK);
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002096
2097 /* Get current status of scrub rate and set bit to disable */
2098 pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr);
2099 dw_ssr &= ~SSR_MODE_MASK;
2100 dw_ssr |= SSR_MODE_DISABLE;
2101 } else {
Nils Carlson535e9c72011-08-08 06:21:26 -03002102 const int cache_line_size = 64;
2103 const u32 freq_dclk_mhz = pvt->dclk_freq;
2104 unsigned long long scrub_interval;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002105 /*
2106 * Translate the desired scrub rate to a register value and
Nils Carlson535e9c72011-08-08 06:21:26 -03002107 * program the corresponding register value.
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002108 */
Nils Carlson535e9c72011-08-08 06:21:26 -03002109 scrub_interval = (unsigned long long)freq_dclk_mhz *
Sedat Dilek4fad8092011-09-21 23:44:52 -03002110 cache_line_size * 1000000;
2111 do_div(scrub_interval, new_bw);
Nils Carlson535e9c72011-08-08 06:21:26 -03002112
2113 if (!scrub_interval || scrub_interval > SCRUBINTERVAL_MASK)
2114 return -EINVAL;
2115
2116 dw_scrub = SCRUBINTERVAL_MASK & scrub_interval;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002117
2118 /* Start the patrol scrub engine */
2119 pci_write_config_dword(pdev, MC_SCRUB_CONTROL,
2120 STARTSCRUB | dw_scrub);
2121
2122 /* Get current status of scrub rate and set bit to enable */
2123 pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr);
2124 dw_ssr &= ~SSR_MODE_MASK;
2125 dw_ssr |= SSR_MODE_ENABLE;
2126 }
2127 /* Disable or enable scrubbing */
2128 pci_write_config_dword(pdev, MC_SSRCONTROL, dw_ssr);
2129
2130 return new_bw;
2131}
2132
2133/*
2134 * get_sdram_scrub_rate This routine convert current scrub rate value
2135 * into byte/sec bandwidth accourding to
2136 * SCRUBINTERVAL formula found in datasheet.
2137 */
2138static int get_sdram_scrub_rate(struct mem_ctl_info *mci)
2139{
2140 struct i7core_pvt *pvt = mci->pvt_info;
2141 struct pci_dev *pdev;
2142 const u32 cache_line_size = 64;
Nils Carlson535e9c72011-08-08 06:21:26 -03002143 const u32 freq_dclk_mhz = pvt->dclk_freq;
2144 unsigned long long scrub_rate;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002145 u32 scrubval;
2146
2147 /* Get data from the MC register, function 2 */
2148 pdev = pvt->pci_mcr[2];
2149 if (!pdev)
2150 return -ENODEV;
2151
2152 /* Get current scrub control data */
2153 pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &scrubval);
2154
2155 /* Mask highest 8-bits to 0 */
Nils Carlson535e9c72011-08-08 06:21:26 -03002156 scrubval &= SCRUBINTERVAL_MASK;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002157 if (!scrubval)
2158 return 0;
2159
2160 /* Calculate scrub rate value into byte/sec bandwidth */
Nils Carlson535e9c72011-08-08 06:21:26 -03002161 scrub_rate = (unsigned long long)freq_dclk_mhz *
Sedat Dilek4fad8092011-09-21 23:44:52 -03002162 1000000 * cache_line_size;
2163 do_div(scrub_rate, scrubval);
Nils Carlson535e9c72011-08-08 06:21:26 -03002164 return (int)scrub_rate;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002165}
2166
2167static void enable_sdram_scrub_setting(struct mem_ctl_info *mci)
2168{
2169 struct i7core_pvt *pvt = mci->pvt_info;
2170 u32 pci_lock;
2171
2172 /* Unlock writes to pci registers */
2173 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
2174 pci_lock &= ~0x3;
2175 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
2176 pci_lock | MC_CFG_UNLOCK);
2177
2178 mci->set_sdram_scrub_rate = set_sdram_scrub_rate;
2179 mci->get_sdram_scrub_rate = get_sdram_scrub_rate;
2180}
2181
2182static void disable_sdram_scrub_setting(struct mem_ctl_info *mci)
2183{
2184 struct i7core_pvt *pvt = mci->pvt_info;
2185 u32 pci_lock;
2186
2187 /* Lock writes to pci registers */
2188 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
2189 pci_lock &= ~0x3;
2190 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
2191 pci_lock | MC_CFG_LOCK);
2192}
2193
Hidetoshi Setoa3aa0a42010-08-20 04:25:18 -03002194static void i7core_pci_ctl_create(struct i7core_pvt *pvt)
2195{
2196 pvt->i7core_pci = edac_pci_create_generic_ctl(
2197 &pvt->i7core_dev->pdev[0]->dev,
2198 EDAC_MOD_STR);
2199 if (unlikely(!pvt->i7core_pci))
Mauro Carvalho Chehabf9902f22010-08-21 09:42:05 -03002200 i7core_printk(KERN_WARNING,
2201 "Unable to setup PCI error report via EDAC\n");
Hidetoshi Setoa3aa0a42010-08-20 04:25:18 -03002202}
2203
2204static void i7core_pci_ctl_release(struct i7core_pvt *pvt)
2205{
2206 if (likely(pvt->i7core_pci))
2207 edac_pci_release_generic_ctl(pvt->i7core_pci);
2208 else
2209 i7core_printk(KERN_ERR,
2210 "Couldn't find mem_ctl_info for socket %d\n",
2211 pvt->i7core_dev->socket);
2212 pvt->i7core_pci = NULL;
2213}
2214
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002215static void i7core_unregister_mci(struct i7core_dev *i7core_dev)
2216{
2217 struct mem_ctl_info *mci = i7core_dev->mci;
2218 struct i7core_pvt *pvt;
2219
2220 if (unlikely(!mci || !mci->pvt_info)) {
2221 debugf0("MC: " __FILE__ ": %s(): dev = %p\n",
2222 __func__, &i7core_dev->pdev[0]->dev);
2223
2224 i7core_printk(KERN_ERR, "Couldn't find mci handler\n");
2225 return;
2226 }
2227
2228 pvt = mci->pvt_info;
2229
2230 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
2231 __func__, mci, &i7core_dev->pdev[0]->dev);
2232
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002233 /* Disable scrubrate setting */
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03002234 if (pvt->enable_scrub)
2235 disable_sdram_scrub_setting(mci);
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002236
Borislav Petkov3653ada2011-12-04 15:12:09 +01002237 mce_unregister_decode_chain(&i7_mce_dec);
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002238
2239 /* Disable EDAC polling */
2240 i7core_pci_ctl_release(pvt);
2241
2242 /* Remove MC sysfs nodes */
2243 edac_mc_del_mc(mci->dev);
2244
2245 debugf1("%s: free mci struct\n", mci->ctl_name);
2246 kfree(mci->ctl_name);
2247 edac_mc_free(mci);
2248 i7core_dev->mci = NULL;
2249}
2250
Hidetoshi Setoaace4282010-08-20 04:32:45 -03002251static int i7core_register_mci(struct i7core_dev *i7core_dev)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002252{
2253 struct mem_ctl_info *mci;
2254 struct i7core_pvt *pvt;
Hidetoshi Setoaace4282010-08-20 04:32:45 -03002255 int rc, channels, csrows;
2256
2257 /* Check the number of active and not disabled channels */
2258 rc = i7core_get_active_channels(i7core_dev->socket, &channels, &csrows);
2259 if (unlikely(rc < 0))
2260 return rc;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002261
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002262 /* allocate a new MC control structure */
Hidetoshi Setoaace4282010-08-20 04:32:45 -03002263 mci = edac_mc_alloc(sizeof(*pvt), csrows, channels, i7core_dev->socket);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002264 if (unlikely(!mci))
2265 return -ENOMEM;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002266
Mauro Carvalho Chehab3cfd0142010-08-10 23:23:46 -03002267 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
2268 __func__, mci, &i7core_dev->pdev[0]->dev);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002269
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002270 pvt = mci->pvt_info;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002271 memset(pvt, 0, sizeof(*pvt));
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -03002272
Mauro Carvalho Chehab6d37d242010-08-20 12:48:26 -03002273 /* Associates i7core_dev and mci for future usage */
2274 pvt->i7core_dev = i7core_dev;
2275 i7core_dev->mci = mci;
2276
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -03002277 /*
2278 * FIXME: how to handle RDDR3 at MCI level? It is possible to have
2279 * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
2280 * memory channels
2281 */
2282 mci->mtype_cap = MEM_FLAG_DDR3;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002283 mci->edac_ctl_cap = EDAC_FLAG_NONE;
2284 mci->edac_cap = EDAC_FLAG_NONE;
2285 mci->mod_name = "i7core_edac.c";
2286 mci->mod_ver = I7CORE_REVISION;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002287 mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d",
2288 i7core_dev->socket);
2289 mci->dev_name = pci_name(i7core_dev->pdev[0]);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002290 mci->ctl_page_to_phys = NULL;
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03002291
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002292 /* Store pci devices at mci for faster access */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002293 rc = mci_bind_devs(mci, i7core_dev);
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -03002294 if (unlikely(rc < 0))
Hidetoshi Seto628c5dd2010-08-20 04:28:40 -03002295 goto fail0;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002296
Hidetoshi Seto59398132010-08-20 04:28:25 -03002297 if (pvt->is_registered)
2298 mci->mc_driver_sysfs_attributes = i7core_sysfs_rdimm_attrs;
2299 else
2300 mci->mc_driver_sysfs_attributes = i7core_sysfs_udimm_attrs;
2301
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002302 /* Get dimm basic config */
Hidetoshi Seto2e5185f2010-08-20 04:32:56 -03002303 get_dimm_config(mci);
Hidetoshi Seto59398132010-08-20 04:28:25 -03002304 /* record ptr to the generic device */
2305 mci->dev = &i7core_dev->pdev[0]->dev;
2306 /* Set the function pointer to an actual operation function */
2307 mci->edac_check = i7core_check_error;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002308
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002309 /* Enable scrubrate setting */
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03002310 if (pvt->enable_scrub)
2311 enable_sdram_scrub_setting(mci);
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002312
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002313 /* add this new MC control structure to EDAC's list of MCs */
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -03002314 if (unlikely(edac_mc_add_mc(mci))) {
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002315 debugf0("MC: " __FILE__
2316 ": %s(): failed edac_mc_add_mc()\n", __func__);
2317 /* FIXME: perhaps some code should go here that disables error
2318 * reporting if we just enabled it
2319 */
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -03002320
2321 rc = -EINVAL;
Hidetoshi Seto628c5dd2010-08-20 04:28:40 -03002322 goto fail0;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002323 }
2324
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03002325 /* Default error mask is any memory */
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002326 pvt->inject.channel = 0;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03002327 pvt->inject.dimm = -1;
2328 pvt->inject.rank = -1;
2329 pvt->inject.bank = -1;
2330 pvt->inject.page = -1;
2331 pvt->inject.col = -1;
2332
Hidetoshi Setoa3aa0a42010-08-20 04:25:18 -03002333 /* allocating generic PCI control info */
2334 i7core_pci_ctl_create(pvt);
2335
Nils Carlson535e9c72011-08-08 06:21:26 -03002336 /* DCLK for scrub rate setting */
2337 pvt->dclk_freq = get_dclk_freq();
2338
Borislav Petkov3653ada2011-12-04 15:12:09 +01002339 mce_register_decode_chain(&i7_mce_dec);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002340
Hidetoshi Seto628c5dd2010-08-20 04:28:40 -03002341 return 0;
2342
Hidetoshi Seto628c5dd2010-08-20 04:28:40 -03002343fail0:
2344 kfree(mci->ctl_name);
2345 edac_mc_free(mci);
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002346 i7core_dev->mci = NULL;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002347 return rc;
2348}
2349
2350/*
2351 * i7core_probe Probe for ONE instance of device to see if it is
2352 * present.
2353 * return:
2354 * 0 for FOUND a device
2355 * < 0 for error code
2356 */
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002357
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002358static int __devinit i7core_probe(struct pci_dev *pdev,
2359 const struct pci_device_id *id)
2360{
Mauro Carvalho Chehab40557592010-11-30 08:14:30 -02002361 int rc, count = 0;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002362 struct i7core_dev *i7core_dev;
2363
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002364 /* get the pci devices we want to reserve for our use */
2365 mutex_lock(&i7core_edac_lock);
2366
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002367 /*
Mauro Carvalho Chehabd4c27792009-09-05 04:12:02 -03002368 * All memory controllers are allocated at the first pass.
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002369 */
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002370 if (unlikely(probed >= 1)) {
2371 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehab76a7bd82010-10-24 11:36:19 -02002372 return -ENODEV;
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002373 }
2374 probed++;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03002375
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03002376 rc = i7core_get_all_devices();
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002377 if (unlikely(rc < 0))
2378 goto fail0;
2379
2380 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
Mauro Carvalho Chehab40557592010-11-30 08:14:30 -02002381 count++;
Hidetoshi Setoaace4282010-08-20 04:32:45 -03002382 rc = i7core_register_mci(i7core_dev);
Mauro Carvalho Chehabd4c27792009-09-05 04:12:02 -03002383 if (unlikely(rc < 0))
2384 goto fail1;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03002385 }
2386
Mauro Carvalho Chehab40557592010-11-30 08:14:30 -02002387 /*
2388 * Nehalem-EX uses a different memory controller. However, as the
2389 * memory controller is not visible on some Nehalem/Nehalem-EP, we
2390 * need to indirectly probe via a X58 PCI device. The same devices
2391 * are found on (some) Nehalem-EX. So, on those machines, the
2392 * probe routine needs to return -ENODEV, as the actual Memory
2393 * Controller registers won't be detected.
2394 */
2395 if (!count) {
2396 rc = -ENODEV;
2397 goto fail1;
2398 }
2399
2400 i7core_printk(KERN_INFO,
2401 "Driver loaded, %d memory controller(s) found.\n",
2402 count);
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03002403
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002404 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002405 return 0;
2406
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002407fail1:
Mauro Carvalho Chehab88ef5ea2010-08-20 15:39:38 -03002408 list_for_each_entry(i7core_dev, &i7core_edac_list, list)
2409 i7core_unregister_mci(i7core_dev);
2410
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03002411 i7core_put_all_devices();
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002412fail0:
2413 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -03002414 return rc;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002415}
2416
2417/*
2418 * i7core_remove destructor for one instance of device
2419 *
2420 */
2421static void __devexit i7core_remove(struct pci_dev *pdev)
2422{
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03002423 struct i7core_dev *i7core_dev;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002424
2425 debugf0(__FILE__ ": %s()\n", __func__);
2426
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03002427 /*
2428 * we have a trouble here: pdev value for removal will be wrong, since
2429 * it will point to the X58 register used to detect that the machine
2430 * is a Nehalem or upper design. However, due to the way several PCI
2431 * devices are grouped together to provide MC functionality, we need
2432 * to use a different method for releasing the devices
2433 */
Mauro Carvalho Chehab87d1d272009-06-22 22:48:29 -03002434
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002435 mutex_lock(&i7core_edac_lock);
Hidetoshi Seto71fe0172010-08-20 04:29:47 -03002436
2437 if (unlikely(!probed)) {
2438 mutex_unlock(&i7core_edac_lock);
2439 return;
2440 }
2441
Mauro Carvalho Chehab88ef5ea2010-08-20 15:39:38 -03002442 list_for_each_entry(i7core_dev, &i7core_edac_list, list)
2443 i7core_unregister_mci(i7core_dev);
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03002444
2445 /* Release PCI resources */
2446 i7core_put_all_devices();
2447
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002448 probed--;
2449
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03002450 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002451}
2452
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002453MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);
2454
2455/*
2456 * i7core_driver pci_driver structure for this module
2457 *
2458 */
2459static struct pci_driver i7core_driver = {
2460 .name = "i7core_edac",
2461 .probe = i7core_probe,
2462 .remove = __devexit_p(i7core_remove),
2463 .id_table = i7core_pci_tbl,
2464};
2465
2466/*
2467 * i7core_init Module entry function
2468 * Try to initialize this module for its devices
2469 */
2470static int __init i7core_init(void)
2471{
2472 int pci_rc;
2473
2474 debugf2("MC: " __FILE__ ": %s()\n", __func__);
2475
2476 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2477 opstate_init();
2478
Mauro Carvalho Chehab54a08ab2010-08-19 15:51:00 -03002479 if (use_pci_fixup)
2480 i7core_xeon_pci_fixup(pci_dev_table);
Keith Manntheybc2d7242009-09-03 00:05:05 -03002481
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002482 pci_rc = pci_register_driver(&i7core_driver);
2483
Mauro Carvalho Chehab3ef288a2009-09-02 23:43:33 -03002484 if (pci_rc >= 0)
2485 return 0;
2486
2487 i7core_printk(KERN_ERR, "Failed to register device with error %d.\n",
2488 pci_rc);
2489
2490 return pci_rc;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002491}
2492
2493/*
2494 * i7core_exit() Module exit function
2495 * Unregister the driver
2496 */
2497static void __exit i7core_exit(void)
2498{
2499 debugf2("MC: " __FILE__ ": %s()\n", __func__);
2500 pci_unregister_driver(&i7core_driver);
2501}
2502
2503module_init(i7core_init);
2504module_exit(i7core_exit);
2505
2506MODULE_LICENSE("GPL");
2507MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2508MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
2509MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - "
2510 I7CORE_REVISION);
2511
2512module_param(edac_op_state, int, 0444);
2513MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");