blob: 41cdefbaf7f3d2b634135207424f076a65bc576e [file] [log] [blame]
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001/*
2 * linux/drivers/video/omap2/dss/dsi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#define DSS_SUBSYS_NAME "DSI"
21
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <linux/clk.h>
25#include <linux/device.h>
26#include <linux/err.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/mutex.h>
Tomi Valkeinenb9eb5d72010-01-11 16:33:56 +020030#include <linux/semaphore.h>
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +020031#include <linux/seq_file.h>
32#include <linux/platform_device.h>
33#include <linux/regulator/consumer.h>
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +020034#include <linux/wait.h>
Tomi Valkeinen18946f62010-01-12 14:16:41 +020035#include <linux/workqueue.h>
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +020036
37#include <plat/display.h>
38#include <plat/clock.h>
39
40#include "dss.h"
41
42/*#define VERBOSE_IRQ*/
43#define DSI_CATCH_MISSING_TE
44
45#define DSI_BASE 0x4804FC00
46
47struct dsi_reg { u16 idx; };
48
49#define DSI_REG(idx) ((const struct dsi_reg) { idx })
50
51#define DSI_SZ_REGS SZ_1K
52/* DSI Protocol Engine */
53
54#define DSI_REVISION DSI_REG(0x0000)
55#define DSI_SYSCONFIG DSI_REG(0x0010)
56#define DSI_SYSSTATUS DSI_REG(0x0014)
57#define DSI_IRQSTATUS DSI_REG(0x0018)
58#define DSI_IRQENABLE DSI_REG(0x001C)
59#define DSI_CTRL DSI_REG(0x0040)
60#define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
61#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
62#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
63#define DSI_CLK_CTRL DSI_REG(0x0054)
64#define DSI_TIMING1 DSI_REG(0x0058)
65#define DSI_TIMING2 DSI_REG(0x005C)
66#define DSI_VM_TIMING1 DSI_REG(0x0060)
67#define DSI_VM_TIMING2 DSI_REG(0x0064)
68#define DSI_VM_TIMING3 DSI_REG(0x0068)
69#define DSI_CLK_TIMING DSI_REG(0x006C)
70#define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
71#define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
72#define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
73#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
74#define DSI_VM_TIMING4 DSI_REG(0x0080)
75#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
76#define DSI_VM_TIMING5 DSI_REG(0x0088)
77#define DSI_VM_TIMING6 DSI_REG(0x008C)
78#define DSI_VM_TIMING7 DSI_REG(0x0090)
79#define DSI_STOPCLK_TIMING DSI_REG(0x0094)
80#define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
81#define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
82#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
83#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
84#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
85#define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
86#define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
87
88/* DSIPHY_SCP */
89
90#define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
91#define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
92#define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
93#define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
94
95/* DSI_PLL_CTRL_SCP */
96
97#define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
98#define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
99#define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
100#define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
101#define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
102
103#define REG_GET(idx, start, end) \
104 FLD_GET(dsi_read_reg(idx), start, end)
105
106#define REG_FLD_MOD(idx, val, start, end) \
107 dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
108
109/* Global interrupts */
110#define DSI_IRQ_VC0 (1 << 0)
111#define DSI_IRQ_VC1 (1 << 1)
112#define DSI_IRQ_VC2 (1 << 2)
113#define DSI_IRQ_VC3 (1 << 3)
114#define DSI_IRQ_WAKEUP (1 << 4)
115#define DSI_IRQ_RESYNC (1 << 5)
116#define DSI_IRQ_PLL_LOCK (1 << 7)
117#define DSI_IRQ_PLL_UNLOCK (1 << 8)
118#define DSI_IRQ_PLL_RECALL (1 << 9)
119#define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
120#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
121#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
122#define DSI_IRQ_TE_TRIGGER (1 << 16)
123#define DSI_IRQ_ACK_TRIGGER (1 << 17)
124#define DSI_IRQ_SYNC_LOST (1 << 18)
125#define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
126#define DSI_IRQ_TA_TIMEOUT (1 << 20)
127#define DSI_IRQ_ERROR_MASK \
128 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
129 DSI_IRQ_TA_TIMEOUT)
130#define DSI_IRQ_CHANNEL_MASK 0xf
131
132/* Virtual channel interrupts */
133#define DSI_VC_IRQ_CS (1 << 0)
134#define DSI_VC_IRQ_ECC_CORR (1 << 1)
135#define DSI_VC_IRQ_PACKET_SENT (1 << 2)
136#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
137#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
138#define DSI_VC_IRQ_BTA (1 << 5)
139#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
140#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
141#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
142#define DSI_VC_IRQ_ERROR_MASK \
143 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
144 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
145 DSI_VC_IRQ_FIFO_TX_UDF)
146
147/* ComplexIO interrupts */
148#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
149#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
150#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
151#define DSI_CIO_IRQ_ERRESC1 (1 << 5)
152#define DSI_CIO_IRQ_ERRESC2 (1 << 6)
153#define DSI_CIO_IRQ_ERRESC3 (1 << 7)
154#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
155#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
156#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
157#define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
158#define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
159#define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
160#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
161#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
162#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
163#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
164#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
165#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
166#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
167#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
168
169#define DSI_DT_DCS_SHORT_WRITE_0 0x05
170#define DSI_DT_DCS_SHORT_WRITE_1 0x15
171#define DSI_DT_DCS_READ 0x06
172#define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
173#define DSI_DT_NULL_PACKET 0x09
174#define DSI_DT_DCS_LONG_WRITE 0x39
175
176#define DSI_DT_RX_ACK_WITH_ERR 0x02
177#define DSI_DT_RX_DCS_LONG_READ 0x1c
178#define DSI_DT_RX_SHORT_READ_1 0x21
179#define DSI_DT_RX_SHORT_READ_2 0x22
180
181#define FINT_MAX 2100000
182#define FINT_MIN 750000
183#define REGN_MAX (1 << 7)
184#define REGM_MAX ((1 << 11) - 1)
185#define REGM3_MAX (1 << 4)
186#define REGM4_MAX (1 << 4)
187#define LP_DIV_MAX ((1 << 13) - 1)
188
189enum fifo_size {
190 DSI_FIFO_SIZE_0 = 0,
191 DSI_FIFO_SIZE_32 = 1,
192 DSI_FIFO_SIZE_64 = 2,
193 DSI_FIFO_SIZE_96 = 3,
194 DSI_FIFO_SIZE_128 = 4,
195};
196
197enum dsi_vc_mode {
198 DSI_VC_MODE_L4 = 0,
199 DSI_VC_MODE_VP,
200};
201
202struct dsi_update_region {
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200203 u16 x, y, w, h;
204 struct omap_dss_device *device;
205};
206
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200207struct dsi_irq_stats {
208 unsigned long last_reset;
209 unsigned irq_count;
210 unsigned dsi_irqs[32];
211 unsigned vc_irqs[4][32];
212 unsigned cio_irqs[32];
213};
214
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200215static struct
216{
217 void __iomem *base;
218
219 struct dsi_clock_info current_cinfo;
220
221 struct regulator *vdds_dsi_reg;
222
223 struct {
224 enum dsi_vc_mode mode;
225 struct omap_dss_device *dssdev;
226 enum fifo_size fifo_size;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200227 } vc[4];
228
229 struct mutex lock;
Tomi Valkeinenb9eb5d72010-01-11 16:33:56 +0200230 struct semaphore bus_lock;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200231
232 unsigned pll_locked;
233
234 struct completion bta_completion;
235
Tomi Valkeinen18946f62010-01-12 14:16:41 +0200236 int update_channel;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200237 struct dsi_update_region update_region;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200238
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200239 bool te_enabled;
240 bool use_ext_te;
241
Tomi Valkeinen18946f62010-01-12 14:16:41 +0200242 struct work_struct framedone_work;
243 void (*framedone_callback)(int, void *);
244 void *framedone_data;
245
246 struct delayed_work framedone_timeout_work;
247
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200248#ifdef DSI_CATCH_MISSING_TE
249 struct timer_list te_timer;
250#endif
251
252 unsigned long cache_req_pck;
253 unsigned long cache_clk_freq;
254 struct dsi_clock_info cache_cinfo;
255
256 u32 errors;
257 spinlock_t errors_lock;
258#ifdef DEBUG
259 ktime_t perf_setup_time;
260 ktime_t perf_start_time;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200261#endif
262 int debug_read;
263 int debug_write;
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200264
265#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
266 spinlock_t irq_stats_lock;
267 struct dsi_irq_stats irq_stats;
268#endif
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200269} dsi;
270
271#ifdef DEBUG
272static unsigned int dsi_perf;
273module_param_named(dsi_perf, dsi_perf, bool, 0644);
274#endif
275
276static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
277{
278 __raw_writel(val, dsi.base + idx.idx);
279}
280
281static inline u32 dsi_read_reg(const struct dsi_reg idx)
282{
283 return __raw_readl(dsi.base + idx.idx);
284}
285
286
287void dsi_save_context(void)
288{
289}
290
291void dsi_restore_context(void)
292{
293}
294
295void dsi_bus_lock(void)
296{
Tomi Valkeinenb9eb5d72010-01-11 16:33:56 +0200297 down(&dsi.bus_lock);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200298}
299EXPORT_SYMBOL(dsi_bus_lock);
300
301void dsi_bus_unlock(void)
302{
Tomi Valkeinenb9eb5d72010-01-11 16:33:56 +0200303 up(&dsi.bus_lock);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200304}
305EXPORT_SYMBOL(dsi_bus_unlock);
306
Tomi Valkeinen4f765022010-01-18 16:27:52 +0200307static bool dsi_bus_is_locked(void)
308{
Tomi Valkeinenb9eb5d72010-01-11 16:33:56 +0200309 return dsi.bus_lock.count == 0;
Tomi Valkeinen4f765022010-01-18 16:27:52 +0200310}
311
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200312static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
313 int value)
314{
315 int t = 100000;
316
317 while (REG_GET(idx, bitnum, bitnum) != value) {
318 if (--t == 0)
319 return !value;
320 }
321
322 return value;
323}
324
325#ifdef DEBUG
326static void dsi_perf_mark_setup(void)
327{
328 dsi.perf_setup_time = ktime_get();
329}
330
331static void dsi_perf_mark_start(void)
332{
333 dsi.perf_start_time = ktime_get();
334}
335
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200336static void dsi_perf_show(const char *name)
337{
338 ktime_t t, setup_time, trans_time;
339 u32 total_bytes;
340 u32 setup_us, trans_us, total_us;
341
342 if (!dsi_perf)
343 return;
344
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200345 t = ktime_get();
346
347 setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
348 setup_us = (u32)ktime_to_us(setup_time);
349 if (setup_us == 0)
350 setup_us = 1;
351
352 trans_time = ktime_sub(t, dsi.perf_start_time);
353 trans_us = (u32)ktime_to_us(trans_time);
354 if (trans_us == 0)
355 trans_us = 1;
356
357 total_us = setup_us + trans_us;
358
Tomi Valkeinen18946f62010-01-12 14:16:41 +0200359 total_bytes = dsi.update_region.w *
360 dsi.update_region.h *
361 dsi.update_region.device->ctrl.pixel_size / 8;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200362
Tomi Valkeinen1bbb2752010-01-11 16:41:10 +0200363 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
364 "%u bytes, %u kbytes/sec\n",
365 name,
366 setup_us,
367 trans_us,
368 total_us,
369 1000*1000 / total_us,
370 total_bytes,
371 total_bytes * 1000 / total_us);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200372}
373#else
374#define dsi_perf_mark_setup()
375#define dsi_perf_mark_start()
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200376#define dsi_perf_show(x)
377#endif
378
379static void print_irq_status(u32 status)
380{
381#ifndef VERBOSE_IRQ
382 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
383 return;
384#endif
385 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
386
387#define PIS(x) \
388 if (status & DSI_IRQ_##x) \
389 printk(#x " ");
390#ifdef VERBOSE_IRQ
391 PIS(VC0);
392 PIS(VC1);
393 PIS(VC2);
394 PIS(VC3);
395#endif
396 PIS(WAKEUP);
397 PIS(RESYNC);
398 PIS(PLL_LOCK);
399 PIS(PLL_UNLOCK);
400 PIS(PLL_RECALL);
401 PIS(COMPLEXIO_ERR);
402 PIS(HS_TX_TIMEOUT);
403 PIS(LP_RX_TIMEOUT);
404 PIS(TE_TRIGGER);
405 PIS(ACK_TRIGGER);
406 PIS(SYNC_LOST);
407 PIS(LDO_POWER_GOOD);
408 PIS(TA_TIMEOUT);
409#undef PIS
410
411 printk("\n");
412}
413
414static void print_irq_status_vc(int channel, u32 status)
415{
416#ifndef VERBOSE_IRQ
417 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
418 return;
419#endif
420 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
421
422#define PIS(x) \
423 if (status & DSI_VC_IRQ_##x) \
424 printk(#x " ");
425 PIS(CS);
426 PIS(ECC_CORR);
427#ifdef VERBOSE_IRQ
428 PIS(PACKET_SENT);
429#endif
430 PIS(FIFO_TX_OVF);
431 PIS(FIFO_RX_OVF);
432 PIS(BTA);
433 PIS(ECC_NO_CORR);
434 PIS(FIFO_TX_UDF);
435 PIS(PP_BUSY_CHANGE);
436#undef PIS
437 printk("\n");
438}
439
440static void print_irq_status_cio(u32 status)
441{
442 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
443
444#define PIS(x) \
445 if (status & DSI_CIO_IRQ_##x) \
446 printk(#x " ");
447 PIS(ERRSYNCESC1);
448 PIS(ERRSYNCESC2);
449 PIS(ERRSYNCESC3);
450 PIS(ERRESC1);
451 PIS(ERRESC2);
452 PIS(ERRESC3);
453 PIS(ERRCONTROL1);
454 PIS(ERRCONTROL2);
455 PIS(ERRCONTROL3);
456 PIS(STATEULPS1);
457 PIS(STATEULPS2);
458 PIS(STATEULPS3);
459 PIS(ERRCONTENTIONLP0_1);
460 PIS(ERRCONTENTIONLP1_1);
461 PIS(ERRCONTENTIONLP0_2);
462 PIS(ERRCONTENTIONLP1_2);
463 PIS(ERRCONTENTIONLP0_3);
464 PIS(ERRCONTENTIONLP1_3);
465 PIS(ULPSACTIVENOT_ALL0);
466 PIS(ULPSACTIVENOT_ALL1);
467#undef PIS
468
469 printk("\n");
470}
471
472static int debug_irq;
473
474/* called from dss */
475void dsi_irq_handler(void)
476{
477 u32 irqstatus, vcstatus, ciostatus;
478 int i;
479
480 irqstatus = dsi_read_reg(DSI_IRQSTATUS);
481
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200482#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
483 spin_lock(&dsi.irq_stats_lock);
484 dsi.irq_stats.irq_count++;
485 dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs);
486#endif
487
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200488 if (irqstatus & DSI_IRQ_ERROR_MASK) {
489 DSSERR("DSI error, irqstatus %x\n", irqstatus);
490 print_irq_status(irqstatus);
491 spin_lock(&dsi.errors_lock);
492 dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK;
493 spin_unlock(&dsi.errors_lock);
494 } else if (debug_irq) {
495 print_irq_status(irqstatus);
496 }
497
498#ifdef DSI_CATCH_MISSING_TE
499 if (irqstatus & DSI_IRQ_TE_TRIGGER)
500 del_timer(&dsi.te_timer);
501#endif
502
503 for (i = 0; i < 4; ++i) {
504 if ((irqstatus & (1<<i)) == 0)
505 continue;
506
507 vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
508
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200509#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
510 dss_collect_irq_stats(vcstatus, dsi.irq_stats.vc_irqs[i]);
511#endif
512
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200513 if (vcstatus & DSI_VC_IRQ_BTA)
514 complete(&dsi.bta_completion);
515
516 if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
517 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
518 i, vcstatus);
519 print_irq_status_vc(i, vcstatus);
520 } else if (debug_irq) {
521 print_irq_status_vc(i, vcstatus);
522 }
523
524 dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
525 /* flush posted write */
526 dsi_read_reg(DSI_VC_IRQSTATUS(i));
527 }
528
529 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
530 ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
531
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200532#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
533 dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs);
534#endif
535
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200536 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
537 /* flush posted write */
538 dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
539
540 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
541 print_irq_status_cio(ciostatus);
542 }
543
544 dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
545 /* flush posted write */
546 dsi_read_reg(DSI_IRQSTATUS);
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200547
548#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
549 spin_unlock(&dsi.irq_stats_lock);
550#endif
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200551}
552
553
554static void _dsi_initialize_irq(void)
555{
556 u32 l;
557 int i;
558
559 /* disable all interrupts */
560 dsi_write_reg(DSI_IRQENABLE, 0);
561 for (i = 0; i < 4; ++i)
562 dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
563 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
564
565 /* clear interrupt status */
566 l = dsi_read_reg(DSI_IRQSTATUS);
567 dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
568
569 for (i = 0; i < 4; ++i) {
570 l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
571 dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
572 }
573
574 l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
575 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
576
577 /* enable error irqs */
578 l = DSI_IRQ_ERROR_MASK;
579#ifdef DSI_CATCH_MISSING_TE
580 l |= DSI_IRQ_TE_TRIGGER;
581#endif
582 dsi_write_reg(DSI_IRQENABLE, l);
583
584 l = DSI_VC_IRQ_ERROR_MASK;
585 for (i = 0; i < 4; ++i)
586 dsi_write_reg(DSI_VC_IRQENABLE(i), l);
587
588 /* XXX zonda responds incorrectly, causing control error:
589 Exit from LP-ESC mode to LP11 uses wrong transition states on the
590 data lines LP0 and LN0. */
591 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE,
592 -1 & (~DSI_CIO_IRQ_ERRCONTROL2));
593}
594
595static u32 dsi_get_errors(void)
596{
597 unsigned long flags;
598 u32 e;
599 spin_lock_irqsave(&dsi.errors_lock, flags);
600 e = dsi.errors;
601 dsi.errors = 0;
602 spin_unlock_irqrestore(&dsi.errors_lock, flags);
603 return e;
604}
605
606static void dsi_vc_enable_bta_irq(int channel)
607{
608 u32 l;
609
610 dsi_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA);
611
612 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
613 l |= DSI_VC_IRQ_BTA;
614 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
615}
616
617static void dsi_vc_disable_bta_irq(int channel)
618{
619 u32 l;
620
621 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
622 l &= ~DSI_VC_IRQ_BTA;
623 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
624}
625
626/* DSI func clock. this could also be DSI2_PLL_FCLK */
627static inline void enable_clocks(bool enable)
628{
629 if (enable)
630 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
631 else
632 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
633}
634
635/* source clock for DSI PLL. this could also be PCLKFREE */
636static inline void dsi_enable_pll_clock(bool enable)
637{
638 if (enable)
639 dss_clk_enable(DSS_CLK_FCK2);
640 else
641 dss_clk_disable(DSS_CLK_FCK2);
642
643 if (enable && dsi.pll_locked) {
644 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
645 DSSERR("cannot lock PLL when enabling clocks\n");
646 }
647}
648
649#ifdef DEBUG
650static void _dsi_print_reset_status(void)
651{
652 u32 l;
653
654 if (!dss_debug)
655 return;
656
657 /* A dummy read using the SCP interface to any DSIPHY register is
658 * required after DSIPHY reset to complete the reset of the DSI complex
659 * I/O. */
660 l = dsi_read_reg(DSI_DSIPHY_CFG5);
661
662 printk(KERN_DEBUG "DSI resets: ");
663
664 l = dsi_read_reg(DSI_PLL_STATUS);
665 printk("PLL (%d) ", FLD_GET(l, 0, 0));
666
667 l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
668 printk("CIO (%d) ", FLD_GET(l, 29, 29));
669
670 l = dsi_read_reg(DSI_DSIPHY_CFG5);
671 printk("PHY (%x, %d, %d, %d)\n",
672 FLD_GET(l, 28, 26),
673 FLD_GET(l, 29, 29),
674 FLD_GET(l, 30, 30),
675 FLD_GET(l, 31, 31));
676}
677#else
678#define _dsi_print_reset_status()
679#endif
680
681static inline int dsi_if_enable(bool enable)
682{
683 DSSDBG("dsi_if_enable(%d)\n", enable);
684
685 enable = enable ? 1 : 0;
686 REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
687
688 if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
689 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
690 return -EIO;
691 }
692
693 return 0;
694}
695
696unsigned long dsi_get_dsi1_pll_rate(void)
697{
698 return dsi.current_cinfo.dsi1_pll_fclk;
699}
700
701static unsigned long dsi_get_dsi2_pll_rate(void)
702{
703 return dsi.current_cinfo.dsi2_pll_fclk;
704}
705
706static unsigned long dsi_get_txbyteclkhs(void)
707{
708 return dsi.current_cinfo.clkin4ddr / 16;
709}
710
711static unsigned long dsi_fclk_rate(void)
712{
713 unsigned long r;
714
Tomi Valkeinen63cf28a2010-02-23 17:40:00 +0200715 if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) {
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200716 /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
717 r = dss_clk_get_rate(DSS_CLK_FCK1);
718 } else {
719 /* DSI FCLK source is DSI2_PLL_FCLK */
720 r = dsi_get_dsi2_pll_rate();
721 }
722
723 return r;
724}
725
726static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
727{
728 unsigned long dsi_fclk;
729 unsigned lp_clk_div;
730 unsigned long lp_clk;
731
732 lp_clk_div = dssdev->phy.dsi.div.lp_clk_div;
733
734 if (lp_clk_div == 0 || lp_clk_div > LP_DIV_MAX)
735 return -EINVAL;
736
737 dsi_fclk = dsi_fclk_rate();
738
739 lp_clk = dsi_fclk / 2 / lp_clk_div;
740
741 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
742 dsi.current_cinfo.lp_clk = lp_clk;
743 dsi.current_cinfo.lp_clk_div = lp_clk_div;
744
745 REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */
746
747 REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0,
748 21, 21); /* LP_RX_SYNCHRO_ENABLE */
749
750 return 0;
751}
752
753
754enum dsi_pll_power_state {
755 DSI_PLL_POWER_OFF = 0x0,
756 DSI_PLL_POWER_ON_HSCLK = 0x1,
757 DSI_PLL_POWER_ON_ALL = 0x2,
758 DSI_PLL_POWER_ON_DIV = 0x3,
759};
760
761static int dsi_pll_power(enum dsi_pll_power_state state)
762{
763 int t = 0;
764
765 REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
766
767 /* PLL_PWR_STATUS */
768 while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
Tomi Valkeinen24be78b2010-01-07 14:19:48 +0200769 if (++t > 1000) {
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200770 DSSERR("Failed to set DSI PLL power mode to %d\n",
771 state);
772 return -ENODEV;
773 }
Tomi Valkeinen24be78b2010-01-07 14:19:48 +0200774 udelay(1);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +0200775 }
776
777 return 0;
778}
779
780/* calculate clock rates using dividers in cinfo */
781static int dsi_calc_clock_rates(struct dsi_clock_info *cinfo)
782{
783 if (cinfo->regn == 0 || cinfo->regn > REGN_MAX)
784 return -EINVAL;
785
786 if (cinfo->regm == 0 || cinfo->regm > REGM_MAX)
787 return -EINVAL;
788
789 if (cinfo->regm3 > REGM3_MAX)
790 return -EINVAL;
791
792 if (cinfo->regm4 > REGM4_MAX)
793 return -EINVAL;
794
795 if (cinfo->use_dss2_fck) {
796 cinfo->clkin = dss_clk_get_rate(DSS_CLK_FCK2);
797 /* XXX it is unclear if highfreq should be used
798 * with DSS2_FCK source also */
799 cinfo->highfreq = 0;
800 } else {
801 cinfo->clkin = dispc_pclk_rate();
802
803 if (cinfo->clkin < 32000000)
804 cinfo->highfreq = 0;
805 else
806 cinfo->highfreq = 1;
807 }
808
809 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
810
811 if (cinfo->fint > FINT_MAX || cinfo->fint < FINT_MIN)
812 return -EINVAL;
813
814 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
815
816 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
817 return -EINVAL;
818
819 if (cinfo->regm3 > 0)
820 cinfo->dsi1_pll_fclk = cinfo->clkin4ddr / cinfo->regm3;
821 else
822 cinfo->dsi1_pll_fclk = 0;
823
824 if (cinfo->regm4 > 0)
825 cinfo->dsi2_pll_fclk = cinfo->clkin4ddr / cinfo->regm4;
826 else
827 cinfo->dsi2_pll_fclk = 0;
828
829 return 0;
830}
831
832int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
833 struct dsi_clock_info *dsi_cinfo,
834 struct dispc_clock_info *dispc_cinfo)
835{
836 struct dsi_clock_info cur, best;
837 struct dispc_clock_info best_dispc;
838 int min_fck_per_pck;
839 int match = 0;
840 unsigned long dss_clk_fck2;
841
842 dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2);
843
844 if (req_pck == dsi.cache_req_pck &&
845 dsi.cache_cinfo.clkin == dss_clk_fck2) {
846 DSSDBG("DSI clock info found from cache\n");
847 *dsi_cinfo = dsi.cache_cinfo;
848 dispc_find_clk_divs(is_tft, req_pck, dsi_cinfo->dsi1_pll_fclk,
849 dispc_cinfo);
850 return 0;
851 }
852
853 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
854
855 if (min_fck_per_pck &&
856 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
857 DSSERR("Requested pixel clock not possible with the current "
858 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
859 "the constraint off.\n");
860 min_fck_per_pck = 0;
861 }
862
863 DSSDBG("dsi_pll_calc\n");
864
865retry:
866 memset(&best, 0, sizeof(best));
867 memset(&best_dispc, 0, sizeof(best_dispc));
868
869 memset(&cur, 0, sizeof(cur));
870 cur.clkin = dss_clk_fck2;
871 cur.use_dss2_fck = 1;
872 cur.highfreq = 0;
873
874 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
875 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
876 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
877 for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
878 if (cur.highfreq == 0)
879 cur.fint = cur.clkin / cur.regn;
880 else
881 cur.fint = cur.clkin / (2 * cur.regn);
882
883 if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
884 continue;
885
886 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
887 for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
888 unsigned long a, b;
889
890 a = 2 * cur.regm * (cur.clkin/1000);
891 b = cur.regn * (cur.highfreq + 1);
892 cur.clkin4ddr = a / b * 1000;
893
894 if (cur.clkin4ddr > 1800 * 1000 * 1000)
895 break;
896
897 /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
898 for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
899 ++cur.regm3) {
900 struct dispc_clock_info cur_dispc;
901 cur.dsi1_pll_fclk = cur.clkin4ddr / cur.regm3;
902
903 /* this will narrow down the search a bit,
904 * but still give pixclocks below what was
905 * requested */
906 if (cur.dsi1_pll_fclk < req_pck)
907 break;
908
909 if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)
910 continue;
911
912 if (min_fck_per_pck &&
913 cur.dsi1_pll_fclk <
914 req_pck * min_fck_per_pck)
915 continue;
916
917 match = 1;
918
919 dispc_find_clk_divs(is_tft, req_pck,
920 cur.dsi1_pll_fclk,
921 &cur_dispc);
922
923 if (abs(cur_dispc.pck - req_pck) <
924 abs(best_dispc.pck - req_pck)) {
925 best = cur;
926 best_dispc = cur_dispc;
927
928 if (cur_dispc.pck == req_pck)
929 goto found;
930 }
931 }
932 }
933 }
934found:
935 if (!match) {
936 if (min_fck_per_pck) {
937 DSSERR("Could not find suitable clock settings.\n"
938 "Turning FCK/PCK constraint off and"
939 "trying again.\n");
940 min_fck_per_pck = 0;
941 goto retry;
942 }
943
944 DSSERR("Could not find suitable clock settings.\n");
945
946 return -EINVAL;
947 }
948
949 /* DSI2_PLL_FCLK (regm4) is not used */
950 best.regm4 = 0;
951 best.dsi2_pll_fclk = 0;
952
953 if (dsi_cinfo)
954 *dsi_cinfo = best;
955 if (dispc_cinfo)
956 *dispc_cinfo = best_dispc;
957
958 dsi.cache_req_pck = req_pck;
959 dsi.cache_clk_freq = 0;
960 dsi.cache_cinfo = best;
961
962 return 0;
963}
964
965int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
966{
967 int r = 0;
968 u32 l;
969 int f;
970
971 DSSDBGF();
972
973 dsi.current_cinfo.fint = cinfo->fint;
974 dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr;
975 dsi.current_cinfo.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
976 dsi.current_cinfo.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
977
978 dsi.current_cinfo.regn = cinfo->regn;
979 dsi.current_cinfo.regm = cinfo->regm;
980 dsi.current_cinfo.regm3 = cinfo->regm3;
981 dsi.current_cinfo.regm4 = cinfo->regm4;
982
983 DSSDBG("DSI Fint %ld\n", cinfo->fint);
984
985 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
986 cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
987 cinfo->clkin,
988 cinfo->highfreq);
989
990 /* DSIPHY == CLKIN4DDR */
991 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
992 cinfo->regm,
993 cinfo->regn,
994 cinfo->clkin,
995 cinfo->highfreq + 1,
996 cinfo->clkin4ddr);
997
998 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
999 cinfo->clkin4ddr / 1000 / 1000 / 2);
1000
1001 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1002
1003 DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
1004 cinfo->regm3, cinfo->dsi1_pll_fclk);
1005 DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
1006 cinfo->regm4, cinfo->dsi2_pll_fclk);
1007
1008 REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
1009
1010 l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
1011 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1012 l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */
1013 l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */
1014 l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0,
1015 22, 19); /* DSI_CLOCK_DIV */
1016 l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0,
1017 26, 23); /* DSIPROTO_CLOCK_DIV */
1018 dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
1019
1020 BUG_ON(cinfo->fint < 750000 || cinfo->fint > 2100000);
1021 if (cinfo->fint < 1000000)
1022 f = 0x3;
1023 else if (cinfo->fint < 1250000)
1024 f = 0x4;
1025 else if (cinfo->fint < 1500000)
1026 f = 0x5;
1027 else if (cinfo->fint < 1750000)
1028 f = 0x6;
1029 else
1030 f = 0x7;
1031
1032 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1033 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1034 l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1,
1035 11, 11); /* DSI_PLL_CLKSEL */
1036 l = FLD_MOD(l, cinfo->highfreq,
1037 12, 12); /* DSI_PLL_HIGHFREQ */
1038 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1039 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1040 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1041 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1042
1043 REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1044
1045 if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
1046 DSSERR("dsi pll go bit not going down.\n");
1047 r = -EIO;
1048 goto err;
1049 }
1050
1051 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
1052 DSSERR("cannot lock PLL\n");
1053 r = -EIO;
1054 goto err;
1055 }
1056
1057 dsi.pll_locked = 1;
1058
1059 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1060 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1061 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1062 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1063 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1064 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1065 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1066 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1067 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1068 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1069 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1070 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1071 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1072 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1073 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1074 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1075
1076 DSSDBG("PLL config done\n");
1077err:
1078 return r;
1079}
1080
1081int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
1082 bool enable_hsdiv)
1083{
1084 int r = 0;
1085 enum dsi_pll_power_state pwstate;
1086
1087 DSSDBG("PLL init\n");
1088
1089 enable_clocks(1);
1090 dsi_enable_pll_clock(1);
1091
1092 r = regulator_enable(dsi.vdds_dsi_reg);
1093 if (r)
1094 goto err0;
1095
1096 /* XXX PLL does not come out of reset without this... */
1097 dispc_pck_free_enable(1);
1098
1099 if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
1100 DSSERR("PLL not coming out of reset.\n");
1101 r = -ENODEV;
1102 goto err1;
1103 }
1104
1105 /* XXX ... but if left on, we get problems when planes do not
1106 * fill the whole display. No idea about this */
1107 dispc_pck_free_enable(0);
1108
1109 if (enable_hsclk && enable_hsdiv)
1110 pwstate = DSI_PLL_POWER_ON_ALL;
1111 else if (enable_hsclk)
1112 pwstate = DSI_PLL_POWER_ON_HSCLK;
1113 else if (enable_hsdiv)
1114 pwstate = DSI_PLL_POWER_ON_DIV;
1115 else
1116 pwstate = DSI_PLL_POWER_OFF;
1117
1118 r = dsi_pll_power(pwstate);
1119
1120 if (r)
1121 goto err1;
1122
1123 DSSDBG("PLL init done\n");
1124
1125 return 0;
1126err1:
1127 regulator_disable(dsi.vdds_dsi_reg);
1128err0:
1129 enable_clocks(0);
1130 dsi_enable_pll_clock(0);
1131 return r;
1132}
1133
1134void dsi_pll_uninit(void)
1135{
1136 enable_clocks(0);
1137 dsi_enable_pll_clock(0);
1138
1139 dsi.pll_locked = 0;
1140 dsi_pll_power(DSI_PLL_POWER_OFF);
1141 regulator_disable(dsi.vdds_dsi_reg);
1142 DSSDBG("PLL uninit done\n");
1143}
1144
1145void dsi_dump_clocks(struct seq_file *s)
1146{
1147 int clksel;
1148 struct dsi_clock_info *cinfo = &dsi.current_cinfo;
1149
1150 enable_clocks(1);
1151
1152 clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
1153
1154 seq_printf(s, "- DSI PLL -\n");
1155
1156 seq_printf(s, "dsi pll source = %s\n",
1157 clksel == 0 ?
1158 "dss2_alwon_fclk" : "pclkfree");
1159
1160 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1161
1162 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1163 cinfo->clkin4ddr, cinfo->regm);
1164
1165 seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n",
1166 cinfo->dsi1_pll_fclk,
1167 cinfo->regm3,
Tomi Valkeinen63cf28a2010-02-23 17:40:00 +02001168 dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
1169 "off" : "on");
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001170
1171 seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n",
1172 cinfo->dsi2_pll_fclk,
1173 cinfo->regm4,
Tomi Valkeinen63cf28a2010-02-23 17:40:00 +02001174 dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
1175 "off" : "on");
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001176
1177 seq_printf(s, "- DSI -\n");
1178
1179 seq_printf(s, "dsi fclk source = %s\n",
Tomi Valkeinen63cf28a2010-02-23 17:40:00 +02001180 dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001181 "dss1_alwon_fclk" : "dsi2_pll_fclk");
1182
1183 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
1184
1185 seq_printf(s, "DDR_CLK\t\t%lu\n",
1186 cinfo->clkin4ddr / 4);
1187
1188 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs());
1189
1190 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1191
1192 seq_printf(s, "VP_CLK\t\t%lu\n"
1193 "VP_PCLK\t\t%lu\n",
1194 dispc_lclk_rate(),
1195 dispc_pclk_rate());
1196
1197 enable_clocks(0);
1198}
1199
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +02001200#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1201void dsi_dump_irqs(struct seq_file *s)
1202{
1203 unsigned long flags;
1204 struct dsi_irq_stats stats;
1205
1206 spin_lock_irqsave(&dsi.irq_stats_lock, flags);
1207
1208 stats = dsi.irq_stats;
1209 memset(&dsi.irq_stats, 0, sizeof(dsi.irq_stats));
1210 dsi.irq_stats.last_reset = jiffies;
1211
1212 spin_unlock_irqrestore(&dsi.irq_stats_lock, flags);
1213
1214 seq_printf(s, "period %u ms\n",
1215 jiffies_to_msecs(jiffies - stats.last_reset));
1216
1217 seq_printf(s, "irqs %d\n", stats.irq_count);
1218#define PIS(x) \
1219 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1220
1221 seq_printf(s, "-- DSI interrupts --\n");
1222 PIS(VC0);
1223 PIS(VC1);
1224 PIS(VC2);
1225 PIS(VC3);
1226 PIS(WAKEUP);
1227 PIS(RESYNC);
1228 PIS(PLL_LOCK);
1229 PIS(PLL_UNLOCK);
1230 PIS(PLL_RECALL);
1231 PIS(COMPLEXIO_ERR);
1232 PIS(HS_TX_TIMEOUT);
1233 PIS(LP_RX_TIMEOUT);
1234 PIS(TE_TRIGGER);
1235 PIS(ACK_TRIGGER);
1236 PIS(SYNC_LOST);
1237 PIS(LDO_POWER_GOOD);
1238 PIS(TA_TIMEOUT);
1239#undef PIS
1240
1241#define PIS(x) \
1242 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1243 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1244 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1245 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1246 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1247
1248 seq_printf(s, "-- VC interrupts --\n");
1249 PIS(CS);
1250 PIS(ECC_CORR);
1251 PIS(PACKET_SENT);
1252 PIS(FIFO_TX_OVF);
1253 PIS(FIFO_RX_OVF);
1254 PIS(BTA);
1255 PIS(ECC_NO_CORR);
1256 PIS(FIFO_TX_UDF);
1257 PIS(PP_BUSY_CHANGE);
1258#undef PIS
1259
1260#define PIS(x) \
1261 seq_printf(s, "%-20s %10d\n", #x, \
1262 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1263
1264 seq_printf(s, "-- CIO interrupts --\n");
1265 PIS(ERRSYNCESC1);
1266 PIS(ERRSYNCESC2);
1267 PIS(ERRSYNCESC3);
1268 PIS(ERRESC1);
1269 PIS(ERRESC2);
1270 PIS(ERRESC3);
1271 PIS(ERRCONTROL1);
1272 PIS(ERRCONTROL2);
1273 PIS(ERRCONTROL3);
1274 PIS(STATEULPS1);
1275 PIS(STATEULPS2);
1276 PIS(STATEULPS3);
1277 PIS(ERRCONTENTIONLP0_1);
1278 PIS(ERRCONTENTIONLP1_1);
1279 PIS(ERRCONTENTIONLP0_2);
1280 PIS(ERRCONTENTIONLP1_2);
1281 PIS(ERRCONTENTIONLP0_3);
1282 PIS(ERRCONTENTIONLP1_3);
1283 PIS(ULPSACTIVENOT_ALL0);
1284 PIS(ULPSACTIVENOT_ALL1);
1285#undef PIS
1286}
1287#endif
1288
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001289void dsi_dump_regs(struct seq_file *s)
1290{
1291#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
1292
1293 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
1294
1295 DUMPREG(DSI_REVISION);
1296 DUMPREG(DSI_SYSCONFIG);
1297 DUMPREG(DSI_SYSSTATUS);
1298 DUMPREG(DSI_IRQSTATUS);
1299 DUMPREG(DSI_IRQENABLE);
1300 DUMPREG(DSI_CTRL);
1301 DUMPREG(DSI_COMPLEXIO_CFG1);
1302 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1303 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1304 DUMPREG(DSI_CLK_CTRL);
1305 DUMPREG(DSI_TIMING1);
1306 DUMPREG(DSI_TIMING2);
1307 DUMPREG(DSI_VM_TIMING1);
1308 DUMPREG(DSI_VM_TIMING2);
1309 DUMPREG(DSI_VM_TIMING3);
1310 DUMPREG(DSI_CLK_TIMING);
1311 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1312 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1313 DUMPREG(DSI_COMPLEXIO_CFG2);
1314 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1315 DUMPREG(DSI_VM_TIMING4);
1316 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1317 DUMPREG(DSI_VM_TIMING5);
1318 DUMPREG(DSI_VM_TIMING6);
1319 DUMPREG(DSI_VM_TIMING7);
1320 DUMPREG(DSI_STOPCLK_TIMING);
1321
1322 DUMPREG(DSI_VC_CTRL(0));
1323 DUMPREG(DSI_VC_TE(0));
1324 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1325 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1326 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1327 DUMPREG(DSI_VC_IRQSTATUS(0));
1328 DUMPREG(DSI_VC_IRQENABLE(0));
1329
1330 DUMPREG(DSI_VC_CTRL(1));
1331 DUMPREG(DSI_VC_TE(1));
1332 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1333 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1334 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1335 DUMPREG(DSI_VC_IRQSTATUS(1));
1336 DUMPREG(DSI_VC_IRQENABLE(1));
1337
1338 DUMPREG(DSI_VC_CTRL(2));
1339 DUMPREG(DSI_VC_TE(2));
1340 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1341 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1342 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1343 DUMPREG(DSI_VC_IRQSTATUS(2));
1344 DUMPREG(DSI_VC_IRQENABLE(2));
1345
1346 DUMPREG(DSI_VC_CTRL(3));
1347 DUMPREG(DSI_VC_TE(3));
1348 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1349 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1350 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1351 DUMPREG(DSI_VC_IRQSTATUS(3));
1352 DUMPREG(DSI_VC_IRQENABLE(3));
1353
1354 DUMPREG(DSI_DSIPHY_CFG0);
1355 DUMPREG(DSI_DSIPHY_CFG1);
1356 DUMPREG(DSI_DSIPHY_CFG2);
1357 DUMPREG(DSI_DSIPHY_CFG5);
1358
1359 DUMPREG(DSI_PLL_CONTROL);
1360 DUMPREG(DSI_PLL_STATUS);
1361 DUMPREG(DSI_PLL_GO);
1362 DUMPREG(DSI_PLL_CONFIGURATION1);
1363 DUMPREG(DSI_PLL_CONFIGURATION2);
1364
1365 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
1366#undef DUMPREG
1367}
1368
1369enum dsi_complexio_power_state {
1370 DSI_COMPLEXIO_POWER_OFF = 0x0,
1371 DSI_COMPLEXIO_POWER_ON = 0x1,
1372 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1373};
1374
1375static int dsi_complexio_power(enum dsi_complexio_power_state state)
1376{
1377 int t = 0;
1378
1379 /* PWR_CMD */
1380 REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
1381
1382 /* PWR_STATUS */
1383 while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
Tomi Valkeinen24be78b2010-01-07 14:19:48 +02001384 if (++t > 1000) {
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001385 DSSERR("failed to set complexio power state to "
1386 "%d\n", state);
1387 return -ENODEV;
1388 }
Tomi Valkeinen24be78b2010-01-07 14:19:48 +02001389 udelay(1);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001390 }
1391
1392 return 0;
1393}
1394
1395static void dsi_complexio_config(struct omap_dss_device *dssdev)
1396{
1397 u32 r;
1398
1399 int clk_lane = dssdev->phy.dsi.clk_lane;
1400 int data1_lane = dssdev->phy.dsi.data1_lane;
1401 int data2_lane = dssdev->phy.dsi.data2_lane;
1402 int clk_pol = dssdev->phy.dsi.clk_pol;
1403 int data1_pol = dssdev->phy.dsi.data1_pol;
1404 int data2_pol = dssdev->phy.dsi.data2_pol;
1405
1406 r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
1407 r = FLD_MOD(r, clk_lane, 2, 0);
1408 r = FLD_MOD(r, clk_pol, 3, 3);
1409 r = FLD_MOD(r, data1_lane, 6, 4);
1410 r = FLD_MOD(r, data1_pol, 7, 7);
1411 r = FLD_MOD(r, data2_lane, 10, 8);
1412 r = FLD_MOD(r, data2_pol, 11, 11);
1413 dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
1414
1415 /* The configuration of the DSI complex I/O (number of data lanes,
1416 position, differential order) should not be changed while
1417 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
1418 the hardware to take into account a new configuration of the complex
1419 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
1420 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
1421 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
1422 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
1423 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
1424 DSI complex I/O configuration is unknown. */
1425
1426 /*
1427 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1428 REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
1429 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
1430 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1431 */
1432}
1433
1434static inline unsigned ns2ddr(unsigned ns)
1435{
1436 /* convert time in ns to ddr ticks, rounding up */
1437 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1438 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1439}
1440
1441static inline unsigned ddr2ns(unsigned ddr)
1442{
1443 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1444 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1445}
1446
1447static void dsi_complexio_timings(void)
1448{
1449 u32 r;
1450 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1451 u32 tlpx_half, tclk_trail, tclk_zero;
1452 u32 tclk_prepare;
1453
1454 /* calculate timings */
1455
1456 /* 1 * DDR_CLK = 2 * UI */
1457
1458 /* min 40ns + 4*UI max 85ns + 6*UI */
1459 ths_prepare = ns2ddr(70) + 2;
1460
1461 /* min 145ns + 10*UI */
1462 ths_prepare_ths_zero = ns2ddr(175) + 2;
1463
1464 /* min max(8*UI, 60ns+4*UI) */
1465 ths_trail = ns2ddr(60) + 5;
1466
1467 /* min 100ns */
1468 ths_exit = ns2ddr(145);
1469
1470 /* tlpx min 50n */
1471 tlpx_half = ns2ddr(25);
1472
1473 /* min 60ns */
1474 tclk_trail = ns2ddr(60) + 2;
1475
1476 /* min 38ns, max 95ns */
1477 tclk_prepare = ns2ddr(65);
1478
1479 /* min tclk-prepare + tclk-zero = 300ns */
1480 tclk_zero = ns2ddr(260);
1481
1482 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1483 ths_prepare, ddr2ns(ths_prepare),
1484 ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
1485 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1486 ths_trail, ddr2ns(ths_trail),
1487 ths_exit, ddr2ns(ths_exit));
1488
1489 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1490 "tclk_zero %u (%uns)\n",
1491 tlpx_half, ddr2ns(tlpx_half),
1492 tclk_trail, ddr2ns(tclk_trail),
1493 tclk_zero, ddr2ns(tclk_zero));
1494 DSSDBG("tclk_prepare %u (%uns)\n",
1495 tclk_prepare, ddr2ns(tclk_prepare));
1496
1497 /* program timings */
1498
1499 r = dsi_read_reg(DSI_DSIPHY_CFG0);
1500 r = FLD_MOD(r, ths_prepare, 31, 24);
1501 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1502 r = FLD_MOD(r, ths_trail, 15, 8);
1503 r = FLD_MOD(r, ths_exit, 7, 0);
1504 dsi_write_reg(DSI_DSIPHY_CFG0, r);
1505
1506 r = dsi_read_reg(DSI_DSIPHY_CFG1);
1507 r = FLD_MOD(r, tlpx_half, 22, 16);
1508 r = FLD_MOD(r, tclk_trail, 15, 8);
1509 r = FLD_MOD(r, tclk_zero, 7, 0);
1510 dsi_write_reg(DSI_DSIPHY_CFG1, r);
1511
1512 r = dsi_read_reg(DSI_DSIPHY_CFG2);
1513 r = FLD_MOD(r, tclk_prepare, 7, 0);
1514 dsi_write_reg(DSI_DSIPHY_CFG2, r);
1515}
1516
1517
1518static int dsi_complexio_init(struct omap_dss_device *dssdev)
1519{
1520 int r = 0;
1521
1522 DSSDBG("dsi_complexio_init\n");
1523
1524 /* CIO_CLK_ICG, enable L3 clk to CIO */
1525 REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
1526
1527 /* A dummy read using the SCP interface to any DSIPHY register is
1528 * required after DSIPHY reset to complete the reset of the DSI complex
1529 * I/O. */
1530 dsi_read_reg(DSI_DSIPHY_CFG5);
1531
1532 if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
1533 DSSERR("ComplexIO PHY not coming out of reset.\n");
1534 r = -ENODEV;
1535 goto err;
1536 }
1537
1538 dsi_complexio_config(dssdev);
1539
1540 r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
1541
1542 if (r)
1543 goto err;
1544
1545 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
1546 DSSERR("ComplexIO not coming out of reset.\n");
1547 r = -ENODEV;
1548 goto err;
1549 }
1550
1551 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
1552 DSSERR("ComplexIO LDO power down.\n");
1553 r = -ENODEV;
1554 goto err;
1555 }
1556
1557 dsi_complexio_timings();
1558
1559 /*
1560 The configuration of the DSI complex I/O (number of data lanes,
1561 position, differential order) should not be changed while
1562 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
1563 hardware to recognize a new configuration of the complex I/O (done
1564 in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
1565 this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
1566 reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
1567 LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
1568 bit to 1. If the sequence is not followed, the DSi complex I/O
1569 configuration is undetermined.
1570 */
1571 dsi_if_enable(1);
1572 dsi_if_enable(0);
1573 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
1574 dsi_if_enable(1);
1575 dsi_if_enable(0);
1576
1577 DSSDBG("CIO init done\n");
1578err:
1579 return r;
1580}
1581
1582static void dsi_complexio_uninit(void)
1583{
1584 dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
1585}
1586
1587static int _dsi_wait_reset(void)
1588{
Tomi Valkeinen24be78b2010-01-07 14:19:48 +02001589 int t = 0;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001590
1591 while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
Tomi Valkeinen24be78b2010-01-07 14:19:48 +02001592 if (++t > 5) {
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001593 DSSERR("soft reset failed\n");
1594 return -ENODEV;
1595 }
1596 udelay(1);
1597 }
1598
1599 return 0;
1600}
1601
1602static int _dsi_reset(void)
1603{
1604 /* Soft reset */
1605 REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
1606 return _dsi_wait_reset();
1607}
1608
1609static void dsi_reset_tx_fifo(int channel)
1610{
1611 u32 mask;
1612 u32 l;
1613
1614 /* set fifosize of the channel to 0, then return the old size */
1615 l = dsi_read_reg(DSI_TX_FIFO_VC_SIZE);
1616
1617 mask = FLD_MASK((8 * channel) + 7, (8 * channel) + 4);
1618 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l & ~mask);
1619
1620 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l);
1621}
1622
1623static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
1624 enum fifo_size size3, enum fifo_size size4)
1625{
1626 u32 r = 0;
1627 int add = 0;
1628 int i;
1629
1630 dsi.vc[0].fifo_size = size1;
1631 dsi.vc[1].fifo_size = size2;
1632 dsi.vc[2].fifo_size = size3;
1633 dsi.vc[3].fifo_size = size4;
1634
1635 for (i = 0; i < 4; i++) {
1636 u8 v;
1637 int size = dsi.vc[i].fifo_size;
1638
1639 if (add + size > 4) {
1640 DSSERR("Illegal FIFO configuration\n");
1641 BUG();
1642 }
1643
1644 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1645 r |= v << (8 * i);
1646 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
1647 add += size;
1648 }
1649
1650 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
1651}
1652
1653static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
1654 enum fifo_size size3, enum fifo_size size4)
1655{
1656 u32 r = 0;
1657 int add = 0;
1658 int i;
1659
1660 dsi.vc[0].fifo_size = size1;
1661 dsi.vc[1].fifo_size = size2;
1662 dsi.vc[2].fifo_size = size3;
1663 dsi.vc[3].fifo_size = size4;
1664
1665 for (i = 0; i < 4; i++) {
1666 u8 v;
1667 int size = dsi.vc[i].fifo_size;
1668
1669 if (add + size > 4) {
1670 DSSERR("Illegal FIFO configuration\n");
1671 BUG();
1672 }
1673
1674 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1675 r |= v << (8 * i);
1676 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
1677 add += size;
1678 }
1679
1680 dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
1681}
1682
1683static int dsi_force_tx_stop_mode_io(void)
1684{
1685 u32 r;
1686
1687 r = dsi_read_reg(DSI_TIMING1);
1688 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
1689 dsi_write_reg(DSI_TIMING1, r);
1690
1691 if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
1692 DSSERR("TX_STOP bit not going down\n");
1693 return -EIO;
1694 }
1695
1696 return 0;
1697}
1698
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001699static int dsi_vc_enable(int channel, bool enable)
1700{
Tomi Valkeinen446f7bf2010-01-11 16:12:31 +02001701 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
1702 channel, enable);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001703
1704 enable = enable ? 1 : 0;
1705
1706 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
1707
1708 if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
1709 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
1710 return -EIO;
1711 }
1712
1713 return 0;
1714}
1715
1716static void dsi_vc_initial_config(int channel)
1717{
1718 u32 r;
1719
1720 DSSDBGF("%d", channel);
1721
1722 r = dsi_read_reg(DSI_VC_CTRL(channel));
1723
1724 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
1725 DSSERR("VC(%d) busy when trying to configure it!\n",
1726 channel);
1727
1728 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
1729 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
1730 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
1731 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
1732 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
1733 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
1734 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
1735
1736 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
1737 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
1738
1739 dsi_write_reg(DSI_VC_CTRL(channel), r);
1740
1741 dsi.vc[channel].mode = DSI_VC_MODE_L4;
1742}
1743
1744static void dsi_vc_config_l4(int channel)
1745{
1746 if (dsi.vc[channel].mode == DSI_VC_MODE_L4)
1747 return;
1748
1749 DSSDBGF("%d", channel);
1750
1751 dsi_vc_enable(channel, 0);
1752
1753 if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */
1754 DSSERR("vc(%d) busy when trying to config for L4\n", channel);
1755
1756 REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
1757
1758 dsi_vc_enable(channel, 1);
1759
1760 dsi.vc[channel].mode = DSI_VC_MODE_L4;
1761}
1762
1763static void dsi_vc_config_vp(int channel)
1764{
1765 if (dsi.vc[channel].mode == DSI_VC_MODE_VP)
1766 return;
1767
1768 DSSDBGF("%d", channel);
1769
1770 dsi_vc_enable(channel, 0);
1771
1772 if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */
1773 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
1774
1775 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
1776
1777 dsi_vc_enable(channel, 1);
1778
1779 dsi.vc[channel].mode = DSI_VC_MODE_VP;
1780}
1781
1782
Tomi Valkeinen61140c92010-01-12 16:00:30 +02001783void omapdss_dsi_vc_enable_hs(int channel, bool enable)
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001784{
1785 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
1786
Tomi Valkeinen61140c92010-01-12 16:00:30 +02001787 WARN_ON(!dsi_bus_is_locked());
1788
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001789 dsi_vc_enable(channel, 0);
1790 dsi_if_enable(0);
1791
1792 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
1793
1794 dsi_vc_enable(channel, 1);
1795 dsi_if_enable(1);
1796
1797 dsi_force_tx_stop_mode_io();
1798}
Tomi Valkeinen61140c92010-01-12 16:00:30 +02001799EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001800
1801static void dsi_vc_flush_long_data(int channel)
1802{
1803 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1804 u32 val;
1805 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
1806 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
1807 (val >> 0) & 0xff,
1808 (val >> 8) & 0xff,
1809 (val >> 16) & 0xff,
1810 (val >> 24) & 0xff);
1811 }
1812}
1813
1814static void dsi_show_rx_ack_with_err(u16 err)
1815{
1816 DSSERR("\tACK with ERROR (%#x):\n", err);
1817 if (err & (1 << 0))
1818 DSSERR("\t\tSoT Error\n");
1819 if (err & (1 << 1))
1820 DSSERR("\t\tSoT Sync Error\n");
1821 if (err & (1 << 2))
1822 DSSERR("\t\tEoT Sync Error\n");
1823 if (err & (1 << 3))
1824 DSSERR("\t\tEscape Mode Entry Command Error\n");
1825 if (err & (1 << 4))
1826 DSSERR("\t\tLP Transmit Sync Error\n");
1827 if (err & (1 << 5))
1828 DSSERR("\t\tHS Receive Timeout Error\n");
1829 if (err & (1 << 6))
1830 DSSERR("\t\tFalse Control Error\n");
1831 if (err & (1 << 7))
1832 DSSERR("\t\t(reserved7)\n");
1833 if (err & (1 << 8))
1834 DSSERR("\t\tECC Error, single-bit (corrected)\n");
1835 if (err & (1 << 9))
1836 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
1837 if (err & (1 << 10))
1838 DSSERR("\t\tChecksum Error\n");
1839 if (err & (1 << 11))
1840 DSSERR("\t\tData type not recognized\n");
1841 if (err & (1 << 12))
1842 DSSERR("\t\tInvalid VC ID\n");
1843 if (err & (1 << 13))
1844 DSSERR("\t\tInvalid Transmission Length\n");
1845 if (err & (1 << 14))
1846 DSSERR("\t\t(reserved14)\n");
1847 if (err & (1 << 15))
1848 DSSERR("\t\tDSI Protocol Violation\n");
1849}
1850
1851static u16 dsi_vc_flush_receive_data(int channel)
1852{
1853 /* RX_FIFO_NOT_EMPTY */
1854 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1855 u32 val;
1856 u8 dt;
1857 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
1858 DSSDBG("\trawval %#08x\n", val);
1859 dt = FLD_GET(val, 5, 0);
1860 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
1861 u16 err = FLD_GET(val, 23, 8);
1862 dsi_show_rx_ack_with_err(err);
1863 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
1864 DSSDBG("\tDCS short response, 1 byte: %#x\n",
1865 FLD_GET(val, 23, 8));
1866 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
1867 DSSDBG("\tDCS short response, 2 byte: %#x\n",
1868 FLD_GET(val, 23, 8));
1869 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
1870 DSSDBG("\tDCS long response, len %d\n",
1871 FLD_GET(val, 23, 8));
1872 dsi_vc_flush_long_data(channel);
1873 } else {
1874 DSSERR("\tunknown datatype 0x%02x\n", dt);
1875 }
1876 }
1877 return 0;
1878}
1879
1880static int dsi_vc_send_bta(int channel)
1881{
Tomi Valkeinen446f7bf2010-01-11 16:12:31 +02001882 if (dsi.debug_write || dsi.debug_read)
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001883 DSSDBG("dsi_vc_send_bta %d\n", channel);
1884
Tomi Valkeinen4f765022010-01-18 16:27:52 +02001885 WARN_ON(!dsi_bus_is_locked());
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001886
1887 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
1888 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
1889 dsi_vc_flush_receive_data(channel);
1890 }
1891
1892 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
1893
1894 return 0;
1895}
1896
1897int dsi_vc_send_bta_sync(int channel)
1898{
1899 int r = 0;
1900 u32 err;
1901
1902 INIT_COMPLETION(dsi.bta_completion);
1903
1904 dsi_vc_enable_bta_irq(channel);
1905
1906 r = dsi_vc_send_bta(channel);
1907 if (r)
1908 goto err;
1909
1910 if (wait_for_completion_timeout(&dsi.bta_completion,
1911 msecs_to_jiffies(500)) == 0) {
1912 DSSERR("Failed to receive BTA\n");
1913 r = -EIO;
1914 goto err;
1915 }
1916
1917 err = dsi_get_errors();
1918 if (err) {
1919 DSSERR("Error while sending BTA: %x\n", err);
1920 r = -EIO;
1921 goto err;
1922 }
1923err:
1924 dsi_vc_disable_bta_irq(channel);
1925
1926 return r;
1927}
1928EXPORT_SYMBOL(dsi_vc_send_bta_sync);
1929
1930static inline void dsi_vc_write_long_header(int channel, u8 data_type,
1931 u16 len, u8 ecc)
1932{
1933 u32 val;
1934 u8 data_id;
1935
Tomi Valkeinen4f765022010-01-18 16:27:52 +02001936 WARN_ON(!dsi_bus_is_locked());
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001937
Tomi Valkeinendd8079d2009-12-16 16:49:03 +02001938 data_id = data_type | channel << 6;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001939
1940 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
1941 FLD_VAL(ecc, 31, 24);
1942
1943 dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
1944}
1945
1946static inline void dsi_vc_write_long_payload(int channel,
1947 u8 b1, u8 b2, u8 b3, u8 b4)
1948{
1949 u32 val;
1950
1951 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
1952
1953/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
1954 b1, b2, b3, b4, val); */
1955
1956 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
1957}
1958
1959static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
1960 u8 ecc)
1961{
1962 /*u32 val; */
1963 int i;
1964 u8 *p;
1965 int r = 0;
1966 u8 b1, b2, b3, b4;
1967
1968 if (dsi.debug_write)
1969 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
1970
1971 /* len + header */
1972 if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
1973 DSSERR("unable to send long packet: packet too long.\n");
1974 return -EINVAL;
1975 }
1976
1977 dsi_vc_config_l4(channel);
1978
1979 dsi_vc_write_long_header(channel, data_type, len, ecc);
1980
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001981 p = data;
1982 for (i = 0; i < len >> 2; i++) {
1983 if (dsi.debug_write)
1984 DSSDBG("\tsending full packet %d\n", i);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02001985
1986 b1 = *p++;
1987 b2 = *p++;
1988 b3 = *p++;
1989 b4 = *p++;
1990
1991 dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
1992 }
1993
1994 i = len % 4;
1995 if (i) {
1996 b1 = 0; b2 = 0; b3 = 0;
1997
1998 if (dsi.debug_write)
1999 DSSDBG("\tsending remainder bytes %d\n", i);
2000
2001 switch (i) {
2002 case 3:
2003 b1 = *p++;
2004 b2 = *p++;
2005 b3 = *p++;
2006 break;
2007 case 2:
2008 b1 = *p++;
2009 b2 = *p++;
2010 break;
2011 case 1:
2012 b1 = *p++;
2013 break;
2014 }
2015
2016 dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
2017 }
2018
2019 return r;
2020}
2021
2022static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
2023{
2024 u32 r;
2025 u8 data_id;
2026
Tomi Valkeinen4f765022010-01-18 16:27:52 +02002027 WARN_ON(!dsi_bus_is_locked());
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002028
2029 if (dsi.debug_write)
2030 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2031 channel,
2032 data_type, data & 0xff, (data >> 8) & 0xff);
2033
2034 dsi_vc_config_l4(channel);
2035
2036 if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
2037 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2038 return -EINVAL;
2039 }
2040
Tomi Valkeinendd8079d2009-12-16 16:49:03 +02002041 data_id = data_type | channel << 6;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002042
2043 r = (data_id << 0) | (data << 8) | (ecc << 24);
2044
2045 dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
2046
2047 return 0;
2048}
2049
2050int dsi_vc_send_null(int channel)
2051{
2052 u8 nullpkg[] = {0, 0, 0, 0};
Tomi Valkeinen397bb3c2009-12-03 13:37:31 +02002053 return dsi_vc_send_long(channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002054}
2055EXPORT_SYMBOL(dsi_vc_send_null);
2056
2057int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
2058{
2059 int r;
2060
2061 BUG_ON(len == 0);
2062
2063 if (len == 1) {
2064 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
2065 data[0], 0);
2066 } else if (len == 2) {
2067 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
2068 data[0] | (data[1] << 8), 0);
2069 } else {
2070 /* 0x39 = DCS Long Write */
2071 r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
2072 data, len, 0);
2073 }
2074
2075 return r;
2076}
2077EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
2078
2079int dsi_vc_dcs_write(int channel, u8 *data, int len)
2080{
2081 int r;
2082
2083 r = dsi_vc_dcs_write_nosync(channel, data, len);
2084 if (r)
2085 return r;
2086
2087 r = dsi_vc_send_bta_sync(channel);
2088
2089 return r;
2090}
2091EXPORT_SYMBOL(dsi_vc_dcs_write);
2092
Tomi Valkeinen828c48f2009-12-16 14:53:15 +02002093int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd)
2094{
2095 return dsi_vc_dcs_write(channel, &dcs_cmd, 1);
2096}
2097EXPORT_SYMBOL(dsi_vc_dcs_write_0);
2098
2099int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param)
2100{
2101 u8 buf[2];
2102 buf[0] = dcs_cmd;
2103 buf[1] = param;
2104 return dsi_vc_dcs_write(channel, buf, 2);
2105}
2106EXPORT_SYMBOL(dsi_vc_dcs_write_1);
2107
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002108int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
2109{
2110 u32 val;
2111 u8 dt;
2112 int r;
2113
2114 if (dsi.debug_read)
Tomi Valkeinenff90a342009-12-03 13:38:04 +02002115 DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002116
2117 r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
2118 if (r)
2119 return r;
2120
2121 r = dsi_vc_send_bta_sync(channel);
2122 if (r)
2123 return r;
2124
2125 /* RX_FIFO_NOT_EMPTY */
2126 if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) {
2127 DSSERR("RX fifo empty when trying to read.\n");
2128 return -EIO;
2129 }
2130
2131 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2132 if (dsi.debug_read)
2133 DSSDBG("\theader: %08x\n", val);
2134 dt = FLD_GET(val, 5, 0);
2135 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
2136 u16 err = FLD_GET(val, 23, 8);
2137 dsi_show_rx_ack_with_err(err);
2138 return -EIO;
2139
2140 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
2141 u8 data = FLD_GET(val, 15, 8);
2142 if (dsi.debug_read)
2143 DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
2144
2145 if (buflen < 1)
2146 return -EIO;
2147
2148 buf[0] = data;
2149
2150 return 1;
2151 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
2152 u16 data = FLD_GET(val, 23, 8);
2153 if (dsi.debug_read)
2154 DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
2155
2156 if (buflen < 2)
2157 return -EIO;
2158
2159 buf[0] = data & 0xff;
2160 buf[1] = (data >> 8) & 0xff;
2161
2162 return 2;
2163 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
2164 int w;
2165 int len = FLD_GET(val, 23, 8);
2166 if (dsi.debug_read)
2167 DSSDBG("\tDCS long response, len %d\n", len);
2168
2169 if (len > buflen)
2170 return -EIO;
2171
2172 /* two byte checksum ends the packet, not included in len */
2173 for (w = 0; w < len + 2;) {
2174 int b;
2175 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2176 if (dsi.debug_read)
2177 DSSDBG("\t\t%02x %02x %02x %02x\n",
2178 (val >> 0) & 0xff,
2179 (val >> 8) & 0xff,
2180 (val >> 16) & 0xff,
2181 (val >> 24) & 0xff);
2182
2183 for (b = 0; b < 4; ++b) {
2184 if (w < len)
2185 buf[w] = (val >> (b * 8)) & 0xff;
2186 /* we discard the 2 byte checksum */
2187 ++w;
2188 }
2189 }
2190
2191 return len;
2192
2193 } else {
2194 DSSERR("\tunknown datatype 0x%02x\n", dt);
2195 return -EIO;
2196 }
2197}
2198EXPORT_SYMBOL(dsi_vc_dcs_read);
2199
Tomi Valkeinen828c48f2009-12-16 14:53:15 +02002200int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data)
2201{
2202 int r;
2203
2204 r = dsi_vc_dcs_read(channel, dcs_cmd, data, 1);
2205
2206 if (r < 0)
2207 return r;
2208
2209 if (r != 1)
2210 return -EIO;
2211
2212 return 0;
2213}
2214EXPORT_SYMBOL(dsi_vc_dcs_read_1);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002215
2216int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
2217{
2218 int r;
2219 r = dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
2220 len, 0);
2221
2222 if (r)
2223 return r;
2224
2225 r = dsi_vc_send_bta_sync(channel);
2226
2227 return r;
2228}
2229EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
2230
2231static void dsi_set_lp_rx_timeout(unsigned long ns)
2232{
2233 u32 r;
2234 unsigned x4, x16;
2235 unsigned long fck;
2236 unsigned long ticks;
2237
2238 /* ticks in DSI_FCK */
2239
2240 fck = dsi_fclk_rate();
2241 ticks = (fck / 1000 / 1000) * ns / 1000;
2242 x4 = 0;
2243 x16 = 0;
2244
2245 if (ticks > 0x1fff) {
2246 ticks = (fck / 1000 / 1000) * ns / 1000 / 4;
2247 x4 = 1;
2248 x16 = 0;
2249 }
2250
2251 if (ticks > 0x1fff) {
2252 ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
2253 x4 = 0;
2254 x16 = 1;
2255 }
2256
2257 if (ticks > 0x1fff) {
2258 ticks = (fck / 1000 / 1000) * ns / 1000 / (4 * 16);
2259 x4 = 1;
2260 x16 = 1;
2261 }
2262
2263 if (ticks > 0x1fff) {
2264 DSSWARN("LP_TX_TO over limit, setting it to max\n");
2265 ticks = 0x1fff;
2266 x4 = 1;
2267 x16 = 1;
2268 }
2269
2270 r = dsi_read_reg(DSI_TIMING2);
2271 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
2272 r = FLD_MOD(r, x16, 14, 14); /* LP_RX_TO_X16 */
2273 r = FLD_MOD(r, x4, 13, 13); /* LP_RX_TO_X4 */
2274 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
2275 dsi_write_reg(DSI_TIMING2, r);
2276
2277 DSSDBG("LP_RX_TO %lu ns (%#lx ticks%s%s)\n",
2278 (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
2279 (fck / 1000 / 1000),
2280 ticks, x4 ? " x4" : "", x16 ? " x16" : "");
2281}
2282
2283static void dsi_set_ta_timeout(unsigned long ns)
2284{
2285 u32 r;
2286 unsigned x8, x16;
2287 unsigned long fck;
2288 unsigned long ticks;
2289
2290 /* ticks in DSI_FCK */
2291 fck = dsi_fclk_rate();
2292 ticks = (fck / 1000 / 1000) * ns / 1000;
2293 x8 = 0;
2294 x16 = 0;
2295
2296 if (ticks > 0x1fff) {
2297 ticks = (fck / 1000 / 1000) * ns / 1000 / 8;
2298 x8 = 1;
2299 x16 = 0;
2300 }
2301
2302 if (ticks > 0x1fff) {
2303 ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
2304 x8 = 0;
2305 x16 = 1;
2306 }
2307
2308 if (ticks > 0x1fff) {
2309 ticks = (fck / 1000 / 1000) * ns / 1000 / (8 * 16);
2310 x8 = 1;
2311 x16 = 1;
2312 }
2313
2314 if (ticks > 0x1fff) {
2315 DSSWARN("TA_TO over limit, setting it to max\n");
2316 ticks = 0x1fff;
2317 x8 = 1;
2318 x16 = 1;
2319 }
2320
2321 r = dsi_read_reg(DSI_TIMING1);
2322 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
2323 r = FLD_MOD(r, x16, 30, 30); /* TA_TO_X16 */
2324 r = FLD_MOD(r, x8, 29, 29); /* TA_TO_X8 */
2325 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
2326 dsi_write_reg(DSI_TIMING1, r);
2327
2328 DSSDBG("TA_TO %lu ns (%#lx ticks%s%s)\n",
2329 (ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1) * 1000) /
2330 (fck / 1000 / 1000),
2331 ticks, x8 ? " x8" : "", x16 ? " x16" : "");
2332}
2333
2334static void dsi_set_stop_state_counter(unsigned long ns)
2335{
2336 u32 r;
2337 unsigned x4, x16;
2338 unsigned long fck;
2339 unsigned long ticks;
2340
2341 /* ticks in DSI_FCK */
2342
2343 fck = dsi_fclk_rate();
2344 ticks = (fck / 1000 / 1000) * ns / 1000;
2345 x4 = 0;
2346 x16 = 0;
2347
2348 if (ticks > 0x1fff) {
2349 ticks = (fck / 1000 / 1000) * ns / 1000 / 4;
2350 x4 = 1;
2351 x16 = 0;
2352 }
2353
2354 if (ticks > 0x1fff) {
2355 ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
2356 x4 = 0;
2357 x16 = 1;
2358 }
2359
2360 if (ticks > 0x1fff) {
2361 ticks = (fck / 1000 / 1000) * ns / 1000 / (4 * 16);
2362 x4 = 1;
2363 x16 = 1;
2364 }
2365
2366 if (ticks > 0x1fff) {
2367 DSSWARN("STOP_STATE_COUNTER_IO over limit, "
2368 "setting it to max\n");
2369 ticks = 0x1fff;
2370 x4 = 1;
2371 x16 = 1;
2372 }
2373
2374 r = dsi_read_reg(DSI_TIMING1);
2375 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2376 r = FLD_MOD(r, x16, 14, 14); /* STOP_STATE_X16_IO */
2377 r = FLD_MOD(r, x4, 13, 13); /* STOP_STATE_X4_IO */
2378 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
2379 dsi_write_reg(DSI_TIMING1, r);
2380
2381 DSSDBG("STOP_STATE_COUNTER %lu ns (%#lx ticks%s%s)\n",
2382 (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
2383 (fck / 1000 / 1000),
2384 ticks, x4 ? " x4" : "", x16 ? " x16" : "");
2385}
2386
2387static void dsi_set_hs_tx_timeout(unsigned long ns)
2388{
2389 u32 r;
2390 unsigned x4, x16;
2391 unsigned long fck;
2392 unsigned long ticks;
2393
2394 /* ticks in TxByteClkHS */
2395
2396 fck = dsi_get_txbyteclkhs();
2397 ticks = (fck / 1000 / 1000) * ns / 1000;
2398 x4 = 0;
2399 x16 = 0;
2400
2401 if (ticks > 0x1fff) {
2402 ticks = (fck / 1000 / 1000) * ns / 1000 / 4;
2403 x4 = 1;
2404 x16 = 0;
2405 }
2406
2407 if (ticks > 0x1fff) {
2408 ticks = (fck / 1000 / 1000) * ns / 1000 / 16;
2409 x4 = 0;
2410 x16 = 1;
2411 }
2412
2413 if (ticks > 0x1fff) {
2414 ticks = (fck / 1000 / 1000) * ns / 1000 / (4 * 16);
2415 x4 = 1;
2416 x16 = 1;
2417 }
2418
2419 if (ticks > 0x1fff) {
2420 DSSWARN("HS_TX_TO over limit, setting it to max\n");
2421 ticks = 0x1fff;
2422 x4 = 1;
2423 x16 = 1;
2424 }
2425
2426 r = dsi_read_reg(DSI_TIMING2);
2427 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
2428 r = FLD_MOD(r, x16, 30, 30); /* HS_TX_TO_X16 */
2429 r = FLD_MOD(r, x4, 29, 29); /* HS_TX_TO_X8 (4 really) */
2430 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
2431 dsi_write_reg(DSI_TIMING2, r);
2432
2433 DSSDBG("HS_TX_TO %lu ns (%#lx ticks%s%s)\n",
2434 (ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
2435 (fck / 1000 / 1000),
2436 ticks, x4 ? " x4" : "", x16 ? " x16" : "");
2437}
2438static int dsi_proto_config(struct omap_dss_device *dssdev)
2439{
2440 u32 r;
2441 int buswidth = 0;
2442
Tomi Valkeinendd8079d2009-12-16 16:49:03 +02002443 dsi_config_tx_fifo(DSI_FIFO_SIZE_32,
2444 DSI_FIFO_SIZE_32,
2445 DSI_FIFO_SIZE_32,
2446 DSI_FIFO_SIZE_32);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002447
Tomi Valkeinendd8079d2009-12-16 16:49:03 +02002448 dsi_config_rx_fifo(DSI_FIFO_SIZE_32,
2449 DSI_FIFO_SIZE_32,
2450 DSI_FIFO_SIZE_32,
2451 DSI_FIFO_SIZE_32);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002452
2453 /* XXX what values for the timeouts? */
2454 dsi_set_stop_state_counter(1000);
2455 dsi_set_ta_timeout(6400000);
2456 dsi_set_lp_rx_timeout(48000);
2457 dsi_set_hs_tx_timeout(1000000);
2458
2459 switch (dssdev->ctrl.pixel_size) {
2460 case 16:
2461 buswidth = 0;
2462 break;
2463 case 18:
2464 buswidth = 1;
2465 break;
2466 case 24:
2467 buswidth = 2;
2468 break;
2469 default:
2470 BUG();
2471 }
2472
2473 r = dsi_read_reg(DSI_CTRL);
2474 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
2475 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
2476 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
2477 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
2478 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
2479 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
2480 r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
2481 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
2482 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
2483 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
2484 r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
2485
2486 dsi_write_reg(DSI_CTRL, r);
2487
2488 dsi_vc_initial_config(0);
Tomi Valkeinendd8079d2009-12-16 16:49:03 +02002489 dsi_vc_initial_config(1);
2490 dsi_vc_initial_config(2);
2491 dsi_vc_initial_config(3);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002492
2493 return 0;
2494}
2495
2496static void dsi_proto_timings(struct omap_dss_device *dssdev)
2497{
2498 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
2499 unsigned tclk_pre, tclk_post;
2500 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
2501 unsigned ths_trail, ths_exit;
2502 unsigned ddr_clk_pre, ddr_clk_post;
2503 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
2504 unsigned ths_eot;
2505 u32 r;
2506
2507 r = dsi_read_reg(DSI_DSIPHY_CFG0);
2508 ths_prepare = FLD_GET(r, 31, 24);
2509 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
2510 ths_zero = ths_prepare_ths_zero - ths_prepare;
2511 ths_trail = FLD_GET(r, 15, 8);
2512 ths_exit = FLD_GET(r, 7, 0);
2513
2514 r = dsi_read_reg(DSI_DSIPHY_CFG1);
2515 tlpx = FLD_GET(r, 22, 16) * 2;
2516 tclk_trail = FLD_GET(r, 15, 8);
2517 tclk_zero = FLD_GET(r, 7, 0);
2518
2519 r = dsi_read_reg(DSI_DSIPHY_CFG2);
2520 tclk_prepare = FLD_GET(r, 7, 0);
2521
2522 /* min 8*UI */
2523 tclk_pre = 20;
2524 /* min 60ns + 52*UI */
2525 tclk_post = ns2ddr(60) + 26;
2526
2527 /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
2528 if (dssdev->phy.dsi.data1_lane != 0 &&
2529 dssdev->phy.dsi.data2_lane != 0)
2530 ths_eot = 2;
2531 else
2532 ths_eot = 4;
2533
2534 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
2535 4);
2536 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
2537
2538 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
2539 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
2540
2541 r = dsi_read_reg(DSI_CLK_TIMING);
2542 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
2543 r = FLD_MOD(r, ddr_clk_post, 7, 0);
2544 dsi_write_reg(DSI_CLK_TIMING, r);
2545
2546 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
2547 ddr_clk_pre,
2548 ddr_clk_post);
2549
2550 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
2551 DIV_ROUND_UP(ths_prepare, 4) +
2552 DIV_ROUND_UP(ths_zero + 3, 4);
2553
2554 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
2555
2556 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
2557 FLD_VAL(exit_hs_mode_lat, 15, 0);
2558 dsi_write_reg(DSI_VM_TIMING7, r);
2559
2560 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
2561 enter_hs_mode_lat, exit_hs_mode_lat);
2562}
2563
2564
2565#define DSI_DECL_VARS \
2566 int __dsi_cb = 0; u32 __dsi_cv = 0;
2567
2568#define DSI_FLUSH(ch) \
2569 if (__dsi_cb > 0) { \
2570 /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
2571 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
2572 __dsi_cb = __dsi_cv = 0; \
2573 }
2574
2575#define DSI_PUSH(ch, data) \
2576 do { \
2577 __dsi_cv |= (data) << (__dsi_cb * 8); \
2578 /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
2579 if (++__dsi_cb > 3) \
2580 DSI_FLUSH(ch); \
2581 } while (0)
2582
2583static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
2584 int x, int y, int w, int h)
2585{
2586 /* Note: supports only 24bit colors in 32bit container */
2587 int first = 1;
2588 int fifo_stalls = 0;
2589 int max_dsi_packet_size;
2590 int max_data_per_packet;
2591 int max_pixels_per_packet;
2592 int pixels_left;
2593 int bytespp = dssdev->ctrl.pixel_size / 8;
2594 int scr_width;
2595 u32 __iomem *data;
2596 int start_offset;
2597 int horiz_inc;
2598 int current_x;
2599 struct omap_overlay *ovl;
2600
2601 debug_irq = 0;
2602
2603 DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
2604 x, y, w, h);
2605
2606 ovl = dssdev->manager->overlays[0];
2607
2608 if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
2609 return -EINVAL;
2610
2611 if (dssdev->ctrl.pixel_size != 24)
2612 return -EINVAL;
2613
2614 scr_width = ovl->info.screen_width;
2615 data = ovl->info.vaddr;
2616
2617 start_offset = scr_width * y + x;
2618 horiz_inc = scr_width - w;
2619 current_x = x;
2620
2621 /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
2622 * in fifo */
2623
2624 /* When using CPU, max long packet size is TX buffer size */
2625 max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
2626
2627 /* we seem to get better perf if we divide the tx fifo to half,
2628 and while the other half is being sent, we fill the other half
2629 max_dsi_packet_size /= 2; */
2630
2631 max_data_per_packet = max_dsi_packet_size - 4 - 1;
2632
2633 max_pixels_per_packet = max_data_per_packet / bytespp;
2634
2635 DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
2636
2637 pixels_left = w * h;
2638
2639 DSSDBG("total pixels %d\n", pixels_left);
2640
2641 data += start_offset;
2642
2643 while (pixels_left > 0) {
2644 /* 0x2c = write_memory_start */
2645 /* 0x3c = write_memory_continue */
2646 u8 dcs_cmd = first ? 0x2c : 0x3c;
2647 int pixels;
2648 DSI_DECL_VARS;
2649 first = 0;
2650
2651#if 1
2652 /* using fifo not empty */
2653 /* TX_FIFO_NOT_EMPTY */
2654 while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002655 fifo_stalls++;
2656 if (fifo_stalls > 0xfffff) {
2657 DSSERR("fifo stalls overflow, pixels left %d\n",
2658 pixels_left);
2659 dsi_if_enable(0);
2660 return -EIO;
2661 }
Tomi Valkeinen24be78b2010-01-07 14:19:48 +02002662 udelay(1);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002663 }
2664#elif 1
2665 /* using fifo emptiness */
2666 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
2667 max_dsi_packet_size) {
2668 fifo_stalls++;
2669 if (fifo_stalls > 0xfffff) {
2670 DSSERR("fifo stalls overflow, pixels left %d\n",
2671 pixels_left);
2672 dsi_if_enable(0);
2673 return -EIO;
2674 }
2675 }
2676#else
2677 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
2678 fifo_stalls++;
2679 if (fifo_stalls > 0xfffff) {
2680 DSSERR("fifo stalls overflow, pixels left %d\n",
2681 pixels_left);
2682 dsi_if_enable(0);
2683 return -EIO;
2684 }
2685 }
2686#endif
2687 pixels = min(max_pixels_per_packet, pixels_left);
2688
2689 pixels_left -= pixels;
2690
2691 dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
2692 1 + pixels * bytespp, 0);
2693
2694 DSI_PUSH(0, dcs_cmd);
2695
2696 while (pixels-- > 0) {
2697 u32 pix = __raw_readl(data++);
2698
2699 DSI_PUSH(0, (pix >> 16) & 0xff);
2700 DSI_PUSH(0, (pix >> 8) & 0xff);
2701 DSI_PUSH(0, (pix >> 0) & 0xff);
2702
2703 current_x++;
2704 if (current_x == x+w) {
2705 current_x = x;
2706 data += horiz_inc;
2707 }
2708 }
2709
2710 DSI_FLUSH(0);
2711 }
2712
2713 return 0;
2714}
2715
2716static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
2717 u16 x, u16 y, u16 w, u16 h)
2718{
2719 unsigned bytespp;
2720 unsigned bytespl;
2721 unsigned bytespf;
2722 unsigned total_len;
2723 unsigned packet_payload;
2724 unsigned packet_len;
2725 u32 l;
2726 bool use_te_trigger;
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002727 const unsigned channel = dsi.update_channel;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002728 /* line buffer is 1024 x 24bits */
2729 /* XXX: for some reason using full buffer size causes considerable TX
2730 * slowdown with update sizes that fill the whole buffer */
2731 const unsigned line_buf_size = 1023 * 3;
2732
2733 use_te_trigger = dsi.te_enabled && !dsi.use_ext_te;
2734
Tomi Valkeinen446f7bf2010-01-11 16:12:31 +02002735 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
2736 x, y, w, h);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002737
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002738 dsi_vc_config_vp(channel);
2739
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002740 bytespp = dssdev->ctrl.pixel_size / 8;
2741 bytespl = w * bytespp;
2742 bytespf = bytespl * h;
2743
2744 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
2745 * number of lines in a packet. See errata about VP_CLK_RATIO */
2746
2747 if (bytespf < line_buf_size)
2748 packet_payload = bytespf;
2749 else
2750 packet_payload = (line_buf_size) / bytespl * bytespl;
2751
2752 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
2753 total_len = (bytespf / packet_payload) * packet_len;
2754
2755 if (bytespf % packet_payload)
2756 total_len += (bytespf % packet_payload) + 1;
2757
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002758 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
2759 dsi_write_reg(DSI_VC_TE(channel), l);
2760
2761 dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
2762
2763 if (use_te_trigger)
2764 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
2765 else
2766 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
2767 dsi_write_reg(DSI_VC_TE(channel), l);
2768
2769 /* We put SIDLEMODE to no-idle for the duration of the transfer,
2770 * because DSS interrupts are not capable of waking up the CPU and the
2771 * framedone interrupt could be delayed for quite a long time. I think
2772 * the same goes for any DSS interrupts, but for some reason I have not
2773 * seen the problem anywhere else than here.
2774 */
2775 dispc_disable_sidle();
2776
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002777 dsi_perf_mark_start();
2778
2779 schedule_delayed_work(&dsi.framedone_timeout_work,
2780 msecs_to_jiffies(250));
2781
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002782 dss_start_update(dssdev);
2783
2784 if (use_te_trigger) {
2785 /* disable LP_RX_TO, so that we can receive TE. Time to wait
2786 * for TE is longer than the timer allows */
2787 REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
2788
2789 dsi_vc_send_bta(channel);
2790
2791#ifdef DSI_CATCH_MISSING_TE
2792 mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250));
2793#endif
2794 }
2795}
2796
2797#ifdef DSI_CATCH_MISSING_TE
2798static void dsi_te_timeout(unsigned long arg)
2799{
2800 DSSERR("TE not received for 250ms!\n");
2801}
2802#endif
2803
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002804static void dsi_framedone_timeout_work_callback(struct work_struct *work)
2805{
2806 int r;
2807 const int channel = dsi.update_channel;
2808 bool use_te_trigger;
2809
2810 DSSERR("Framedone not received for 250ms!\n");
2811
2812 /* SIDLEMODE back to smart-idle */
2813 dispc_enable_sidle();
2814
2815 use_te_trigger = dsi.te_enabled && !dsi.use_ext_te;
2816
2817 if (use_te_trigger) {
2818 /* enable LP_RX_TO again after the TE */
2819 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
2820 }
2821
2822 /* Send BTA after the frame. We need this for the TE to work, as TE
2823 * trigger is only sent for BTAs without preceding packet. Thus we need
2824 * to BTA after the pixel packets so that next BTA will cause TE
2825 * trigger.
2826 *
2827 * This is not needed when TE is not in use, but we do it anyway to
2828 * make sure that the transfer has been completed. It would be more
2829 * optimal, but more complex, to wait only just before starting next
2830 * transfer. */
2831 r = dsi_vc_send_bta_sync(channel);
2832 if (r)
2833 DSSERR("BTA after framedone failed\n");
2834
2835 /* RX_FIFO_NOT_EMPTY */
2836 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
2837 DSSERR("Received error during frame transfer:\n");
2838 dsi_vc_flush_receive_data(channel);
2839 }
2840
2841 dsi.framedone_callback(-ETIMEDOUT, dsi.framedone_data);
2842}
2843
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002844static void dsi_framedone_irq_callback(void *data, u32 mask)
2845{
2846 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
2847 * turns itself off. However, DSI still has the pixels in its buffers,
2848 * and is sending the data.
2849 */
2850
2851 /* SIDLEMODE back to smart-idle */
2852 dispc_enable_sidle();
2853
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002854 schedule_work(&dsi.framedone_work);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002855}
2856
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002857static void dsi_handle_framedone(void)
2858{
2859 int r;
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002860 const int channel = dsi.update_channel;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002861 bool use_te_trigger;
2862
2863 use_te_trigger = dsi.te_enabled && !dsi.use_ext_te;
2864
Tomi Valkeinen446f7bf2010-01-11 16:12:31 +02002865 DSSDBG("FRAMEDONE\n");
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002866
2867 if (use_te_trigger) {
2868 /* enable LP_RX_TO again after the TE */
2869 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
2870 }
2871
2872 /* Send BTA after the frame. We need this for the TE to work, as TE
2873 * trigger is only sent for BTAs without preceding packet. Thus we need
2874 * to BTA after the pixel packets so that next BTA will cause TE
2875 * trigger.
2876 *
2877 * This is not needed when TE is not in use, but we do it anyway to
2878 * make sure that the transfer has been completed. It would be more
2879 * optimal, but more complex, to wait only just before starting next
2880 * transfer. */
2881 r = dsi_vc_send_bta_sync(channel);
2882 if (r)
2883 DSSERR("BTA after framedone failed\n");
2884
2885 /* RX_FIFO_NOT_EMPTY */
2886 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
2887 DSSERR("Received error during frame transfer:\n");
Tomi Valkeinendd8079d2009-12-16 16:49:03 +02002888 dsi_vc_flush_receive_data(channel);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002889 }
2890
2891#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2892 dispc_fake_vsync_irq();
2893#endif
2894}
2895
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002896static void dsi_framedone_work_callback(struct work_struct *work)
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002897{
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002898 DSSDBGF();
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002899
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002900 cancel_delayed_work_sync(&dsi.framedone_timeout_work);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002901
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002902 dsi_handle_framedone();
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002903
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002904 dsi_perf_show("DISPC");
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002905
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002906 dsi.framedone_callback(0, dsi.framedone_data);
2907}
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002908
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002909int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
2910 u16 *x, u16 *y, u16 *w, u16 *h)
2911{
2912 u16 dw, dh;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002913
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002914 dssdev->driver->get_resolution(dssdev, &dw, &dh);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002915
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002916 if (*x > dw || *y > dh)
2917 return -EINVAL;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002918
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002919 if (*x + *w > dw)
2920 return -EINVAL;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002921
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002922 if (*y + *h > dh)
2923 return -EINVAL;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002924
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002925 if (*w == 1)
2926 return -EINVAL;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002927
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002928 if (*w == 0 || *h == 0)
2929 return -EINVAL;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002930
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002931 dsi_perf_mark_setup();
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002932
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002933 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
2934 dss_setup_partial_planes(dssdev, x, y, w, h);
2935 dispc_set_lcd_size(*w, *h);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002936 }
2937
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002938 return 0;
2939}
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002940EXPORT_SYMBOL(omap_dsi_prepare_update);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002941
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002942int omap_dsi_update(struct omap_dss_device *dssdev,
2943 int channel,
2944 u16 x, u16 y, u16 w, u16 h,
2945 void (*callback)(int, void *), void *data)
2946{
2947 dsi.update_channel = channel;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002948
Tomi Valkeinen18946f62010-01-12 14:16:41 +02002949 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
2950 dsi.framedone_callback = callback;
2951 dsi.framedone_data = data;
2952
2953 dsi.update_region.x = x;
2954 dsi.update_region.y = y;
2955 dsi.update_region.w = w;
2956 dsi.update_region.h = h;
2957 dsi.update_region.device = dssdev;
2958
2959 dsi_update_screen_dispc(dssdev, x, y, w, h);
2960 } else {
2961 dsi_update_screen_l4(dssdev, x, y, w, h);
2962 dsi_perf_show("L4");
2963 callback(0, data);
2964 }
2965
2966 return 0;
2967}
2968EXPORT_SYMBOL(omap_dsi_update);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02002969
2970/* Display funcs */
2971
2972static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
2973{
2974 int r;
2975
2976 r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL,
2977 DISPC_IRQ_FRAMEDONE);
2978 if (r) {
2979 DSSERR("can't get FRAMEDONE irq\n");
2980 return r;
2981 }
2982
2983 dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT);
2984
2985 dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_DSI);
2986 dispc_enable_fifohandcheck(1);
2987
2988 dispc_set_tft_data_lines(dssdev->ctrl.pixel_size);
2989
2990 {
2991 struct omap_video_timings timings = {
2992 .hsw = 1,
2993 .hfp = 1,
2994 .hbp = 1,
2995 .vsw = 1,
2996 .vfp = 0,
2997 .vbp = 0,
2998 };
2999
3000 dispc_set_lcd_timings(&timings);
3001 }
3002
3003 return 0;
3004}
3005
3006static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
3007{
3008 omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL,
3009 DISPC_IRQ_FRAMEDONE);
3010}
3011
3012static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
3013{
3014 struct dsi_clock_info cinfo;
3015 int r;
3016
3017 /* we always use DSS2_FCK as input clock */
3018 cinfo.use_dss2_fck = true;
3019 cinfo.regn = dssdev->phy.dsi.div.regn;
3020 cinfo.regm = dssdev->phy.dsi.div.regm;
3021 cinfo.regm3 = dssdev->phy.dsi.div.regm3;
3022 cinfo.regm4 = dssdev->phy.dsi.div.regm4;
3023 r = dsi_calc_clock_rates(&cinfo);
3024 if (r)
3025 return r;
3026
3027 r = dsi_pll_set_clock_div(&cinfo);
3028 if (r) {
3029 DSSERR("Failed to set dsi clocks\n");
3030 return r;
3031 }
3032
3033 return 0;
3034}
3035
3036static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
3037{
3038 struct dispc_clock_info dispc_cinfo;
3039 int r;
3040 unsigned long long fck;
3041
3042 fck = dsi_get_dsi1_pll_rate();
3043
3044 dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div;
3045 dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div;
3046
3047 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
3048 if (r) {
3049 DSSERR("Failed to calc dispc clocks\n");
3050 return r;
3051 }
3052
3053 r = dispc_set_clock_div(&dispc_cinfo);
3054 if (r) {
3055 DSSERR("Failed to set dispc clocks\n");
3056 return r;
3057 }
3058
3059 return 0;
3060}
3061
3062static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
3063{
3064 int r;
3065
3066 _dsi_print_reset_status();
3067
3068 r = dsi_pll_init(dssdev, true, true);
3069 if (r)
3070 goto err0;
3071
3072 r = dsi_configure_dsi_clocks(dssdev);
3073 if (r)
3074 goto err1;
3075
Tomi Valkeinen2f18c4d2010-01-08 18:00:36 +02003076 dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
3077 dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003078
3079 DSSDBG("PLL OK\n");
3080
3081 r = dsi_configure_dispc_clocks(dssdev);
3082 if (r)
3083 goto err2;
3084
3085 r = dsi_complexio_init(dssdev);
3086 if (r)
3087 goto err2;
3088
3089 _dsi_print_reset_status();
3090
3091 dsi_proto_timings(dssdev);
3092 dsi_set_lp_clk_divisor(dssdev);
3093
3094 if (1)
3095 _dsi_print_reset_status();
3096
3097 r = dsi_proto_config(dssdev);
3098 if (r)
3099 goto err3;
3100
3101 /* enable interface */
3102 dsi_vc_enable(0, 1);
Tomi Valkeinendd8079d2009-12-16 16:49:03 +02003103 dsi_vc_enable(1, 1);
3104 dsi_vc_enable(2, 1);
3105 dsi_vc_enable(3, 1);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003106 dsi_if_enable(1);
3107 dsi_force_tx_stop_mode_io();
3108
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003109 return 0;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003110err3:
3111 dsi_complexio_uninit();
3112err2:
Tomi Valkeinen2f18c4d2010-01-08 18:00:36 +02003113 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3114 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003115err1:
3116 dsi_pll_uninit();
3117err0:
3118 return r;
3119}
3120
3121static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
3122{
Tomi Valkeinen2f18c4d2010-01-08 18:00:36 +02003123 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3124 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003125 dsi_complexio_uninit();
3126 dsi_pll_uninit();
3127}
3128
3129static int dsi_core_init(void)
3130{
3131 /* Autoidle */
3132 REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
3133
3134 /* ENWAKEUP */
3135 REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
3136
3137 /* SIDLEMODE smart-idle */
3138 REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
3139
3140 _dsi_initialize_irq();
3141
3142 return 0;
3143}
3144
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003145int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003146{
3147 int r = 0;
3148
3149 DSSDBG("dsi_display_enable\n");
3150
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003151 WARN_ON(!dsi_bus_is_locked());
3152
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003153 mutex_lock(&dsi.lock);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003154
3155 r = omap_dss_start_device(dssdev);
3156 if (r) {
3157 DSSERR("failed to start device\n");
3158 goto err0;
3159 }
3160
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003161 enable_clocks(1);
3162 dsi_enable_pll_clock(1);
3163
3164 r = _dsi_reset();
3165 if (r)
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003166 goto err1;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003167
3168 dsi_core_init();
3169
3170 r = dsi_display_init_dispc(dssdev);
3171 if (r)
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003172 goto err1;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003173
3174 r = dsi_display_init_dsi(dssdev);
3175 if (r)
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003176 goto err2;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003177
3178 dsi.use_ext_te = dssdev->phy.dsi.ext_te;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003179
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003180 mutex_unlock(&dsi.lock);
3181
3182 return 0;
3183
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003184err2:
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003185 dsi_display_uninit_dispc(dssdev);
3186err1:
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003187 enable_clocks(0);
3188 dsi_enable_pll_clock(0);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003189 omap_dss_stop_device(dssdev);
3190err0:
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003191 mutex_unlock(&dsi.lock);
3192 DSSDBG("dsi_display_enable FAILED\n");
3193 return r;
3194}
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003195EXPORT_SYMBOL(omapdss_dsi_display_enable);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003196
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003197void omapdss_dsi_display_disable(struct omap_dss_device *dssdev)
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003198{
3199 DSSDBG("dsi_display_disable\n");
3200
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003201 WARN_ON(!dsi_bus_is_locked());
3202
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003203 mutex_lock(&dsi.lock);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003204
3205 dsi_display_uninit_dispc(dssdev);
3206
3207 dsi_display_uninit_dsi(dssdev);
3208
3209 enable_clocks(0);
3210 dsi_enable_pll_clock(0);
3211
3212 omap_dss_stop_device(dssdev);
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003213
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003214 mutex_unlock(&dsi.lock);
3215}
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003216EXPORT_SYMBOL(omapdss_dsi_display_disable);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003217
Tomi Valkeinen225b6502010-01-11 15:11:01 +02003218int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003219{
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003220 dsi.te_enabled = enable;
Tomi Valkeinen225b6502010-01-11 15:11:01 +02003221 return 0;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003222}
Tomi Valkeinen225b6502010-01-11 15:11:01 +02003223EXPORT_SYMBOL(omapdss_dsi_enable_te);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003224
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003225void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
3226 u32 fifo_size, enum omap_burst_size *burst_size,
3227 u32 *fifo_low, u32 *fifo_high)
3228{
3229 unsigned burst_size_bytes;
3230
3231 *burst_size = OMAP_DSS_BURST_16x32;
3232 burst_size_bytes = 16 * 32 / 8;
3233
3234 *fifo_high = fifo_size - burst_size_bytes;
3235 *fifo_low = fifo_size - burst_size_bytes * 8;
3236}
3237
3238int dsi_init_display(struct omap_dss_device *dssdev)
3239{
3240 DSSDBG("DSI init\n");
3241
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003242 /* XXX these should be figured out dynamically */
3243 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
3244 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
3245
3246 dsi.vc[0].dssdev = dssdev;
3247 dsi.vc[1].dssdev = dssdev;
3248
3249 return 0;
3250}
3251
3252int dsi_init(struct platform_device *pdev)
3253{
3254 u32 rev;
3255 int r;
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003256
3257 spin_lock_init(&dsi.errors_lock);
3258 dsi.errors = 0;
3259
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +02003260#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3261 spin_lock_init(&dsi.irq_stats_lock);
3262 dsi.irq_stats.last_reset = jiffies;
3263#endif
3264
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003265 init_completion(&dsi.bta_completion);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003266
3267 mutex_init(&dsi.lock);
Tomi Valkeinenb9eb5d72010-01-11 16:33:56 +02003268 sema_init(&dsi.bus_lock, 1);
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003269
Tomi Valkeinen18946f62010-01-12 14:16:41 +02003270 INIT_WORK(&dsi.framedone_work, dsi_framedone_work_callback);
3271 INIT_DELAYED_WORK_DEFERRABLE(&dsi.framedone_timeout_work,
3272 dsi_framedone_timeout_work_callback);
3273
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003274#ifdef DSI_CATCH_MISSING_TE
3275 init_timer(&dsi.te_timer);
3276 dsi.te_timer.function = dsi_te_timeout;
3277 dsi.te_timer.data = 0;
3278#endif
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003279 dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS);
3280 if (!dsi.base) {
3281 DSSERR("can't ioremap DSI\n");
3282 r = -ENOMEM;
3283 goto err1;
3284 }
3285
Tomi Valkeinen8a2cfea2010-02-04 17:03:41 +02003286 dsi.vdds_dsi_reg = dss_get_vdds_dsi();
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003287 if (IS_ERR(dsi.vdds_dsi_reg)) {
3288 iounmap(dsi.base);
3289 DSSERR("can't get VDDS_DSI regulator\n");
3290 r = PTR_ERR(dsi.vdds_dsi_reg);
3291 goto err2;
3292 }
3293
3294 enable_clocks(1);
3295
3296 rev = dsi_read_reg(DSI_REVISION);
3297 printk(KERN_INFO "OMAP DSI rev %d.%d\n",
3298 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3299
3300 enable_clocks(0);
3301
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003302 return 0;
3303err2:
3304 iounmap(dsi.base);
3305err1:
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003306 return r;
3307}
3308
3309void dsi_exit(void)
3310{
Tomi Valkeinen3de7a1d2009-10-28 11:59:56 +02003311 iounmap(dsi.base);
3312
3313 DSSDBG("omap_dsi_exit\n");
3314}
3315